Semiconductor device and preparation method thereof, chip, and electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, a chip, and an electronic device, which relate to the field of semiconductor technology and are intended to improve the performance of semiconductor devices. The semiconductor device includes a substrate, a cap layer, a gate layer, a protective layer, a source electrode, and a drain electrode. The cap layer is arranged on one side of the substrate, the gate layer is arranged on the side of the cap layer away from the substrate, the protective layer is at least located on two opposite sides of the gate layer in a first direction, and is arranged on the side of the cap layer away from the substrate, the first direction is parallel to the substrate, and the source electrode and the drain electrode are located on two opposite sides of the cap layer along the first direction. The above-mentioned semiconductor device is applied to a chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] Gallium nitride semiconductor materials are called third-generation semiconductor materials. Compared with the first-generation semiconductor materials represented by silicon, they have higher bandgap width, critical breakdown field strength, and electron saturation drift velocity. They have significant advantages in high frequency, high voltage resistance, high power, and low on-resistance. They can be used as core components in various power conversion systems and have broad prospects in consumer electronics, 5G RF, servers, and telecommunications applications. Summary of the invention

[0003] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device, aiming to improve the performance of the semiconductor device.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, a method for preparing a semiconductor device is provided. The method for preparing a semiconductor device comprises the following steps:

[0006] An initial capping layer and an initial protection layer are sequentially formed on one side of the substrate, wherein the initial protection layer covers a surface of the initial capping layer that is away from the substrate.

[0007] The initial capping layer and the initial protective layer in the first target area and the second target area are removed to form a capping layer and a transition protective layer. The transition protective layer covers a surface of the capping layer away from the substrate.

[0008] A source electrode is formed in the first target region, and a drain electrode is formed in the second target region. The source electrode and the drain electrode are located at opposite sides of the cap layer along a first direction, and the first direction is parallel to the substrate.

[0009] The transition protection layer in the third target area is removed to form a protection layer, wherein the protection layer is located on a side of the cap layer away from the substrate.

[0010] A gate layer is formed in the third target region. The gate layer is located on a side of the cap layer away from the substrate, and the protection layer is at least located on two opposite sides of the gate layer in the first direction.

[0011] In the method for preparing a semiconductor device provided by the above-mentioned embodiment of the present disclosure, an initial cap layer and an initial protective layer are first formed in sequence on one side of a substrate, the initial protective layer covers the surface of the initial cap layer on the side away from the substrate, and then the initial cap layer and the initial protective layer of the first target area and the second target area are removed to form a cap layer and a transition protective layer, that is, before the initial cap layers of the first target area and the second target area are removed to form the cap layer, an initial protective layer is first formed on the side of the initial cap layer away from the substrate, so that when the initial cap layers of the first target area and the second target area are removed to form the cap layer, the initial protective layer can protect the initial cap layer.

[0012] For example, when the initial capping layer of the first target area and the second target area is removed by an etching process to form a capping layer, it is usually necessary to coat a photoresist on the side of the initial capping layer away from the substrate, and perform steps such as exposure and development. The initial protective layer can isolate the initial capping layer from organic materials such as photoresist, thereby preventing the initial capping layer from being contaminated by organic materials such as photoresist, and further preventing the finally formed capping layer from being contaminated by organic materials such as photoresist, which is beneficial to improving the stability and reliability of the capping layer, and further beneficial to improving the performance of semiconductor devices.

[0013] In some embodiments, the step of sequentially forming an initial capping layer and an initial protective layer on one side of the substrate comprises the following steps:

[0014] An initial capping layer is formed on one side of the substrate.

[0015] An initial protection layer is in-situ grown on a side of the initial cap layer away from the substrate.

[0016] In some embodiments, after removing the initial capping layer and the initial protective layer in the first target area and the second target area to form a capping layer and a transition protective layer, the preparation method further comprises the following steps:

[0017] The cap layer is subjected to annealing treatment.

[0018] In some embodiments, removing the transition protection layer in the third target area to form a protection layer comprises the following steps:

[0019] The transition protection layer in the third target area is removed by a wet etching process to form a protection layer.

[0020] In some embodiments, removing the transition protection layer in the third target area to form a protection layer comprises the following steps:

[0021] A portion of the transition protection layer in a third target area is removed by dry etching from a surface of the transition protection layer on one side away from the substrate along a third direction, wherein the third direction is a thickness direction of the substrate.

[0022] The remaining transition protection layer in the third target area is removed by a wet etching process to form a protection layer.

[0023] In some embodiments, before forming the source electrode in the first target region and forming the drain electrode in the second target region, the preparation method further comprises the following steps:

[0024] An initial passivation layer is formed; the initial passivation layer covers the transition protection layer and two opposite sides of the cap layer along the first direction, and the initial passivation layer is also located in the first target area, the area between the cap layer and the first target area, the second target area, and the area between the cap layer and the second target area.

[0025] Between forming a source electrode in the first target region, forming a drain electrode in the second target region, and removing the transition protection layer in the third target region to form a protection layer, the preparation method further comprises the following steps:

[0026] The initial passivation layer in the third target area is removed to form a passivation layer.

[0027] On the other hand, a semiconductor device is provided. The semiconductor device includes a substrate, a cap layer, a gate layer, a protective layer, a source electrode and a drain electrode. The cap layer is arranged on one side of the substrate. The gate layer is arranged on a side of the cap layer away from the substrate. The protective layer is at least located on two opposite sides of the gate layer in a first direction and is arranged on a side of the cap layer away from the substrate, and the first direction is parallel to the substrate. The source electrode and the drain electrode are located on two opposite sides of the cap layer along the first direction.

[0028] In some embodiments, a surface of the protective layer close to the substrate is in contact with a surface of the cap layer away from the substrate, and some elements in the protective layer diffuse into the cap layer.

[0029] In some embodiments, a boundary of the protection layer away from the gate layer and a boundary of the cap layer overlap in a thickness direction of the substrate.

[0030] In some embodiments, the protection layer is also located on at least one side of the gate layer in a second direction, where the second direction is perpendicular to the first direction and parallel to the substrate.

[0031] In some embodiments, the protection layer is disposed around the gate layer.

[0032] In some embodiments, a dimension of the protection layer along a second direction is the same as a dimension of the capping layer along the second direction, the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

[0033] In some embodiments, the semiconductor device further comprises a passivation layer. The passivation layer covers the protective layer, two opposite sides of the cap layer along the first direction, a region between the cap layer and the source electrode, and a region between the cap layer and the drain electrode. The passivation layer is located on opposite sides of the gate layer along the first direction.

[0034] In some embodiments, the material of the passivation layer is different from the material of the protection layer.

[0035] In some embodiments, the material of the protection layer and the material of the passivation layer both include at least one of silicon nitride, silicon oxide, aluminum nitride, aluminum oxide, silicon oxynitride, and aluminum oxynitride.

[0036] In some embodiments, a size of the protective layer along the first direction is greater than or equal to 50 nm and less than or equal to 300 nm.

[0037] In some embodiments, a dimension of the protective layer along a third direction is greater than or equal to 5 nm and less than or equal to 30 nm; the third direction is a thickness direction of the substrate.

[0038] In some embodiments, the interface trap density of the capping layer is less than or equal to 1×10 12 cm -2 .

[0039] In some embodiments, the passivation layer includes a first portion covering the protection layer, and the gate layer further covers a surface of a side of the first portion of the passivation layer away from the substrate.

[0040] In another aspect, a chip is provided, wherein the chip includes the semiconductor device described in any one of the above embodiments.

[0041] In another aspect, an electronic device is provided, wherein the electronic device comprises a circuit board and a chip as described in any one of the above embodiments, wherein the chip is electrically connected to the circuit board.

[0042] It can be understood that the beneficial effects that can be achieved by the semiconductor devices, chips and electronic devices provided by the above embodiments of the present disclosure can refer to the beneficial effects of the method for preparing the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0044] Figure 1 is a schematic structural diagram of an electronic device according to some embodiments;

[0045] Figure 2 is a schematic diagram of the structure of a chip according to some embodiments;

[0046] Figure 3 A process for preparing a semiconductor device according to some embodiments Figure 1 ;

[0047] Figure 4 A process for preparing a semiconductor device according to some embodiments Figure 2 ;

[0048] Figure 5 for Figure 3 and Figure 4 A schematic structural diagram of a semiconductor device corresponding to step S1 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0049] Figure 6 for Figure 3 and Figure 4 A schematic structural diagram of a semiconductor device corresponding to step S2 and step S6 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0050] Figure 7 for Figure 3 and Figure 4 A schematic structural diagram of a semiconductor device corresponding to step S3 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0051] Figure 8 for Figure 3 and Figure 4 A schematic structural diagram of a semiconductor device corresponding to step S4 in the flowchart of the method for preparing a semiconductor device in FIG.

[0052] Fig. 9 for Figure 3 and Figure 4 A schematic structural diagram of a semiconductor device corresponding to step S5 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0053] Fig.10 for Figure 3 and Figure 4 A schematic structural diagram of a semiconductor device corresponding to step S11 and step S12 in the flowchart of the method for preparing a semiconductor device in FIG.

[0054] Fig.11is a schematic structural diagram of a contact interface between an initial protective layer and an initial capping layer, or a contact interface between a protective layer and a capping layer according to some embodiments;

[0055] Fig.12 for Figure 3 A schematic structural diagram of a semiconductor device corresponding to step S41 in the flowchart of the method for preparing a semiconductor device in FIG.

[0056] Fig.13 for Figure 4 A schematic structural diagram of a semiconductor device corresponding to step S42 and step S43 in the flowchart of the method for preparing a semiconductor device in FIG.

[0057] Fig.14 for Figure 3 and Figure 4 A schematic structural diagram of a semiconductor device corresponding to step S7 in the flowchart of the method for preparing a semiconductor device in FIG.

[0058] Fig.15 for Figure 3 and Figure 4 A schematic structural diagram of a semiconductor device corresponding to step S8 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0059] Fig.16 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 1 ;

[0060] Fig.17A Schematic diagram of a planar structure of a protection layer and a gate layer in a semiconductor device according to some embodiments Figure 1 ;

[0061] Fig. 17B Schematic diagram of a planar structure of a protection layer and a gate layer in a semiconductor device according to some embodiments Figure 2 ;

[0062] Fig. 17C Schematic diagram of a planar structure of a protection layer and a gate layer in a semiconductor device according to some embodiments Figure 3 ;

[0063] Fig.18A Schematic diagram of a planar structure of a protection layer and a cap layer in a semiconductor device according to some embodiments Figure 1 ;

[0064] Fig.18B Schematic diagram of a planar structure of a protection layer and a cap layer in a semiconductor device according to some embodiments Figure 2 ;

[0065] Fig.18C Schematic diagram of a planar structure of a protection layer and a cap layer in a semiconductor device according to some embodiments Figure 3 ;

[0066] Fig.19 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 2 .

[0067] Reference numerals:

[0068] 1000-electronic device; 100-chip; 200-circuit board; 10-semiconductor device; 1-substrate; 2-channel layer; 3-barrier layer; 4a-initial passivation layer; 4-passivation layer; 5a-initial capping layer; 5-capping layer; 6a-initial protective layer; 6b-transition protective layer; 6-protective layer; 7-nucleation layer; 8-buffer layer; 9-insertion layer; G-gate layer; S-source; D-drain; M1-first target region; M2 -second target region; M3 -third target region. DETAILED DESCRIPTION

[0069] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0070] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0071] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0072] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0073] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0074] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0075] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0076] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0077] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0078] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0079] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0080] The words "exemplary" or "for example" are used herein to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific way.

[0081] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0082] For the convenience of the following description, an XYZ coordinate system is established. The third direction Z is the thickness direction of the substrate 1, the XY plane is perpendicular to the third direction Z, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0083] like Figure 1 As shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include communication equipment (e.g., satellite communication equipment, wireless television receiver, etc.), radar equipment (e.g., millimeter wave radar, weather radar, etc.), radio navigation equipment (e.g., GPS receiver, etc.), etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device 1000.

[0084] In some embodiments, please refer to Figure 1 , the electronic device 1000 may include a chip 100 and a circuit board 200. The chip 100 and the circuit board 200 are electrically connected.

[0085] Exemplarily, the circuit board 200 in the electronic device 1000 may include a printed circuit board (PCB) or the like.

[0086] For example, the circuit board 200 in the electronic device 1000 may include a plurality of conductive layers. The plurality of conductive layers in the circuit board 200 may be separated from each other by a dielectric layer.

[0087] The chip 100 is described in detail below.

[0088] In some embodiments, Figure 2 As shown, Figure 2 FIG. 1 is a schematic structural diagram of a chip 100 according to some embodiments. The chip 100 includes a semiconductor device 10 .

[0089] Exemplarily, the chip 100 may include a processor chip. For example, the processor chip may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0090] The method for manufacturing the semiconductor device 10 is described in detail below.

[0091] In some embodiments, Figure 3 and Figure 4 As shown, Figure 3 and Figure 4 1 and 2 are flowcharts of methods for manufacturing a semiconductor device 10 according to some embodiments. It should be noted that: Figure 3 and Figure 4 The method for preparing the semiconductor device 10 shown in FIG. 1 is not exclusive and may also be Figure 3 and Figure 4 Other steps are performed before, after or between any steps in the method for manufacturing the semiconductor device 10. The method for manufacturing the semiconductor device 10 includes steps S1-S5.

[0092] S1: Figure 5 As shown, Figure 5 for Figure 3 and Figure 4Schematic diagram of the structure of the semiconductor device 10 corresponding to step S1 in the flowchart of the method for preparing the semiconductor device 10 in FIG. An initial cap layer 5a and an initial protective layer 6a are sequentially formed on one side of the substrate 1. The initial protective layer 6a covers a surface 5aa of the initial cap layer 5a away from the substrate 1.

[0093] By way of example, the material of the substrate 1 may include one of silicon (Si), silicon carbide (SiC), sapphire and the like.

[0094] S2: Figure 6 As shown, Figure 6 for Figure 3 and Figure 4 The schematic diagram of the structure of the semiconductor device 10 corresponding to step S2 and step S6 in the flowchart of the method for preparing the semiconductor device 10 in FIG. The initial cap layer 5a and the initial protective layer 6a of the first target area M1 and the second target area M2 are removed to form a cap layer 5 and a transition protective layer 6b. The transition protective layer 6b covers the side surface 5ab of the cap layer 5 away from the substrate 1.

[0095] For example, please refer to Figure 6 The initial capping layer 5a and the initial protective layer 6a of the first target area M1 and the second target area M2 can be removed by an etching process to form a capping layer 5 and a transition protective layer 6b.

[0096] S3: Figure 7 As shown, combined with Figure 6 , Figure 7 for Figure 3 and Figure 4 A schematic diagram of the structure of the semiconductor device 10 corresponding to step S3 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A source electrode S is formed in the first target region M1, and a drain electrode D is formed in the second target region M2. The source electrode S and the drain electrode D are located on opposite sides of the cap layer 5 along a first direction X, and the first direction X is parallel to the substrate 1.

[0097] Exemplarily, when a source S is formed in the first target area M1 and a drain D is formed in the second target area M2, a source-drain metal (e.g., titanium (Ti), aluminum (Al), titanium nitride (TiN), etc.) can be grown by a sputtering process, and the source-drain metal (e.g., titanium (Ti), aluminum (Al), titanium nitride (TiN), etc.) outside the first target area M1 and the second target area M2 can be removed by an etching process (e.g., a dry etching process), and then rapidly annealed in a nitrogen (N2) or argon (Ar) atmosphere to form a source S in the first target area M1 and a drain D in the second target area M2, respectively.

[0098] S4: Figure 8 As shown, combined with Figure 7 , Figure 8 for Figure 3 and Figure 4 The structural schematic diagram of the semiconductor device 10 corresponding to step S4 in the flowchart of the method for preparing the semiconductor device 10 in FIG. The transition protection layer 6 b of the third target area M3 is removed to form a protection layer 6. The protection layer 6 is located on the side of the cap layer 5 away from the substrate 1.

[0099] S5: Fig. 9 As shown, combined with Figure 8 , Fig. 9 for Figure 3 and Figure 4 A schematic diagram of the structure of the semiconductor device 10 corresponding to step S5 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A gate layer G is formed in the third target region M3. The gate layer G is located on the side of the cap layer 5 away from the substrate 1, and the protection layer 6 is located at least on two opposite sides of the gate layer G in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10).

[0100] Exemplarily, the material of the gate layer G may include at least one of conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0101] For example, the material of the gate layer G may include one of conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0102] For another example, the material of the gate layer G may include multiple (greater than or equal to two) conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0103] In the preparation method of the above-mentioned semiconductor device 10, an initial capping layer 5a and an initial protective layer 6a are first formed in sequence on one side of the substrate 1, and the initial protective layer 6a covers the surface 5aa of the initial capping layer 5a away from the substrate 1. Then, the initial capping layer 5a and the initial protective layer 6a of the first target area M1 and the second target area M2 are removed to form a capping layer 5 and a transition protective layer 6b. That is, before the initial capping layer 5a of the first target area M1 and the second target area M2 are removed to form the capping layer 5, the initial protective layer 6a is first formed on the side of the initial capping layer 5a away from the substrate 1, so that when the initial capping layer 5a of the first target area M1 and the second target area M2 are removed to form the capping layer 5, the initial protective layer 6a can protect the initial capping layer 5a.

[0104] For example, when the initial capping layer 5a of the first target area M1 and the second target area M2 is removed by an etching process to form the capping layer 5, it is usually necessary to coat the side of the initial capping layer 5a away from the substrate 1 with photoresist, and perform exposure and development steps. The initial protective layer 6a can isolate the initial capping layer 5a from organic materials such as photoresist, thereby preventing the initial capping layer 5a from being contaminated by organic materials such as photoresist, and further preventing the finally formed capping layer 5 from being contaminated by organic materials such as photoresist, which is beneficial to improving the stability and reliability of the capping layer 5, and further beneficial to improving the performance of the semiconductor device 10.

[0105] In some embodiments, please refer to Figure 3 and Figure 4 , step S1 (ie, sequentially forming an initial cap layer 5 a and an initial protection layer 6 a on one side of the substrate 1 ) in the method for preparing the semiconductor device 10 may include steps S11 - S12 .

[0106] S11: Fig.10 As shown, Fig.10 for Figure 3 and Figure 4 The schematic structural diagram of the semiconductor device 10 corresponding to step S11 and step S12 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0107] By way of example, the material of the initial capping layer 5 a may include p-type gallium nitride (p-GaN), which may be formed by doping elements such as magnesium (Mg) into gallium nitride (GaN) material.

[0108] For example, when doping elements such as magnesium (Mg) into gallium nitride (GaN) materials to form p-type gallium nitride (p-GaN), a gas-phase doping process or an ion implantation process may be used.

[0109] Understandably, please continue to refer to Fig.10 , and combined with Figure 6 In the case where the material of the initial capping layer 5a includes p-type gallium nitride (p-GaN), the material of the capping layer 5 formed by removing the initial capping layer 5a of the first target area M1 and the second target area M2 is the same as the material of the initial capping layer 5a, that is, the material of the capping layer 5 also includes p-type gallium nitride (p-GaN).

[0110] S12: Please continue reading Fig.10 , an initial protection layer 6a is in-situ grown on a side of the initial cap layer 5a away from the substrate 1 .

[0111] For example, the initial protection layer 6 a may be in-situ grown on a side of the initial cap layer 5 a away from the substrate 1 by at least one of a Metal Organic Chemical Vapor Deposition (MOCVD) process and a Molecular Beam Epitaxy (MBE) process.

[0112] Exemplarily, the material of the initial protection layer 6a may include an insulating material.

[0113] For example, the material of the preliminary protection layer 6 a may include at least one of silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), silicon oxynitride (SiON), and aluminum oxynitride (AION).

[0114] Understandably, please continue to refer to Fig.10 , and combined with Figure 6 and Figure 8 In the case where the material of the initial protective layer 6a includes an insulating material (for example, at least one of silicon nitride (Si3N4), silicon oxide (SiO2), aluminum nitride (AlN), aluminum oxide (Al2O3), silicon oxynitride (SiON), and aluminum oxynitride (AION)), the material of the transition protective layer 6b formed by removing the initial protective layer 6a of the first target area M1 and the second target area M2, and the material of the protective layer 6 formed by removing the transition protective layer 6b of the third target area M3 can be the same as the material of the initial protective layer 6a. That is, the material of the transition protective layer 6b and the material of the protective layer 6 can both include an insulating material (for example, at least one of silicon nitride (Si3N4), silicon oxide (SiO2), aluminum nitride (AlN), aluminum oxide (Al2O3), silicon oxynitride (SiON), and aluminum oxynitride (AION)).

[0115] For example, Fig.11 As shown, combined with Fig.10 , Fig.11Schematic diagram of the contact interface J1 between the initial protective layer 6a and the initial capping layer 5a, or the contact interface J2 between the protective layer 6 and the capping layer 5 according to some embodiments. In the case where the initial protective layer 6a is in-situ grown on the side of the initial capping layer 5a away from the substrate 1, some elements in the initial protective layer 6a may diffuse into the initial capping layer 5a (for example, when the material of the initial protective layer 6a includes at least one of silicon nitride (Si3N4), silicon oxide (SiO2) and silicon oxynitride (SiON), the silicon (Si) element in the initial protective layer 6a may diffuse into the initial capping layer 5a, and when the material of the initial protective layer 6a includes at least one of aluminum nitride (AlN), aluminum oxide (Al2O3) and aluminum oxynitride (AION), the aluminum (Al) element in the initial protective layer 6a may diffuse into the initial capping layer 5a), and an element diffusion region W is formed between the initial protective layer 6a and the initial capping layer 5a, which easily causes the contact interface J1 between the initial protective layer 6a and the initial capping layer 5a to be uneven.

[0116] Please continue reading Fig. 9 , Fig.10 and Fig.11 In the finally formed protective layer 6 and cap layer 5, the side surface 61a of the protective layer 6 close to the substrate 1 is in contact with the side surface 5ab of the cap layer 5 away from the substrate 1. When the contact interface J1 between the initial protective layer 6a and the initial cap layer 5a is uneven, the contact interface J2 between the protective layer 6 and the cap layer 5 is also uneven.

[0117] Please continue reading Fig.10 , and combined with Figure 6 In the preparation method of the semiconductor device 10, when the initial capping layer 5a and the initial protective layer 6a are sequentially formed on one side of the substrate 1, the initial protective layer 6a is in situ grown on the side of the initial capping layer 5a away from the substrate 1, so that the surface 5aa of the initial capping layer 5a away from the substrate 1 can be prevented from being oxidized by the air in the external environment, and the surface 5ab of the finally formed capping layer 5 away from the substrate 1 can be prevented from being oxidized by the air in the external environment, which is beneficial to improving the stability and reliability of the capping layer 5, and further beneficial to improving the performance of the semiconductor device 10.

[0118] In some embodiments, please refer to Figure 3 and Figure 4 After step S2 in the method for preparing the semiconductor device 10 (i.e., removing the initial cap layer 5a and the initial protective layer 6a of the first target area M1 and the second target area M2 to form the cap layer 5 and the transition protective layer 6b), the method for preparing the semiconductor device 10 further includes step S6.

[0119] S6: Please continue reading Figure 6 , the cap layer 5 is annealed.

[0120] Exemplarily, the temperature during the annealing treatment of the cap layer 5 may be greater than or equal to 300° C. and less than or equal to 1000° C.

[0121] For example, the temperature during the annealing treatment of the cap layer 5 may be 300° C., 400° C., 500° C., 600° C., 700° C., 800° C., 900° C., or 1000° C., etc.

[0122] Please continue reading Fig.10 In the method for preparing the semiconductor device 10, when the initial protective layer 6a is in-situ grown on the side of the initial capping layer 5a away from the substrate 1, the P-type impurities (e.g., magnesium (Mg) etc.) in the initial capping layer 5a may react with hydrogen atoms (H) to form compounds (e.g., magnesium hydride (MgH2) etc.), which may easily lead to the inactivation of the initial capping layer 5a and further the inactivation of the finally formed capping layer 5.

[0123] In this case, please continue to Figure 6 , and combined with Fig.10 In the preparation method of the semiconductor device 10, after removing the initial capping layer 5a and the initial protective layer 6a of the first target area M1 and the second target area M2 to form the capping layer 5 and the transition protective layer 6b, the formed capping layer 5 is annealed to allow the P-type impurities (e.g., magnesium (Mg) etc.) in the capping layer 5 to react with hydrogen atoms (H) to form compounds (e.g., magnesium hydride (MgH2) etc.) to undergo a decomposition reaction, so that the P-type impurities (e.g., magnesium (Mg) etc.) in the capping layer 5 can function again, thereby achieving the purpose of reactivating the capping layer 5.

[0124] In some embodiments, please refer to Figure 3 , step S4 (ie, removing the transition protection layer 6 b of the third target area M3 to form the protection layer 6 ) in the method for preparing the semiconductor device 10 may include step S41 .

[0125] S41: Fig.12 As shown, combined with Figure 7 , Fig.12 for Figure 3 The structural diagram of the semiconductor device 10 corresponding to step S41 in the flowchart of the method for preparing the semiconductor device 10 in FIG. 6 is formed by removing the transition protection layer 6 b of the third target area M3 through a wet etching process.

[0126] Alternatively, continue to Figure 4 , step S4 (ie, removing the transition protection layer 6 b of the third target area M3 to form the protection layer 6 ) in the method for preparing the semiconductor device 10 may include step S42 and step S43 .

[0127] S42: Fig.13 As shown, Fig.13 for Figure 4 A schematic diagram of the structure of the semiconductor device 10 corresponding to step S42 and step S43 in the flowchart of the method for preparing the semiconductor device 10 in FIG. From a side surface 6ba of the transition protection layer 6b away from the substrate 1, along the third direction (i.e., the thickness direction of the substrate 1) Z, a portion of the transition protection layer 6b in the third target area M3 is removed by a dry etching process.

[0128] S43: Please continue reading Fig.13 , the remaining transition protection layer 6 b of the third target area M3 is removed by a wet etching process to form a protection layer 6 .

[0129] Illustratively, when the transition protective layer 6 b of the third target area M3 is removed by a wet etching process to form the protective layer 6, or when the remaining transition protective layer 6 b of the third target area M3 is removed by a wet etching process to form the protective layer 6, a mixed solution of concentrated sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), and dilute hydrochloric acid (HCl) can be used as etching solutions, respectively, to alternately etch the transition protective layer 6 b of the third target area M3 to remove the transition protective layer 6 b of the third target area M3 and form the protective layer 6.

[0130] Please continue reading Fig.12 and Fig.13 When the transition protective layer 6b of the third target area M3 is removed by a wet etching process to form the protective layer 6, or when a portion of the transition protective layer 6b of the third target area M3 is first removed by a dry etching process and then the remaining transition protective layer 6b of the third target area M3 is removed by a wet etching process to form the protective layer 6, a portion of the transition protective layer 6b of the third target area M3 close to the cap layer 5 is removed by the wet etching process. The wet etching process mainly relies on the chemical reaction between chemical reagents and the etched material (i.e., the transition protection layer 6b of the third target area M3). This chemical reaction is usually carried out under relatively mild conditions. Therefore, in the process of removing the transition protection layer 6b of the third target area M3 to form the protective layer 6, when etching to the contact interface between the transition protection layer 6b and the cap layer 5, compared with the physical bombardment of the side surface 5ab of the cap layer 5 away from the substrate 1 by high-energy plasma in the dry etching process, the wet etching process causes less physical damage to the side surface 5ab of the cap layer 5 away from the substrate 1, and is beneficial to reducing the interface trap density of the cap layer 5.

[0131] For example, please refer to Fig.12 and Fig.13 , and combined with Figure 3 and Figure 4When the transition protection layer 6b of the third target region M3 is removed by a wet etching process to form the protection layer 6, or when a portion of the transition protection layer 6b of the third target region M3 is first removed by a dry etching process and then the remaining transition protection layer 6b of the third target region M3 is removed by a wet etching process to form the protection layer 6, the interface trap density of the cap layer 5 can be less than or equal to 1×10 12 cm -2 .

[0132] In some embodiments, please refer to Figure 3 and Figure 4 Before step S3 (i.e., forming a source electrode S in the first target region M1 and forming a drain electrode D in the second target region M2) in the method for preparing the semiconductor device 10, the method for preparing the semiconductor device 10 further includes step S7. Between step S3 (i.e., forming a source electrode S in the first target region M1 and forming a drain electrode D in the second target region M2) and step S4 (i.e., removing the transition protection layer 6b of the third target region M3 to form a protection layer 6) in the method for preparing the semiconductor device 10, the method for preparing the semiconductor device 10 further includes step S8.

[0133] S7: Fig.14 As shown, Fig.14 for Figure 3 and Figure 4 A schematic diagram of the structure of the semiconductor device 10 corresponding to step S7 in the flowchart of the method for preparing the semiconductor device 10 in FIG. An initial passivation layer 4a is formed. The initial passivation layer 4a covers the transition protection layer 6b and two opposite side surfaces of the cap layer 5 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, and the initial passivation layer 4a is also located in the first target area M1, the area between the cap layer 5 and the first target area M1, the second target area M2, and the area between the cap layer 5 and the second target area M2.

[0134] S8: Fig.15 As shown, Fig.15 for Figure 3 and Figure 4 The initial passivation layer 4a of the third target area M3 is removed to form a passivation layer 4.

[0135] Exemplarily, the initial passivation layer 4 a of the third target region M3 may be removed by an etching process to form the passivation layer 4 .

[0136] For example, the initial passivation layer 4 a of the third target region M3 may be removed by a dry etching process to form the passivation layer 4 .

[0137] Exemplarily, the material of the initial passivation layer 4 a and the material of the transition protection layer 6 b are different.

[0138] For example, the material of the initial passivation layer 4 a may include at least one of silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), silicon oxynitride (SiON), aluminum oxynitride (AION), and the like.

[0139] Please continue reading Fig.12 , Fig.13 and Fig.15 By making the material of the initial passivation layer 4a and the material of the transition protection layer 6b different, a higher etching selectivity ratio is achieved between the material of the initial passivation layer 4a and the material of the transition protection layer 6b. When the initial passivation layer 4a of the third target area M3 is removed to form the passivation layer 4, the etching can be stopped at the side of the transition protection layer 6b away from the substrate 1. This makes it easier to change the etching process parameters or the etching process type when the transition protection layer 6b of the third target area M3 is removed by an etching process to form the protection layer 6.

[0140] Understandably, please continue to refer to Fig.12 , Fig.13 and Fig.15 Since the material of the protective layer 6 formed by removing the transition protective layer 6b of the third target area M3 is the same as the material of the transition protective layer 6b, and the material of the passivation layer 4 formed by removing the initial passivation layer 4a of the third target area M3 is the same as the material of the initial passivation layer 4a, when the material of the initial passivation layer 4a is different from the material of the transition protective layer 6b, the material of the passivation layer 4 is also different from the material of the protective layer 6.

[0141] For example, the material of the transition protection layer 6 b may include silicon nitride, and the material of the initial passivation layer 4 a may include aluminum nitride.

[0142] In the case where the material of the transition protection layer 6b includes silicon nitride and the material of the initial passivation layer 4a includes aluminum nitride, the material of the protection layer 6 includes silicon nitride and the material of the passivation layer 4 includes aluminum nitride.

[0143] For example, the initial passivation layer 4 a may be formed by at least one of a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, and an atomic layer deposition (ALD) process.

[0144] Exemplarily, the initial passivation layer 4a may be a single-layer structure, that is, along the third direction (ie, the thickness direction of the substrate 1 ) Z, the initial passivation layer 4a includes a film layer structure.

[0145] Alternatively, the initial passivation layer 4a may also be a multi-layer (greater than or equal to two layers) structure, that is, along the third direction (ie, the thickness direction of the substrate 1) Z, the initial passivation layer 4a includes a multi-layer (greater than or equal to two layers) film structure.

[0146] For example, the initial passivation layer 4 a may be a two-layer structure, that is, along the third direction (ie, the thickness direction of the substrate 1 ) Z, the initial passivation layer 4 a may include a silicon oxide (SiO 2 ) layer and an aluminum nitride (AlN) layer.

[0147] Understandably, please continue to refer to Fig.15 , and combined with Fig.14 , the film structure of the passivation layer 4 formed by removing the initial passivation layer 4a of the third target area M3 is the same as the film structure of the initial passivation layer 4a. That is, when the initial passivation layer 4a is a single-layer structure, the passivation layer 4 is also a single-layer structure. When the initial passivation layer 4a is a multi-layer (greater than or equal to two-layer) structure, the passivation layer 4 is also a multi-layer (greater than or equal to two-layer) structure.

[0148] The semiconductor device 10 manufactured by the method for manufacturing the semiconductor device 10 described above will be described in detail below.

[0149] In some embodiments, Fig.16 As shown, Fig.16 : is a cross-sectional schematic diagram of a semiconductor device 10 according to some embodiments. The semiconductor device includes a substrate 1, a cap layer 5, a gate layer G, a protective layer 6, a source S and a drain D. The cap layer 5 is disposed on one side of the substrate 1. The gate layer G is disposed on a side of the cap layer 5 away from the substrate 1. The protective layer 6 is at least located on two opposite sides of the gate layer G in a first direction, and is disposed on a side of the cap layer 5 away from the substrate 1, and the first direction is parallel to the substrate 1. The source S and the drain D are located on two opposite sides of the cap layer 5 along the first direction.

[0150] By making the protective layer 6 at least located on two opposite sides of the gate layer G in the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and being arranged on the side of the cap layer 5 away from the substrate 1, it can play the role of passivating the portion of the cap layer 5 that has no contact with the gate layer G, which is beneficial to reducing the interface state of the semiconductor device 10, and further beneficial to achieving the flattening of the electric field in the gate region, thereby beneficial to improving the breakdown characteristics of the semiconductor device 10, and beneficial to improving the reliability of the semiconductor device 10.

[0151] For example, please refer to Fig.16, a dimension d6 of the protection layer 6 along the first direction (ie, the arrangement direction of the source S and the drain D in the semiconductor device 10 ) X is greater than or equal to 50 nm and less than or equal to 300 nm.

[0152] For example, a dimension d6 of the protective layer 6 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X can be 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm or 300 nm, etc.

[0153] For example, please refer to Fig.16 , a dimension L6 of the protective layer 6 along the third direction (ie, the thickness direction of the substrate 1 ) Z is greater than or equal to 5 nm and less than or equal to 100 nm.

[0154] For example, the dimension L6 of the protective layer 6 along the third direction (i.e., the thickness direction of the substrate 1) Z can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm or 100 nm, etc.

[0155] For example, Fig.17A As shown, Fig.17A Schematic diagram of the planar structure of the protection layer 6 and the gate layer G in the semiconductor device 10 according to some embodiments. The protection layer 6 may be located on two opposite sides of the gate layer G in the first direction (ie, the arrangement direction of the source S and the drain D in the semiconductor device 10).

[0156] Or, if Fig. 17B and Fig. 17C As shown, Fig. 17B and Fig. 17C All of them are schematic diagrams of the planar structure of the protection layer 6 and the gate layer G in the semiconductor device 10 according to some embodiments. On the basis that the protection layer 6 is located on two opposite sides of the gate layer G in the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, the protection layer 6 can also be located on at least one side of the gate layer G in the second direction Y, the second direction Y is perpendicular to the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, and the second direction Y is parallel to the substrate 1.

[0157] For example, see Fig. 17BOn the basis that the protection layer 6 is located on two opposite sides of the gate layer G in the first direction X (ie, the arrangement direction of the source S and the drain D in the semiconductor device 10 ), the protection layer 6 can also be located on one side of the gate layer G in the second direction Y.

[0158] For another example, please continue to see Fig. 17C On the basis that the protection layer 6 is located on two opposite sides of the gate layer G in the first direction X (ie, the arrangement direction of the source S and the drain D in the semiconductor device 10 ), the protection layer 6 can also be located on two opposite sides of the gate layer G in the second direction Y.

[0159] Understandably, please continue to refer to Fig. 17C When the protection layer 6 is located on two opposite sides of the gate layer G in a first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and on two opposite sides of the gate layer G in a second direction Y, the protection layer 6 is arranged around the gate layer G.

[0160] For example, Fig.18A , Fig.18B and Fig.18C As shown, combined with Fig.17A , Fig. 17B and Fig. 17C , Fig.18A , Fig.18B and Fig.18C 1 and 2 are schematic diagrams of the planar structures of the protection layer 6 and the cap layer 5 in the semiconductor device 10 according to some embodiments. Fig.18A , Fig.18B and Fig.18C The difference is that Fig.18A The middle protection layer 6 is located at two opposite sides of the gate layer G in a first direction X (ie, an arrangement direction of the source S and the drain D in the semiconductor device 10 ). Fig.18B The middle protection layer 6 is located on two opposite sides of the gate layer G in a first direction X (ie, the arrangement direction of the source S and the drain D in the semiconductor device 10 ) and on one side of the gate layer G in a second direction Y. Fig.18C The middle protection layer 6 is located on two opposite sides of the gate layer G in a first direction X (ie, the arrangement direction of the source S and the drain D in the semiconductor device 10 ) and on two opposite sides of the gate layer G in a second direction Y.

[0161] The dimension h6 of the protection layer 6 along the second direction Y is the same as the dimension h5 of the cap layer 5 along the second direction Y. The second direction Y is perpendicular to the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10 ), and the second direction Y is parallel to the substrate 1 .

[0162] It should be noted that the dimension h6 of the protective layer 6 along the second direction Y is the same as the dimension h5 of the cap layer 5 along the second direction Y, which means that the difference between the dimension h6 of the protective layer 6 along the second direction Y and the dimension h5 of the cap layer 5 along the second direction Y is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range can be a process accuracy range when forming the protective layer 6 and the cap layer 5 with the same dimension along the second direction Y.

[0163] When the dimension h6 of the protective layer 6 along the second direction Y is the same as the dimension h5 of the cap layer 5 along the second direction Y, the threshold range of the difference between the dimension h6 of the protective layer 6 along the second direction Y and the dimension h5 of the cap layer 5 along the second direction Y can be 0~0.1μm.

[0164] For example, when the dimension h6 of the protective layer 6 along the second direction Y is the same as the dimension h5 of the cap layer 5 along the second direction Y, the difference between the dimension h6 of the protective layer 6 along the second direction Y and the dimension h5 of the cap layer 5 along the second direction Y can be 0, 0.01μm, 0.03μm, 0.05μm, 0.06μm, 0.08μm or 0.1μm, etc.

[0165] For example, please refer to Fig.16 , a boundary 6 m of the protection layer 6 away from the gate layer G and a boundary 5 m of the cap layer 5 overlap in the third direction Z (ie, the thickness direction of the substrate 1 ).

[0166] In some embodiments, please refer to Fig.16 The semiconductor device 10 may further include a channel layer 2. The channel layer 2 may be disposed on a side of the cap layer 5 in the semiconductor device 10 close to the substrate 1.

[0167] Exemplarily, the material of the channel layer 2 may include gallium nitride (GaN).

[0168] For example, the channel layer 2 may be formed by a process such as a Metal-organic Chemical Vapor Deposition (MOCVD) process, a Molecular Beam Epitaxy (MBE) process, or a Physical Vapor Deposition (PVD) process.

[0169] In some embodiments, please refer to Fig.16 The semiconductor device 10 may further include a barrier layer 3 . The barrier layer 3 may be disposed between the channel layer 2 and the cap layer 5 .

[0170] For example, the material of the barrier layer 3 may include a plurality of nitride Alx In y Ga (1-x-y) N, at least one of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0171] For example, the material of the barrier layer 3 may include nitrides of various different components, such as Al x In y Ga (1-x-y) N, one of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0172] Again for example, the material of the barrier layer 3 may include multiple (greater than or equal to two) nitrides of various different components, such as Al x In y Ga (1-x-y) N, (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0173] Exemplarily, the barrier layer 3 can be formed by processes such as Metal-organic Chemical Vapor Deposition (MOCVD) process, Molecular Beam Epitaxy (MBE) process, or Physical Vapor Deposition (PVD) process.

[0174] When the barrier layer 3 in the semiconductor device 10 is disposed between the channel layer 2 and the capping layer 5, and the band gap of the material of the barrier layer 3 (e.g., aluminum gallium nitride (AlGaN)) is greater than the band gap of the material of the channel layer 2 (e.g., gallium nitride (GaN)), due to the different electron affinities and work functions of the material of the barrier layer 3 (e.g., aluminum gallium nitride (AlGaN)) and the material of the channel layer 2 (e.g., gallium nitride (GaN)), a heterojunction structure will be formed at the interface between the barrier layer 3 and the channel layer 2. This heterojunction structure will cause the energy band structure of the channel layer 2 to bend, and then a potential well will be formed in the channel layer 2. To balance the charge distribution at the interface between the barrier layer 3 and the channel layer 2, the electrons in the barrier layer 3 will transfer to the potential well in the channel layer 2. The potential well in the channel layer 2 can restrict the electrons, enabling the electrons to move freely only in the direction parallel to the interface between the barrier layer 3 and the channel layer 2, thereby inducing the formation of a two-dimensional electron gas (2DEG) near the interface between the barrier layer 3 and the channel layer 2, which is beneficial to improving the electron mobility and enhancing the performance of the semiconductor device 10.

[0175] It should be noted that the above-mentioned band gap refers to the fact that the energy of electrons in solids cannot take continuous values, but forms some discontinuous energy bands, among which the energy difference between the conduction band and the valence band is the band gap. Specifically, for bound electrons to become free electrons or holes, they must obtain enough energy to jump from the valence band to the conduction band, and the minimum value of this energy is the band gap.

[0176] For example, please refer to Fig.16 In the case where a two-dimensional electron gas (2DEG) is formed in the semiconductor device 10 , the semiconductor device 10 may be used to form a high electron mobility transistor (HEMT).

[0177] For example, please refer to Fig.16 In the case where a two-dimensional electron gas (2DEG) is formed in the semiconductor device 10, the source S and the drain D in the semiconductor device 10 can form an ohmic contact with the two-dimensional electron gas (2DEG), which can reduce the contact resistance between the source S in the semiconductor device 10 and the two-dimensional electron gas (2DEG), and the contact resistance between the drain D in the semiconductor device 10 and the two-dimensional electron gas (2DEG), and can form a low-impedance current channel between the source S, the drain D and the two-dimensional electron gas (2DEG) in the semiconductor device 10, so that the current can flow smoothly, which is beneficial to improving the performance of the semiconductor device 10.

[0178] For example, please refer to Fig.16In the case where two-dimensional electron gas (2DEG) is formed in the semiconductor device 10, by making the material of the cap layer 5 include p-type gallium nitride (p-GaN), on the one hand, an energy band difference (for example, conduction band difference) can be made between the cap layer 5 and the barrier layer 3, and the energy band difference (for example, conduction band difference) between the cap layer 5 and the barrier layer 3 can be used to regulate the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 3 and the channel layer 2, which is beneficial to depleting the two-dimensional electron gas (2DEG) under the cap layer 5, thereby enabling the semiconductor device 10 to achieve an enhanced operating mode.

[0179] On the other hand, due to the depletion effect of the cap layer 5 in the semiconductor device 10 on the two-dimensional electron gas (2DEG) located below the cap layer 5, the semiconductor device 10 needs to overcome a higher potential barrier when turned on, which is beneficial to increasing the threshold voltage of the semiconductor device 10.

[0180] In some embodiments, please refer to Fig.16 The semiconductor device 10 may further include a passivation layer 4. The passivation layer 4 is located on two opposite sides of the gate layer G along a first direction X (ie, an arrangement direction of the source S and the drain D in the semiconductor device 10).

[0181] The passivation layer 4 covers the protective layer 6, two opposite side surfaces of the cap layer 5 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, the area between the cap layer 5 and the source S, and the area between the cap layer 5 and the drain D.

[0182] Exemplarily, a boundary 6 n of the protection layer 6 close to the gate layer G and a boundary 4 n of the passivation layer 4 close to the gate layer G overlap in the third direction Z (ie, the thickness direction of the substrate 1 ).

[0183] Exemplarily, the passivation layer 4 includes a first portion 41 covering the protection layer 6 , and the gate layer G further covers a surface of the first portion 41 of the passivation layer 4 that is away from the substrate 1 .

[0184] In some embodiments, Fig.19 As shown, Fig.19 is a cross-sectional schematic diagram of a semiconductor device 10 according to some embodiments. The semiconductor device 10 may further include a nucleation layer 7 and a buffer layer 8 located between the substrate 1 and the channel layer 2 , and an insertion layer 9 located between the channel layer 2 and the barrier layer 3 .

[0185] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A cap layer is disposed on one side of the substrate; the material of the cap layer includes P-type impurities; A gate layer, disposed on a side of the cap layer away from the substrate; A protective layer is at least located on two opposite sides of the gate layer in a first direction and is arranged on a side of the cap layer away from the substrate, the first direction is parallel to the substrate; a surface of the protective layer close to the substrate is in contact with a surface of the cap layer away from the substrate, and an element diffusion region exists between the protective layer and the cap layer; The source electrode and the drain electrode are located on opposite sides of the cap layer along the first direction.

2. The semiconductor device according to claim 1, wherein: A boundary of the protection layer on a side away from the gate layer and a boundary of the cap layer overlap in a thickness direction of the substrate.

3. The semiconductor device according to claim 1, wherein: The protection layer is also located on at least one side of the gate layer in a second direction; the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

4. The semiconductor device according to claim 3, characterized in that The protection layer is disposed around the gate layer.

5. The semiconductor device according to claim 1, wherein: The dimension of the protection layer along the second direction is the same as the dimension of the cap layer along the second direction; the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

6. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a passivation layer, wherein the passivation layer covers the protection layer, two opposite side surfaces of the cap layer along the first direction, a region between the cap layer and the source electrode, and a region between the cap layer and the drain electrode; The passivation layer is located at two opposite sides of the gate layer along the first direction.

7. The semiconductor device according to claim 6, characterized in that The material of the passivation layer is different from the material of the protection layer.

8. The semiconductor device according to claim 7, characterized in that The material of the protection layer and the material of the passivation layer both include at least one of silicon nitride, silicon oxide, aluminum nitride, aluminum oxide, silicon oxynitride, and aluminum oxynitride.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: A size of the protection layer along the first direction is greater than or equal to 50 nm and less than or equal to 300 nm.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that: The dimension of the protective layer along the third direction is greater than or equal to 5 nm and less than or equal to 30 nm; the third direction is the thickness direction of the substrate.

11. The semiconductor device according to any one of claims 1 to 8, characterized in that: The interface trap density of the capping layer is less than or equal to 1×10 12 cm -2 .

12. The semiconductor device according to any one of claims 6 to 8, characterized in that: The passivation layer includes a first portion covering the protection layer, and the gate layer further covers a surface of a side of the first portion of the passivation layer away from the substrate.

13. A method for preparing a semiconductor device, characterized in that: include: forming an initial capping layer on one side of the substrate; In-situ growing an initial protective layer on a side of the initial cap layer away from the substrate; The initial capping layer and the initial protective layer of the first target region and the second target region are removed to form a capping layer and a transition protective layer; the transition protective layer covers a surface of the capping layer away from the substrate; the material of the capping layer includes P-type impurities; forming a source electrode in the first target region and forming a drain electrode in the second target region; the source electrode and the drain electrode are located at opposite sides of the cap layer along a first direction, and the first direction is parallel to the substrate; The transition protection layer in the third target area is removed to form a protection layer; the protection layer is located on a side of the cap layer away from the substrate; a surface of the protection layer close to the substrate is in contact with a surface of the cap layer away from the substrate, and an element diffusion region exists between the protection layer and the cap layer; A gate layer is formed in the third target region; the gate layer is located on a side of the cap layer away from the substrate, and the protection layer is at least located on two opposite sides of the gate layer in the first direction.

14. The method for preparing a semiconductor device according to claim 13, characterized in that: After removing the initial capping layer and the initial protective layer in the first target area and the second target area to form a capping layer and a transition protective layer, the preparation method further comprises: The cap layer is subjected to annealing treatment.

15. The method for preparing a semiconductor device according to claim 13 or 14, characterized in that: The step of removing the transition protection layer in the third target area to form a protection layer includes: The transition protection layer in the third target area is removed by a wet etching process to form a protection layer.

16. The method for preparing a semiconductor device according to claim 13 or 14, characterized in that: The step of removing the transition protection layer in the third target area to form a protection layer includes: From a surface of the transition protection layer on one side away from the substrate, along a third direction, removing a portion of the transition protection layer in a third target area by a dry etching process; the third direction is a thickness direction of the substrate; The remaining transition protection layer in the third target area is removed by a wet etching process to form a protection layer.

17. The method for preparing a semiconductor device according to claim 13 or 14, characterized in that: Before forming a source electrode in the first target region and forming a drain electrode in the second target region, the preparation method further includes: forming an initial passivation layer; the initial passivation layer covers the transition protection layer and two opposite sides of the cap layer along the first direction, and the initial passivation layer is also located in the first target area, the area between the cap layer and the first target area, the second target area, and the area between the cap layer and the second target area; Between forming a source electrode in the first target region, forming a drain electrode in the second target region, and removing the transition protection layer in the third target region to form a protection layer, the preparation method further comprises: The initial passivation layer in the third target area is removed to form a passivation layer.

18. A chip, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 12.

19. An electronic device, characterized in that: include: Circuit boards; The chip as claimed in claim 18, wherein the chip is electrically connected to the circuit board.

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