Wiring and passive component in direct bonding layer

Abstract

The invention relates to wiring and passive components in a direct bonding layer. Integrated circuit devices are described herein that include conductive structures formed by direct bonding of different components (e.g., direct bonding of two dies or direct bonding of a die to a wafer). A conductive structure is formed from the top metallization layer of each of the features. For example, the elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high frequency and / or high power signals. In another example, the bonded conductive structure may form a radio frequency passive device, such as an inductor or transformer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of integrated circuit (IC) structures and devices, and more particularly to conductive structures in multi-die IC packages. Background Art

[0002] Multi-die chips are increasingly being used in high-performance computing systems. In a multi-die package, several dies are mounted together in a larger die or interposer. One way to combine dies is to use copper bonding, also known as hybrid bonding or direct bonding. This technique uses the top metal layer at the face of each die to provide bonding pads, and then mounts the dies face to face. When the dies are bonded using the top layer of the die, the routing area within each die is reduced because the top layer is only used to provide pads to interconnect the dies, not to route signals within each die.

[0003] In an IC die, the top two or three layers of the die are typically thicker than the rest of the metal stack. These thick layers can be used for radio frequency (RF) systems and high-speed and high-power routing. In addition, passive components such as inductors or transmission lines achieve better performance in thicker layers than in lower, thinner layers due to the lower resistance of thicker metal lines. Using thick top layers for die-to-die bonding limits the area available for RF components and high-power and high-speed routing. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments will be easily understood according to the following detailed description in conjunction with the accompanying drawings. For ease of description, the same reference numerals represent the same structural elements. In the figures of the accompanying drawings, various embodiments are shown by way of example and not limitation.

[0005] Figure 1A is a cross section showing a die coupled to another die at a direct bonding interface according to some embodiments of the present disclosure.

[0006] Figure 1B is a cross section showing a die coupled to a wafer at a direct bonding interface according to some embodiments of the present disclosure.

[0007] Figure 2A and Figure 2B are two cross sections of exemplary direct bonding for routing or passive components according to some embodiments of the present disclosure.

[0008] Figures 3A-3C are three cross sections of exemplary direct bonding according to some embodiments of the present disclosure, where the metal includes an offset hole.

[0009] Figures 4A-4C are three cross sections of exemplary direct bonds according to some embodiments of the present disclosure, wherein electrical signals are passed between and along two components.

[0010] Figure 5A and Figure 5B sectional and perspective views, respectively, of a conductive path extending between a bonding layer and a lower metal layer of one of the components according to some embodiments of the present disclosure.

[0011] Figure 6 is a perspective view of an inductor partially formed within a direct bonding interface according to some embodiments of the present disclosure.

[0012] Fig. 7A and Figure 7B is a top view of a wafer and die according to any embodiment disclosed herein, which may include a direct bonding interface in combination with wiring or passive devices.

[0013] Figure 8 is a cross-sectional side view of an IC device that may form a portion of a die or other component bonded to another component in a direct bonding interface incorporating wiring or passive devices according to any embodiment disclosed herein.

[0014] Fig. 9 is a cross-sectional side view of an IC device assembly that may include a direct bonding interface in combination with wiring or passive devices according to any embodiment disclosed herein.

[0015] Fig.10 is a block diagram of an example computing device that may include a direct bonding interface in combination with wiring or passive devices in accordance with any embodiment disclosed herein. DETAILED DESCRIPTION

[0016] Overview

[0017] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein.The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0018] Direct bonding has recently attracted attention for coupling microelectronic components (e.g., two dies, or a die and one of a packaging substrate, circuit board, or interposer). As used herein, the term "direct bonding" is used to include metal-metal bonding techniques (e.g., copper-copper bonding, or other techniques in which direct bonding contacts (DB contacts) of opposing direct bonding interfaces (DB interfaces) are first contacted and then subjected to heating and compression) and hybrid bonding techniques (e.g., techniques in which direct bonding dielectrics (DB dielectrics) of opposing DB interfaces that may first be subjected to previous surface activation are first contacted and then subjected to heating and sometimes compression, or techniques in which DB contacts and DB dielectrics of opposing DB interfaces (which may first be subjected to previous surface activation) are contacted substantially simultaneously and subjected to heating and sometimes compression). The materials of the opposing DB dielectrics may be homogeneous (i.e., having substantially the same material composition) or non-homogeneous (i.e., having different material compositions). In such techniques, a DB contact and a DB dielectric at one DB interface (e.g., at a DB interface of a first microelectronic component) are contacted with a DB contact and a DB dielectric at another DB interface (e.g., at a DB interface of a second microelectronic component), respectively, and elevated pressure and / or temperature may be applied to engage the contacting DB contacts and / or contacting DB dielectrics.

[0019] The DB contact is typically a bonding pad that can have a square or circular shape when viewed from the face of the IC component. For example, the DB pad is typically a copper post formed in a dielectric. The bonding pad provides signal and / or power connections between components that meet at the DB interface. For example, each bonding pad can be coupled to one or more interconnects in the lower metal layer in each component.

[0020] Direct bonding can provide significant advantages over conventional coupling techniques such as solder-based interconnects or wire bonding. Direct bond interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, some conventional solder interconnects may form large amounts of brittle intermetallic compounds when current flows, and the maximum current provided through such an interconnect may be constrained to mitigate mechanical failure.

[0021] Direct bonding uses the top metal layer at the face of each component to provide DB contacts. In a single die package, the top metal layer is typically used for routing within the die and / or for RF components, such as inductors, transformers, filters, etc. As described above, in an IC die, the top or top layers of the die are typically thicker than the layers in the rest of the metal stack, which makes these upper layers particularly suitable for RF components and high-speed and high-power routing. By using the top metal layer to provide DB contacts instead of for routing or RF components, the space available for these structures in the die is reduced.

[0022] As described herein, instead of using a bonding pad (e.g., a columnar pad) to provide a direct engagement of a conductive structure, a DB contact can be an elongated conductive structure extending along the plane of a DB interface. These elongated DB contacts are also referred to herein as interconnects, DB interconnects, conductive structures, or DB conductive structures. The DB interconnects can be substantially overlapped, thereby providing a wiring path with a large cross-section at the bonding interface (e.g., twice the height of the wiring path in the top layer, because the wiring path is formed from the top layer of each die). High-speed and / or high-power wiring will benefit from the extra thickness and reduced resistance of the bonding trace. In other examples, the DB interconnects can be partially overlapped structures, in which the conductive path can extend back and forth between two components. The DB interconnects (or more generally, the DB conductive structure) can be used to form various types of transmission lines, including coplanar waveguides or microstrips. In some embodiments, the DB conductive structure can form an RF passive device within the bonding interface or partially within the bonding interface. For example, the DB conductive structure for connecting two dies can be shaped to form an inductor, a transformer, or a passive filter.

[0023] In the following detailed description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

[0024] For example, the term "interconnect" can be used to describe any element formed by a conductive material for providing an electrical connection to one or more components associated with an IC and / or an electrical connection between various such components. Typically, the term "interconnect" can refer to electrical traces (sometimes also referred to as "wires" or "trench contacts") and conductive vias. Generally speaking, in the context of interconnection, the term "conductive trace" can be used to describe a conductive element isolated by an insulator material (e.g., a low-k dielectric material) provided in the plane of an IC die. These traces are typically stacked into several levels or several layers of a metallization stack. On the other hand, the term "via" can be used to describe a conductive element that interconnects two or more traces of different levels. To this end, a via substantially perpendicular to the plane of the IC die can be provided, and the via can interconnect two traces in adjacent levels or two traces in non-adjacent levels. The term "metallization stack" can be used to refer to one or more interconnected stacks for providing connections to different circuit components of an IC chip. Sometimes, traces and vias may be referred to as "conductive traces" and "conductive vias," respectively, to emphasize the fact that these elements include conductive materials such as metals.

[0025] The interconnects as described herein, and in particular the interconnects formed at the bonding layers as described herein, can be used to provide connections to one or more components associated with an IC or / and connections between various such components, wherein, in various embodiments, the components associated with the IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, transformers, sensors, transceivers, receivers, antennas, etc. The components associated with the IC may include components mounted on the IC or components connected to the IC. The IC may be analog or digital and may be used in many applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be used as part of a chipset for performing one or more related functions in a computer.

[0026] In another example, the terms "package" and "IC package" are synonymous, the terms "die" and "IC die" are also synonymous, and unless otherwise specified, the term "insulation" means "electrical insulation", and the term "conduction" means "conductive conduction". In addition, the term "connected" may be used to describe a direct electrical or magnetic connection between connected objects without any intermediate devices, while the term "coupled" may be used to describe a direct electrical or magnetic connection between connected objects, or an indirect connection through one or more passive or active intermediate devices. The term "circuit" may be used to describe one or more passive and / or active components that are arranged to cooperate with each other to provide a desired functionality.

[0027] For the purpose of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without the specific details, or / and may be practiced with only some of the described aspects. In other cases, well-known features are omitted or simplified so as not to obscure the illustrative embodiments.

[0028] In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed in a limiting sense. For convenience, if there is a collection of drawings that are designated by different letters, e.g. Figure 1A-1B , then such a set may be referred to herein without a letter, e.g., “Figure 1”.

[0029] The various operations may be described in turn as a plurality of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0030] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). When used with reference to a measurement range, the term "between" includes the endpoints of the measurement range. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0031] This specification uses the phrases "in one embodiment" or "in an embodiment", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. as used with respect to the embodiments of the present disclosure are synonymous. The present disclosure may use perspective-based descriptions, such as "above", "below", "top", "bottom", and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. The terms "substantially", "close", "approximately", "close to", and "approximately" generally refer to within + / -20% of a target value. Unless otherwise specified, the use of ordinal adjectives "first", "second", and "third", etc. to describe common objects only indicates that different instances of similar objects are being referenced, and it is not intended to imply that the objects described in this way must be in a given sequence in time, space, order, or in any other way.

[0032] In the following detailed description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the essence of their work to other technicians in the field. For example, as used herein, the "logical state" of a ferroelectric memory cell refers to one of a finite number of states that the cell can have, such as logical states "1" and "0", each state represented by a different polarization of the ferroelectric material of the cell. In another example, as used herein, "read" and "write" memory access or operations refer to determining / sensing the logical state of a memory cell and programming / setting the logical state of a memory cell, respectively. In other examples, the term "connection" means a direct electrical connection or magnetic connection between objects connected without any intermediate devices, while the term "coupling" means a direct electrical connection or magnetic connection between connected objects or an indirect connection through one or more passive or active intermediate devices. The term "circuit" means one or more passive and / or active components arranged to cooperate with each other to provide a desired function. In yet another example, "high-k dielectric" refers to a material having a higher dielectric constant (k) than silicon oxide. The terms "oxide", "carbide", "nitride" and the like refer to compounds containing oxygen, carbon, nitrogen and the like, respectively.

[0033] Example assembly with components coupled by direct bonding

[0034] The embodiments described herein are applicable to direct bonding of electronic components. In different embodiments, different types of electronic components can be assembled together using direct bonding. For example, a die can be coupled to another die, a wafer, a package substrate, a circuit board, or an interposer. As another example, a wafer can be coupled to another wafer. In general, the conductive structures described herein can be included at a direct bonding interface between any combination of electronic components.

[0035] As described above, the term "direct bonding" is used to include metal-to-metal bonding techniques, such as copper-to-copper bonding, or other techniques in which conductive structures at opposing surfaces of an electronic component are first contacted and then subjected to heating and compression. The term "direct bonding" is also used to include hybrid bonding techniques, including techniques in which dielectric materials at opposing surfaces that may first be subjected to previous surface activation are contacted and then subjected to heating and sometimes compression, and techniques in which conductive structures and dielectric materials at opposing surfaces that may first be subjected to previous surface activation are contacted substantially simultaneously and then subjected to heating and sometimes compression. In some embodiments, bonding can be achieved without the use of an intermediate solder or anisotropic conductive material. In some other embodiments, a thin cap of solder may be used between the conductive structures to accommodate planarity, and the solder may become an intermetallic compound in the bonding interface during processing.

[0036] FIG. 1 shows two examples of direct bonding between electronic components. Figure 1A is a cross-section showing a die coupled to another die at a direct bonding interface according to some embodiments of the present disclosure. Specifically, Figure 1A An assembly 100 is shown including a first die 110 and a second die 120. The first die 110 and the second die 120 are coupled at a bonding interface 130. As described above, the bonding interface 130 may be a direct bonding interface.

[0037] Figure 1B is a cross-section showing a die coupled to a wafer at a direct bonding interface according to some embodiments of the present disclosure. Specifically, Figure 1B An assembly 150 is shown that includes a die 160 and a wafer 170. The die 160 and the wafer 170 are coupled at a bonding interface 180. As described above, the bonding interface 180 can be a direct bonding interface. Although one die 160 is shown coupled to the wafer 170, in other embodiments, one or more additional dies can be coupled to the wafer 170 in a direct bonding interface or using other types of bonding or coupling.

[0038] Typically, the components described herein may include one or more support structures. For example, each die and / or wafer may include a support structure on the side opposite to the bonding interface. The support structure may be a semiconductor substrate composed of a semiconductor material system including, for example, an N-type or P-type material system. In one embodiment, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In other embodiments, the semiconductor substrate may be formed using an alternative material that may or may not be combined with silicon, the alternative material including but not limited to germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or III-V group materials (i.e., materials from III and V groups of the periodic table), II-VI groups (i.e., materials from II and IV groups of the periodic table) or other combinations of IV group materials (i.e., materials from IV groups of the periodic table). In some embodiments, the substrate may be non-crystalline. In some embodiments, the support structure can be a printed circuit board (PCB) substrate. Although several examples of materials that can form the substrate are described herein, any material that can be used as a foundation on which a semiconductor device can be built falls within the spirit and scope of the present disclosure, including direct bonding interfaces incorporating wiring or passive devices, as described herein.

[0039] In some embodiments, various layers may be formed above each support structure. For example, die 110 and die 120 may each include one or more device layers and a set of metallization layers formed above the respective support structures. Die 110 may be arranged to have a support structure at the top in the orientation shown, and a "top" metallization layer at the bottom in the orientation shown. Thus, die 110 may be flipped from the orientation used to manufacture die 110. Die 120 may be arranged to have a support structure at the bottom in the orientation shown, and a top metallization at the top of die 120 in the orientation shown. Thus, the "top" metal layers of dies 110 and 120 contact at bonding interface 130. Die 160 and wafer 170 may be arranged in a similar manner, with the "top" metal layers of die 160 and wafer 170 contacting at bonding interface 180.

[0040] Example structures formed by direct bonding

[0041] 2-6 provide examples of IC devices including features (such as interconnects and passive devices) formed by direct bonding of elongated conductive structures. Different regions of the IC device are indicated by different patterns, wherein the legend provided at the top of the accompanying drawing page shows the correspondence between the reference numerals and the patterns. Certain patterns are used throughout FIG. 2-6 to refer to different materials or regions. For example, the legend of FIG. 2 shows that different patterns show a dielectric 202 of a first component (e.g., a first die or a first wafer), a dielectric 204 of a second component (e.g., a second die or a second wafer), a conductive material 206 of the first component, and a conductive material 208 of the second component.

[0042] Dielectrics 202 and 204 may include one or more dielectric materials, such as one or more inorganic dielectric materials. For example, each of dielectrics 202 and 204 may include silicon, carbon, and nitrogen (e.g., in the form of silicon carbon nitride); silicon and nitrogen (e.g., in the form of silicon nitride); silicon and oxygen (e.g., in the form of silicon oxide); carbon and oxygen (e.g., in the form of carbon-doped oxide); silicon, oxygen, and nitrogen (e.g., in the form of silicon oxynitride); aluminum and oxygen (e.g., in the form of aluminum oxide); titanium and oxygen (e.g., in the form of titanium oxide); hafnium and oxygen (e.g., in the form of hafnium oxide); silicon, oxygen, carbon, and hydrogen (e.g., in the form of tetraethyl orthosilicate (TEOS)); zirconium and oxygen (e.g., in the form of zirconium oxide); niobium and oxygen (e.g., in the form of niobium oxide); tantalum and oxygen (e.g., in the form of tantalum oxide); and combinations thereof. In some embodiments, a given component (e.g., a wafer or die) includes multiple layers of dielectric material, wherein the dielectric material may be the same or different in different layers. In some embodiments, a layer of dielectric 202 or 204 closest to the bonding surface of the direct bonding interface (e.g., closer to the bonding interface 230) can have a higher carbon content than the other layers of dielectric. Although dielectrics 202 and 204 are shown as having different patterns, in some embodiments, dielectrics 202 and 204 can include the same material.

[0043] Conductive materials 206 and 208 may include any one or more conductive materials, such as copper (e.g., PCC or FGC), manganese, titanium, gold, silver, palladium, nickel, aluminum, copper and aluminum (e.g., in the form of a copper-aluminum alloy), tantalum (e.g., tantalum and nitrogen in the form of tantalum metal or tantalum nitride), cobalt, cobalt and iron (e.g., in the form of a cobalt-iron alloy), or any alloy of any of the foregoing (e.g., copper, manganese, and nickel in the form of manganese copper). Although conductive materials 206 and 208 are shown as having different patterns, in some embodiments, conductive materials 206 and 208 may include the same one or more materials, for example, conductive materials 206 and 208 may both be copper.

[0044] Figure 2A and Figure 2B are two cross sections of exemplary direct bonding for routing or passive components according to some embodiments of the present disclosure. Figure 2B It passes through Figure 2A Section of plane AA' in. Figure 2ATwo components 210 and 220 are shown. Each of components 210 and 220 can be any component that can be directly bonded as described above. For example, component 210 can be die 110 or die 160, and component 220 can be die 120 or wafer 170. Components 210 and 220 meet at bonding interface 230, which can be an example of bonding interface 130 or bonding interface 180. Bonding interface 230 is a plane extending in the x and y directions in the example coordinate system; Figure 2B The AA′ plane shown in FIG. 2 is parallel to the xy plane and to the plane of the bonding interface 230 .

[0045] Component 210 includes dielectric 202 and conductive material 206. Component 220 includes dielectric 204 and conductive material 208. As described above, although dielectrics 202 and 204 of respective components 210 and 220 are shown using different patterns, in some embodiments, dielectrics 202 and 204 may be the same dielectric material. Furthermore, although conductive materials 206 and 208 of respective components 210 and 220 are shown using different patterns, in some embodiments, conductive materials 206 and 208 may be the same conductive material (e.g., copper). In a cross-section of the device (e.g., a TEM image), even if materials 206 and 208 are the same, the boundary between conductive materials 206 and 208 may be visible, for example, as a seam. Furthermore, the boundary between dielectrics 202 and 204 may be visible, for example, as a seam, or by the presence of an additional material layer formed by a bonding material (e.g., a bonding oxide).

[0046] Conductive material 206 is in the top metallization layer of component 210. Component 210 has been flipped over component 220 so that the top metallization layer (which may be the last metallization layer formed during the manufacturing process) is located on the bottom of component 210 in the orientation shown. Likewise, conductive material 208 is in the top metallization layer of component 220 (in the orientation shown and during the manufacturing process). Conductive materials 206 and 208 shown in FIG. 2 form a trench structure. For example, as shown in FIG. Figure 2B As shown, conductive material 206 is formed into three trenches 240A-240C, each of which extends in the y-direction in the example coordinate system shown. That is, trenches 240A-240C extend along the plane of bonding interface 230, which, as described above, extends in the y-direction (and the x-direction).

[0047] Each of trench structures 240 and 250 has a length and a width, where the length is the longer dimension of the trench structure in the plane of the bonding interface 230 (ie, the xy plane in the example coordinate system) and the width is the shorter dimension of the trench structure in the plane of the bonding interface. Figure 2BA length 270 and a width 280 of trench structure 240C are shown. Length 270 can be, for example, at least two, three, five, or ten times greater than width 280. For different wiring arrangements, different trench structures can have different lengths, for example, trench structure 240B can have a shorter length than length 270 of trench structure 240C. In some examples, different trench structures can have different widths.

[0048] Conductive material 208 is formed into three trenches 250A-250C, where each of the trenches extends in the y-direction in the example coordinate system shown. Trenches 250A-250C may have similar shapes and dimensions as trenches 240A-240C.

[0049] In this example, the trench structures formed by the conductive materials 206 and 208 substantially overlap. For example, the trench structure 240A in the component 210 is formed above the trench structure 250A in the component 220. Each of the trench structures 240 and 250 can be considered an interconnect structure, for example, an interconnect formed in the top metal layer. The trench structures 240 and 250 are joined to form a joined interconnect structure 260; for example, the trench structures 240A and 250 together form the joined interconnect structure 260A. Each joined interconnect structure 260 has a large cross-section; for example, the cross-sectional area of ​​the joined interconnect structure 260A is the sum of the cross-sectional areas of the trench structures 240A and 250A. The cross-sectional area of ​​the joined interconnect structure 260 is generally larger than the cross-sectional area of ​​the interconnect formed in the top metallization layer of the component, for example, larger than the cross-sectional area of ​​the trench structure 240A or the cross-sectional area of ​​the trench structure 250A. This large cross-sectional area may make the bonding interconnect structure 260 particularly well suited for certain applications, such as the transmission of high power signals and the transmission of high frequency signals (eg, RF signals).

[0050] In some embodiments, the bonded interconnect structure 260 forms a signal transmission structure. In some embodiments, the bonded interconnect structure 260 (or more generally, the bonded conductive structure 260) is formed as a passive device, such as an inductor, a filter, or a transformer.

[0051] In some embodiments, the bonding interconnect structure 260 can form a coplanar waveguide. For example, the bonding interconnect structure 260B can be a signal path of the coplanar waveguide, while the bonding interconnect structures 260A and 260C on either side of the signal path 260B are ground planes. In the coplanar waveguide example, the ground planes 260A and 260C are separated from the signal path 260B by dielectric materials (i.e., dielectric materials 202 and 204).

[0052] A cross section of component 210 and / or component 220 may include Figure 2AVarious additional features not shown in the drawings. For example, component 210 may include a conductive material 206 (on the Figure 2A 206 to other metallization layers, such as shown in FIG. 5 . The vias may provide signal routing to other portions of the component 210. The component 210 may also include an additional metal layer above the conductive material 206 (in the z-direction, or underneath during fabrication). Figure 2A 206, or underneath during fabrication). The device layers may include transistors, capacitors, memory devices, etc. Component 210 may also include one or more device layers above conductive material 206 (in the Figure 2A 202 is shown extending from the bottom to the top of component 210, it should be understood that component 210 may include one or more layers of different dielectric materials therein. Additionally, component 210 may include support structures formed of different materials (e.g., silicon or another semiconductor material).

[0053] Likewise, component 220 may include additional metallization layers beneath conductive material 208, with trench structures extending in the x and / or y directions in different layers, and via structures extending between layers in the z direction. Component 220 may also include one or more device layers and / or a substrate or other support structure, as described above.

[0054] 2 are shown as being formed of solid regions of conductive materials 206 and 208, in other examples, vacant structures called holes are formed in trenches 240 and / or 250. Including holes in large conductive structures reduces the metal density across the bonding layer, which may be useful for complying with design rules for manufacturing upper metal layers. The holes in conductive materials 206 and 208 may be arranged so that they are offset from each other, for example, so that the holes do not overlap.

[0055] Figures 3A-3C are three cross sections of exemplary direct bonding according to some embodiments of the present disclosure, wherein the conductive material includes an offset hole. Figure 3B It passes through Figure 3A The cross section of plane BB' in Figure 3C It passes through Figure 3AFIG. 3 shows two components 310 and 320 joined at a bonding interface 330. Each of components 310 and 320 can be any component that can be directly joined as described above. For example, components 310 and 320 can be similar to components 210 and 220 described above. Component 310 and / or component 320 may include various additional features not shown in FIG. 3 (e.g., metallization layers, device layers, memory layers, support structures, etc.).

[0056] Component 310 includes conductive material 206 in the top metallization layer of component 310; conductive material 206 is at the bottom of component 310 in the orientation shown. Similarly, component 320 includes conductive material 208 in the top metallization layer of component 320. Conductive materials 206 and 208 shown in FIG. 3 form trench structures 340 and 350, which have shapes and arrangements similar to the trench structures 240 and 250 described above. In this example, each trench structure 340 includes a hole 360, and each trench structure 350 includes a hole 370. For example, trench structure 340A includes holes 360A, 360B, and 360C, while trench structure 350A includes holes 370A and 370B. Holes 360 and 370 can be vacancies in conductive materials 206 and 208, or holes 360 and 370 can be filled with different materials (e.g., dielectric materials). Holes 360 and 370 are offset from each other in the y direction. For example, in the y direction, hole 370A is between holes 360A and 360B. Figure 3A When the engagement groove structures 340A and 350A are shown, the hole 360 ​​is offset from the hole 370 and does not overlap with the hole 370. In other examples, the holes 360 and 370 in the engagement groove structures 340 and 350 can substantially overlap or partially overlap.

[0057] In the examples of Figures 2 and 3, the bonding interconnect structures are substantially overlapped, for example to form a thick wiring path or a large conductive structure. In other examples, the groove structures in the two bonding components can partially overlap in an alternating manner, for example, to provide a transmission path in which a signal is passed back and forth between the two components, or to provide a conductive path for an inductor or other passive device, where the conductive path extends between the two components.

[0058] Figures 4A-4C are three cross sections of exemplary direct bonds according to some embodiments of the present disclosure, wherein electrical signals are passed between and along two components. Figure 4B It passes through Figure 4A The cross section of the plane DD' in Figure 4C It passes through Figure 4AFIG. 4 shows two components 410 and 420 joined at a bonding interface 430. Each of components 410 and 420 can be any component that can be directly joined as described above. For example, components 410 and 420 can be similar to components 210 and 220 described above. Component 410 and / or component 420 may include various additional features (e.g., metallization layers, device layers, memory layers, support structures, etc.) not shown in FIG. 4, as described above with respect to FIG. 2.

[0059] Component 410 includes conductive material 206 in the top metallization layer of component 410; conductive material 206 is at the bottom of component 410 in the orientation shown. Likewise, component 420 includes conductive material 208 in the top metallization layer of component 420. Conductive materials 206 and 208 shown in FIG. 4 form trench structures 440 and 450, respectively.

[0060] For example, Figure 4B As shown, the conductive material 206 is formed into two rows of grooves 440, each row extending in the x-direction in the example coordinate system shown. The first row includes three grooves 440A-440C and the second row includes three grooves 440D-440F. The first row of grooves 440A-440C also extends in the x-direction. Figure 4A Each of the grooves 440 extends in the x-direction. The grooves 440A-440F extend in a direction parallel to the bonding interface 430, which, as described above, extends in the x-direction (and the y-direction). Figure 4C As shown, the conductive material 208 is formed into two rows of grooves 450, each row extending in the x-direction in the example coordinate system shown. The first row includes three grooves 450A-450C and the second row includes three grooves 450D-450F. The first row of grooves 450A-450C also extends in the x-direction. Figure 4A Shown in.

[0061] Groove 450 is offset from groove 440 in the x-direction. Figure 4AAs shown, groove 440A and 440B overlap with groove 450A part respectively.Groove 450A is coupled to groove 440A and 440B and extends between groove 440A and 440B.Therefore, groove 450A electrically couples groove 440A and 440B.Similarly, groove 440B electrically couples groove 450A and 450B, and so on.Groove 440A-440C and 450A-450C can provide the joint interconnection structure that transmits signal along joint interface 430, wherein signal moves back and forth between component 410 and 420 along groove 440A-440C and 450A-450C.Groove 440D-440F and 450D-450F can provide separate joint interconnection structure.In some embodiments, joint interconnection structure (or more generally, joint conductive structure) is formed as passive device, for example inductor, filter or transformer.

[0062] Each of the groove structures 440 and 450 has a length and a width, wherein the length is the longer dimension of the groove structure in the plane of the bonding interface (i.e., the xy plane in the example coordinate system), and the width is the shorter dimension of the groove structure in the plane of the bonding interface. In the orientation shown, the length is measured in the x direction, and the width is measured in the y direction. The length of the groove structure 440 or 450 can be, for example, at least two times, three times, five times, or ten times the width of the groove structure 440 or 450. For different wiring arrangements, different groove structures can have different lengths and / or different widths.

[0063] In the examples shown in Figures 2-4, the conductive path is formed by a groove at the bonding interface, that is, a bonding interconnect structure formed at the top metal layer. In other examples, the conductive path can extend into one or more additional metal layers (e.g., a lower metal layer on one of the dies). Figure 5A and Figure 5B are cross-sectional and perspective views, respectively, of a conductive path extending between a bonding layer and a lower metal layer of one of the components according to some embodiments of the present disclosure. Figure 5B In the illustration of FIG. 2 , only the elements of the conductive path are shown, while the dielectrics 202 and 204 are omitted. Figure 5B Shows Figure 5A A portion of the trench structure and via shown in FIG.

[0064] Figure 5A Two components 510 and 520 are shown joined at a joining interface 530. Each of the components 510 and 520 can be any components that can be directly joined as described above. For example, the components 510 and 520 can be similar to the components 210 and 220 described above.

[0065] Component 510 includes conductive material 206 in the top metallization layer of component 510; conductive material 206 is at the bottom of component 510 in the orientation shown. Similarly, component 520 includes conductive material 208 in the top metallization layer of component 520. Conductive materials 206 and 208 shown in FIG. 5 form trench structures 540 and 550, respectively. Trench structures 540 and 550 can be similar to trench structures 440 and 450 shown in FIG. 4 and described above. Trench structures 540 and 550 extend in the x-direction in the coordinate system shown. Unlike trench structures 440 and 450 in FIG. 4, in this example, trench structure 540 is aligned with trench structure 550 so that trench structure 540 is directly above trench structure 550. Therefore, trench structures 540 and 550 form a bonding interconnect structure, similar to bonding interconnect structure 260 shown in FIG. 2.

[0066] Figure 5A Further shown is a second metal layer 580 including a trench structure 560. The trench structure 560 is formed of a conductive material 504, which can be the same material as the conductive material 208 or a different material. The trench structure 560 extends in the x-direction in the coordinate system shown. The trench structure 560 extends in the same direction as the trench structures 540 and 550 (i.e., parallel to the trench structures 540 and 550). The trench structure 560 is coupled to the trench structure 550 by a via 570. The via 570 is formed of a via material 502, which can be any conductive material, such as the same conductive material as the trench structures 560 and / or 550, or a different conductive material.

[0067] For example, trench structure 560A in lower metal layer 580 is coupled to trench structure 550A at bonding interface 530 through via 570A. Trench structure 560A is also coupled to trench structure 550B through via 570B. Thus, trench structures 550A and 540A (which may be considered a first bonding interconnect structure) are electrically coupled to trench structures 550B and 540B (which may be considered a second bonding interconnect structure) through via 570A, lower trench structure 560A, and via 570B.

[0068] Component 510 and / or component 520 may include various additional features (e.g., metallization layers, device layers, memory layers, support structures, etc.) not shown in Figure 5. For example, component 510A may have additional metallization layers below metallization layer 580 and one or more device layers below other metallization layers.

[0069] As described above, bonded interconnect structures and / or conductive paths including bonded interconnect structures may be used to form various devices, such as RF passive devices. Figure 62 is a perspective view of an example passive device (inductor) partially formed in a direct bonding interface according to some embodiments of the present disclosure. In this example, the inductor is a loop formed by a bonding interconnect structure formed by conductive materials 206 and 208. The loop is connected by vias and grooves (e.g., vias 570 and grooves 560 shown in Figure 5) in the lower metal layer. The structure allows the inductor loop to extend around the corner, with two bonding interconnect structures extending in the vertical direction. For example, the bonding interconnect structure 610A extends in the x direction in the coordinate system shown, and the bonding interconnect structure 610B extends in the y direction. The bonding interconnect structures 610A and 610B are coupled together by the lower groove structure 620. In other examples, the inductor or other passive devices can be formed by the groove structure in the top metal layer of each component, for example, using the groove arrangement shown in any one of Figures 2-5.

[0070] Example Device

[0071] The direct bonding interface incorporating wiring or passive devices disclosed herein may be included in any suitable electronic device. FIGS. 7-10 show various examples of devices that may include the direct bonding interface incorporating wiring or passive devices disclosed herein, or may be included in a device or assembly that includes the direct bonding interface incorporating wiring or passive devices.

[0072] Fig. 7A and Figure 7B is a top view of a wafer and die according to any embodiments disclosed herein, which may include direct bonding interfaces incorporating wiring or passive devices. Wafer 1500 may be comprised of semiconductor material and may include one or more die 1502 having IC structures formed on a surface of wafer 1500. Each of die 1502 may be a repeating unit of a semiconductor product including any suitable IC structure (e.g., an IC structure as shown in any of FIG. 1 , FIG. 3 , or FIG. 5 , or any other embodiment of an IC structure described herein). After fabrication of the semiconductor product is completed, wafer 1500 may undergo a singulation process in which each die 1502 is separated from one another to provide discrete “chips” of the semiconductor product. Die 1502 may include one or more transistors (e.g., the IC structures discussed below). Figure 81640) and / or supporting circuitry for transmitting electrical signals to the transistors, as well as any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., SRAM devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed of multiple memory devices may be formed on a processor (e.g., a processor) that is connected to a processor. Fig.10 The wafer 1500 and / or one of the dies 1502 may be assembled with another wafer, die, or another component using direct bonding, as described above. The direct bonding interface may be a direct bonding interface incorporating wiring or passive devices, for example, as described with respect to FIGS. 1-6 .

[0073] Figure 8 1 is a cross-sectional side view of an IC device 1600 that may form a portion of a die or other component bonded to another component in a direct bonding interface incorporating wiring or passive devices in accordance with any embodiment disclosed herein. The IC device 1600 may be formed on a substrate 1602 (e.g., Fig. 7A 1500) and may include on a die (e.g., Figure 7B The substrate 1602 may be any substrate as described herein. The substrate 1602 may be a singulated die (e.g., Figure 7B of a die 1502) or a wafer (e.g., Fig. 7A A portion of wafer 1500).

[0074] IC device 1600 may include one or more device layers 1604 disposed on substrate 1602. Device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on substrate 1602. Device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the flow of current in transistor 1640 between S / D regions 1620, and one or more S / D contacts 1624 for transmitting electrical signals to / from S / D regions 1620. Transistor 1640 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. Transistor 1640 is not limited to Figure 8The types and configurations shown in the drawings and may include a variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of the two. Non-planar transistors may include FinFET transistors, such as dual-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

[0075] Each transistor 1640 may include a gate 1622 formed of at least two layers: a gate electrode layer and a gate dielectric layer.

[0076] The gate electrode layer may be formed on the gate interconnect support layer and may be composed of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode layer may be composed of a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a fill metal layer. Additional metal layers, such as barrier layers and / or adhesion layers, may be included for other purposes.

[0077] For PMOS transistors, metals that can be used for gate electrodes include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9 electron volts (eV) and about 5.2 eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, tungsten, and tungsten carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV.

[0078] In some embodiments, when a cross section of transistor 1640 is observed along the source-channel-drain direction, the gate electrode may be formed as a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be implemented as a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be implemented as one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers. In some embodiments, the gate electrode may be composed of a V-shaped structure (for example, when the fins of a FinFET transistor do not have a "flat" upper surface but instead have rounded peaks).

[0079] Typically, the gate dielectric layer of transistor 1640 may include one or more layers, and one or more layers may include silicon oxide, silicon dioxide, and / or a high-k dielectric material. The high-k dielectric material included in the gate dielectric layer of transistor 1640 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric layer to improve its quality.

[0080] The S / D region 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640 using any suitable process known in the art. For example, the S / D region 1620 may be formed using an implantation / diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the substrate 1602 to form the S / D region 1620. An annealing process to activate the dopants and further diffuse them into the substrate 1602 may follow the ion implantation process. In the latter process, an epitaxial deposition process may provide materials for fabricating the S / D region 1620. In some embodiments, the S / D region 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1620 may be formed using one or more alternative semiconductor materials such as germanium or a III-V material or alloy. In further embodiments, one or more layers of metal and / or metal alloys may be used to form S / D regions 1620. In some embodiments, an etching process may be performed prior to epitaxial deposition to create recesses in substrate 1602 in which material for S / D regions 1620 is deposited.

[0081] By providing one or more interconnect layers (in Figure 8 1606-1610) to and / or from transistors 1640 of device layer 1604. For example, conductive features of device layer 1604 (e.g., gate 1622 and S / D contacts 1624) can be electrically coupled to interconnect structures 1628 of interconnect layers 1606-1610. One or more interconnect layers 1606-1610 can form an ILD stack 1619 of IC device 1600.

[0082] Interconnect structures 1628 may be arranged within interconnect layers 1606-1610 to transmit electrical signals according to various designs (particularly, the arrangement is not limited to Figure 8 ). Although Figure 8 A particular number of interconnect layers 1606 - 1610 are shown in , but embodiments of the present disclosure include IC devices having more or fewer interconnect layers than shown.

[0083] In some embodiments, the interconnect structure 1628 may include a trench contact structure 1628a (sometimes referred to as a "line") and / or a via structure 1628b (sometimes referred to as a "hole") filled with a conductive material (such as a metal). The trench contact structure 1628a may be arranged to transmit electrical signals in a direction substantially parallel to a plane of the surface of the substrate 1602 on which the device layer 1604 is formed. For example, the trench contact structure 1628a may be arranged to transmit electrical signals in a direction substantially parallel to a plane of the surface of the substrate 1602 on which the device layer 1604 is formed. Figure 8 The via structure 1628b may be arranged to transmit electrical signals in a direction that is substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the via structure 1628b may electrically couple the trench contact structures 1628a of different interconnect layers 1606-1610 together.

[0084] The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between interconnect structures 1628, such as Figure 8 Dielectric material 1626 can take the form of any of the embodiments of dielectric materials provided between interconnects of IC structures disclosed herein.

[0085] In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606 - 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606 - 1610 may be the same.

[0086] A first interconnect layer 1606 (referred to as metal 1 or "M1") can be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 can include a trench contact structure 1628a and / or a via structure 1628b, as shown. The trench contact structure 1628a of the first interconnect layer 1606 can be coupled with a contact of the device layer 1604 (e.g., S / D contact 1624).

[0087] A second interconnect layer 1608 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include a via structure 1628b to couple the trench contact structure 1628a of the second interconnect layer 1608 with the trench contact structure 1628a of the first interconnect layer 1606. Although the trench contact structure 1628a and the via structure 1628b are structurally outlined with lines within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments, the trench contact structure 1628a and the via structure 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0088] A third interconnect layer 1610 (referred to as metal 3 or “M3”) may be formed successively on the second interconnect layer 1608 (and additional interconnect layers as needed) according to similar techniques and configurations described in conjunction with the second interconnect layer 1608 or the first interconnect layer 1606 .

[0089] The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or a similar material) formed on the interconnect layers 1606-1610 and one or more bonding pads 1636. The bonding pads 1636 may be electrically coupled to the interconnect structure 1628 and configured to transmit the electrical signals of the (multiple) transistors 1640 to other external devices. For example, a solder joint may be formed on one or more bonding pads 1636 to mechanically and / or electrically couple the chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may have other alternative configurations other than those shown in other embodiments to transmit electrical signals from the interconnect layers 1606-1610. For example, the bonding pads 1636 may be replaced by or may also include other similar features (e.g., columns) that transmit electrical signals to external components.

[0090] Fig. 9 1 is a cross-sectional side view of an IC device assembly 1700 that may include a direct bonding interface incorporating wiring or passive devices in accordance with any embodiment disclosed herein. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposite second side 1742 of the circuit board 1702; generally, the components may be disposed on one or both of the sides 1740 and 1742. Specifically, as disclosed herein, any suitable component of the components of the IC device assembly 1700 may be bonded to another component of the components in a direct bonding interface incorporating wiring or passive devices.

[0091] In some embodiments, circuit board 1702 may be a printed circuit board (PCB) including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 1702 (optionally in combination with other metal layers). In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0092] Fig. 9 The IC device assembly 1700 shown in FIG. 1 includes a package structure on an interposer 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling component 1716. The coupling component 1716 can electrically and mechanically couple the package structure on the interposer 1736 to the circuit board 1702 and can include solder balls (e.g., Fig. 9 as shown), male and female portions of the socket, adhesives, bottom fill materials, and / or any other suitable electrical and / or mechanical coupling structures.

[0093] The package-on-interposer structure 1736 may include an IC package 1720 coupled to the interposer 1704 via a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as those discussed above with reference to the coupling component 1716. Fig. 9 1702 and 1704. A single IC package 1720 is shown in FIG. 1703 , but multiple IC packages may be coupled to interposer 1704; indeed, additional interposers may be coupled to interposer 1704. Interposer 1704 may provide an intermediate substrate for bridging circuit board 1702 and IC package 1720. IC package 1720 may be or include, for example, a die ( Figure 7B 1502), IC devices (e.g., Figure 8 1600), or any other suitable component. In general, interposer 1704 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 1704 can couple IC package 1720 (e.g., die) to a ball grid array (BGA) of coupling component 1716 for coupling to circuit board 1702. Fig. 9 In the illustrated embodiment, IC package 1720 and circuit board 1702 are attached to opposite sides of interposer 1704; in other embodiments, IC package 1720 and circuit board 1702 can be attached to the same side of interposer 1704. In some embodiments, three or more components can be interconnected through interposer 1704.

[0094] The interposer 1704 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternating rigid or flexible materials, which may include the same materials as those described above for the semiconductor substrate, such as silicon, germanium, and other III-V and IV materials. The interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to TSVs 1706. The interposer 1704 may also include embedded devices 1714, including both passive and active devices. These devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 1704. The interposer-on-package structure 1736 may take the form of any interposer-on-package structure known in the art.

[0095] IC device assembly 1700 may include an IC package 1724 coupled to first side 1740 of circuit board 1702 via coupling component 1722. Coupling component 1722 may take the form of any of the embodiments discussed above with reference to coupling component 1716, and IC package 1724 may take the form of any of the embodiments discussed above with reference to IC package 1720.

[0096] Fig. 9 The IC device assembly 1700 shown in the figure includes a stacked package structure 1734 coupled to the second side 1742 of the circuit board 1702 by a coupling component 1728. The stacked package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by a coupling component 1730, so that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any embodiment of the coupling component 1716 described above, and the IC packages 1726 and 1732 may take the form of any embodiment of the IC package 1720 described above. The stacked package structure 1734 may be configured according to any stacked package structure known in the art.

[0097] Fig.10 is a block diagram of an example computing device 1800 that may include a direct bonding interface in combination with wiring or passive devices according to any embodiment disclosed herein. For example, any suitable component of the components of computing device 1800 may include a die (e.g., Figure 7B1502) that is coupled to another component via a direct bonding interface in combination with wiring or passive devices, as described herein. Any one or more components of computing device 1800 may include IC device 1600 ( Figure 8 ) or is included in the IC device 1600 ( Figure 8 ). Any one or more components of computing device 1800 may include IC device assembly 1700 ( Fig. 9 ) or is included in the IC device assembly 1700 ( Fig. 9 )middle.

[0098] Fig.10 1800, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-chip (SoC) die.

[0099] Additionally, in various embodiments, computing device 1800 may not include Fig.10 , but computing device 1800 may include interface circuitry for coupling to one or more of the components. For example, computing device 1800 may not include display device 1812, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 1812 may be coupled. In another set of examples, computing device 1800 may not include audio input device 1816 or audio output device 1814, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which audio input device 1816 or audio output device 1814 may be coupled.

[0100] The computing device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 1800 may include a memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 1804 may include a memory that shares a die with the processing device 1802. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).

[0101] In some embodiments, computing device 1800 may include a communication chip 1806 (e.g., one or more communication chips). For example, communication chip 1806 may be configured to manage wireless communications for transmitting data to and from computing device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated devices do not include any wires, although in some embodiments they may not.

[0102] The communication chip 1806 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 1806 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE network. The communication chip 1806 can operate according to Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1806 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher generations. In other embodiments, the communication chip 1806 can operate according to other wireless protocols. The computing device 1800 may include an antenna 1808 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0103] In some embodiments, the communication chip 1806 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1806 may include multiple communication chips. For example, the first communication chip 1806 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 1806 may be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 1806 may be dedicated to wireless communications, and the second communication chip 1806 may be dedicated to wired communications.

[0104] Computing device 1800 may include battery / power circuitry 1810. Battery / power circuitry 1810 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 1800 to an energy source separate from computing device 1800 (e.g., AC line power).

[0105] Computing device 1800 may include a display device 1812 (or corresponding interface circuitry, as described above). Display device 1812 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0106] Computing device 1800 may include an audio output device 1814 (or corresponding interface circuitry, as described above). Audio output device 1814 may include any device that generates an audible indicator, such as a speaker, headphones or earbuds, and the like.

[0107] Computing device 1800 may include audio input device 1816 (or corresponding interface circuitry, as described above). Audio input device 1816 may include any device that produces a signal representative of sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0108] Computing device 1800 may include a GPS device 1822 (or corresponding interface circuitry, as described above). GPS device 1822 may communicate with a satellite-based system and may receive the location of computing device 1800, as is known in the art.

[0109] Computing device 1800 may include other output devices 1818 (or corresponding interface circuitry, as described above). Examples of other output devices 1818 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0110] Computing device 1800 may include other input devices 1820 (or corresponding interface circuitry, as described above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touch pad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0111] The computing device 1800 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 1800 may be any other electronic device that processes data.

[0112] Select Example

[0113] The following paragraphs provide various examples of the embodiments disclosed herein.

[0114] Example 1 provides an IC device, comprising: a first die, the first die including a first metal layer at a lower surface of the first die, the first metal layer having a first interconnect extending along the lower surface, wherein the first interconnect has a length along the lower surface and a width along the lower surface, and the length is at least three times the width; a second die, the second die including a second metal layer at an upper surface of the second die, the second metal layer having a second interconnect extending along the upper surface of the second die; and a bonding interface, the bonding interface coupling the first die to the second die, wherein the bonding interface couples the first interconnect to the second interconnect.

[0115] Example 2 provides the IC device of Example 1, wherein the first interconnect partially overlaps the second interconnect.

[0116] Example 3 provides the IC device of Example 2, wherein the first metal layer further includes a third interconnect extending along the lower face, the third interconnect being spaced apart from the first interconnect, wherein the second interconnect couples the first interconnect to the third interconnect.

[0117] Example 4 provides the IC device of Example 1, wherein the first metal layer further includes a third interconnect extending along the lower surface, the third interconnect being separated from the first interconnect, and the first die further includes a second metal layer, the second metal layer includes a fourth interconnect, the fourth interconnect is coupled to the first interconnect through a first via, and the fourth interconnect is coupled to the third interconnect through a second via.

[0118] Example 5 provides the IC device of Example 1, wherein the first interconnect and the second interconnect form a signal path of a coplanar waveguide.

[0119] Example 6 provides the IC device of Example 5, wherein the first metal layer further includes a third interconnect separated from the first interconnect and extending parallel to the first interconnect, and the second metal layer further includes a fourth interconnect separated from the second interconnect and extending parallel to the second interconnect, wherein the bonding interface couples the third interconnect to the fourth interconnect, and the third interconnect and the fourth interconnect form a grounding structure of a coplanar waveguide.

[0120] Example 7 provides the IC device of any of the preceding examples, wherein the second interconnect has a second length along the upper face and a second width along the upper face, the second length being at least three times the second width.

[0121] Example 8 provides the IC device of any of the preceding examples, wherein the first interconnect includes a metal having a first hole formed therein, and the second interconnect includes a metal having a second hole formed therein, the first hole being offset from the second hole.

[0122] Example 9 provides the IC device of any of the preceding examples, wherein the first interconnect and the second interconnect form one side of an inductor including additional coupled interconnect pairs in the first die and the second die.

[0123] Example 10 provides the IC device of any of the preceding examples, wherein the bonding interface includes a seam formed between the first interconnect and the second interconnect.

[0124] Example 11 provides the IC device of any of the preceding examples, wherein the bonding interface further comprises a bonding material formed between a first dielectric material in the first die and a second dielectric material in the second die.

[0125] Example 12 provides a device comprising: a wafer having an upper surface, the upper surface of the wafer including a first trench interconnect extending along the upper surface of the wafer; and a die comprising a metal layer at a lower surface of the die, the metal layer having a second trench interconnect extending along the lower surface of the wafer; wherein the first trench interconnect is physically coupled to the second trench interconnect.

[0126] Example 13 provides the device of Example 12, wherein the first trench interconnect partially overlaps the second trench interconnect.

[0127] Example 14 provides the device of Example 13, wherein the upper surface of the wafer further includes a third trench interconnect, the third trench interconnect being separated from the first trench interconnect, wherein the second trench interconnect is also physically coupled to the third trench interconnect.

[0128] Example 15 provides the device of Example 12, the die further comprising a second metal layer over the lower face of the die, the second metal layer comprising a third interconnect coupled to the second interconnect through a via.

[0129] Example 16 provides the device of Example 12, wherein the first trench interconnect and the second trench interconnect form a signal path of a coplanar waveguide.

[0130] Example 17 provides an electronic component, comprising: a first device, the first device including a first metal layer at the lower surface of the first device; a second device, the second device including a second metal layer at the upper surface of the first device; a bonding interface, the bonding interface between the first metal layer and the second metal layer; and a passive circuit element, the passive circuit element including a first metal structure in the first metal layer and a second metal structure in the second metal layer, the first metal structure and the second metal structure being bonded at the bonding interface.

[0131] Example 18 provides the electronic assembly of Example 17, wherein the passive circuit element includes an inductor.

[0132] Example 19 provides the electronic assembly of Example 18, wherein the passive circuit element is a transformer.

[0133] Example 20 provides the electronic assembly of Example 17, wherein the passive circuit element is a filter.

[0134] Example 21 provides the electronic assembly of any of Examples 17-19, wherein the passive circuit element is coupled to a third metal layer of the first device, the third metal layer being above the first metal layer.

[0135] Example 22 provides the electronic assembly of Example 21, wherein the passive circuit element is further coupled to a fourth metal layer of the second device, the fourth metal layer being below the second metal layer.

[0136] Example 23 provides the electronic assembly of Example 17, wherein the first device is a first die and the second device is a second die.

[0137] Example 24 provides an IC package, comprising an IC die, the IC die comprising one or more devices according to any of the preceding examples. The IC package may further include additional components coupled to the IC die.

[0138] Example 25 provides the IC package according to Example 24, wherein the additional component is one of a package substrate, a flexible substrate, or an interposer.

[0139] Example 26 provides the IC package of Example 24 or 25, wherein the additional components are coupled to the IC die via one or more first level interconnects.

[0140] Example 27 provides the IC package of Example 26, wherein the one or more first level interconnects include one or more solder bumps, solder pillars, or bond wires.

[0141] Example 28 provides a computing device comprising: a circuit board; and an IC die coupled to the circuit board, wherein the IC die includes one or more of the memory / IC devices according to any of the preceding examples (e.g., the memory / IC devices according to any of Examples 1-23), and / or the IC die is included in an IC package according to any of the preceding examples (e.g., the IC package according to any of Examples 24-27).

[0142] Example 29 provides a computing device according to Example 28, wherein the computing device is a wearable computing device (e.g., a smart watch) or a handheld computing device (e.g., a mobile phone).

[0143] Example 30 provides a computing device according to Example 28 or 29, wherein the computing device is a server processor.

[0144] Example 31 provides the computing device according to Example 28 or 29, wherein the computing device is a motherboard.

[0145] Example 32 provides a computing device according to any one of Examples 28-31, wherein the computing device further comprises one or more communication chips and an antenna.

[0146] The above description of the illustrated embodiments of the present disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Although the specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art. These modifications may be made to the present disclosure according to the above specific embodiments.

Claims

1. An integrated circuit (IC) device, comprising: a first die comprising a first metal layer at a lower face of the first die, the first metal layer having a first interconnect extending along the lower face, wherein the first interconnect has a length along the lower face and a width along the lower face, the length being at least three times the width; a second die comprising a second metal layer at an upper face of the second die, the second metal layer having second interconnects extending along the upper face of the second die; and A bonding interface couples the first die to the second die, wherein the bonding interface couples the first interconnect to the second interconnect.

2. The IC device according to claim 1, wherein: The first interconnection partially overlaps with the second interconnection.

3. The IC device according to claim 2, wherein: The first metal layer also includes a third interconnect extending along the lower face, the third interconnect being spaced apart from the first interconnect, wherein the second interconnect couples the first interconnect to the third interconnect.

4. The IC device according to claim 1, wherein: The first metal layer also includes a third interconnect extending along the lower face, the third interconnect being separated from the first interconnect, and the first die also includes a second metal layer, the second metal layer including a fourth interconnect, the fourth interconnect being coupled to the first interconnect through a first via, and the fourth interconnect being coupled to the third interconnect through a second via.

5. The IC device according to claim 1, wherein: The first interconnect and the second interconnect form a signal path of a coplanar waveguide.

6. The IC device according to claim 5, wherein: The first metal layer further includes a third interconnect separated from the first interconnect and extending parallel to the first interconnect, and the second metal layer further includes a fourth interconnect separated from the second interconnect and extending parallel to the second interconnect, wherein the bonding interface couples the third interconnect to the fourth interconnect, and the third interconnect and the fourth interconnect form a grounding structure of the coplanar waveguide.

7. The IC device according to claim 1, wherein: The first interconnect and the second interconnect form one side of an inductor including an additional coupled pair of interconnects in the first die and the second die.

8. The IC device according to any one of claims 1 to 7, wherein: The second interconnect has a second length along the upper face and a second width along the upper face, the second length being at least three times the second width.

9. The IC device according to any one of claims 1 to 7, wherein: The first interconnect includes a metal having a first hole formed therein, and the second interconnect includes a metal having a second hole formed therein, the first hole being offset from the second hole.

10. The IC device according to any one of claims 1 to 7, wherein: The bonding interface includes a seam formed between the first interconnect and the second interconnect.

11. The IC device according to any one of claims 1 to 7, wherein: The bonding interface also includes a bonding material formed between a first dielectric material in the first die and a second dielectric material in the second die.

12. A device comprising: a wafer having an upper face, the upper face of the wafer comprising a first trench interconnect extending along the upper face of the wafer, wherein the first trench interconnect has a length along the upper face and a width along the upper face, the length being at least three times the width; and a die including a metal layer at a lower face of the die, the metal layer having a second trench interconnect extending along the lower face of the wafer; Wherein, the first trench interconnect is physically coupled to the second trench interconnect.

13. The device according to claim 12, wherein The first trench interconnection partially overlaps with the second trench interconnection.

14. The device according to claim 13, wherein The upper face of the wafer also includes a third trench interconnect that is spaced apart from the first trench interconnect, wherein the second trench interconnect is also physically coupled to the third trench interconnect.

15. The device according to claim 12, wherein: The die also includes a second metal layer over the lower face of the die, the second metal layer including a third interconnect coupled to the second interconnect through a via.

16. The device according to claim 12, wherein: The first trench interconnect and the second trench interconnect form a signal path of a coplanar waveguide.

17. An electronic assembly comprising: a first device comprising a first metal layer at a lower face of the first device; a second device comprising a second metal layer at an upper face of the first device; a bonding interface between the first metal layer and the second metal layer; as well as A passive circuit element includes a first metal structure in the first metal layer and a second metal structure in the second metal layer, the first metal structure and the second metal structure being bonded at the bonding interface.

18. The electronic component according to claim 17, wherein: The passive circuit element includes an inductor.

19. The electronic component according to claim 18, wherein: The passive circuit element is a transformer.

20. The electronic assembly according to claim 17, wherein: The passive circuit element is a filter.

21. The electronic component according to any one of claims 17 to 19, wherein: The passive circuit element is coupled to a third metal layer of the first device, the third metal layer being above the first metal layer.

22. The electronic component according to claim 21, wherein The passive circuit element is further coupled to a fourth metal layer of the second device, the fourth metal layer being below the second metal layer.

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