Electronic device

By incorporating trenches with air pockets around three-dimensional capacitors, the stress-induced deformation issues in manufacturing high-density capacitors are resolved, enabling efficient and stable production of high-capacity capacitors.

CN119208300APending Publication Date: 2024-12-27STMICROELECTRONICS INT NV
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Patent Information

Application Number
CN202410822612.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2024-06-14
Filing Date
2024-06-25
Publication Date
2024-12-27

AI Technical Summary

Technical Problem

Existing electronic devices face challenges in manufacturing high-density three-dimensional capacitors without causing deformation due to stress generated by filling cavities with conductive materials, which can disrupt manufacturing processes.

Method used

The implementation of three-dimensional capacitors surrounded by trenches with air pockets, where the trenches are electrically insulating and absorb stress, allowing for the formation of high-density capacitors without deformation.

Benefits of technology

This design enables the formation of high-density capacitors without deformation, maintaining capacitor efficiency and reducing the number of manufacturing steps by utilizing trenches to absorb stress, thus ensuring stable manufacturing processes.

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Abstract

The invention relates to an electronic device. The present description relates to an electronic device comprising at least two three-dimensional capacitors, each capacitor being surrounded by a trench comprising an air pocket.
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Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French patent application No. FR2306700, filed on June 27, 2023, entitled “Dispositifélectronique”, which is hereby incorporated by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic devices and methods of making the same, and to devices including three-dimensional capacitors. Background Art

[0004] There are several types of capacitors. One particularly common type of capacitor corresponds to the so-called MOM capacitor or metal-oxide-metal capacitor. This capacitor comprises a stack of two conductive layers (preferably made of metal) separated by an insulating layer (preferably made of oxide, such as silicon oxide).

[0005] MOM capacitors can be, for example, planar, i.e. stacked over planar layers. MOM capacitors can also be three-dimensional, i.e. over non-planar layers, such as including cavities. Therefore, for the same chip surface area, three-dimensional capacitors can have a capacitance significantly higher than that of planar capacitors. Summary of the invention

[0006] Embodiments overcome all or part of the disadvantages of known electronic devices.

[0007] One embodiment provides an electronic device including at least two three-dimensional capacitors, each capacitor being surrounded by a trench including an air pocket.

[0008] Another embodiment provides a method of manufacturing an electronic device, the method comprising forming at least two three-dimensional capacitors, each capacitor being surrounded by a trench including an air pocket.

[0009] According to an embodiment, the capacitor and the trench are in the first insulating layer.

[0010] According to an embodiment, each capacitor is located in a first region of the first layer, each trench is located in a second region of the first layer, the second region being separated from the first region by a third region of the first layer.

[0011] According to an embodiment, each third region is not covered by the conductive material.

[0012] According to an embodiment, each capacitor comprises a first stack of two conductive layers separated by an insulating layer, the first stack extending conformally over a first region of the first layers, the first region comprising at least two first cavities, the first stack filling the first cavities.

[0013] According to an embodiment, each groove comprises a second stack of the same layers as the first stack, the second stack extending conformally in the second cavity, the air pocket being located in the second cavity, partly delimited by the second stack.

[0014] According to an embodiment, the device comprises a second layer enclosing each second cavity and partially defining an air pocket located in the second cavity.

[0015] According to an embodiment, each first zone is covered with a third layer made of the material of the second layer.

[0016] According to an embodiment, the second layer extends in the second cavity over less than 20% of the height of the second cavity.

[0017] According to an embodiment, each air pocket extends to at least half the height of the first cavity.

[0018] According to an embodiment, the trenches surrounding at least two adjacent capacitors comprise a common portion.

[0019] According to an embodiment, trenches surrounding at least two adjacent capacitors are separated from each other by portions of the first layer.

[0020] According to an embodiment, the device comprises a filter, the capacitor forming part of the filter.

[0021] According to one embodiment, the method includes: forming a first cavity and a second cavity in a first layer; forming a third stack of two conductive layers separated by an insulating layer in a conformal form, the first cavity is filled and the second cavity is not filled, forming a fourth non-conformal layer enclosing the second cavity; etching the third stack and the fourth layer in the third region to form the first stack and the second stack and the second layer and the third layer.

[0022] According to an embodiment, the forming of the fourth layer is performed by a physical vapor deposition method or a plasma enhanced chemical vapor deposition method. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above features and advantages as well as other features and advantages will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0024] Figure 1A shows a cross-sectional view of an embodiment of a device including a three-dimensional capacitor;

[0025] Figure 1B Shows Figure 1A A top view of an embodiment of the present invention;

[0026] Figure 2A Shows the manufacturing Figure 1A and Figure 1B a step of a method for a device;

[0027] Figure 2B Shows the manufacturing Figure 1A and Figure 1B another step of the method of the device;

[0028] Figure 2C Shows the manufacturing Figure 1A and Figure 1B another step of the method of the device;

[0029] Figure 3A and Figure 3B Shown in figure Figure 1A and Figure 1B Two views of two arrangements of capacitors. DETAILED DESCRIPTION

[0030] In the various drawings, similar features have been indicated with similar reference numerals. Specifically, common structural and / or functional features in various embodiments may have the same reference numerals and may be arranged with the same structure, dimensions and material properties.

[0031] For clarity, only the steps and elements that are helpful for understanding the described embodiments are illustrated and described in detail.

[0032] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements except conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0033] In the following description, when referring to terms defining absolute positions (such as terms "edge", "rear / back", "top", "bottom", "left", "right", etc.), or terms defining relative positions (such as terms "upper", "lower", "upper", "lower", etc.), or terms defining directions (such as terms "horizontal", "vertical", etc.), unless otherwise specified, they refer to the orientation of the drawings.

[0034] Unless otherwise indicated, the expressions “around,” “approximately,” “substantially,” and “about” mean plus or minus 10%, preferably plus or minus 5%.

[0035] Figure 1A A cross-sectional view of a device 10 including a three-dimensional capacitor 12 is shown. Figure 1B Shows Figure 1A A top view of an embodiment of the present invention.

[0036] Device 10 includes an insulating layer 14. Layer 14 is, for example, made of an electrically insulating material (e.g., silicon oxide). Layer 14 corresponds, for example, to a layer of a metallization level of an interconnect network. Thus, layer 14 covers, for example, a semiconductor substrate (not shown). Layer 14 covers, for example, one or more other insulating layers, each of which includes a metallization or a conductive via.

[0037] The layer 14 comprises a collection of cavities 16. The cavities 16 are, for example, identical in size. Each groove 16 extends from the upper surface of the layer 14 to the inner level of the layer 14. In other words, each groove does not pass through the layer 14. In other words, the height of the cavity 16 is lower than the height of the layer 14.

[0038] The cavities 16 of the collection are all present in a zone 17 of the layer 14. The cavities 16 of the collection are arranged, for example, in an array in the zone 17. Each collection of cavities 16 comprises, for example, at least two cavities (between 2 and 3000 cavities). Each cavity 16 is separated from the nearest cavity 16 in the same collection only by a portion of the layer 14.

[0039] Capacitor 12 is formed inside and on the top of cavity 16. Capacitor 12 is, for example, a metal-insulator-metal capacitor. In other words, capacitor 12 includes conductive layer 18, insulating layer 20, and conductive layer 22. Conductive layers 18 and 22 are made of metal, for example. Layer 20 is made of a dielectric material.

[0040] Layer 18, which corresponds to the lower electrode of capacitor 12, covers the walls and bottom of the collective cavities 16. Layer 18 also covers portions of the upper surface of layer 14 located between cavities 16 and covers portions of the upper surface of layer 14 around cavities 16. In other words, layer 18 completely covers the upper surface of region 17 of layer 14 and the interior of cavity 16. Thus, layer 18 conformally covers region 17 of layer 14.

[0041] Layer 20 extends over layer 18, such as over the entire layer 18. Layer 20 extends conformally over layer 18. Layer 20 extends over the portion of layer 18 that is located in cavity 16 and over the portion of layer 18 that is located on the upper surface of layer 14.

[0042] A layer 22 corresponding to the upper electrode of the capacitor 12 extends over the layer 20, for example over the entire layer 20. In particular, the layer 22 extends in the cavity 16, preferably over at least half the height of the cavity 16. The dimensions of the cavity 16 and the layers 18, 20, 22 are selected so that the cavity 16 is completely filled by the layers 18, 20, 22.

[0043] The layers 18, 20, 22 extend only in the region 17. The region 17 is surrounded by the region 24 of the layer 14. The layers 18, 20, 22 do not extend over the upper surface of the region 24.

[0044] Region 24 is preferably made only of material of layer 14. Region 24 preferably does not comprise conductive material. Region 24 is preferably not covered by conductive material.

[0045] Layer 14 also comprises region 26. Region 26 surrounds region 24. Region 26 thus surrounds region 17. Region 26 is separated from region 17 (preferably at all points) by region 24.

[0046] Device 10 includes trench 27. Trench 27 includes cavity 28 located in region 26. Cavity 28 forms a ring. Cavity 28 surrounds regions 17 and 24. Thus, cavity 28 surrounds the collection of cavities 16.

[0047] The dimensions of cavity 28 are preferably greater than the dimensions of one of cavities 16. More specifically, the height of cavity 28 is preferably greater than the height of one of cavities 16. At least one of the dimensions of the opening of cavity 28, i.e. the dimension of cavity 28 in the plane of the upper surface of layer 14, is greater than the dimension of the opening of one of cavities 16. Preferably, all dimensions of the opening of cavity 28 are greater than the dimensions of the opening of cavity 16.

[0048] Trench 27 includes a stack of layers 30, 32, 34 that conformally extend in region 26. Layer 30 is made of the same material as layer 18 and has a thickness substantially equal to the thickness of layer 18. Similarly, layer 32 is made of the same material as layer 20 and has a thickness substantially equal to the thickness of layer 20. Similarly, layer 34 is made of the same material as layer 22 and has a thickness substantially equal to the thickness of layer 22.

[0049] Layer 30 conformally covers region 26. Thus, layer 30 covers the sidewalls and the bottom of cavity 28. Layer 30 also covers the portion of the upper surface of layer 14 that is located in region 26.

[0050] Layer 32 conformally covers layer 30. Preferably, layer 30 is completely covered by layer 32. Thus, layer 32 extends in cavity 28 and over the upper surface of region 26.

[0051] Layer 34 conformally covers layer 32. Preferably, layer 32 is completely covered by layer 34. Thus, layer 34 extends in cavity 28 and over the upper surface of region 26.

[0052] The layers 30, 32, 34 extend only in the region 26. The layers 30, 32, 34 do not extend over the upper surface of the region 24.

[0053] Groove 27 also includes layer 36. Layer 36 extends over the portion of layer 34 that is located outside cavity 28. Thus, layer 36 extends in front of the upper surface of zone 26. Layer 36 also extends over the opening of cavity 28. Cavity 28 is thus closed by layer 36. Layer 36 preferably includes a first portion extending in the plane of the upper surface of layer 14 and a second portion extending in the upper portion of the cavity. Preferably, the second portion extends from the opening of cavity 28 to a height less than 20% of the height of cavity 28, preferably to a height less than 10% of the height of cavity 28. Layer 36 does not fill cavity 28. Thus, a cavity or pocket 37 filled with a gas (e.g., air) remains in cavity 28. Pocket 37 is defined by layer 34 and layer 36. Pocket 37 preferably extends to at least 50% of the height of cavity 16, more preferably to at least 75% of the height of cavity 16.

[0054] Device 10 also includes a layer 38 made of the material of layer 36. Layer 38 preferably covers layer 22 completely.

[0055] Layer 36 preferably does not extend above the upper surface of region 24. Similarly, layer 38 preferably does not extend above the upper surface of region 24.

[0056] Layers 36 and 38 are made, for example, of an insulating material or of an electrically conductive material, for example a metal.

[0057] For example, device 10 includes connecting elements (not shown) that enable upper electrode 22 and lower electrode 18 of capacitor 12 to be connected to a circuit. The connecting elements correspond, for example, to conductive vias that pass through layer 38 to layer 22 or, in the portion of layer 20 that is not covered by layer 22, through layers 38 and 20 to layer 18.

[0058] Filling cavity 16 with a material layer generates stress on layer 14. More specifically, filling cavity 16 with a material layer generates lateral stress on layer 14, such as Figure 1A and Figure 1B . The filling of each cavity 16 generates stresses that increase the stresses generated by the other cavities 16. During the formation of a board comprising only filled cavities 16, the filling of the cavities 16 may generate stresses sufficient to distort the board, thereby disrupting the manufacturing steps. The distorted board may not be able to be fed into the machine that performs the steps of the manufacturing method.

[0059] Pocket 37 allows to absorb the stresses generated by layers 18, 20, 22 in cavity 16. Zones 17 and 24 are thus subjected to the stresses generated by layers 18, 20, 22 in cavity 16 of zone 17, but not to the stresses generated by other zones 17 located outside trench 27.

[0060] The trench 27 is preferably electrically insulating. In other words, the layers 30 , 32 , 34 are preferably not coupled to electronic components and not coupled to conductive elements. For example, the sole purpose of the trench 27 is to absorb the stress generated by the capacitor 12 .

[0061] The presence of gas in pockets 37 may result in undesired elements being present in the cavity and in contact with layer 34. However, since trenches 27 have no electrical function, the formation of defects on layer 34 does not alter the absorption of the stress generated by capacitor 12.

[0062] FIG. 2A to FIG. 2C Shows the manufacturing Figure 1A and Figure 1B The steps of the method of device 10 are preferably sequential.

[0063] Figure 2A Shows the manufacturing Figure 1A and 1B The steps of the method of the device.

[0064] During this step, a layer 14 is formed. The layer 14 is for example formed on a substrate or a support (not shown). The layer 14 is for example a planar layer. The upper surface and the lower surface of the layer 14 are then parallel.

[0065] Figure 2A The steps of etching then include forming cavity 16 in region 17 and forming cavity 28 in region 26. The formation of cavities 16 and 28 is preferably performed simultaneously by the same etching step.

[0066] Forming cavities 16 and 28 includes, for example, forming a mask (not shown) over the upper surface of layer 14. The mask (not shown) includes openings facing the locations of cavities 16 and 18, the dimensions of which are substantially equal to the dimensions of the openings of cavities 16 and 18. Forming the cavities then includes etching layer 14 through the mask openings. The difference between the dimensions of the opening of trench 16 and the dimensions of the opening of trench 28 creates a height difference in the cavities formed during etching.

[0067] Figure 2B Shows the manufacturing Figure 1A and Figure 1B The device is another step in the method.

[0068] During this step, a stack of layers 40 , 42 , 44 is conformally formed over at least regions 17 , 24 and 26 , and preferably over the entire layer 14 .

[0069] Layer 40 is made of the material of layers 18 and 30. The thickness of layer 40 is substantially equal to the thickness of layers 18 and 30. Layer 42 is made of the material of layers 20 and 32. The thickness of layer 42 is substantially equal to the thickness of layers 20 and 32. Layer 44 is made of the material of layers 22 and 34. The thickness of layer 44 is substantially equal to the thickness of layers 22 and 34.

[0070] Layer 40 conformally covers regions 17, 24, 28. Preferably, layer 40 conformally covers the entire layer 14. Thus, layer 40 covers the sidewalls and the bottom of cavities 16 and 28. Layer 40 also covers the upper surface of regions 17, 24, 26 of layer 14.

[0071] Layer 42 conformally covers layer 40. Preferably, layer 42 completely covers layer 40. In particular, layer 42 covers the portions of layer 40 that are located in cavities 16 and 28 and that are located on the upper surfaces of regions 17, 24, 26.

[0072] Similarly, layer 44 conformally covers layer 42. Preferably, layer 44 completely covers layer 42. Specifically, layer 44 covers the portion of layer 42 located in cavities 16 and 28 and on the upper surfaces of regions 17, 24, 26. The thickness of layer 44 is such that after forming layer 44, cavity 16 is filled with the stack of layers 40, 42, 44. The thickness of layers 40, 42, 44 is such that cavity 28 is not filled with layers 40, 42, 44. The dimensions of cavity 28 and of layers 40, 42, 44 are such that the portions of layer 44 extending over opposing sidewalls of cavity 28 are not in contact over at least half of the height of cavity 28.

[0073] Figure 2C Shows the manufacturing Figure 1A and Figure 1B The device is another step in the method.

[0074] During this step, Figure 2B A non-conformal layer 46 is formed on the structure produced by the step of forming the non-conformal layer 46. The layer 46 is made of the materials of the layers 36 and 38. The layer 46 is formed in such a way as to close the cavity 28 while keeping the air pocket 37 in the cavity 28. The layer 46 is formed, for example, by a physical vapor deposition (PVD) method, and the layer 46 is made of, for example, a metal, or is formed by a plasma enhanced chemical vapor deposition (PECVD) method, and the layer 46 is made of, for example, a dielectric (e.g., silicon oxide).

[0075] exist Figure 2C After the step of etching, the method further comprises the step of etching the portion of the layers 40, 42, 44, 46 located on the region 24. The layers 18, 20, 22, 30, 32, 34 are thus formed.

[0076] The method also includes forming a connecting element (not shown) that allows for connection of electrodes 18 and 22 .

[0077] Figure 3A and Figure 3B The diagram shows Figure 1A and Figure 1B Two views of the two arrangements of capacitors shown in Figure 3A and 3B Each arrangement comprises four capacitors 12. However, the device may comprise any number of capacitors 12, for example at least two capacitors. The capacitors 12 are for example used in filters.

[0078] exist Figure 3A and Figure 3B , region 26 including trench 27 is shown by a single line, region 17 including capacitor 12 is shown by a shaded rectangle, and region 24 separating regions 26 and 17 is shown by a white strip separating the rectangle and the single line.

[0079] According to the visual Figure 3A , a first example of an arrangement is illustrated, with grooves 27 forming a grid, defining areas 24. Figure 3A In the embodiment of the present invention, the grooves 27 form the columns and rows of a grid and define an array of locations, each location comprising a region 17 and a region 24, preferably comprising a single region 17 and a single region 24. Therefore, all the grooves 27 are coupled to each other.

[0080] Two adjacent capacitors are separated by a single trench 27. Thus, two adjacent capacitors are separated by a portion of a region 24, a trench 27, and a portion of another region 24.

[0081] According to the visual Figure 3B , illustrating a second example of an arrangement, the device comprises an array of components, the components comprising region 17, region 24 and region 26, the different components being separated from each other by portion 50 of substrate 14. Thus, trenches 27 are independent of each other. In other words, trenches 27 are separated from each other by portion 50.

[0082] Two adjacent capacitors are separated by two trenches 27. Thus, two adjacent capacitors are separated by a portion of a region 24, a trench 27, a portion 50, a trench 27 and a portion of another region 24.

[0083] Despite Figure 3A and Figure 3B In FIG. 4 , capacitors 12 are aligned in rows and columns, but capacitors may, for example, be aligned in rows with offset columns.

[0084] Furthermore, a device including capacitor 12 may include a portion where the capacitor is arranged according to a first arrangement and a portion where the capacitor is arranged according to a second arrangement.

[0085] One advantage of the described embodiments is that a board with a high density of three-dimensional capacitors can be formed without causing any deformation.

[0086] Another advantage of the described embodiment is that, since the grooves 27 are not electrically active, the presence of the air pockets does not cause any damage and does not affect the efficiency of the capacitor.

[0087] Another advantage of the described embodiment is that the simultaneous formation of the trench 27 and the capacitor 12 makes it possible to avoid deformation of the plate and to avoid increasing the number of formation steps.

[0088] A number of embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

[0089] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0090] An electronic device (10) comprises at least two three-dimensional capacitors (12), each capacitor (12) being surrounded by a trench (27) comprising an air pocket (37).

[0091] A method of manufacturing an electronic device (10) includes forming at least two three-dimensional capacitors (12), each capacitor (12) being surrounded by a trench (27) including an air pocket (37).

[0092] The capacitor (12) and the trench (27) are in the first insulating layer (14).

[0093] Each capacitor (12) is located in a first region (17) of the first layer (14), each trench (27) is located in a second region (26) of the first layer (14), and the second region of the first layer is separated from the first region (17) by a third region (24) of the first layer (14).

[0094] Each third region (24) is not covered by the conductive material.

[0095] Each capacitor (12) comprises a first stack (18, 20, 22) of two conductive layers separated by an insulating layer, the first stack extending conformally over a first region of the first layer, the first region comprising at least two first cavities (16), the first stack filling the first cavities (16).

[0096] Each groove (27) includes a second stack (30, 32, 34) of the same layers as the first stack (18, 20, 22), the second stack extending conformally in the second cavity (28), and an air pocket (37) is located in the second cavity (28) and partially defined by the second stack (30, 32, 34).

[0097] The device (10) includes a second layer (36) enclosing each second cavity (28) and partially defining an air pocket (37) located within the second cavity.

[0098] Each first zone (17) is covered with a third layer (38) made of the material of the second layer (36).

[0099] The second layer (36) extends within the second cavity (28) for less than 20% of the height of the second cavity.

[0100] Each air pocket (37) extends to at least half the height of the first cavity (16).

[0101] A trench (27) surrounding at least two adjacent capacitors (12) includes a common portion.

[0102] The trenches (27) surrounding at least two adjacent capacitors (12) are separated from each other by portions (50) of the first layer.

[0103] The device comprises a filter, the capacitor forming a part of the filter.

[0104] The method includes forming a first cavity and a second cavity in a first layer; forming a third stack of two conductive layers conformally separated by an insulating layer in a conformal form, the first cavity is filled and the second cavity is not filled, forming a fourth non-conformal layer enclosing the second cavity; etching the third stack and the fourth layer in the third region to form the first stack and the second stack and the second layer and the third layer.

[0105] The formation of the fourth layer is performed by a physical vapor deposition method or a plasma enhanced chemical vapor deposition method.

[0106] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

[0107] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalent forms granted by these claims. Therefore, the claims are not limited by the present disclosure.

Claims

1. An electronic device comprising: a first insulating layer; at least two three-dimensional capacitors in the first insulating layer; as well as A plurality of trenches are formed in the first insulating layer around the at least two capacitors, each trench of the plurality of trenches comprising an air pocket. The device of claim 1 , wherein the first insulating layer comprises a first plurality of cavities.

3. The device of claim 2, wherein each capacitor is located in a first region of the first insulating layer, each trench is located in a second region of the first insulating layer, and the second region of the first insulating layer is separated from the first region along the first direction by a third region of the first insulating layer. 4 . The device of claim 3 , wherein each capacitor comprises a first stack of two conductive layers separated by a second insulating layer, the first stack extending over a first region of the first insulating layer and filling the first plurality of cavities. 5 . The device of claim 4 , wherein each trench of the plurality of trenches comprises a second stack having the same layers as the first stack, the second stack extending into the second cavity, the air pocket being located in the second cavity. 6 . The device of claim 5 , wherein each first stack is separated from the corresponding second stack along the first direction by a first gap, and each first gap overlaps with the corresponding third region. 7 . The device of claim 5 , comprising a second layer enclosing each of the plurality of trenches and partially defining an air pocket within the second cavity. 8 . The device according to claim 7 , wherein each first region is covered by a third layer made of the material of the second layer. 9 . The device of claim 7 , wherein the second layer extends in the second cavity along a second direction perpendicular to the first direction to less than 20% of the depth of the second cavity.

10. The device of claim 6, wherein each air pocket extends along the second direction to at least half of the depth of the first cavity. 11 . The device of claim 1 , wherein the plurality of trenches surrounding the at least two capacitors are shared by the at least two capacitors. 12 . The device of claim 1 , wherein the plurality of trenches surrounding the at least two capacitors are separated from each other by portions of a first insulating layer.

13. The device of claim 1, wherein the device comprises a filter comprising the at least two capacitors.

14. A method comprising: forming a first plurality of cavities and a second plurality of cavities in the first surface of the first layer; forming a first stack of two conductive layers separated by an insulating layer on the first surface, the first stack being located in the first plurality of cavities and the second plurality of cavities, the first plurality of cavities being completely filled; forming a second layer on the first stack, the second layer enclosing the second plurality of cavities; as well as The first stack and the second layer are etched to form a first plurality of gaps between the first plurality of cavities and the second plurality of cavities. 15 . The method according to claim 14 , wherein forming the second layer is performed by a physical vapor deposition method or by a plasma enhanced chemical vapor deposition method.

16. The method of claim 14, wherein each of the second plurality of cavities comprises a gas-filled opening.

17. A device comprising: A first insulating layer having a first surface; a first plurality of trenches extending in the first insulating layer from the first surface along a first direction; a second plurality of grooves separated from the first plurality of grooves along a second direction perpendicular to the first direction, the second plurality of grooves extending from the first surface along the first direction; an air-filled cavity in each groove of the second plurality of grooves; as well as A first stack of layers in the first plurality of trenches.

18. The device of claim 17, wherein the first stack of layers comprises: a first conductive layer directly on the substrate in the first plurality of trenches; a second insulating layer on the first conductive layer; as well as The second conductive layer is on the second insulating layer.

19. The device of claim 18, further comprising a second stack of layers in each trench in the second plurality of trenches, the second stack of layers separated from the first stack of layers along a second direction.

20. The device of claim 19, further comprising a first capping layer on the second plurality of trenches.

Citation Information

Patent Citations

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