Structure of silicon carbide device for reducing contact resistance and manufacturing method thereof

Abstract

The invention discloses a structure of a silicon carbide device for reducing contact resistance. The structure comprises a silicon carbide substrate; the heavily-doped recrystallization layer is located in an area where ohmic contact needs to be manufactured on the surface of the silicon carbide substrate, and a metal film is deposited on the surface of the heavily-doped recrystallization layer so as to reduce the contact resistance between the metal film and the silicon carbide substrate. The semiconductor device has the advantages that relatively small contact resistance can be obtained, so that the current driving capability of the semiconductor device can be improved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a structure of a silicon carbide device with reduced contact resistance and a manufacturing method thereof. Background Art

[0002] As a new type of compound semiconductor material, silicon carbide (SiC) has the characteristics of large bandgap (three times that of Si), high thermal conductivity (three times that of Si), high saturated electron drift velocity (twice that of Si) and high breakdown field strength (eight times that of Si) compared with traditional silicon (Si) materials. Especially in the power device market, SiC devices have very broad application prospects.

[0003] However, in the manufacturing process of SiC power devices, the manufacturing process of electrodes has always been the focus and difficulty. Usually, the electrode is electrically connected to the silicon carbide substrate through a metal lead or a metal film on the back, and the metal lead or the metal film on the back is electrically connected to the silicon carbide substrate through an ohmic contact. This leads to a problem, that is, the contact resistance between the silicon carbide material and the metal material is too large, which affects the input or output current capability of the silicon carbide device. Therefore, for silicon carbide devices, it is necessary to reduce the contact resistance as much as possible, so that the switching resistance of the silicon carbide device is smaller and the performance is further improved. Summary of the invention

[0004] In order to solve the above problems in the prior art, the present invention provides a structure of a silicon carbide device with reduced contact resistance and a method for manufacturing the same.

[0005] In a first aspect, the present invention provides a structure of a silicon carbide device with reduced contact resistance, comprising:

[0006] Silicon carbide substrate;

[0007] The heavily doped recrystallized layer is located in the area on the surface of the silicon carbide substrate where ohmic contact needs to be made. A metal film is deposited on the surface of the heavily doped recrystallized layer to reduce the contact resistance between the metal film and the silicon carbide substrate.

[0008] In a possible implementation of the first aspect above, the structure above further includes: the region where the ohmic contact needs to be made includes a source terminal and a drain terminal.

[0009] In a possible implementation of the first aspect above, the above structure further includes: an impurity concentration in the heavily doped recrystallized layer is greater than 1E18 cm-3.

[0010] In a possible implementation of the first aspect above, the structure above also includes: a main crystal type in the heavily doped recrystallized layer is 3C-SiC.

[0011] In a second aspect, the present invention further provides a method for manufacturing a silicon carbide device with reduced contact resistance, comprising:

[0012] Performing photolithography on the surface of the device to expose a first area where an ohmic contact needs to be made;

[0013] Implanting the first region with the same impurities as those doped in the first region to obtain a first amorphized region, wherein the doping concentration of the impurities is greater than 1E14 cm-2;

[0014] Cleaning residual glue, and performing photolithography on the surface of the device again to expose a second area where an ohmic contact needs to be made;

[0015] implanting the second region with the same impurities as those doped in the second region to obtain a second amorphized region, wherein the doping concentration of the impurities is greater than 1E14 cm-2;

[0016] Cleaning the residual glue, and performing laser annealing on the amorphized region to obtain a heavily doped recrystallized layer, wherein the amorphized region includes the first amorphized region and the second amorphized region;

[0017] A metal film is formed on the heavily doped recrystallized layer to reduce the contact resistance between the metal film and the silicon carbide substrate.

[0018] In a possible implementation of the second aspect, the manufacturing method further includes: the method of injecting impurities includes ion implantation, molecular implantation, molecular cluster implantation, plasma immersion implantation, and any combination of the above implantation methods.

[0019] In a possible implementation of the second aspect, the manufacturing method further includes: a method of injecting impurities includes injection with glue or injection without glue.

[0020] In a possible implementation of the second aspect, the manufacturing method further includes: a main crystal type in the heavily doped recrystallized layer is 3C-SiC.

[0021] In a possible implementation of the second aspect, the manufacturing method further includes: when performing laser annealing, the surface temperature of the amorphized region is maintained greater than 1000 degrees Celsius, and the laser wavelength range is 100 nanometers to 10 micrometers.

[0022] In a possible implementation of the second aspect, the manufacturing method further includes: before laser annealing the amorphized region, depositing a protective layer on the surface thereof.

[0023] In a possible implementation of the second aspect, the manufacturing method further includes: the protective layer includes a carbon film.

[0024] In a possible implementation of the second aspect, the manufacturing method further includes: the impurity concentration in the amorphized region is greater than 1E18 cm-3.

[0025] In a third aspect, the present invention further provides a method for manufacturing a silicon carbide device with reduced contact resistance, comprising:

[0026] Performing photolithography on the surface of the device to expose a first area where an ohmic contact needs to be made;

[0027] Implanting the first region with the same impurities as those doped in the first region to obtain a first amorphized region, wherein the doping concentration of the impurities is greater than 1E14 cm-2;

[0028] Cleaning residual glue, and performing photolithography on the surface of the device again to expose a second area where an ohmic contact needs to be made;

[0029] implanting the second region with the same impurities as those doped in the second region to obtain a second amorphized region, wherein the doping concentration of the impurities is greater than 1E14 cm-2;

[0030] Cleaning residual glue and forming a carbon film on the surface of the device;

[0031] Performing high temperature annealing on the amorphized region to obtain a heavily doped recrystallized layer, wherein the amorphized region includes the first amorphized region and the second amorphized region;

[0032] A metal film is formed on the heavily doped recrystallized layer to reduce the contact resistance between the metal film and the silicon carbide substrate.

[0033] In a possible implementation of the third aspect above, the above-mentioned manufacturing method also includes: before manufacturing a carbon film on the surface of the device, it also includes injecting silicon into the surface of the device, wherein the doping concentration of silicon is greater than 1E14cm-2; or depositing a thin layer of silicon on the surface of the device, wherein the thickness of the thin layer of silicon is less than 100nm.

[0034] In a possible implementation of the third aspect, the manufacturing method further includes: the method of injecting impurities includes ion implantation, molecular implantation, molecular cluster implantation, plasma immersion implantation, and any combination of the above implantation methods.

[0035] In a possible implementation of the third aspect, the manufacturing method further includes: a method of injecting impurities includes injection with glue or injection without glue.

[0036] In a possible implementation of the third aspect, the manufacturing method further includes: a main crystal form in the heavily doped recrystallized layer is 3C-SiC.

[0037] In a possible implementation of the third aspect, the manufacturing method further includes: the impurity concentration in the amorphized region is greater than 1E18 cm-3.

[0038] In a possible implementation of the third aspect, the manufacturing method further includes: the carbon film is manufactured by carbonizing a photoresist, or by a physical and chemical vapor deposition method.

[0039] In a possible implementation of the third aspect, the manufacturing method further includes: when performing high temperature annealing, the annealing temperature is greater than 1000 degrees Celsius, and the annealing is performed in an inert gas atmosphere.

[0040] In a possible implementation of the third aspect, the manufacturing method further includes: the inert gas includes nitrogen, argon, helium, neon and a combination thereof.

[0041] Compared with the prior art, the present application further processes the surface of the drain or source terminal on the basis of preliminarily manufacturing the drain or source terminal, further doping N-type impurities in the N-type region and further doping P-type impurities in the P-type region, and then re-crystallizes the surface of the source or drain terminal through an annealing process, thereby obtaining a heavily doped recrystallized layer. Since the heavily doped recrystallized layer has good conductivity, a relatively small contact resistance can be obtained by connecting the lead metal or the back metal and the silicon carbide substrate through the heavily doped recrystallized layer, thereby improving the current driving capability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 The crystal structures of 3C-SiC and 4H / 6H-SiC are shown respectively;

[0043] Figure 2a A schematic diagram of the structure of a planar silicon carbide VDMOS produced by a conventional process is shown;

[0044] Figure 2b A schematic diagram of the structure of a planar silicon carbide IGBT produced by conventional technology is shown;

[0045] Figure 2c A schematic diagram of the structure of a trench silicon carbide VDMOS produced by a conventional process is shown;

[0046] Figure 2d A schematic diagram of the structure of a trench silicon carbide IGBT produced by a conventional process is shown;

[0047] Figure 3 shows the energy band diagram of 4H-SiC;

[0048] Figure 4 The relationship between the work function and the Schottky barrier height difference of the metal semiconductor contact in the 4H-SiC material is shown;

[0049] Figure 5a A schematic structural diagram of a planar silicon carbide VDMOS produced according to the manufacturing method proposed in this application is shown;

[0050] Figure 5b A schematic diagram of the structure of a planar silicon carbide IGBT produced according to the manufacturing method proposed in this application is shown;

[0051] Figure 5c A schematic structural diagram of a trench silicon carbide VDMOS produced according to the manufacturing method proposed in this application is shown;

[0052] Figure 5d A schematic diagram of the structure of a trench silicon carbide IGBT produced according to the manufacturing method proposed in this application is shown;

[0053] Figure 6a -f shows a method for manufacturing a semiconductor device including a heavily doped recrystallized layer;

[0054] Figure 7a -g shows yet another method of manufacturing a semiconductor device including a heavily doped recrystallized layer. DETAILED DESCRIPTION

[0055] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0056] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items. "Include" or "include" and similar words mean that the elements or objects appearing in front of "include" or "include" cover the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect.

[0057] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0058] The embodiments of the present application will be described in further detail below in conjunction with the accompanying drawings.

[0059] As described in the background art, silicon carbide (SiC), as a new type of material, has many advantages over silicon (Sillcon) material.

[0060] Compared with silicon (Sillcon) materials, the performance of silicon carbide (SiC) materials in many aspects such as bandgap width, breakdown field strength, and electron mobility are far superior to silicon materials. In addition, silicon carbide is a complex of atoms rather than a single crystal, and it has a variety of crystal forms. The physical properties of silicon carbide of different crystal forms depend on the arrangement structure of carbon atoms and silicon atoms in the crystal. The main difference in performance lies in the relative number of carbon atoms and silicon atoms and the different structures of atomic arrangement. The most common and typical is the hexagonal structure, among which 4H-SiC, 6H-SiC and 3C-SiC are common. Table 1 shows a comparison of various properties between silicon Si, silicon carbide 4H-SiC, silicon carbide 6H-SiC and silicon carbide 3C-SiC. It can be seen from Table 1 that the above three structures of silicon carbide have an innate overwhelming advantage in high pressure, high temperature, high frequency, high current and other occasions, and are typical representatives of the third generation of semiconductors.

[0061] Table 1

[0062]

[0063]

[0064] As can be seen from Table 1, the three structures of silicon carbide have inherent overwhelming advantages in high voltage, high temperature, high frequency, high current and other occasions, and are typical representatives of the third generation of semiconductors. First, the electron breakdown field strength of silicon carbide 4H-SiC is eight times that of silicon material. Higher electron breakdown field strength brings higher breakdown voltage to semiconductor devices. The breakdown voltage of semiconductor devices made of silicon carbide materials is much higher than that of semiconductor devices made of silicon materials. Therefore, under the condition of increasing the doping density, the width of the drift region of silicon carbide power devices can be reduced, thereby reducing the size of semiconductor devices. The performance of silicon carbide VDMOS devices and silicon carbide IGBT devices made of silicon carbide is more ideal. According to some data comparison views in the industry, silicon carbide power devices, especially silicon carbide VDMOS devices and silicon carbide IGBT devices, are the next generation of devices that replace the previous generation of silicon VDMOS devices and silicon IGBT devices, and are key devices for achieving energy conservation and emission reduction goals such as carbon peak and carbon neutrality.

[0065] Figure 1 The crystal structures of 3C-SiC and 4H / 6H-SiC are shown. Due to its excellent Baliga factor, 4H-SiC is most widely used in the field of commercial high voltage and high current, and its structure is HCP (Hexagonal ClosePacked Crystal). 6H-SiC has the same crystal structure as 4H-Si. 3C-SiC has an FCC (Face Center Cubic / Face-Centered Cubic) structure, and is used in some fields such as low voltage and high temperature sensors due to its relatively narrow band gap and isotropic performance.

[0066] Figure 2a -d shows the cross-sectional structure of some semiconductor devices produced according to traditional processes.

[0067] Figure 2a The schematic diagram of the structure of a planar silicon carbide VDMOS produced by conventional technology is shown. It includes: an N-type silicon carbide substrate, a drain terminal 50 is made on the back side of the substrate (i.e., the bottom side of the figure), and a gate 30 and a source terminal 40 are made on the front side of the substrate (i.e., the top side of the figure). Lead metal or back metal needs to be made on the drain terminal 50, the gate 30 and the source terminal 40 to achieve electrical connection with the device pin. The gate oxide layer 20 is also included below the gate 30. The source terminal 40 is an N-type doped area in the P-type body region 10 (or called P well). Among them, in the conventional process, the source terminal 40 and the drain terminal 50 are usually provided with ohmic contact to the lead metal or back metal by making a metal silicide layer (metal film) on the N-type silicon carbide substrate. And the contact resistance of the ohmic contact is expected to be as small as possible.

[0068] Figure 2b The schematic diagram of the structure of a planar silicon carbide IGBT produced by conventional technology is shown. It includes: an N-type silicon carbide substrate, a P-type region is made on the back side (i.e., the bottom side in the figure) of the N-type silicon carbide substrate, a drain terminal 50 is made on the P-type region, and a gate 30 and a source terminal 40 are made on the front side (i.e., the top side in the figure). Lead metal or back metal needs to be made on the drain terminal 50, the gate 30 and the source terminal 40 to achieve electrical connection with the device pin. The gate oxide layer 20 is also included below the gate 30. The source terminal 40 is an N-type doped region in the P-type body region 10 (or called P well). Among them, in the conventional process, the source terminal 40 and the drain terminal 50 are usually provided with ohmic contact to the lead metal or back metal by making a metal silicide layer on the N-type silicon carbide substrate. And the contact resistance of the ohmic contact is expected to be as small as possible.

[0069] Figure 2c The schematic diagram of the structure of a trench silicon carbide VDMOS produced by conventional technology is shown. It includes: an N-type silicon carbide substrate, a drain terminal 50 is made on the back side of the substrate (i.e., the bottom side of the figure), and a gate 30 and a source terminal 40 are made on the front side of the substrate (i.e., the top side of the figure). Lead metal or back metal needs to be made on the drain terminal 50, the gate 30 and the source terminal 40 to achieve electrical connection with the device pins. The source terminal 40 is an N-type doped area in the P-type body region 10 (or called P well). Among them, in the conventional process, the source terminal 40 and the drain terminal 50 are usually provided with ohmic contact to the lead metal or back metal by making a metal silicide layer on the N-type silicon carbide substrate. And the contact resistance of the ohmic contact is expected to be as small as possible.

[0070] Figure 2d The schematic diagram of the structure of a trench silicon carbide IGBT produced by conventional technology is shown. An N-type silicon carbide substrate is provided with a P-type region on the back side (i.e., the bottom side in the figure), a drain terminal 50 is provided on the P-type region, and a gate 30 and a source terminal 40 are provided on the front side (i.e., the top side in the figure). Lead metal or back metal needs to be provided on the drain terminal 50, the gate 30 and the source terminal 40 to achieve electrical connection with the device pins. The source terminal 40 is an N-type doped region in the P-type body region 10 (or P-well). Among them, in conventional technology, the source terminal 40 and the drain terminal 50 are usually provided with ohmic contact to the lead metal or back metal by making a metal silicide layer on the N-type silicon carbide substrate. The contact resistance of the ohmic contact is expected to be as small as possible.

[0071] Figure 3 An energy band diagram of 4H-SiC including the vacuum level is shown. Figure 4 The relationship between the work function and Schottky barrier height difference of the metal semiconductor contact in 4H-SiC material is shown.

[0072] like Figure 3 As shown in the figure, the electron affinity of the commonly used 4H-SiC is about 3.8eV, and the band gap at room temperature is 3.26eV. Therefore, the work function of the ideal contact metal for n-type 4H-SiC ohmic contact should be lower than 4eV, and the P-type should be greater than 7eV. This metal selection range is greatly limited. There are still some options for N-type, but it is very difficult to choose a heshhi metal for P-type. Figure 4 For wide bandgap materials such as silicon carbide, due to the existence of high electric field, the barrier thickness is very thin, and its tunneling current is determined by thermal electron field emission. Its contact resistivity is calculated by the classic tunneling effect leakage current formula, which is consistent with exp{φ B / (N d ) 1 / 2} is proportional to (where φ B is the metal semiconductor barrier height, Nd is the doping concentration). So if a lower φ B and a higher doping concentration Nd, a lower contact resistance can be obtained. For different crystal types, φ B The metal semiconductor barrier height is basically proportional to the bandgap width. The bandgap width of 4H-SiC is 0.2eV larger than that of 6H-SiC. B It is also 0.2eV larger; for 3C-SiC and 4H-SiC, due to the bandgap width φ of 3C-SiC B 0.9eV smaller, the corresponding barrier height will be 0.9eV lower. Considering the contact resistivity and φ B It is directly proportional to the exponential of , and it can be predicted that the ohmic contact performance of 3C-SiC will be much better than that of 4H-SiC. This effect is particularly important for P-type.

[0073] In addition, 3C-SiC is the crystal form that is most easily produced and exists in the conventional crystal growth process. Most of the SiC crystal structures in polycrystalline exist in 3C-SiC. The crystal form formed by deviation from the equilibrium state during the crystal growth and epitaxy process is mainly 3C-SiC. Therefore, if it is a recrystallization and polycrystalline process, 3C-SiC should be the main crystal form.

[0074] For the doping problem, to obtain a lower resistivity, a higher doping concentration is required according to the formula, and the contact resistivity is inversely proportional to the square root of the doping concentration. As shown in Table 2, various impurities have a certain solid solubility limit. Beyond the solid solubility limit, silicon carbide deviates from the equilibrium state, the lattice distortion increases, and strong stress is formed, which is released by a large number of defects. In this case, a strong annealing is required to destroy the current lattice status, or form a polycrystalline structure, or solid phase epitaxial growth, so as to obtain a doping concentration that exceeds that of a general single crystal. This process can be achieved through various process methods.

[0075] Table 2

[0076] Ionization energies and solubility limits of nitrogen, phosphorus, aluminum, and boron in major SiC polytypes

[0077]

[0078] The present invention uses a specific manufacturing process to form a highly doped polycrystalline structure or 3C-SiC at the location where an ohmic contact (low contact resistance) is required, thereby reducing the resistance of the ohmic contact.

[0079] Figure 5a -d corresponds to Figure 2a -d shows the formation of a highly doped polycrystalline structure at a specific location proposed in the present application. This junction can reduce the contact resistance between the metal film 70 and the silicon carbide substrate.

[0080] in, Figure 5a The schematic diagram of the structure of a planar silicon carbide VDMOS produced according to the manufacturing method proposed in this application is shown. Figure 2a In comparison, Figure 5a In the structure shown, a heavily doped recrystallized layer 60 is added above the source terminal 40 and the P-type body region 10 (or called P-well). The heavily doped recrystallized layer 60 covers most of the surface of the source terminal 40 and the body diode region 11 in the P-type body region 10. The heavily doped recrystallized layer 60 has a polycrystalline structure, in which the main crystal type is 3C-SiC. When a semiconductor material contacts a metal, a barrier layer is often formed, but when the doping concentration in the semiconductor material is very high, electrons can pass through the barrier layer based on the tunneling effect, thereby forming a low-resistance ohmic contact at the contact interface between the semiconductor material and the metal. As mentioned above, the size of the contact resistance is very important to semiconductor devices, and the formation of a good ohmic contact (low contact resistance) is beneficial to the input or output of current in semiconductor devices. The heavily doped recrystallized layer 60 is located between the silicon carbide substrate and the metal film 70. The metal film 70 is a base for connecting the lead metal or the back metal. When the metal film 70 has a good ohmic contact with the silicon carbide substrate, the pins / pins for outputting or inputting signals outward in the semiconductor device can have good conductivity and can stably provide a channel for signal conduction. The heavily doped recrystallized layer 60 is a structural layer that is heavily doped and contains a large amount of 3C-SiC. Free electrons can flow based on the tunneling effect. That is, the contact resistance between the heavily doped recrystallized layer 60 and the metal film 70 (or between the metal film 70 and the substrate) can be greatly reduced, thereby improving the performance of the silicon carbide VDMOS.

[0081] The structure of the source terminal 40 is described above as an example. For the drain terminal 50, the same structure can also be used to achieve the effect of low contact resistance. Figure 5a As shown in

[0082] Figure 5b The schematic diagram of the structure of a planar silicon carbide IGBT produced according to the manufacturing method proposed in this application is shown. Figure 5a Similar, no further elaboration is needed here.

[0083] Figure 5c The structure diagram of a trench type silicon carbide VDMOS produced according to the manufacturing method proposed in this application is shown. Figure 5a Similar, no further elaboration is needed here.

[0084] Figure 5d The schematic diagram of the structure of a trench type silicon carbide IGBT produced according to the manufacturing method proposed in this application is shown. Figure 5a Similar, no further elaboration is needed here.

[0085] The following Figure 6a -f is used to illustrate the method for manufacturing the semiconductor device including the heavily doped recrystallized layer 60. Figure 6a -f only illustrates the process of manufacturing the heavily doped recrystallized layer 60 on the source terminal 40, and a similar manufacturing method can also be applied to the drain terminal 50, so that the contact resistance of the drain terminal is also greatly reduced.

[0086] First, the source terminal 40, the gate 30 and the drain terminal 50 are manufactured according to conventional processes. Specifically, a clean N-type silicon carbide epitaxial wafer is prepared, and when the source terminal 40 is processed, it is manufactured on the silicon surface (front side) (when the drain terminal 50 needs to be processed, it is manufactured on the carbon surface, that is, the back side). Then, photolithography, etching, film formation, ion implantation and other methods are used to manufacture the P-type body region (P-body or P-well) 10. Then, the surface is cleaned, an oxide layer 20 is grown in the gate area, and polysilicon material is deposited on the oxide layer 20, and then photolithography, etching, film formation, ion implantation and other methods are used to define and manufacture the gate 30. Then, the source terminal (source) 40 is formed by oxidation or deposition film formation, implantation, photolithography, etching and other methods.

[0087] On the basis of the source terminal 40 and the gate 30 manufactured by the conventional process, the present application further proposes that the surface of the P-type body region 10 and the source terminal 40 needs to be in contact with the metal film 70 (refer to Figure 5a -d) A film layer structure with good conductive properties is produced in the contact area, thereby reducing the contact resistance between the metal film and the substrate.

[0088] Specifically, Figure 6aAs shown, a photoresist 41 is applied to the front of the device, and then photolithography is performed to expose the surface of the portion of the source terminal 40 that needs to be ion implanted (i.e., the first area where the ohmic contact needs to be made). The surface of the portion of the source terminal 40 that needs to be ion implanted refers to the portion of the surface that needs to contact the metal film 70 in the subsequent manufacturing steps. Then, as shown in FIG. Figure 6b As shown, a high dose of N-type impurities is implanted into the exposed surface. The N-type impurities can be implanted by ion implantation, molecular implantation, molecular cluster implantation, plasma immersion implantation, or any combination of the above implantation methods, and the implantation concentration is greater than 1E14cm-2. After the implantation, the crystal structure of the implanted part needs to be close to or completely amorphous to form an amorphous layer 61, and the N-type doping concentration of the amorphous layer 61 is greater than 1E18cm-3.

[0089] Next, remove the residual glue, re-apply photoresist 42, and then perform photolithography to expose the Figure 6c The surface of the body diode region 11 (i.e., the second region where an ohmic contact is to be made) shown in FIG. The surface of the body diode region 11 needs to be in contact with the metal film 70 in the subsequent manufacturing steps. Then, as shown in FIG. Figure 6d As shown, a high dose of P-type impurities is implanted into the exposed surface. The P-type impurities can also be implanted by ion implantation, molecular implantation, molecular cluster implantation, plasma immersion implantation, or any combination of the above implantation methods, and the implantation concentration is greater than 1E14cm-2. After the implantation, the crystal structure of the implanted part needs to be close to or completely amorphous, that is, the amorphous layer 61 is Figure 6b The amorphized layer 61 is expanded on the basis shown in the figure, and the entire amorphized layer 61 covers the body diode region 11 and part of the source terminal 40. And similarly to the above, the P-type doping concentration of the part of the amorphized layer 61 corresponding to the body diode region 11 is greater than 1E18 cm-3.

[0090] Next, remove all residual glue and clean to expose the entire device surface, then Figure 6e As shown, a high dose of silicon Si is implanted into the surface of the entire device, and the implanted concentration is greater than 1E14cm-2. The implantation of silicon is beneficial to reduce the loss of silicon in the subsequent high temperature environment and to make it easier to form 3C-SiC. The implantation of silicon is a supplementary measure, and its execution is flexible. In some embodiments, it can be performed in multiple times (or repeatedly) to meet the needs of making up for the silicon that may be lost in the subsequent process. In other embodiments, the steps of implanting silicon can be performed in Figure 6b and Figure 6d Then, it is performed in different regions. Even, it may not be performed in some embodiments.

[0091] Finally, the amorphous layer 61 is laser annealed to regenerate crystals, and the following is obtained: Figure 6f The heavily doped recrystallized layer 60 shown. When laser annealing is performed, the surface temperature of the region of the amorphized layer 61 needs to be maintained at greater than 1000 degrees Celsius, and the laser wavelength is from 100 nanometers to 10 microns, so that the amorphous formation in this region is recrystallized or localized solid phase nucleation, recrystallization, merging or solid phase epitaxy occurs, thereby forming a surface of a polycrystalline structure (i.e., the heavily doped recrystallized layer 60). According to the principle description previously described in this specification, the crystal type in the heavily doped recrystallized layer 60 is mainly 3C-SiC, and the impurity doping concentration therein is very high, greater than 1E18cm-3, which is conducive to reducing the contact resistance. In other embodiments, a protective layer can also be deposited on the surface of the device before laser annealing, for example, the photoresist is carbonized to form a carbon film to protect the surface of the device. Alternatively, physical and chemical vapor phase methods can also be used for deposition.

[0092] Afterwards, the conventional silicon carbide VDMOS manufacturing process can be used to complete the normal process of the device using semiconductor process lithography, etching, cleaning, film formation, ion implantation, planarization and other processes to complete the entire device manufacturing. Figure 5a The structure of the planar silicon carbide VDMOS is shown.

[0093] Figure 5b The manufacturing method of the device structure shown in -d is similar to the manufacturing method of the planar silicon carbide VDMOS structure, which will not be described in detail here.

[0094] In the production process described above, only Figure 6a -f order is used to illustrate, but those skilled in the art should know that Figure 6a -f is not used to limit the order of step execution, for example, Figure 6a The steps shown in -b can also be Figure 6c -d to execute the steps indicated. For example, Figure 6e In the step of implanting high-dose Si shown in -f, if ion implantation is used, the Figure 6a -b The steps shown and Figure 6c -d is executed in the steps shown, that is, it can be executed after Figure 6a After the step of implanting N-type ions shown in FIG. 1-b, high-dose Si implantation is performed directly in the source end 40 region. Figure 6c After the step of implanting P-type ions shown in -d, high-dose Si implantation is performed directly in the body diode 11 region without waiting until the amorphous layer 61 is completely formed.

[0095] Figure 7a -g shows another production process under the same concept. Figure 6aThe difference between the manufacturing process shown in FIG. 1 and FIG. 2 is that the source terminal 40 is first manufactured according to the conventional process, and the gate 30 is not manufactured. In other words, a dummy gate 30 and a gate oxide layer 20 are manufactured according to the process requirements, and then the dummy gate 30 and the gate oxide layer 20 are removed at the appropriate nodes to expose the silicon carbide surface. Then, the same process as Figure 6a -e Similar Figure 7a -e step to obtain an amorphous layer 61.

[0096] The difference is that Figure 7e In the steps shown, silicon Si can be deposited in a variety of ways, for example, by injection, sputtering, or a combination of the above two methods to form the device surface. The thickness of the silicon is less than 100nm, and more preferably, less than

[0097] Another difference is that in the subsequent steps, since the gate 30 has not yet been made, Figure 7f As shown, a layer of carbon film 43 is covered on the surface of the entire device for protection, and then a high temperature annealing is performed in an inert gas atmosphere, rather than a laser annealing method, to transform the amorphous layer 61 into a heavily doped recrystallized layer 60. And, after the heavily doped recrystallized layer 60 is formed, Figure 7g As shown, the gate 30 is continuously manufactured in the gate region. The inert gas may be any one of nitrogen, argon, helium and neon, or a mixture of two or more of nitrogen, argon, helium and neon.

[0098] In the above-mentioned embodiment, the gate is manufactured after annealing, which avoids the possibility of the gate material reacting with the substrate under the annealing condition and improves the reliability of the device.

[0099] In summary, the present application, based on the preliminary preparation of the drain or source terminal, continues to process the surface of the drain or source terminal, continues to dope N-type impurities in the N-type region, and continues to dope P-type impurities in the P-type region, and then uses an annealing process to make the surface of the source or drain terminal crystallize again, thereby obtaining a heavily doped recrystallized layer. Since the heavily doped recrystallized layer has good conductivity, a relatively small contact resistance can be obtained by connecting the lead metal or the back metal and the silicon carbide substrate through the heavily doped recrystallized layer, thereby improving the current driving capability of the semiconductor device.

[0100] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0101] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A structure of a silicon carbide device with reduced contact resistance, characterized in that: include: Silicon carbide substrate; The heavily doped recrystallized layer is located in the area on the surface of the silicon carbide substrate where ohmic contact needs to be made. A metal film is deposited on the surface of the heavily doped recrystallized layer to reduce the contact resistance between the metal film and the silicon carbide substrate.

2. The structure according to claim 1, characterized in that The region where ohmic contact needs to be made includes a source terminal and a drain terminal.

3. The structure according to claim 1, characterized in that The impurity concentration in the heavily doped recrystallized layer is greater than 1E18 cm-3.

4. The structure according to claim 1, characterized in that The main crystal type in the heavily doped recrystallized layer is 3C-SiC.

5. A method for manufacturing a silicon carbide device with reduced contact resistance, characterized in that: include: Performing photolithography on the surface of the device to expose a first area where an ohmic contact needs to be made; Implanting the first region with the same impurities as those doped in the first region to obtain a first amorphized region, wherein the doping concentration of the impurities is greater than 1E14 cm-2; Cleaning residual glue, and performing photolithography on the surface of the device again to expose a second area where an ohmic contact needs to be made; implanting the second region with the same impurities as those doped in the second region to obtain a second amorphized region, wherein the doping concentration of the impurities is greater than 1E14 cm-2; Cleaning the residual glue, and performing laser annealing on the amorphized region to obtain a heavily doped recrystallized layer, wherein the amorphized region includes the first amorphized region and the second amorphized region; A metal film is formed on the heavily doped recrystallized layer to reduce the contact resistance between the metal film and the silicon carbide substrate.

6. The method according to claim 5, characterized in that: Before laser annealing the amorphized region, the method further includes implanting silicon into the surface of the device, wherein the doping concentration of silicon is greater than 1E14 cm-2.

7. The method according to claim 5, characterized in that: The methods of implanting impurities include ion implantation, molecular implantation, molecular cluster implantation, plasma immersion implantation, and any combination of the above implantation methods.

8. The method according to claim 5, characterized in that: The method of injecting impurities includes injection with glue or injection without glue.

9. The method according to claim 5, characterized in that: The main crystal type in the heavily doped recrystallized layer is 3C-SiC.

10. The manufacturing method according to claim 5, characterized in that: The impurity concentration in the amorphized region is greater than 1E18 cm-3.

11. The method according to claim 5, characterized in that: When laser annealing is performed, the surface temperature of the amorphized region is maintained at more than 1000 degrees Celsius, and the laser wavelength ranges from 100 nanometers to 10 micrometers.

12. The method according to claim 5, characterized in that: Before laser annealing the amorphized region, a protective layer is deposited on its surface.

13. The method according to claim 12, characterized in that: The protective layer includes a carbon film.

14. A method for manufacturing a silicon carbide device with reduced contact resistance, characterized in that: include: Performing photolithography on the surface of the device to expose a first area where an ohmic contact needs to be made; Implanting the first region with the same impurities as those doped in the first region to obtain a first amorphized region, wherein the doping concentration of the impurities is greater than 1E14 cm-2; Cleaning residual glue, and performing photolithography on the surface of the device again to expose a second area where an ohmic contact needs to be made; implanting the second region with the same impurities as those doped in the second region to obtain a second amorphized region, wherein the doping concentration of the impurities is greater than 1E14 cm-2; Cleaning residual glue and forming a carbon film on the surface of the device; Performing high temperature annealing on the amorphized region to obtain a heavily doped recrystallized layer, wherein the amorphized region includes the first amorphized region and the second amorphized region; A metal film is formed on the heavily doped recrystallized layer to reduce the contact resistance between the metal film and the silicon carbide substrate.

15. The manufacturing method according to claim 14, characterized in that: Before manufacturing the carbon film on the device surface, the method further includes implanting silicon into the device surface, wherein the doping concentration of silicon is greater than 1E14cm-2; or depositing a thin layer of silicon on the device surface, wherein the thickness of the thin layer of silicon is less than 100nm.

16. The method of claim 14, wherein: The methods of implanting impurities include ion implantation, molecular implantation, molecular cluster implantation, plasma immersion implantation, and any combination of the above implantation methods.

17. The manufacturing method according to claim 14, characterized in that: The method of injecting impurities includes injection with glue or injection without glue.

18. The manufacturing method according to claim 14, characterized in that: The main crystal type in the heavily doped recrystallized layer is 3C-SiC.

19. The method of claim 14, wherein: The impurity concentration in the amorphized region is greater than 1E18 cm-3.

20. The method of claim 14, wherein: The carbon film is manufactured by carbonizing photoresist or by physical and chemical vapor deposition methods.

21. The method of claim 14, wherein: When high temperature annealing is performed, the annealing temperature is greater than 1000 degrees Celsius, and the annealing is performed in an inert gas atmosphere.

22. The method of claim 21, wherein: The inert gas includes nitrogen, argon, helium, neon and combinations thereof.

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