Nanosheet device

Abstract

Provided herein is a nanosheet device comprising: a first transistor structure and a second transistor structure, each transistor structure comprising a source region, a drain region, and a channel region extending between the source region and the drain region, a dielectric wall, a gate structure, and a gate spacer, wherein the channel region of the first transistor structure comprises a first set of vertically stacked channel layers, and wherein the channel region of the second transistor structure comprises a second set of vertically stacked channel layers, and wherein a top portion of the gate structure is arranged over a top surface of the dielectric wall, and wherein a material of the gate spacer is arranged at a third side surface and a fourth side surface of the dielectric wall, the third side surface and the fourth side surface being transverse to the first side surface and the second side surface of the dielectric wall.

Description

Technical Field

[0001] The present disclosure relates to nanosheet devices. Background Art

[0002] In order to provide a more area-efficient circuit design, non-planar transistor devices such as FinFET and horizontal or lateral nanosheet FET (NSHFET) have been developed. In NSHFET, multiple nanosheets can be stacked in the vertical dimension to provide an increased drive current with a reduced horizontal footprint. A more recent NSHFET design is a so-called fork-sheet device. The fork-sheet device includes two transistors of complementary conductivity types, which include a corresponding set of vertically stacked channel nanosheets on opposite sides of a vertically oriented dielectric wall. The transistors are controlled by corresponding gate stacks separated by dielectric walls. The dielectric wall can be formed before gate patterning and source / drain epitaxy S / D epi, and thus can facilitate separate processing of N-type and P-type source / drain regions and gate stacks for the two transistors. Therefore, the fork-sheet device enables aggressive scaling of the N to P spacing.

[0003] However, nanosheet devices in general, and forksheet devices in particular, remain challenged due to their continued miniaturization, and improvements are therefore needed to overcome difficulties associated therewith, such as avoiding N / P merging at the dielectric walls, and / or reducing the relatively large number of etch-back steps during replacement metal gate RMG formation. In addition, the relatively narrow walls typically present in forksheet devices complicate (fin) formation when etching the nanosheet stack. Summary of the invention

[0004] The aim is to provide an overall improved nanosheet device.

[0005] Another object is to provide a nanosheet device associated with reduced epitaxial source / drain and gate metal shorts.

[0006] Yet another object is to provide a nanosheet device with a smaller footprint.

[0007] Yet another object is to provide a nanosheet device with lower capacitance at the cell level.

[0008] Yet another object is to provide a nanosheet device with reduced parasitic series resistance.

[0009] Yet another object is to provide a nanosheet device that is easier to manufacture.

[0010] Other objects or further objects may be understood from the following.

[0011] According to a first aspect of the inventive concept, a nanosheet device is provided, the nanosheet device comprising: first and second transistor structures, each transistor structure comprising a source region, a drain region and a channel region extending between the source region and the drain region, a dielectric wall, a gate structure, and a gate spacer, wherein the channel region of the first transistor structure comprises a first group of vertically stacked channel layers, wherein each channel layer in the first group of vertically stacked channel layers has an inwardly facing surface contacting a first side surface of the dielectric wall, and wherein the channel region of the second transistor structure comprises a second group of vertically stacked channel layers, wherein each channel layer in the second group of vertically stacked channel layers has an inwardly facing surface contacting a second side surface of the dielectric wall opposite to the first side surface, wherein a top portion of the gate structure is arranged above a top surface of the dielectric wall, and wherein a material of the gate spacer is also arranged at a third side surface and a fourth side surface of the dielectric wall, the third side surface and the fourth side surface being transverse to the first side surface and the second side surface of the dielectric wall.

[0012] Thus, it will be appreciated that the dielectric wall is surrounded by the first and second sets of vertically stacked channel layers, gate structures and gate spacers. This is in contrast to conventional fork-sheet devices, where the dielectric wall is also present in the S / D region.

[0013] This geometrical configuration of the layers / components facilitates easier manufacturing, as the dielectric walls can be made relatively wide without compromising the footprint of the nanosheet device. In other words, the distance between the two vertically stacked channel layers can be relatively large. Thus, the "width" of the dielectric wall is understood as the (closest) distance between the first and second sets of vertically stacked channel layers, i.e. along a horizontal extension transverse to the electron / hole transport direction in one of the nanosheets.

[0014] The present nanosheet device also facilitates the survival of the dielectric wall material during front-end FEOL processing.

[0015] Furthermore, conventional fork-sheet devices usually require relatively high dielectric walls to avoid n / p merging at the walls, resulting in a taller gate. This can be prevented by the proposed inventive concept.

[0016] The spatial terms used herein, such as "horizontal" and "vertical", are to be understood as relating to the substrate on which the transistor structure is to be placed or manufactured, wherein "horizontal" means an orientation or direction parallel to the main extension plane of the substrate, and "vertical" means an orientation or direction perpendicular to the main extension plane of the substrate. Throughout the text, if not otherwise specified, the term "longitudinal" refers to the extension of the channel in which charge transfer occurs, i.e. along the channel. Accordingly, relative spatial terms, such as "upper", "lower", "top", "bottom", "above", "below", "below", "under", are to be understood as relating to the substrate, as seen in the vertical / normal direction.

[0017] The terms "front side" and "back side" of a substrate (on which the nanosheet device is arranged) refer to the two mutually opposite (primary) sides of the substrate, where the front side is the side of the substrate on which the transistors (and any other active devices) are formed, and the back side is the opposite side of the substrate.

[0018] The term "source / drain" used herein should be understood as a source or a drain. Therefore, a "source / drain region" can be a source region or a drain region.

[0019] Preferably, a top surface of the dielectric wall is flush with a top surface of the channel region of the first transistor structure and a top surface of the channel region of the second transistor structure.

[0020] Thus, the top surface of the dielectric wall is substantially at the same vertical level as the top surface of the channel region of the first and second transistor structures. Compared to conventional fork-sheet devices where the dielectric wall protrudes vertically above the top surface of the channel region, the concept of the present invention facilitates reducing the vertical extension of the nanosheet device. This can further reduce the height of the gate structure without compromising the electrical characteristics of the device.

[0021] In various embodiments, a length of the channel region of the first transistor structure and a length of the channel region of the second transistor structure correspond to a length of the gate structure.

[0022] The above-mentioned length should be understood as the length extending along the longitudinal direction.

[0023] Preferably, a distance between the third side surface of the dielectric wall and the fourth side surface of the dielectric wall corresponds to a length of the gate structure.

[0024] Hence, the length, ie the longitudinal extension, of the dielectric wall is substantially equal to the length, ie the longitudinal extension, of the gate structure.

[0025] In various embodiments, the dielectric wall has substantially the same extension as the channel region.

[0026] Preferably, a bottom surface of the dielectric wall is arranged above the shallow trench isolation STI layer.

[0027] This is a particularly advantageous way of arranging the dielectric walls in the present device.

[0028] Preferably, the dielectric wall and the STI layer are formed of the same material.

[0029] This makes the fabrication of nanosheet devices simpler because the dielectric wall can be formed in the same step as the STI.

[0030] Preferably, one or more of the dielectric wall and the STI layer comprises an oxide or nitride material.

[0031] These materials are particularly advantageous for nanosheet devices.

[0032] Preferably, each of the first set of vertically stacked channel layers and the second set of vertically stacked channel layers includes three or more stacked channel layers.

[0033] Therefore, the present nanosheet device allows a greater number of channel layers to be stacked than is currently feasible in forksheet devices. This is because the dielectric walls are typically wider than in conventional forksheet devices. This further facilitates reducing the footprint of the nanosheet device while maintaining or increasing the number of logic gates per unit area of ​​the substrate.

[0034] Preferably, the shortest distance between the first and second side surfaces of the dielectric wall is at least 50% of the width of each of the first set of vertically stacked first channel layers and the second set of vertically stacked second channel layers.

[0035] This prevents epitaxy and gate metal shorts across the n / p devices. In addition, the (parasitic) capacitance between gate and drain can be reduced. Furthermore, the above 50% figure has proven to be a reasonable compromise in terms of performance and ease / difficulty in terms of lithography, etching and nanosheet release.

[0036] Preferably, the shortest distance between the first side surface and the second side surface of the dielectric wall is at least 10 nm.

[0037] This may facilitate manufacturing compared to devices having dielectric walls with smaller lateral dimensions.

[0038] Preferably, the first transistor structure comprises an n-FET type material and the second transistor structure comprises a p-FET type material.

[0039] This is typically the case when the nanosheet device is a forksheet device, enabling significant scaling in terms of N to P spacing that is substantially similar to the width of the dielectric wall. As will be appreciated by those skilled in the art, n-FET / p-FET type materials are therefore typically present in the S / D regions (in the form of epitaxial layers) of the transistor structure in question.

[0040] Further scope of application of the present invention will become apparent from the specific embodiments provided below. However, it should be understood that while indicating preferred embodiments of the present invention, the specific embodiments and specific examples are given by way of illustration only, because various changes and modifications within the scope of the present invention will become apparent to those skilled in the art based on the specific embodiments.

[0041] Therefore, it will be understood that the inventive concept is not limited to the specific components of the described device, or the action of the described method, because such devices and methods can change. It will also be understood that the terms used in this article are only for the purpose of describing specific embodiments, and are not intended to be restrictive. It must be noted that the articles "a (one)", "an (one)", "the (the)" and "said (said)" used in the specification and the appended claims are intended to represent the presence of one or more elements, unless the context clearly stipulates otherwise. Therefore, for example, a reference to "a unit" or "the unit" can include several units, and so on. In addition, the words "comprise", "include", "contain" and similar expressions do not exclude other elements or steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other objects, features and advantages of the inventive concept will be better understood through the following detailed description which is illustrative and non-restrictive with reference to the accompanying drawings. In the accompanying drawings, like reference numerals will be used for like elements unless otherwise specified.

[0043] FIG. 1 schematically depicts a prior art fork blade device.

[0044] Figure 2 A vertical-lateral cross-sectional profile of a nanosheet device according to an embodiment of the present invention is schematically depicted.

[0045] Figure 3A A top view of a nanosheet device according to an embodiment of the present invention is schematically shown.

[0046] Figure 3B-3D Schematically shows the Figure 3A Vertical-lateral cross-sectional profile of the nanosheet device.

[0047] Figure 4A A top view of a nanosheet device according to an embodiment of the present invention is schematically shown.

[0048] Figure 4B Schematically shows Figure 4A Vertical-longitudinal cross-sectional profile of the nanosheet device. DETAILED DESCRIPTION

[0049] The inventive concept will now be described more fully below with reference to the accompanying drawings showing currently preferred variations of the inventive concept. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided for thoroughness and completeness and to fully convey the scope of the inventive concept to those skilled in the art. Figure 3A The top view (longitudinal direction L1 versus transverse direction T1 ) of the nanosheet device 100 is schematically shown. Figure 3A Arrows 3B, 3C, and 3D in FIG. 3B refer to cross-sections extending vertically V1 and horizontally T1 of the nanosheet device. These cross-sections are Figure 3B , 3C and 3D schematically shown, that is, according to Figure 3A The arrows 3B, 3C, and 3D in the drawings are numbered.

[0050] As depicted in the attached example drawings, the nanosheet device 100 herein has a structure similar to that of a conventional forksheet device 100. FIG. 1 (Prior Art) schematically depicts a conventional forksheet device. Thus, the term "forksheet device" refers to a device 10 comprising a first group 4 and a second group 5 of vertically stacked channel layers (nanosheets) formed on opposite sides of a vertically oriented dielectric wall. Each of the first group 4 vertically stacked channel layers has an inner edge that contacts a first side of the dielectric wall 2, and each of the second group 5 vertically stacked channel layers has an inner edge that contacts a second side of the dielectric wall 2 opposite to the first side. The forksheet device 10 comprises a first gate stack 3-1 that surrounds the first group 4 vertically stacked channel layers and contacts a first side of the dielectric wall 2, and a second gate stack 3-2 that surrounds the second group 5 vertically stacked channel layers and contacts a second side of the dielectric wall 2. The first transistor may include an N-type gate stack, while the second transistor may include a P-type gate stack, or vice versa. Alternatively, both the first and second transistors may include an N-type gate stack or a P-type gate stack. Therefore, four combinations of gate stack types are possible within the scope of the claims.

[0051] Shallow trench isolation (STI) regions 1 are typically present on respective lateral sides of the gate stack, ie, trenches in the substrate on which the transistors are arranged. The material type of the STI regions is conventionally different from that of the dielectric walls 2 .

[0052] The formation of the fork-piece device 10 may be accomplished according to a process flow known to those skilled in the art, which process flow may include forming a first group 4 of vertically stacked channel layers and a second group 5 of vertically stacked channel layers by a separation trench extending into the base, thereby forming the two vertically stacked channel layers. Thereafter, the trench may be filled with a dielectric material to form a dielectric wall 2. A first gate stack 3-1 is formed that surrounds the first group 4 of vertically stacked channel layers and contacts a first side of the dielectric wall 2, and a second gate stack 3-2 that surrounds the second group 5 of vertically stacked channel layers and contacts a second side of the dielectric wall.

[0053] Thus, thus far, a conventional fork blade device 10 (FIG. 1) has been briefly described to facilitate understanding of the upcoming description of the inventive concept and its differences compared to the prior art. Figure 2 A cross section of the present nanosheet device is schematically depicted, similar to the cross section in FIG. 1 , to emphasize the structural differences compared to the prior art. Figure 2 Depicted in Figure 3B The views shown are identical views and will therefore be explained further below.

[0054] More specifically, with respect to the terms set forth in the present disclosure and claims, the nanosheet device 100 includes a first transistor structure 110 and a second transistor structure 120. Because the first transistor structure 110 and the second transistor structure 120 are generally similar in geometry, the figures occasionally indicate only a reference numeral for one of the transistor structures 110, 120, such as a reference numeral for the first transistor structure 100. Each of the first transistor structure 110 and the second transistor structure 120 includes a source region 104, 108, a drain region 102, 106, and a channel region 130 extending between the source region 104, 108 and the drain region 102, 106. Therefore, the channel region 130 can be viewed as a normal depletion region / region, in which the amount of charge carriers (electrons or holes) moving longitudinally per unit time is controlled by the voltage or potential field applied by the gate to the channel region 130. The nanosheet device 100 also includes a dielectric wall 140. The dielectric wall 140 is formed at a dielectric layer 140. Figure 3B is best seen in. Figure 3A and Figure 4A In FIG. 1 , the lateral position of the dielectric wall 140 , that is, in the L1 -T1 (longitudinal-lateral) plane is regarded as the dashed area. This position will be discussed further in detail below.

[0055] The nanosheet device 100 also includes a gate structure 150. Figure 3A and Figure 4A , when viewed from above, the gate structure 150 shields the dielectric wall 140 (dashed area).

[0056] As understood by those skilled in the art, due to the possible different types of nanosheet stacks (N-type, P-type, etc.) of the different transistor structures 110 , 120 , the gate structure 150 may be different for the first transistor structure 110 and the second transistor structure 120 . Figure 3C A cross-sectional profile of the nanosheet device 100 is shown across the gate spacer 160, i.e., in the V1-T1 (vertical-lateral) plane. At this cross-section, the first set 112 of vertically stacked channel layers and the second set 122 of vertically stacked channel layers are laterally embedded in the gate spacer 160 and the inner spacer 124 (which are present between the nanosheets).

[0057] The gate spacer 160 includes a sidewall spacer material in contact with the gate structure on top of the nanosheet stack, thereby providing isolation between the source / drain contacts and the gate contact, and the gate spacer 160 also includes material arranged at the third side surface 146 and the fourth side surface 148 of the dielectric wall 140.

[0058] The channel region 130 of the first transistor structure 110 further comprises a first set 112 of vertically stacked channel layers, ie stacked along a vertical extension V1 . Each channel layer of the first set 112 of vertically stacked channel layers has an inwardly facing surface 113 contacting a first side surface 142 of the dielectric wall 140 .

[0059] The channel region 130 of the second transistor structure 120 also includes a second group 122 of vertically stacked (i.e., stacked along a vertical extension V1) channel layers. Each of the second group 122 of vertically stacked channel layers has an inwardly facing surface 123 of a second side surface 144 that contacts the dielectric wall 140 and is opposite to the first side surface. The wording "relative" should be understood as "substantially relative" because, for example, due to the small size of the nanosheet device, there may be significant local variations in the surface. This applies to other surfaces throughout the present disclosure, as will be readily understood by those skilled in the art. As further understood, the corners may be rounded / blunt for the same reason.

[0060] A top portion 152 of the gate structure 150 is disposed above the top surface 141 of the dielectric wall 140 .

[0061] The gate spacer 160 (the material of the gate spacer 160) is arranged at the third and fourth side surfaces 146, 148 of the dielectric wall 140. The third and fourth side surfaces 146, 148 are thus transverse to the first and second side surfaces 142, 144 of the dielectric wall 140.

[0062] A top surface 141 of the dielectric wall 140 may be flush with a top surface 132 of the channel region 130 of the first transistor structure 110 and a top surface 134 of the channel region 130 of the second transistor structure 120 .

[0063] The length LC of the channel region 130, that is, the channel length LC of the first transistor structure 110 and the length LC of the channel region 130 of the second transistor structure 120, may correspond to the length LG of the gate structure 150. Therefore, the lengths LG and LC refer to the distances along the longitudinal extension L1. Figure 4A -B. It will be appreciated that this correspondence is not necessarily exact. This is because precise manufacturing obscures the components that exactly manufacture the transistor at the length scales currently involved.

[0064] A distance between the third side surface 146 of the dielectric wall 140 and the fourth side surface 148 of the dielectric wall 140 may correspond to the length LG of the gate structure 150 A bottom surface 143 of the dielectric wall 140 may be disposed over the shallow trench isolation STI layer 170 .

[0065] The dielectric wall 140 and the STI layer 170 may be formed of the same material. The dielectric wall 140 and the STI layer 170 may be formed of the same material during the same processing step. In this case, the bottom surface 143 of the dielectric wall 140 obviously coincides with the bottom surface 171 of the STI layer 170.

[0066] One or more of the dielectric wall 140 and the STI layer 170 may include an oxide or nitride material. Example materials in this regard may be SiO2 (silicon oxide), SiN, Si3N4 (silicon nitride), SiO x N y (Silicon Oxynitride) and Si.

[0067] Each of the first group 112 of vertically stacked channel layers and the second group 122 of vertically stacked channel layers may include three or more stacked channel layers 112, 122. However, within the scope of the claims, any appropriate number of stacked channel layers is possible. As an example and as shown in some of the drawings, the first group 112 and the second group 122 of vertically stacked channel layers 122 may include four stacked channel layers 112, 122.

[0068] The shortest distance WI1 between the first and second side surfaces 142 and 144 of the dielectric wall is at least 50% of the width WL1 , WL2 of each of the first and second groups 112 and 122 of vertically stacked first and second channel layers.

[0069] The shortest distance between the first side surface 142 and the second side surface 144 of the dielectric wall may be at least 10 nm. Preferably, the shortest distance between the first side surface 142 and the second side surface 144 of the dielectric wall is in the range of 5-25 nm.

[0070] The first transistor structure 100 may comprise an n-FET type material and the second transistor structure 120 may comprise a p-FET type material. The reverse is obviously also possible. Furthermore, the first transistor structure 110, or more precisely, the two epitaxial layers constituting the longitudinal ends of the respective nanosheet stack, may be doped so as to define an n-FET type or a p-FET type transistor. Preferably, the vertically stacked channel layers 112, 122 themselves are undoped, but at least optical doping of these layers is possible. As is familiar to those skilled in the art, a nanosheet stack that may be doped may exhibit different dopant distributions between the individual nanosheets of the nanosheet stack.

[0071] Figure 3D Schematically shows Figure 3A 3D. The cross-sectional profile schematically depicts the source / drain regions of a respective set of vertically stacked channel layers 112, 122. The first set 112 of vertically stacked layers may be terminated longitudinally by the N-epitaxial layers 102, 104 on respective sides of the channel region 130, while the second set 122 of vertically stacked layers 122 may be terminated longitudinally by the P-epitaxial layers 106, 108 on respective sides of the channel region 130. The N-epitaxial layers 102, 104 and the P-epitaxial layers 106, 108 are preferably surrounded by a dielectric layer 180 in a V1-T1 (vertical-lateral) plane. Preferably, the dielectric layer 180 is a first interlayer dielectric (sometimes referred to as ILD0) layer 180 located above the STI layer 170 including SiO2. The depicted pyramidal / diamond geometries of N epitaxial layer 104 and P epitaxial layer 108 may result from the crystalline growth of these materials at the S / D regions and therefore depend on the Miller indices of these materials relative to the surface on which they are grown (eg, 110, 111, etc.).

[0072] To further promote the understanding of the above-mentioned nanosheet device 100, Figure 4B The cross-sectional profile along the longitudinal extension L1 of the nanosheet device 100 is shown. Figure 4A Therefore, it can be clearly understood from the above description that Figure 4A and 4B .

[0073] Accordingly and in summary, in some of the variations discussed above, a nanosheet device 100 having a first set 112 and a second set 122 of vertically stacked channel layers separated by dielectric walls 130 has been described. The dielectric walls 130 are geometrically / physically enclosed between the first set 112 and the second set 122 of vertically stacked channel layers, the gate structure 150, and the gate spacer 160, thereby providing a nanosheet device 100 that can include further vertically aligned nanosheets in each channel stack 112, 122, thereby increasing the number of logic operations per area unit of the nanosheet device 100. Other benefits are smaller capacitance at the cell level, reduced parasitic series resistance, thereby avoiding n / p merging at the dielectric walls, and reducing the relatively large number of etch-back steps during the formation of the replacement metal gate RMG.

[0074] Those skilled in the art will appreciate that the inventive concept is by no means limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims. In implementing the claimed invention, other variations of the disclosed embodiments may be understood and implemented by those skilled in the art from a study of the drawings, the present disclosure, and the appended claims.

Claims

1. A nanosheet device (100), comprising: A first transistor structure (110) and a second transistor structure (120), each transistor structure (110, 120) comprising a source region (102, 106), a drain region (104, 108) and a channel region (130) extending between the source region and the drain region, a dielectric wall (140), a gate structure (150), and a gate spacer (160), wherein the channel region (130) of the first transistor structure (110) comprises a first group (112) of vertically stacked channel layers, wherein each channel layer of the first group (112) of vertically stacked channel layers has an inwardly facing surface (113) contacting a first side surface (142) of the electrically insulating wall (140), and wherein the channel region (130) of the second transistor structure (120) comprises a second group (122) of vertically stacked channel layers, wherein each channel layer of the second group (122) of vertically stacked channel layers has an inwardly facing surface (123) contacting a second side surface (144) of the dielectric wall (140) opposite to the first side surface (142), wherein a top portion (152) of the gate structure (150) is arranged above a top surface (141) of the dielectric wall (140), and The material of the gate spacer (160) is also arranged at a third side surface (146) and a fourth side surface (148) of the dielectric wall (140), and the third side surface (146) and the fourth side surface (148) are transverse to the first side surface (142) and the second side surface (144) of the dielectric wall (140).

2. The nanosheet device (100) according to claim 1, characterized in that: The top surface (141) of the dielectric wall (140) is flush with the top surface (132) of the channel region (130) of the first transistor structure (110) and with the top surface (134) of the channel region (130) of the second transistor structure (120).

3. The nanosheet device according to claim 1 or 2, characterized in that: The length (LC) of the channel region of the first transistor structure (110) and the length (LC) of the channel region of the second transistor structure (120) correspond to the length (LG) of the gate structure.

4. The nanosheet device (100) according to any one of claims 1 to 3, characterized in that: The distance between the third side surface (146) of the dielectric wall (140) and the fourth side surface (148) of the dielectric wall (140) corresponds to the length (LG) of the gate structure (150).

5. The nanosheet device (100) according to any one of claims 1 to 4, characterized in that: The bottom surface (143) of the dielectric wall (140) is disposed above the shallow trench isolation (STI) layer (170).

6. The nanosheet device (100) according to claim 5, characterized in that: The dielectric wall (140) and the STI layer (170) are formed of the same material.

7. The nanosheet device (100) according to any one of claims 1 to 6, characterized in that: One or more of the dielectric wall (140) and the STI layer (170) includes an oxide or nitride material.

8. The nanosheet device (100) according to any one of claims 1 to 7, characterized in that: Each of the first set (112) of vertically stacked channel layers and the second set (122) of vertically stacked channel layers includes three or more stacked channel layers (112, 122).

9. The nanosheet device (100) according to any one of claims 1 to 8, characterized in that: The shortest distance (WI1) between the first side surface (142) and the second side surface (144) of the dielectric wall (140) is at least 50% of the width (WL1, WL2) of each of the vertically stacked first channel layers of the first group (112) and the vertically stacked second channel layers of the second group (122).

10. The nanosheet device (100) according to any one of claims 1 to 9, characterized in that: The shortest distance (WI1) between the first side surface (142) and the second side surface (144) of the dielectric wall (140) is at least 10 nm.

11. The nanosheet device (100) according to any one of claims 1 to 10, characterized in that: The first set (112) of vertically stacked channel layers comprises an n-FET type material, and wherein the second set (122) of vertically stacked channel layers comprises a p-FET type material.

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