Light-emitting diode epitaxial wafer, preparation method thereof and LED

Abstract

The invention relates to the technical field of photoelectricity, and discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and an LED, the light-emitting diode epitaxial wafer comprises a substrate, and the substrate is sequentially provided with a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer; the stress release layer comprises a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence. According to the light-emitting diode epitaxial wafer provided by the invention, the tensile stress of the GaN epitaxial layer and the mismatch stress of the multi-quantum well layer are released, the polarization effect of the multi-quantum well layer is reduced, and the light-emitting efficiency of the light-emitting diode is improved.

Description

Technical Field

[0001] The invention relates to the field of optoelectronic technology, and in particular to a light emitting diode epitaxial wafer and a preparation method thereof, and an LED. Background Art

[0002] At present, GaN-based LED devices with InGaN quantum wells as multi-quantum well layers are widely used in various fields. However, due to the lack of suitable homogeneous epitaxial substrates, GaN is usually grown on sapphire, silicon carbide or silicon substrates with large lattice mismatches. The lattice mismatch between GaN and the substrate will undoubtedly form a large number of dislocation defects, thereby affecting its epitaxial quality. In addition, there is also a large lattice mismatch between the quantum well multi-quantum well layer InGaN and GaN, and the InGaN quantum well will be subject to compressive stress from GaN. Both dislocation defects and compressive stress will have an adverse effect on the performance of LED devices. To solve the above problems, an InGaN stress release layer is usually inserted between the N-type GaN layer and the quantum well active region. The inserted InGaN stress release layer provides a new growth platform for the subsequent quantum well multi-quantum well layer. If quantum wells with a high In component are to be grown, such as green and yellow quantum wells, an InGaN preparation layer growth platform with a high In component is required to more fully relieve the quantum well stress. The quality of this platform directly determines the growth quality of the quantum well active region. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a light-emitting diode epitaxial wafer, which releases the tensile stress of the GaN epitaxial layer and the mismatch stress of the multi-quantum well layer, reduces the polarization effect of the multi-quantum well layer, and improves the luminous efficiency of the light-emitting diode.

[0004] The technical problem to be solved by the present invention is also to provide a method for preparing a light emitting diode epitaxial wafer, which has a simple process and can stably prepare a light emitting diode epitaxial wafer with good luminous efficiency.

[0005] In order to solve the above technical problems, the present invention provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially arranged;

[0006] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0007] In some embodiments, the C doping concentration of the C-high Si co-doped nitride layer>the C doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer=the C doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer>the C doping concentration of the C-high Si co-doped nitride layer>the C doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer.

[0008] In some embodiments, the Si doping concentration of the C-high Si co-doped nitride layer>the Si doping concentration of the low C-high Si co-doped nitride layer>the Si doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer=the Si doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer>the Si doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer.

[0009] In some embodiments, the nitride is one of GaN, AlGaN, InGaN, AlInGaN, BGaN, and BInGaN.

[0010] In some embodiments, the thickness of the C-high Si co-doped nitride layer is 10 nm to 100 nm;

[0011] The C doping concentration of the C-high Si co-doped nitride layer is 3×10 17 atoms / cm 3 ~5×10 17 atoms / cm 3 ;

[0012] The Si doping concentration of the C-high Si co-doped nitride layer is 4×10 18 atoms / cm 3 ~4×10 19 atoms / cm 3 .

[0013] In some embodiments, the thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 50 nm to 500 nm;

[0014] The C doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 1×10 17 atoms / cm 3 ~3×10 17 atoms / cm 3 ;

[0015] The Si doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 5×10 17 atoms / cm 3 ~5×10 18 atoms / cm 3 .

[0016] In some embodiments, the thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 1 nm to 550 nm;

[0017] The C doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 1×10 17 atoms / cm 3 ~3×10 17 atoms / cm 3 ;

[0018] The Si doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 5×10 17 atoms / cm 3 ~5×10 18 atoms / cm 3 .

[0019] In some embodiments, the thickness of the low C-high Si co-doped nitride layer is 1 nm to 50 nm;

[0020] The C doping concentration of the low C-high Si co-doped nitride layer is 1×10 17 atoms / cm 3 ~2×10 17 atoms / cm 3 ;

[0021] The Si doping concentration of the low C-high Si co-doped nitride layer is 1×10 18 atoms / cm 3 ~4×10 18 atoms / cm 3 .

[0022] In some embodiments, the thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 1 nm to 700 nm;

[0023] The C doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 1×10 16 atoms / cm 3 ~5×10 16 atoms / cm 3;

[0024] The Si doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 1×10 17 atoms / cm 3 ~5×10 17 atoms / cm 3 .

[0025] In order to solve the above problems, the present invention provides a method for preparing a light emitting diode epitaxial wafer, comprising the following steps:

[0026] S1. providing a substrate;

[0027] S2, depositing a buffer layer, an undoped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate in sequence;

[0028] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0029] Correspondingly, the present invention further provides an LED, wherein the LED comprises the light emitting diode epitaxial wafer as described above.

[0030] The implementation of the present invention has the following beneficial effects:

[0031] In the present invention, the stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer stacked in sequence.

[0032] Among them, the C-high Si co-doped nitride layer uses a lower deposition temperature to release the thermal stress caused by thermal mismatch and serves as an opening layer of the V-shaped pit; a higher C doping concentration is conducive to the V-shaped opening, and a higher Si doping concentration can serve as a limiting layer of the light-emitting diode depletion region to control the thickness of the light-emitting diode depletion region.

[0033] The C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer adopts a lower deposition temperature to release the thermal stress caused by thermal mismatch. In addition, the temperature is low, the atomic mobility is low, and the C doping concentration is high, which is conducive to the continued growth and opening of the V-shaped pit; the Si doping adopts a periodic high and low doping method to improve the directional voltage of the light-emitting diode.

[0034] The C-Si co-doped nitride layer / InGaN layer superlattice structure layer can release the stress of the quantum well and reduce the polarization electric field in the quantum well. At the same time, the InGaN layer can expand the V-shaped pit. When the device is reverse biased, the smaller the electric field strength is, the smaller the inclination of the defect center barrier is, the smaller the reduction in the barrier height for carriers to escape from the defect center when activated, and it is difficult for carriers to escape from the defect center to form leakage current, thereby reducing non-radiative recombination of luminescence and leakage current.

[0035] The low C-high Si co-doped nitride layer has a high Si doping concentration, which improves the injection efficiency of electrons into the multi-quantum well layer, allowing more electrons to enter the multi-quantum well layer and undergo radiation recombination with holes.

[0036] The low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer can gradually transition the lattice constant from N-GaN to InGaN / AlGaN multiple quantum wells, promote the incorporation of In atoms in the InGaN quantum wells, improve crystal quality, and enhance device luminescence efficiency.

[0037] In summary, the light-emitting diode epitaxial structure provided by the present invention can release the tensile stress of the GaN epitaxial layer and the mismatch stress of the multi-quantum well layer, reduce the polarization effect of the multi-quantum well layer, and improve the luminous efficiency of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic structural diagram of the light emitting diode epitaxial wafer provided by the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0040] In the description of the present invention, it is necessary to understand that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0042] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0044] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0045] In the present invention, "preferred" and "better" are only used to describe implementation methods or embodiments with better effects, and it should be understood that they do not constitute a limitation on the scope of protection of the present invention. In the present invention, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features. In the present invention, when involving numerical ranges, unless otherwise specified, the two endpoints of the numerical range are included.

[0046] To solve the above problems, the present invention provides a light emitting diode epitaxial wafer, such as Figure 1 As shown, it includes a substrate 100, on which a buffer layer 200, a non-doped GaN layer 300, an N-type GaN layer 400, a stress release layer 500, a multi-quantum well layer 600, an electron blocking layer 700, and a P-type GaN layer 800 are sequentially arranged;

[0047] The stress release layer 500 includes a C-high Si co-doped nitride layer 510, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530, a low C-high Si co-doped nitride layer 540 and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 which are stacked in sequence.

[0048] The specific structure of the stress release layer 500 provided by the present invention is as follows:

[0049] In some embodiments, the C doping concentration of the C-high Si co-doped nitride layer 510 > the C doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 = the C doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 > the C doping concentration of the C-high Si co-doped nitride layer 540 > the C doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550.

[0050] In some embodiments, the Si doping concentration of the C-high Si co-doped nitride layer 510 > the Si doping concentration of the low C-high Si co-doped nitride layer 540 > the Si doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 = the Si doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 > the Si doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550.

[0051] In some embodiments, the nitride is one of GaN, AlGaN, InGaN, AlInGaN, BGaN, and BInGaN.

[0052] In some embodiments, the thickness of the C-high Si co-doped nitride layer 510 is 10 nm to 100 nm. The exemplary thickness of the C-high Si co-doped nitride layer 510 is 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, but is not limited to the above. The C doping concentration of the C-high Si co-doped nitride layer 510 is 3×10 17 atoms / cm 3 ~5×10 17 atoms / cm 3 The exemplary C doping concentration of the C-high Si co-doped nitride layer 510 is 3.5×10 17 atoms / cm 3 , 4×10 17 atoms / cm 3 , 4.5×10 17 atoms / cm 3 , but not limited to the above. The Si doping concentration of the C-high Si co-doped nitride layer 510 is 4×10 18 atoms / cm 3 ~4×10 19 atoms / cm 3 The exemplary Si doping concentration of the C-high Si co-doped nitride layer 510 is 5×10 18 atoms / cm 3 , 6×10 18 atoms / cm 3 ,7×10 18 atoms / cm 3 , 8×10 18 atoms / cm 3 ,9×10 18 atoms / cm 3 , 1×10 19atoms / cm 3 , 2×10 19 atoms / cm 3 , 3×10 19 atoms / cm 3 The growth temperature of the C-high Si co-doped nitride layer 510 is 800°C to 900°C.

[0053] The C-high Si co-doped nitride layer can release the thermal stress caused by thermal mismatch by using a lower deposition temperature, and can serve as an opening layer of the V-shaped pit; a higher C doping concentration is conducive to the V-shaped opening, and a higher Si doping concentration can serve as a limiting layer of the light-emitting diode depletion region to control the thickness of the light-emitting diode depletion region.

[0054] In some embodiments, the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 includes alternately stacked C-Si co-doped nitride layers and C-low Si co-doped nitride layers, and the number of alternating periods is 1 to 20. The ratio of the Si doping concentration of the C-Si co-doped nitride layer to the Si doping concentration of the C-low Si co-doped nitride layer is (1.1 to 2): 1. The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 is 50nm to 500nm; the exemplary thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 is 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, but is not limited to the above list. The C doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 is 1×10 17 atoms / cm 3 ~3×10 17 atoms / cm 3 The exemplary C doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 is 1.5×10 17 atoms / cm 3 , 2×10 17 atoms / cm 3 , 2.5×10 17 atoms / cm 3 , but not limited to the above. The Si doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 is 5×10 17 atoms / cm 3 ~5×10 18 atoms / cm 3The exemplary Si doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 is 6×10 17 atoms / cm 3 ,7×10 17 atoms / cm 3 , 8×10 17 atoms / cm 3 ,9×10 17 atoms / cm 3 , 1×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 4×10 18 atoms / cm 3 The growth temperature of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 is 800°C to 900°C.

[0055] The C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer adopts a lower deposition temperature to release the thermal stress caused by thermal mismatch. In addition, the temperature is low, the atomic mobility is low, and the C doping concentration is high, which is conducive to the continued growth and opening of the V-shaped pit; the Si doping adopts a periodic high and low doping method to improve the directional voltage of the light-emitting diode.

[0056] In some embodiments, the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 includes alternating C-high Si co-doped nitride layers and InGaN layers, and the number of alternating stacking periods is 1 to 10. The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 is 1nm to 550nm; the exemplary thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 is 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, but is not limited to the above. The C doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 is 1×10 17 atoms / cm 3 ~3×10 17 atoms / cm 3 The exemplary C doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 is 1.5×10 17atoms / cm 3 , 2×10 17 atoms / cm 3 , 2.5×10 17 atoms / cm 3 , but not limited to the above. The Si doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 is 5×10 17 atoms / cm 3 ~5×10 18 atoms / cm 3 The exemplary Si doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 is 6×10 17 atoms / cm 3 ,7×10 17 atoms / cm 3 , 8×10 17 atoms / cm 3 ,9×10 17 atoms / cm 3 , 1×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 4×10 18 atoms / cm 3 The growth temperature of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 is 800°C to 900°C.

[0057] The C-Si co-doped nitride layer / InGaN layer superlattice structure layer can release the stress of the quantum well and reduce the polarization electric field in the quantum well. At the same time, the InGaN layer can expand the V-shaped pit. When the device is reverse biased, the smaller the electric field strength is, the smaller the inclination of the defect center barrier is, the smaller the reduction in the barrier height for carriers to escape from the defect center when activated, and it is difficult for carriers to escape from the defect center to form leakage current, thereby reducing non-radiative recombination of luminescence and leakage current.

[0058] In some embodiments, the thickness of the low C-high Si co-doped nitride layer 540 is 1 nm to 50 nm; exemplary thicknesses of the low C-high Si co-doped nitride layer 540 are 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, and 45 nm, but are not limited to the above. The C doping concentration of the low C-high Si co-doped nitride layer 540 is 1×10 17 atoms / cm3 ~2×10 17 atoms / cm 3 The exemplary C doping concentration of the low C-high Si co-doped nitride layer 540 is 1.2×10 17 atoms / cm 3 , 1.4×10 17 atoms / cm 3 , 1.6×10 17 atoms / cm 3 , 1.8×10 17 atoms / cm 3 , but not limited to the above. The Si doping concentration of the low C-high Si co-doped nitride layer 540 is 1×10 18 atoms / cm 3 ~4×10 18 atoms / cm 3 The exemplary Si doping concentration of the low C-high Si co-doped nitride layer 540 is 1.5×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 2.5×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 3.5×10 18 atoms / cm 3 The growth temperature of the low C-high Si co-doped nitride layer 540 is 800°C to 900°C.

[0059] The low C-high Si co-doped nitride layer has a high Si doping concentration, which improves the injection efficiency of electrons into the multi-quantum well layer, allowing more electrons to enter the multi-quantum well layer and undergo radiation recombination with holes.

[0060] In some embodiments, the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 includes alternating low C-low Si co-doped nitride layers and InGaN layers, and the number of alternating stacking periods is 1 to 20. The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 is 1nm to 700nm; the exemplary thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 is 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, but not limited to the above. The C doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 is 1×10 16 atoms / cm 3 ~5×10 16 atoms / cm 3 The exemplary C doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 is 2×10 16 atoms / cm 3 , 3×10 16 atoms / cm 3 , 4×10 16 atoms / cm 3 , but not limited to the above. The Si doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 is 1×10 17 atoms / cm 3 ~5×10 17 atoms / cm 3 The exemplary Si doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 is 2×10 17 atoms / cm 3 , 3×10 17 atoms / cm 3 , 4×10 17 atoms / cm 3 The growth temperature of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 is 800°C to 900°C.

[0061] The low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer can gradually transition the lattice constant from N-GaN to InGaN / AlGaN multiple quantum wells, promote the incorporation of In atoms in the InGaN quantum wells, improve crystal quality, and enhance device luminescence efficiency.

[0062] In summary, the light-emitting diode epitaxial structure provided in some embodiments can release the tensile stress of the GaN epitaxial layer and the mismatch stress of the multi-quantum well layer, reduce the polarization effect of the multi-quantum well layer, and improve the luminous efficiency of the light-emitting diode.

[0063] Accordingly, the present invention provides a method for preparing a light emitting diode epitaxial wafer, comprising the following steps:

[0064] S1, providing a substrate 100;

[0065] In some embodiments, the substrate 100 may be selected from one of a sapphire substrate, a SiO2 sapphire composite substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a zinc oxide substrate. Preferably, the substrate 100 is a sapphire substrate, which is a commonly used GaN-based LED substrate material. The sapphire substrate has a mature preparation process, a low price, is easy to clean and handle, and has good stability at high temperatures.

[0066] S2, sequentially depositing a buffer layer 200, a non-doped GaN layer 300, an N-type GaN layer 400, a stress release layer 500, a multi-quantum well layer 600, an electron blocking layer 700, and a P-type GaN layer 800 on the substrate 100;

[0067] The stress release layer 500 includes a C-high Si co-doped nitride layer 510, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530, a low C-high Si co-doped nitride layer 540 and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 which are stacked in sequence.

[0068] Specifically, the above step S2 specifically includes the following steps:

[0069] S21 , depositing the buffer layer 200 on the substrate 100 .

[0070] In some embodiments, the buffer layer 200 is an AlN buffer layer.

[0071] S22 , depositing the undoped GaN layer 300 on the buffer layer 200 .

[0072] In some embodiments, the temperature of the reaction chamber is controlled at 1050° C. to 1200° C., the pressure is controlled at 100 torr to 600 torr, N source and Ga source are introduced, and a non-doped GaN layer with a thickness of 1 μm to 5 μm is grown.

[0073] S23 , depositing the N-type GaN layer 400 on the undoped GaN layer 300 .

[0074] In some embodiments, the temperature of the reaction chamber is controlled at 1050° C. to 1200° C., the pressure is controlled at 100 torr to 600 torr, and an N source, a Ga source, and a Si source are introduced to grow the N-type GaN layer.

[0075] S24 , depositing the stress release layer 500 on the N-type GaN layer 400 .

[0076] In some embodiments, the growth temperature of the C-high Si co-doped nitride layer 510 is 800° C. to 900° C., and the growth pressure is 50 torr to 500 torr;

[0077] The growth temperature of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer 520 is 800° C. to 900° C., and the growth pressure is 50 torr to 500 torr;

[0078] The growth temperature of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer 530 is 800° C. to 900° C., and the growth pressure is 50 torr to 500 torr;

[0079] The growth temperature of the low C-high Si co-doped nitride layer 540 is 800° C. to 900° C., and the growth pressure is 50 torr to 500 torr;

[0080] The growth temperature of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer 550 is 800° C. to 900° C., and the growth pressure is 50 torr to 500 torr.

[0081] S25 , depositing the multi-quantum well layer 600 on the stress release layer 500 .

[0082] In some embodiments, the multi-quantum well layer is an alternately stacked InGaN quantum well layer and an AlGaN quantum barrier layer, with a stacking period number of 1 to 20. The growth temperature of the InGaN quantum well layer is 790°C to 810°C, the thickness is 2nm to 5nm, and the growth pressure is 50torr to 300torr; the growth temperature of the AlGaN quantum barrier layer is 800°C to 900°C, the thickness is 5nm to 15nm, and the growth pressure is 50torr to 300torr.

[0083] S26, depositing the electron blocking layer 700 on the multi-quantum well layer 600;

[0084] In some embodiments, the temperature of the reaction chamber is controlled at 900° C. to 1000° C., the pressure is controlled at 100 torr to 300 torr, N source, Al source, Ga source, and In source are introduced to grow an AlInGaN electron blocking layer with a thickness of 10 nm to 40 nm.

[0085] S27 , depositing the P-type GaN layer 800 on the electron blocking layer 700 .

[0086] In some embodiments, the temperature of the reaction chamber is controlled at 900° C. to 1050° C., the pressure is controlled at 100 torr to 600 torr, and an N source, a Mg source, and a Ga source are introduced to grow the P-type GaN layer.

[0087] Accordingly, the present invention further provides an LED, which comprises the above-mentioned light-emitting diode epitaxial wafer, wherein the photoelectric efficiency of the LED is effectively improved and other electrical properties are good.

[0088] The present invention is further described below with specific embodiments:

[0089] Example 1

[0090] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0091] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0092] The thickness of the C-high Si co-doped nitride layer is 56 nm, and the C doping concentration is 3.7×10 17 atoms / cm 3 , Si doping concentration is 5.2×10 18 atoms / cm 3 .

[0093] The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 180 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3, the thickness ratio of the C-Si co-doped nitride layer to the C-low Si co-doped nitride layer is 2:1, and the Si doping concentration ratio is 3:2.

[0094] The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 40.8 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 .

[0095] The thickness of the low C-high Si co-doped nitride layer is 15 nm, and the C doping concentration is 1.4×10 17 atoms / cm 3 , Si doping concentration is 2.5×10 18 atoms / cm 3 .

[0096] The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 75.6 nm, and the C doping concentration is 2.4×10 16 atoms / cm 3 , Si doping concentration is 2.7×10 17 atoms / cm 3 .

[0097] Example 2

[0098] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0099] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0100] The thickness of the C-high Si co-doped nitride layer is 65 nm, and the C doping concentration is 3.7×10 17 atoms / cm 3 , Si doping concentration is 5.2×10 18 atoms / cm 3 .

[0101] The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 205 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 , the thickness ratio of the C-Si co-doped nitride layer to the C-low Si co-doped nitride layer is 3:2, and the Si doping concentration ratio is 3:2.

[0102] The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 45 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 .

[0103] The thickness of the low C-high Si co-doped nitride layer is 18 nm, and the C doping concentration is 1.4×10 17 atoms / cm 3 , Si doping concentration is 2.5×10 18 atoms / cm 3 .

[0104] The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 90 nm, and the C doping concentration is 2.4×10 16 atoms / cm 3 , Si doping concentration is 2.7×10 17 atoms / cm 3 .

[0105] Example 3

[0106] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0107] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0108] The thickness of the C-high Si co-doped nitride layer is 48 nm, and the C doping concentration is 3.7×10 17atoms / cm 3 , Si doping concentration is 5.2×10 18 atoms / cm 3 .

[0109] The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 150 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 , the thickness ratio of the C-Si co-doped nitride layer to the C-low Si co-doped nitride layer is 3:1, and the Si doping concentration ratio is 3:2.

[0110] The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 33.6 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 .

[0111] The thickness of the low C-high Si co-doped nitride layer is 12 nm, and the C doping concentration is 1.4×10 17 atoms / cm 3 , Si doping concentration is 2.5×10 18 atoms / cm 3 .

[0112] The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 64.8 nm, and the C doping concentration is 2.4×10 16 atoms / cm 3 , Si doping concentration is 2.7×10 17 atoms / cm 3 .

[0113] Example 4

[0114] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0115] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0116] The thickness of the C-high Si co-doped nitride layer is 56 nm, and the C doping concentration is 3.7×10 17 atoms / cm 3 , Si doping concentration is 5.2×10 18 atoms / cm 3 .

[0117] The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 180 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 , the thickness ratio of the C-Si co-doped nitride layer to the C-low Si co-doped nitride layer is 2:1, and the Si doping concentration ratio is 3:2.

[0118] The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 68 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 .

[0119] The thickness of the low C-high Si co-doped nitride layer is 15 nm, and the C doping concentration is 1.4×10 17 atoms / cm 3 , Si doping concentration is 2.5×10 18 atoms / cm 3 .

[0120] The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 37.8 nm, and the C doping concentration is 2.4×10 16 atoms / cm 3 , Si doping concentration is 2.7×10 17 atoms / cm 3 .

[0121] Example 5

[0122] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0123] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0124] The thickness of the C-high Si co-doped nitride layer is 56 nm, and the C doping concentration is 3.7×10 17 atoms / cm 3 , Si doping concentration is 5.2×10 18 atoms / cm 3 .

[0125] The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 180 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 , the thickness ratio of the C-Si co-doped nitride layer to the C-low Si co-doped nitride layer is 2:1, and the Si doping concentration ratio is 3:2.

[0126] The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 13.6 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 .

[0127] The thickness of the low C-high Si co-doped nitride layer is 15 nm, and the C doping concentration is 1.4×10 17 atoms / cm 3 , Si doping concentration is 2.5×10 18 atoms / cm 3 .

[0128] The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 37.8 nm, and the C doping concentration is 2.4×10 16 atoms / cm 3, Si doping concentration is 2.7×10 17 atoms / cm 3 .

[0129] Example 6

[0130] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0131] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0132] The thickness of the C-high Si co-doped nitride layer is 56 nm, and the C doping concentration is 4×10 17 atoms / cm 3 , Si doping concentration is 5.2×10 18 atoms / cm 3 .

[0133] The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 180 nm, and the C doping concentration is 2.8×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 , the thickness ratio of the C-Si co-doped nitride layer to the C-low Si co-doped nitride layer is 2:1, and the Si doping concentration ratio is 3:2.

[0134] The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 40.8 nm, and the C doping concentration is 2.8×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 .

[0135] The thickness of the low C-high Si co-doped nitride layer is 15 nm, and the C doping concentration is 1.6×10 17 atoms / cm 3 , Si doping concentration is 2.5×10 18 atoms / cm 3 .

[0136] The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 75.6 nm, and the C doping concentration is 2.8×10 16 atoms / cm 3 , Si doping concentration is 2.7×10 17 atoms / cm 3 .

[0137] Example 7

[0138] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0139] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0140] The thickness of the C-high Si co-doped nitride layer is 56 nm, and the C doping concentration is 3.7×10 17 atoms / cm 3 , Si doping concentration is 5.2×10 18 atoms / cm 3 .

[0141] The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 180 nm, and the C doping concentration is 2.1×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 , the thickness ratio of the C-Si co-doped nitride layer to the C-low Si co-doped nitride layer is 2:1, and the Si doping concentration ratio is 3:2.

[0142] The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 40.8 nm, and the C doping concentration is 2.1×10 17 atoms / cm 3 , Si doping concentration is 8.7×10 17 atoms / cm 3 .

[0143] The thickness of the low C-high Si co-doped nitride layer is 15 nm, and the C doping concentration is 1.2×1017 atoms / cm 3 , Si doping concentration is 2.5×10 18 atoms / cm 3 .

[0144] The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 75.6 nm, and the C doping concentration is 2.2×10 16 atoms / cm 3 , Si doping concentration is 2.7×10 17 atoms / cm 3 .

[0145] Example 8

[0146] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0147] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0148] The thickness of the C-high Si co-doped nitride layer is 56 nm, and the C doping concentration is 3.7×10 17 atoms / cm 3 , Si doping concentration is 6×10 18 atoms / cm 3 .

[0149] The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 180 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.1×10 17 atoms / cm 3 , the thickness ratio of the C-Si co-doped nitride layer to the C-low Si co-doped nitride layer is 2:1, and the Si doping concentration ratio is 3:2.

[0150] The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 40.8 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 8.1×1017 atoms / cm 3 .

[0151] The thickness of the low C-high Si co-doped nitride layer is 15 nm, and the C doping concentration is 1.4×10 17 atoms / cm 3 , Si doping concentration is 2.7×10 18 atoms / cm 3 .

[0152] The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 75.6 nm, and the C doping concentration is 2.4×10 16 atoms / cm 3 , Si doping concentration is 3×10 17 atoms / cm 3 .

[0153] Example 9

[0154] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0155] The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

[0156] The thickness of the C-high Si co-doped nitride layer is 56 nm, and the C doping concentration is 3.7×10 17 atoms / cm 3 , Si doping concentration is 4.5×10 18 atoms / cm 3 .

[0157] The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 180 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 1×10 18 atoms / cm 3 , the thickness ratio of the C-Si co-doped nitride layer to the C-low Si co-doped nitride layer is 2:1, and the Si doping concentration ratio is 3:2.

[0158] The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 40.8 nm, and the C doping concentration is 2.4×10 17 atoms / cm 3 , Si doping concentration is 1×10 18 atoms / cm 3 .

[0159] The thickness of the low C-high Si co-doped nitride layer is 15 nm, and the C doping concentration is 1.4×10 17 atoms / cm 3 , Si doping concentration is 2.1×10 18 atoms / cm 3 .

[0160] The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 75.6 nm, and the C doping concentration is 2.4×10 16 atoms / cm 3 , Si doping concentration is 2.3×10 17 atoms / cm 3 .

[0161] Comparative Example 1

[0162] This comparative example provides a light emitting diode epitaxial wafer, which is different from the other embodiment 1 in that its stress release layer is alternately stacked GaN layers and InGaN layers, and the rest is the same as the embodiment 1.

[0163] The light-emitting diode epitaxial wafers prepared in Examples 1 to 9 and Comparative Example 1 were prepared into 10 mil×24 mil chips using the same chip process conditions. 300 LED chips were respectively extracted and tested at a current of 120 mA. Compared with the LED prepared in Comparative Example 1, the luminous efficiency improvement rate of each example was calculated. The specific test results are shown in Table 1.

[0164] Table 1 Performance test results of LEDs prepared in Examples 1 to 9 and Comparative Example 1

[0165]

[0166] It can be seen from the above results that the light-emitting diode epitaxial wafer provided by the present invention can release the tensile stress of the GaN epitaxial layer and the mismatch stress of the multi-quantum well layer, reduce the polarization effect of the multi-quantum well layer, and improve the luminous efficiency of the light-emitting diode.

[0167] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0168] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A light emitting diode epitaxial wafer, characterized in that: It comprises a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially arranged; The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

2. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The C doping concentration of the C-high Si co-doped nitride layer>the C doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer=the C doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer>the C doping concentration of the C-high Si co-doped nitride layer>the C doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer.

3. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The Si doping concentration of the C-high Si co-doped nitride layer>the Si doping concentration of the low C-high Si co-doped nitride layer>the Si doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer=the Si doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer>the Si doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer.

4. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The nitride is one of GaN, AlGaN, InGaN, AlInGaN, BGaN, and BInGaN.

5. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the C-high Si co-doped nitride layer is 10nm to 100nm; The C doping concentration of the C-high Si co-doped nitride layer is 3×10 17 atoms / cm 3 ~5×10 17 atoms / cm 3 ; The Si doping concentration of the C-high Si co-doped nitride layer is 4×10 18 atoms / cm 3 ~4×10 19 atoms / cm 3 .

6. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 50nm to 500nm; The C doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 1×10 17 atoms / cm 3 ~3×10 17 atoms / cm 3 ; The Si doping concentration of the C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer is 5×10 17 atoms / cm 3 ~5×10 18 atoms / cm 3 .

7. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 1nm to 550nm; The C doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 1×10 17 atoms / cm 3 ~3×10 17 atoms / cm 3 ; The Si doping concentration of the C-high Si co-doped nitride layer / InGaN layer superlattice structure layer is 5×10 17 atoms / cm 3 ~5×10 18 atoms / cm 3 .

8. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the low C-high Si co-doped nitride layer is 1 nm to 50 nm; The C doping concentration of the low C-high Si co-doped nitride layer is 1×10 17 atoms / cm 3 ~2×10 17 atoms / cm 3 ; The Si doping concentration of the low C-high Si co-doped nitride layer is 1×10 18 atoms / cm 3 ~4×10 18 atoms / cm 3 .

9. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 1nm to 700nm; The C doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 1×10 16 atoms / cm 3 ~5×10 16 atoms / cm 3 ; The Si doping concentration of the low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer is 1×10 17 atoms / cm 3 ~5×10 17 atoms / cm 3 .

10. A method for preparing a light emitting diode epitaxial wafer according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1. providing a substrate; S2, depositing a buffer layer, an undoped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate in sequence; The stress release layer includes a C-high Si co-doped nitride layer, a C-Si co-doped nitride layer / C-low Si co-doped nitride layer periodic structure layer, a C-high Si co-doped nitride layer / InGaN layer superlattice structure layer, a low C-high Si co-doped nitride layer and a low C-low Si co-doped nitride layer / InGaN layer superlattice structure layer which are stacked in sequence.

11. An LED, characterized in that: The LED comprises the light emitting diode epitaxial wafer as claimed in any one of claims 1 to 9.

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