Two-dimensional addressable VCSEL array and preparation method thereof

Abstract

The present application discloses a two-dimensional addressable VCSEL array and a preparation method thereof. The two-dimensional addressable VCSEL array comprises: a plurality of VCSEL units; each VCSEL unit is separated by a groove; each VCSEL unit comprises: a substrate and a first-type reflector layer, an active layer and a second-type reflector layer sequentially arranged on the substrate; the groove exposes a portion of the surface of the first-type reflector layer; a first electrode structure is arranged on a portion of the surface of the first-type reflector layer and is electrically connected to the first-type reflector layer; the first electrode structure comprises a first sub-electrode and a second sub-electrode; in the same VCSEL unit, the distance between the first sub-electrode and the side wall of the groove is greater than the distance between the second sub-electrode and the same side wall; the second electrode structure is arranged on the second-type reflector layer and is electrically connected to the second-type reflector layer; the polarity of the second electrode structure is opposite to that of the first electrode structure. The performance and reliability of the VCSEL unit are improved.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor laser technology, and in particular to a two-dimensional addressable VCSEL array and a method for preparing the same. Background Art

[0002] The laser chip in the two-dimensional addressable vertical cavity surface emitting laser array (VCSEL) has a coplanar electrode structure. The N-type electrode and P-type electrode in the laser chip are located on the same side of the substrate, shortening the path of current flowing from the P-type electrode to the N-type electrode. During the performance and reliability testing of the laser chip, with the flow of electrons and the accumulation of heat inside the laser chip, the metal components in the N-type electrode will diffuse to the semiconductor epitaxial structure on one side, causing the laser chip to fail. Summary of the invention

[0003] The embodiments of the present disclosure provide a two-dimensional addressable VCSEL array and a method for manufacturing the same, which can improve the performance and reliability of VCSEL units in the two-dimensional addressable VCSEL array.

[0004] A two-dimensional addressable VCSEL array comprises a plurality of VCSEL units, each of the VCSEL units being separated by a groove;

[0005] Each of the VCSEL units comprises: a substrate, and a first-type reflector layer, an active layer, and a second-type reflector layer sequentially arranged on the substrate;

[0006] The groove exposes a portion of the surface of the first type reflector layer;

[0007] A plurality of first electrode structures are provided on a portion of the surface of the first type reflector layer and are electrically connected to the first type reflector layer; wherein some of the first electrode structures are located near a first side wall of the groove, and some of the first electrode structures are located near a second side wall of the groove, and the first side wall and the second side wall are located opposite to each other;

[0008] The first electrode structure includes a first sub-electrode and a second sub-electrode; in the same VCSEL unit, the distance between the first sub-electrode and the sidewall of the trench is greater than the distance between the second sub-electrode and the same sidewall;

[0009] A plurality of second electrode structures are disposed on the second-type reflector layer and electrically connected to the second-type reflector layer; the second electrode structures have opposite polarities to the first electrode structures.

[0010] In one of the embodiments, the orthographic projection of the first sub-electrode on the substrate is located within the orthographic projection of the second sub-electrode on the substrate.

[0011] In one embodiment, the two-dimensional addressable VCSEL array further comprises:

[0012] a passivation layer, covering the first electrode structure and the second electrode structure;

[0013] The metal interconnection electrode is located on a side of the passivation layer away from the second electrode structure, penetrates the passivation layer in a direction perpendicular to the substrate, and is electrically connected to the second electrode structures of the plurality of VCSEL units arranged in a second direction parallel to the substrate.

[0014] In one of the embodiments, the two-dimensional addressable VCSEL array further includes: an isolation trench or an isolation layer;

[0015] The isolation trench is located below the trench and communicates with the trench, and the bottom of the isolation trench is between the bottom of the trench and the surface of the substrate;

[0016] The isolation layer is located below the groove, and the isolation layer is formed by proton implantation of a portion of the surface of the first type reflector layer between adjacent first electrode structures. In one embodiment, the two-dimensional addressable VCSEL array further includes:

[0017] an isolation trench and an isolation layer;

[0018] The isolation trench is located below the trench and communicates with the trench, and the bottom of the isolation trench is between the bottom of the trench and the top surface of the substrate;

[0019] The isolation layer is located below the isolation groove, and the isolation layer is formed by proton implantation of the first type reflector layer at the bottom of the isolation groove. In one embodiment, the first type reflector layer includes:

[0020] a first Bragg reflector, located on the substrate;

[0021] a first semiconductor confinement layer, having the same conductivity type as the first Bragg reflector, and located on a top surface of the first Bragg reflector away from the substrate;

[0022] The active layer is located on the first semiconductor confinement layer; the groove exposes a portion of the surface of the first semiconductor confinement layer, and the bottom surface of the first electrode structure is in contact with the exposed portion of the surface of the first semiconductor confinement layer.

[0023] In one embodiment, the second type reflector layer comprises:

[0024] A second Bragg reflector is located on a top surface of the active layer away from the substrate;

[0025] a second semiconductor confinement layer, having the same conductivity type as the second Bragg reflector, and located on a top surface of the second Bragg reflector away from the substrate;

[0026] Wherein, a bottom surface of the second electrode structure contacts a top surface of the second semiconductor confinement layer.

[0027] In one of the embodiments, the two-dimensional addressable VCSEL array further includes: a back metal layer located on a side of the substrate away from the VCSEL units.

[0028] In one embodiment, a plurality of the VCSEL units arranged along a third direction parallel to the substrate share the first electrode structure.

[0029] In one embodiment, the VCSEL unit further comprises:

[0030] A photoelectric limiting layer, located between the active layer and the second-type reflector layer, the photoelectric limiting layer is used to limit the light emitting area of ​​the VCSEL unit;

[0031] Wherein, the orthographic projection of the second electrode structure on the substrate is located within the orthographic projection of the photoelectric limiting layer on the substrate.

[0032] A method for preparing a two-dimensional addressable VCSEL array, comprising:

[0033] A wafer is provided; the wafer comprises a substrate and an epitaxial material structure, the epitaxial material structure comprises a first type reflector layer, an active layer and a second type reflector layer sequentially arranged on the substrate;

[0034] Performing mesa etching on the epitaxial material structure to form a plurality of epitaxial structures; wherein each of the epitaxial structures is separated by a groove, and the groove exposes a portion of the surface of the first type reflector layer;

[0035] A first electrode structure electrically connected to the first type reflector layer is formed on the exposed surface of the first type reflector layer; wherein the first electrode structure comprises a first sub-electrode and a second sub-electrode; and the distance between the first sub-electrode and the sidewall of the groove is greater than the distance between the second sub-electrode and the same sidewall;

[0036] A second electrode structure electrically connected to the second type reflector layer is formed on the surface of the second type reflector layer; the second electrode structure has opposite polarity to the first electrode structure.

[0037] In one embodiment, after the step of mesa etching the epitaxial material structure to form a plurality of epitaxial structures, the method further comprises:

[0038] The sidewalls of each epitaxial structure are oxidized by a wet oxidation process, so that part of the second-type reflector layer is oxidized to form a photoelectric confinement layer.

[0039] In one embodiment, the step of forming a first electrode structure electrically connected to the first type reflector layer on the exposed surface of the first type reflector layer comprises:

[0040] forming a protective layer covering the exposed first-type reflector layer and the second electrode structure; forming a first through hole in the protective layer, wherein the first through hole exposes the first-type reflector layer; and forming the first electrode structure based on the first through hole;

[0041] Alternatively, the first sub-electrode of the first electrode structure is formed on the top surface of the exposed first-type reflector layer; a protective layer is formed to cover the exposed first-type reflector layer, the second electrode structure and the first sub-electrode; a first through hole is formed in the protective layer, the first through hole exposing the first sub-electrode; and the second sub-electrode of the first electrode structure is formed in the first through hole.

[0042] In the above two-dimensional addressable VCSEL array, in a direction parallel to the substrate, the distance between the first sub-electrode in the first electrode structure of the same VCSEL unit and the side wall of the groove is greater than the distance between the second sub-electrode and the same side wall, thereby reducing the probability of the constituent material of the first electrode structure laterally diffusing to the side wall of the groove, reducing the risk of failure of the VCSEL unit in the two-dimensional addressable VCSEL array due to the lateral diffusion, and improving the performance and reliability of the VCSEL unit in the two-dimensional addressable VCSEL array.

[0043] In the above-mentioned method for preparing the two-dimensional addressable VCSEL array, the distance between the first sub-electrode in the first electrode structure formed on the surface of the exposed first-type reflector layer and the side wall of the groove is greater than the distance between the second sub-electrode and the same side wall, thereby reducing the probability of the constituent material of the first electrode structure to diffuse laterally to the side wall of the groove, reducing the risk of failure of the VCSEL unit in the two-dimensional addressable VCSEL array due to the lateral diffusion, and improving the performance and reliability of the VCSEL unit in the two-dimensional addressable VCSEL array. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] FIG1 is a cross-sectional schematic diagram of a two-dimensional addressable VCSEL array in some embodiments;

[0046] FIG2 is a cross-sectional schematic diagram of a two-dimensional addressable VCSEL array in another embodiment;

[0047] Figure 3 is a cross-sectional schematic diagram of a two-dimensional addressable VCSEL array in yet another embodiment;

[0048] Figure 4 Schematic diagram of the process of preparing a two-dimensional addressable VCSEL array in some embodiments.

[0049] Description of reference numerals:

[0050] Groove 101; epitaxial material structure 102; protective layer 104; first electrode structure 106; second electrode structure 108; substrate 110; passivation layer 112; metal interconnect electrode 114; isolation grooves 116, 120; isolation layers 118, 122; back metal layer 126; photoelectric confinement layer 128; third passivation layer 130; first type reflector layer 202; active layer 204; second type reflector layer 206; first sub-electrode 208; second sub-electrode 210; first Bragg reflector 302; first semiconductor confinement layer 304; second Bragg reflector 306; second semiconductor confinement layer 308. DETAILED DESCRIPTION

[0051] In order to facilitate understanding of the embodiments of the present disclosure, the embodiments of the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present disclosure are shown in the drawings. However, the embodiments of the present disclosure can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present disclosure more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the disclosed embodiments belong. The terms used herein in the specification of the disclosed embodiments are only for the purpose of describing specific embodiments and are not intended to limit the disclosed embodiments. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0053] In the description of the embodiments of the present disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc. indicating orientations or positional relationships are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present disclosure.

[0054] It is understood that the terms "first", "second", etc. used in the present disclosure may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of the present disclosure, a first electrode structure may be referred to as a second electrode structure, and similarly, a second electrode structure may be referred to as a first electrode structure. Both the first electrode structure and the second electrode structure are electrode structures, but they are not the same electrode structure.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of the present disclosure, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0056] FIG1 is a cross-sectional schematic diagram of a two-dimensional addressable VCSEL array in some embodiments. For example, the X direction may be a first direction perpendicular to the substrate 110 shown in FIG1 , the Y direction may be a third direction parallel to the substrate 110 in FIG1 , and the Z direction may be a second direction parallel to the substrate 110 in FIG1 . The third direction Y and the second direction Z intersect.

[0057] As shown in FIG. 1 , in this embodiment, a two-dimensional addressable VCSEL array is provided, comprising: a plurality of VCSEL units, each of which is separated by a groove 101; each of the VCSEL units comprises: a substrate 110, a first-type reflector layer 202, an active layer 204, a second-type reflector layer 206, a plurality of first electrode structures 106 and a plurality of second electrode structures 108; the first-type reflector layer 202, the active layer 204 and the second-type reflector layer 206 are sequentially arranged on the substrate 110 along a first direction perpendicular to the substrate 110; the groove 101 exposes a portion of the surface of the first-type reflector layer 202.

[0058] The first electrode structure 106 is arranged on the partial surface of the first-type reflector layer 202 exposed by the groove 101, and is electrically connected to the first-type reflector layer 202; wherein, part of the first electrode structure 106 is located near the first side wall of the groove 101 (the left side wall of the groove 101 in FIG. 1 ), and part of the first electrode structure 106 is located near the second side wall of the groove 101 (the right side wall of the groove 101 in FIG. 1 ), and the positions of the first side wall and the second side wall are opposite; the first electrode structure 106 includes a first sub-electrode 208 and a second sub-electrode 210; in the same VCSEL unit, the distance L1 between the first sub-electrode 208 and the side wall of the groove 101 is greater than the distance L2 between the second sub-electrode 210 and the same side wall; the second electrode structure 108 is arranged on the second-type reflector layer 206 and is electrically connected to the second-type reflector layer 206; the polarity of the second electrode structure 108 and the first electrode structure 106 are opposite.

[0059] In one embodiment of the present application, the material of the substrate 110 includes a silicon substrate, a sapphire substrate or a low-doped III-V compound, where the III-V compound refers to a compound including a III-group element and a V-group element, such as GaAs. The first-type reflector layer 202 and the second-type reflector layer 206 have opposite conductivity types, that is, one is N-type doped and the other is P-type doped. As an example, the first-type reflector layer 202 is N-type and the second-type reflector layer 206 is P-type. As an example, the orthographic projection of the second electrode structure 108 on the substrate 110 is a ring with a certain width.

[0060] As an example, the active layer 204 is used to form a resonant cavity between the first type reflector layer 202 and the second type reflector layer 206. The active layer 204 includes a quantum well, and the material of the active layer 204 includes one or more of AlInGaAs (e.g., AlInGaAs, GaAs, AlGaAs, and InGaAs), InGaAsP (e.g., InGaAsP, GaAs, InGaAs, GaAsP, and GaP), GaAsSb (e.g., GaAsSb, GaAs, and GaSb), InGaAsN (e.g., InGaAsN, GaAs, InGaAs, GaAsN, and GaN), or AlInGaAsP (e.g., AlInGaAsP, AlInGaAs, AlGaAs, InGaAs, InGaAsP, GaAs, InGaAs, GaAsP, and GaP).

[0061] As an example, the first sub-electrode 208 and the second sub-electrode 210 in the first electrode structure 106 are sequentially arranged in contact with each other in the first direction X along a direction away from the substrate 110 , and opposite polarities mean that one is a cathode electrode and the other is an anode electrode.

[0062] In the above two-dimensional addressable VCSEL array, in a direction parallel to the substrate 110, a distance L1 between the first sub-electrode 208 in the first electrode structure 106 of the same VCSEL unit and the side wall of the groove 101 is greater than a distance L2 between the second sub-electrode 210 and the same side wall, thereby reducing the probability of the constituent material of the first electrode structure 106 laterally diffusing to the side wall of the groove 101, reducing the risk of failure of the VCSEL unit in the two-dimensional addressable VCSEL array due to the lateral diffusion, and improving the performance and reliability of the VCSEL unit in the two-dimensional addressable VCSEL array.

[0063] 1 , in one embodiment, the orthographic projection of the first sub-electrode 208 on the substrate 110 is located within the orthographic projection of the second sub-electrode 210 on the substrate 110. The cross-sectional area of ​​the second sub-electrode 210 far from the substrate 110 in the first electrode structure 106 is larger than the cross-sectional area of ​​the first sub-electrode 208 close to the substrate 110, thereby reducing the device resistance of the VCSEL unit in the two-dimensional addressable VCSEL array, and the first electrode structure 106 has a large heat dissipation area, thereby improving the heat dissipation effect of the VCSEL unit in the two-dimensional addressable VCSEL array.

[0064] Further, referring to FIG. 1 , in this specific embodiment, the cross-sectional shape of the first electrode structure 106 can be a "T" shape, that is, the first sub-electrode 208 is an "I" shape, and the second sub-electrode 210 is an "I" shape. In this way, the second sub-electrode 210 can further make up for the defects of the first sub-electrode 208 in terms of heat dissipation and resistance because it has a larger cross-sectional area. It is easy to understand that in other embodiments, under the conception of this specific embodiment, the first sub-electrode 208 and the second sub-electrode 210 in the first electrode structure 106 can also be a combination of various other shapes, so that the first electrode structure 106 has different cross-sectional shapes, and this application does not impose further restrictions on this.

[0065] Specifically, in the first direction X, the thickness of the first sub-electrode 208 may be smaller than the thickness of the second sub-electrode 210, or the thickness of the first sub-electrode 208 is equal to the thickness of the second sub-electrode 210, or the thickness of the first sub-electrode 208 may be greater than the thickness of the second sub-electrode 210. In this way, the requirements of various scenarios can be met and flexible configuration can be achieved.

[0066] Furthermore, considering a more thorough insulation effect, in this specific embodiment, the first sub-electrode 208 and the second sub-electrode 210 of the same VCSEL unit are set to be flush with each other on the side away from the side wall of the groove 101, so that the cross-sectional shape of the first electrode structure 106 finally formed is similar to a "7" shape, so that in the horizontal direction Z, the distance between the first electrode structures 106 of two different VCSEL units will not become closer because the second sub-electrode 210 is longer than the first sub-electrode 208 in the horizontal direction Z, and the distance between the first electrode structures 106 of the two different VCSEL units can be reduced accordingly, thereby improving the insulation effect. It is easy to understand that in other embodiments, under the conception of this specific embodiment, the first sub-electrode 208 and the second sub-electrode 210 in the first electrode structure 106 can also be a combination of various other shapes, so that the first electrode structure 106 has different cross-sectional shapes, and this application does not impose further restrictions on this.

[0067] Referring to FIG. 1 , in one embodiment, the two-dimensional addressable VCSEL array further includes: a passivation layer 112 and a metal interconnection electrode 114; the passivation layer 112 covers the first electrode structure 106 and the second electrode structure 108; the metal interconnection electrode 114 is located on a side of the passivation layer 112 away from the second electrode structure 108, covers the inner wall of the groove 101, penetrates the passivation layer 112 along a first direction X perpendicular to the substrate 110, and is electrically connected to the second electrode structure 108 of the plurality of VCSEL units arranged along a second direction Z parallel to the substrate 110, that is, the plurality of VCSEL units arranged at intervals along the second direction Z share a common metal interconnection electrode 114.

[0068] The passivation layer 112 can separate the metal interconnection electrode 114 and the first electrode structure 106. The metal interconnection electrode 114 connects the second electrode structures 108 of the VCSEL units arranged along the second direction Z together. The second electrode structures 108 of the multiple VCSEL units arranged along the second direction Z can be led out through the metal interconnection electrode 114.

[0069] As an example, the metal interconnection electrodes 114 extend along the second direction Z, and a plurality of metal interconnection electrodes 114 are arranged at intervals along a third direction Y parallel to the substrate 110 , and are respectively connected to a plurality of VCSEL units arranged at intervals along the third direction Y.

[0070] Referring to FIG. 1 , in one embodiment, the first type reflector layer 202 includes: a first Bragg reflector 302 and a first semiconductor confinement layer 304; the first Bragg reflector 302 is located on the substrate 110; the first semiconductor confinement layer 304 has the same conductivity type as the first Bragg reflector 302 and is located on the top surface of the first Bragg reflector 302 away from the substrate 110; wherein the active layer 204 is located on the first semiconductor confinement layer 304; the groove 101 exposes a portion of the surface of the first semiconductor confinement layer 304, and the bottom surface of the first electrode structure 106 contacts the exposed portion of the surface of the first semiconductor confinement layer 304. The first semiconductor confinement layer 304 can be used for ohmic contact conduction and is also used to adjust the length of the resonant cavity, and the length of the resonant cavity corresponds to the emission wavelength of the laser.

[0071] As an example, the first Bragg reflector 302 includes a first AlGaAs layer and a second AlGaAs layer which are alternately stacked and have the same doping type; the first AlGaAs layer and the second AlGaAs layer both contain aluminum, and the content of the aluminum in the first AlGaAs layer is greater than the content of the aluminum in the second AlGaAs layer. The first AlGaAs layer and the second AlGaAs layer have different refractive indices, forming a distributed Bragg reflector (DBR). The material of the first semiconductor confinement layer 304 includes a doped semiconductor, such as doped gallium arsenide or doped indium gallium arsenide.

[0072] Referring to FIG. 1 , in one embodiment, the second type reflector layer 206 includes: a second Bragg reflector 306 and a second semiconductor confinement layer 308; the second Bragg reflector 306 is located on the top surface of the active layer 204 away from the substrate 110; the second semiconductor confinement layer 308 has the same conductivity type as the second Bragg reflector 306 and is located on the top surface of the second Bragg reflector 306 away from the substrate 110; wherein the bottom of the second electrode structure 108 contacts the top surface of the second semiconductor confinement layer 308. The second semiconductor confinement layer 308 is used for ohmic contact conduction and is also used to adjust the resonant cavity length, which corresponds to the emission wavelength of the laser.

[0073] As an example, the second Bragg reflector 306 includes a third AlGaAs layer and a fourth AlGaAs layer which are alternately stacked and have the same doping type; the third AlGaAs layer and the fourth AlGaAs layer both contain aluminum, and the content of the aluminum in the third AlGaAs layer is greater than the content of the aluminum in the fourth AlGaAs layer. The third AlGaAs layer and the fourth AlGaAs layer have different refractive indices, forming a distributed Bragg reflector (DBR). The material of the second semiconductor confinement layer 308 includes a doped semiconductor, such as doped gallium arsenide or doped gallium indium arsenide.

[0074] Referring to FIG. 1 , in one embodiment, the two-dimensional addressable VCSEL array further includes: an isolation groove 116; the isolation groove 116 is located below the groove 101 and communicates with the groove 101, that is, the isolation groove 116 is located between the first type reflector layer 202 of adjacent VCSEL units, the bottom of the isolation groove 116 is between the bottom of the groove 101 and the surface of the substrate 110, that is, the bottom of the isolation groove 116 is between the bottom of the groove 101 and the top surface of the substrate 110 forming the first type reflector layer 202, or the bottom of the isolation groove 116 is between the bottom of the groove 101 and the bottom surface of the substrate 110, at this time, the isolation groove 116 is opened to the inside of the substrate 110; the bottom surface of the substrate 110 is arranged opposite to the top surface of the substrate 110. The arrangement of the isolation groove 116 realizes the electrical isolation between the first type reflector layers 202 of two adjacent VCSEL units. It can be understood that the passivation layer 112 extends to cover the inner wall of the isolation groove 116.

[0075] As an example, when the bottom of the isolation groove 116 is between the bottom of the groove 101 and the top surface of the substrate 110 forming the first type reflector layer, the distance between the bottom of the isolation groove 116 and the top surface of the first type reflector layer 202 is greater than or equal to 2 / 3 of the thickness of the first type reflector layer 202 in the first direction X.

[0076] FIG2 is a cross-sectional schematic diagram of a two-dimensional addressable VCSEL array in another embodiment. Referring to FIG2 , in one embodiment, the two-dimensional addressable VCSEL array further includes: an isolation layer 118; located below the groove 101, the isolation layer 118 is formed by proton implantation of a portion of the surface of the first type reflector layer 202 between adjacent first electrode structures 106. The provision of the isolation layer 118 realizes electrical isolation between the first type reflector layers 202 of two adjacent VCSEL units. It can be understood that the passivation layer 112 extends to cover the isolation layer 118. After proton implantation, the bottom of the isolation layer 118 is located between the top surface of the first type reflector layer 202 and the top surface of the substrate 110. By reducing the distance between the bottom of the isolation layer 118 and the top surface of the substrate 110, the insulation capacity between adjacent VCSEL units can be increased.

[0077] As an example, the distance between the bottom of the isolation layer 118 and the top surface of the first-type reflector layer 202 is greater than or equal to ⅔ of the thickness of the first-type reflector layer 202 in the first direction X.

[0078] Figure 3 FIG. 1 is a cross-sectional schematic diagram of a two-dimensional addressable VCSEL array in another embodiment, see Figure 3 In one embodiment, the two-dimensional addressable VCSEL array further includes: an isolation groove 120 and an isolation layer 122; the isolation groove 120 is located below the groove 101 and is connected to the groove 101, and the bottom of the isolation groove 120 is between the bottom of the groove 101 and the top surface of the substrate 110; the isolation layer 122 is located below the isolation groove, and the isolation layer 122 is formed by proton implantation of the first type reflector layer 202 at the bottom of the isolation groove 120; wherein the passivation layer 112 extends to cover the inner wall of the isolation groove 120, and the setting of the isolation groove 120 and the isolation layer 122 jointly realizes the electrical isolation between the first type reflector layers 202 of two adjacent VCSEL units.

[0079] As an example, the bottom of the isolation trench 120 is lower than the bottom surface of the first semiconductor confinement layer 304, thereby achieving physical isolation between adjacent first semiconductor confinement layers 304. The isolation layer 122 is located between adjacent first Bragg reflectors 302, thereby achieving electrical isolation between adjacent first Bragg reflectors 302.

[0080] See also Figure 3 In one embodiment, the two-dimensional addressable VCSEL array further includes: a back metal layer 126; the back metal layer 126 is located on a side of the substrate 110 away from the VCSEL unit, for forming an ohmic contact.

[0081] See also Figure 3In one embodiment, the VCSEL unit further includes: a photoelectric limiting layer 128; the photoelectric limiting layer 128 is located between the active layer 204 and the second-type reflector layer 206, and the photoelectric limiting layer 128 is used to limit the light-emitting area of ​​the VCSEL unit; wherein the orthographic projection of the second electrode structure 108 on the substrate 110 is located within the orthographic projection of the photoelectric limiting layer 128 on the substrate 110.

[0082] Specifically, the photoelectric confinement layer 128 may include any one of an air column type photoelectric confinement layer, an oxidation confinement type photoelectric confinement layer, an ion implantation type photoelectric confinement layer, and a tunnel junction type photoelectric confinement layer. Among them, the air column type photoelectric confinement layer realizes the restriction of current and light through an air column, and the air column is a hollow structure formed by dry etching technology, and its refractive index is lower than that of the surrounding semiconductor material, thereby effectively restricting the light in the central area. The ion implantation type photoelectric confinement layer changes its electrical properties by injecting ions into the semiconductor material to form a high resistance area, which can restrict the flow of current, thereby indirectly restricting the light generation area.

[0083] In one embodiment, with continued reference to FIG. 1, the oxidation-restricted photoelectric confinement layer includes an unoxidized region of AlGaAs material with a high aluminum component and an oxidized region of aluminum oxide material, the oxidized region is located outside the unoxidized region, and the unoxidized region forms a light-emitting region for effective current injection. Among them, the semiconductor layer in the unoxidized region of the photoelectric confinement layer can be understood as an opening, and the opening is used to define the light-emitting region of the VCSEL unit. When the current enters, the current can only flow to the active layer 204 through the opening in the photoelectric confinement layer 128, thereby achieving the restriction of the current injection path and the optical mode field. Further, the AlGaAs layer with a high aluminum component can be converted into aluminum oxide through a selective oxidation process to form an unoxidized region on the periphery. Further, the opening sizes of different photoelectric confinement layers 128 can be the same or different. In the case where the openings of multiple photoelectric confinement layers 128 are different, the light-emitting region defined by the photoelectric confinement layer 128 with the smallest opening is used as the light-emitting region of the VCSEL unit.

[0084] In one of the embodiments, the tunnel junction type photoelectric confinement layer includes at least one highly doped N-type structure layer and at least one highly doped P-type structure layer. Specifically, a potential barrier is formed between the highly doped N-type structure layer and the highly doped P-type structure layer, and electrons are allowed to pass through the potential barrier by tunneling, thereby achieving lateral confinement of the current. In one of the embodiments, the material of the N-type structure layer and the P-type structure layer is selected as AlxGa1-xAs, and the doping concentration of the N-type structure layer and the P-type structure layer is greater than 1e18cm-3, where 0≤x≤1.

[0085] See also Figure 3In one embodiment, the two-dimensional addressable VCSEL array further includes: a protective layer 104 and a third passivation layer 130; the protective layer 104 is disposed on the top surface of the second-type reflector layer 206 away from the substrate 110, and extends to cover the inner wall of the groove 101; the third passivation layer 130 covers the top surface and sidewall of the second electrode structure 108 away from the substrate 110, and extends along the sidewall of the second electrode structure 108 to cover the top surface of the second-type reflector layer 206; wherein the protective layer 104 covers the third passivation layer 130, and the metal interconnect electrode 114 penetrates the third passivation layer 130. The third passivation layer 130 is used to protect the second electrode structure 108 and prevent the second electrode structure 108 from oxidation or electrochemical effects.

[0086] In one embodiment, the plurality of VCSEL units arranged along a third direction Y parallel to the substrate 110 share the first electrode structure 106. As an example, the first electrode structure 106 extends along the third direction Y, and the plurality of first electrode structures 106 are arranged at intervals along a second direction Z parallel to the substrate 110, and are electrically connected to the plurality of VCSEL chips arranged at intervals along the second direction Z, respectively.

[0087] In one embodiment, the first sub-electrode 208 and the second sub-electrode 210 in the first electrode structure 106 are an integrally formed structure, which prevents the abnormal contact between the first sub-electrode 208 and the second sub-electrode 210 from affecting the performance of the VCSEL unit in the two-dimensional addressable VCSEL array.

[0088] A and B are an integrated structure, which means that there is no obvious boundary interface such as a fault or gap between A and B in the microstructure. Generally, a structure formed by patterning a film layer or a structure formed by a film layer is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0089] In one embodiment of the present application, the materials of each passivation layer and protection layer include silicon oxide and silicon nitride.

[0090] The two-dimensional addressable VCSEL array and the method for preparing the two-dimensional addressable VCSEL array of the present application are based on the same inventive concept. For the contents not specifically described in the method for preparing the two-dimensional addressable VCSEL array, please refer to the introduction to the two-dimensional addressable VCSEL array in the previous text.

[0091] Figure 4 1 is a schematic diagram of a method for preparing a two-dimensional addressable VCSEL array in some embodiments, as shown in FIG. Figure 4 As shown, in this embodiment, the present application accordingly provides a method for preparing a two-dimensional addressable VCSEL array, comprising:

[0092] S102, providing a wafer.

[0093] The wafer includes a substrate 110 and an epitaxial material structure 102 . The epitaxial material structure 102 includes a first-type reflector layer 202 , an active layer 204 , and a second-type reflector layer 206 which are sequentially disposed on the substrate 110 .

[0094] S104, performing mesa etching on the epitaxial material structure to form a plurality of epitaxial structures.

[0095] The epitaxial material structure 102 is mesa-etched to form a groove 101 in the epitaxial material structure 102 to obtain a plurality of epitaxial structures. Each of the epitaxial structures is separated by the groove 101 , and the groove 101 exposes a portion of the surface of the first-type reflector layer 202 .

[0096] S106 , forming a first electrode structure electrically connected to the first type reflector layer on the exposed surface of the first type reflector layer.

[0097] A first electrode structure 106 electrically connected to the first type reflector layer 202 is formed on the surface of the first type reflector layer 202 exposed at the bottom of the groove 101; wherein the first electrode structure 106 includes a first sub-electrode 208 and a second sub-electrode 210; and a distance L1 between the first sub-electrode 208 and the side wall of the groove 101 is greater than a distance L2 between the second sub-electrode 210 and the same side wall.

[0098] S108 , forming a second electrode structure electrically connected to the second type reflector layer on the surface of the second type reflector layer.

[0099] A second electrode structure 108 electrically connected to the second-type reflector layer 206 is formed on the surface of the second-type reflector layer 206 , and the second electrode structure 108 and the first electrode structure 106 have opposite polarities.

[0100] In the above-mentioned method for preparing the two-dimensional addressable VCSEL array, the distance L1 between the first sub-electrode 208 in the first electrode structure 106 formed on the surface of the exposed first-type reflector layer 202 and the side wall of the groove 101 is greater than the distance L2 between the second sub-electrode 210 and the same side wall, thereby reducing the probability of the constituent material of the first electrode structure 106 to diffuse laterally to the side wall of the groove 101, reducing the risk of failure of the VCSEL unit in the two-dimensional addressable VCSEL array due to the lateral diffusion, and improving the performance and reliability of the VCSEL unit in the two-dimensional addressable VCSEL array.

[0101] In one embodiment, before the epitaxial material structure 102 is mesa-etched to form a plurality of epitaxial structures, a second electrode structure 108 electrically connected to the second type reflector layer 206 is formed on the surface of the second type reflector layer 206; the method for preparing a two-dimensional addressable VCSEL array further includes: forming a third passivation layer 130 on the second electrode structure 108, the third passivation layer 130 covering the top surface and sidewalls of the second electrode structure 108, and extending to cover the surface of the second type reflector layer 206; wherein the groove 101 penetrates the third passivation layer 130. The third passivation layer 130 can protect the second electrode structure 108 and prevent the second electrode structure 108 from oxidation or electrochemical effects.

[0102] Referring to FIG. 1 , in one embodiment, the method for preparing a two-dimensional addressable VCSEL array further includes: forming an isolation groove 116 connected to the groove 101 below the groove 101, the isolation groove 116 is located between the first-type reflector layers 202 of adjacent epitaxial structures, and the bottom of the isolation groove 116 is between the bottom of the groove 101 and the surface of the substrate 110. The setting of the isolation groove 116 separates the first-type reflector layers 202 of two adjacent epitaxial structures. The distance between the opposite side walls of the groove 101 is greater than the distance between the opposite side walls of the isolation groove 116, that is, the orthographic projection of the isolation groove 116 on the substrate 110 is located in the orthographic projection of the groove 101 on the substrate 110. The setting of the isolation groove 116 realizes the insulation between the first-type reflector layers 202 of two adjacent epitaxial structures.

[0103] Referring to FIG. 2 , in one embodiment, the method for preparing a two-dimensional addressable VCSEL array further includes: forming an isolation layer 118 below the groove 101, the isolation layer 118 being formed by proton implantation of a portion of the surface of the first type reflector layer 202 between adjacent first electrode structures 106; the distance between opposite side walls of the groove 101 is greater than the distance between opposite side walls of the isolation layer 118, that is, the orthographic projection of the isolation layer 118 on the substrate 110 is located in the orthographic projection of the groove 101 on the substrate 110. The provision of the isolation layer 118 realizes electrical isolation between the first type reflector layers 202 of two adjacent epitaxial structures.

[0104] See also Figure 3 In one embodiment, the method for preparing a two-dimensional addressable VCSEL array further includes: steps S202-S204.

[0105] S202 , based on the trench 101 , forming an isolation trench 120 in the first type reflector layer 202 exposed at the bottom of the trench 101 .

[0106] Specifically, based on the groove 101, part of the first-type reflector layer 202 at the bottom of the groove 101 is etched away to form an isolation groove 120 located in the first-type reflector layer 202, and the bottom of the isolation groove 120 exposes the first-type reflector layer 202. The distance between the opposite side walls of the groove 101 is greater than the distance between the opposite side walls of the isolation groove 120, that is, the orthographic projection of the isolation groove 120 on the substrate 110 is located in the orthographic projection of the groove 101 on the substrate 110.

[0107] S204 , ion implantation is performed on the first type reflector layer 202 exposed by the isolation groove 120 to form an isolation layer 122 , and the top surface of the isolation layer 122 is exposed at the bottom of the isolation groove 120 .

[0108] See Figure 1- Figure 3 In one of the embodiments, after the step of performing mesa etching on the epitaxial material structure 102 to form a plurality of epitaxial structures, it further includes: performing oxidation treatment on the sidewalls of each of the epitaxial structures using a wet oxidation process so that a portion of the second-type reflector layer 206 is oxidized to form a photoelectric confinement layer.

[0109] See Figure 1- Figure 3 In one embodiment, forming a first electrode structure 106 electrically connected to the first type reflector layer 202 on the exposed surface of the first type reflector layer 202 includes: steps S302-S306.

[0110] S302 , forming a protection layer 104 covering the exposed first-type reflector layer 202 and the second electrode structure 108 .

[0111] S304 , forming a first through hole in the protection layer 104 , wherein the first through hole exposes the first type reflector layer 202 .

[0112] S306 , forming the second sub-electrode 210 of the first electrode structure 106 based on the first through hole.

[0113] Steps S302-S306 specifically include forming a protective layer 104 on the epitaxial structure using a film forming process, such as an atomic layer deposition process, wherein the protective layer 104 covers the top surface of the epitaxial structure and the second electrode structure 108. Figure 3For example, the protective layer 104 extends to cover the inner wall of the trench 101 and the inner wall of the isolation trench 120. Secondly, a first through hole is formed in the protective layer 104 at the bottom of the trench 101, and the bottom of the first through hole exposes the first type reflector layer 202. Thirdly, a first electrode structure 106 is formed based on the first through hole, and the first sub-electrode 208 of the first electrode structure 106 is located in the first through hole, and the second sub-electrode 210 of the first electrode structure 106 is located on the top of the first sub-electrode 208 and covers a portion of the surface of the protective layer 104 close to the first through hole. It can be clearly seen that the protective layer 104 is provided between the second sub-electrode 210 close to the side wall of the epitaxial structure and the side wall of the epitaxial structure. Furthermore, the passivation layer 112 is provided between the second sub-electrode 210 close to the side wall of the epitaxial structure and the side wall of the epitaxial structure.

[0114] It can be understood that when the first through hole is a step hole and the size of the opening part of the step hole away from the substrate 110 is larger than the size close to the bottom of the substrate 110, the first sub-electrode 208 and the second sub-electrode 210 of the first electrode structure 106 can be formed in the step hole.

[0115] See Figure 1- Figure 3 In one embodiment, forming a first electrode structure 106 electrically connected to the first type reflector layer 202 on the exposed surface of the first type reflector layer 202 includes: steps S402-S408.

[0116] S402 , forming the first sub-electrode 208 of the first electrode structure 106 on the exposed top surface of the first-type reflector layer 202 .

[0117] S404 , forming a protection layer covering the exposed first-type reflector layer 202 , the second electrode structure 108 , and the first sub-electrode 208 .

[0118] S406 , forming a first through hole in the protection layer, wherein the first through hole exposes the first sub-electrode.

[0119] S408 , forming the second sub-electrode of the first electrode structure in the first through hole.

[0120] Steps S402-S408 are specifically to form the first sub-electrode 208 of the first electrode structure 106 on the top surface of the first type reflector layer 202 at the bottom of the groove 101 by using a film forming process, such as an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process. Next, a protective layer 104 is formed on the epitaxial structure, and the protective layer 104 covers the top surface of the epitaxial structure, the second electrode structure 108, and the first sub-electrode 208. Figure 3For example, the protective layer 104 extends to cover the inner wall of the trench 101 and the inner wall of the isolation trench 120. Again, a first through hole is formed in the protective layer 104, and the bottom of the first through hole exposes the top surface of the first sub-electrode 208 and the protective layer 104 on one side of the first sub-electrode 208, that is, the bottom size of the first through hole is larger than the size of the top surface of the first sub-electrode 208. Then, the second sub-electrode 210 of the first electrode structure 106 is formed in the first through hole.

[0121] In one embodiment, the method for preparing a two-dimensional addressable VCSEL array further includes: forming a passivation layer 112 on the first electrode structure 106, the passivation layer 112 covers the first electrode structure 106 and the second electrode structure 108, and the passivation layer 112 isolates the first electrode structure 106 from a subsequently formed metal interconnect electrode 114. Further, the passivation layer 112 covers the top surface and sidewalls of the first electrode structure 106.

[0122] In one of the embodiments, the method for preparing a two-dimensional addressable VCSEL array further includes: forming a plurality of second through holes in the passivation layer 112, the second through holes exposing corresponding second electrode structures 108; forming metal interconnect electrodes 114 corresponding to the second electrode structures 108 in the second through holes arranged along a second direction Z parallel to the substrate 110, the metal interconnect electrodes 114 being in contact and connected with the second electrode structure 108 at the bottom.

[0123] In one embodiment, the method for preparing a two-dimensional addressable VCSEL array further includes: thinning the surface of the substrate 110 away from the epitaxial structure; forming a back metal layer 126 on the surface of the substrate 110 away from the epitaxial structure, wherein the back metal layer 126 is used to form an ohmic contact.

[0124] It should be understood that although Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0125] The embodiments of the present disclosure also provide a laser device, including any of the vertical cavity surface emitting laser arrays described above and / or a vertical cavity surface emitting laser array manufactured using any of the methods for manufacturing a vertical cavity surface emitting laser array described above. The laser device may include a laser, a laser cutting device, or a laser marking device.

[0126] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The above-mentioned embodiments only express several implementation methods of the embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the embodiments of the present disclosure, and these all belong to the protection scope of the embodiments of the present disclosure.

Claims

1. A two-dimensional addressable VCSEL array, characterized in that: comprising a plurality of VCSEL units, each of the VCSEL units being separated by a groove; Each of the VCSEL units comprises: a substrate, and a first-type reflector layer, an active layer, and a second-type reflector layer sequentially arranged on the substrate; The groove exposes a portion of the surface of the first type reflector layer; A plurality of first electrode structures are provided on a portion of the surface of the first type reflector layer and are electrically connected to the first type reflector layer; wherein some of the first electrode structures are located near a first side wall of the groove, and some of the first electrode structures are located near a second side wall of the groove, and the first side wall and the second side wall are located opposite to each other; The first electrode structure includes a first sub-electrode and a second sub-electrode; in the same VCSEL unit, the distance between the first sub-electrode and the sidewall of the trench is greater than the distance between the second sub-electrode and the same sidewall; A plurality of second electrode structures are disposed on the second-type reflector layer and electrically connected to the second-type reflector layer; the second electrode structures have opposite polarities to the first electrode structures.

2. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: The orthographic projection of the first sub-electrode on the substrate is located within the orthographic projection of the second sub-electrode on the substrate.

3. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: Also includes: a passivation layer, covering the first electrode structure and the second electrode structure; The metal interconnection electrode is located on a side of the passivation layer away from the second electrode structure, penetrates the passivation layer in a direction perpendicular to the substrate, and is electrically connected to the second electrode structures of the plurality of VCSEL units arranged in a second direction parallel to the substrate.

4. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: Also includes: an isolation trench or an isolation layer; The isolation trench is located below the trench and communicates with the trench, and the bottom of the isolation trench is between the bottom of the trench and the surface of the substrate; The isolation layer is located below the groove, and the isolation layer is formed by performing proton implantation on a portion of the surface of the first-type reflector layer between adjacent first electrode structures.

5. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: Also includes an isolation groove and an isolation layer; The isolation trench is located below the trench and communicates with the trench, and the bottom of the isolation trench is between the bottom of the trench and the top surface of the substrate; The isolation layer is located below the isolation groove, and the isolation layer is formed by proton implantation of the first type reflector layer at the bottom of the isolation groove.

6. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: Also includes: A photoelectric limiting layer, located between the active layer and the second-type reflector layer, the photoelectric limiting layer is used to limit the light emitting area of ​​the VCSEL unit; Wherein, the orthographic projection of the second electrode structure on the substrate is located within the orthographic projection of the photoelectric limiting layer on the substrate.

7. The two-dimensional addressable VCSEL array according to any one of claims 1 to 6, characterized in that: The first type reflector layer comprises: a first Bragg reflector, located on the substrate; a first semiconductor confinement layer, having the same conductivity type as the first Bragg reflector, and located on a top surface of the first Bragg reflector away from the substrate; The active layer is located on the first semiconductor confinement layer; the groove exposes a portion of the surface of the first semiconductor confinement layer, and the bottom surface of the first electrode structure is in contact with the exposed portion of the surface of the first semiconductor confinement layer.

8. The two-dimensional addressable VCSEL array according to any one of claims 1 to 6, characterized in that: The second type reflector layer comprises: A second Bragg reflector is located on a top surface of the active layer away from the substrate; a second semiconductor confinement layer, having the same conductivity type as the second Bragg reflector, and located on a top surface of the second Bragg reflector away from the substrate; Wherein, a bottom surface of the second electrode structure contacts a top surface of the second semiconductor confinement layer.

9. The two-dimensional addressable VCSEL array according to any one of claims 1 to 6, characterized in that: Also includes: The back metal layer is located on a side of the substrate away from the VCSEL unit.

10. A method for preparing a two-dimensional addressable VCSEL array, characterized in that: include: A wafer is provided; the wafer comprises a substrate and an epitaxial material structure, the epitaxial material structure comprises a first type reflector layer, an active layer and a second type reflector layer sequentially arranged on the substrate; Performing mesa etching on the epitaxial material structure to form a plurality of epitaxial structures; wherein each of the epitaxial structures is separated by a groove, and the groove exposes a portion of the surface of the first type reflector layer; A first electrode structure electrically connected to the first type reflector layer is formed on the exposed surface of the first type reflector layer; wherein the first electrode structure comprises a first sub-electrode and a second sub-electrode; and the distance between the first sub-electrode and the sidewall of the groove is greater than the distance between the second sub-electrode and the same sidewall; A second electrode structure electrically connected to the second type reflector layer is formed on the surface of the second type reflector layer; the second electrode structure has opposite polarity to the first electrode structure.

11. The method for preparing a two-dimensional addressable VCSEL array according to claim 10, characterized in that: After the step of performing mesa etching on the epitaxial material structure to form a plurality of epitaxial structures, the method further includes: The sidewalls of each epitaxial structure are oxidized by a wet oxidation process, so that part of the second-type reflector layer is oxidized to form a photoelectric confinement layer.

12. The method for preparing a two-dimensional addressable VCSEL array according to claim 10, characterized in that: The step of forming a first electrode structure electrically connected to the first type reflector layer on the exposed surface of the first type reflector layer comprises: forming a protective layer covering the exposed first-type reflector layer and the second electrode structure; forming a first through hole in the protective layer, wherein the first through hole exposes the first-type reflector layer; and forming the first electrode structure based on the first through hole; Alternatively, the first sub-electrode of the first electrode structure is formed on the top surface of the exposed first-type reflector layer; a protective layer is formed to cover the exposed first-type reflector layer, the second electrode structure and the first sub-electrode; a first through hole is formed in the protective layer, the first through hole exposing the first sub-electrode; and the second sub-electrode of the first electrode structure is formed in the first through hole.

Images