Radio frequency electrostatic protection circuit and radio frequency electrostatic protection system

Abstract

The invention provides a radio frequency electrostatic protection circuit and a radio frequency electrostatic protection system. The radio frequency electrostatic protection circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a first RC network and a second RC network, wherein the first NMOS tube is a deep N-well NMOS tube. According to the radio frequency electrostatic protection circuit, the voltage of the connection point of the body end and the source electrode of the first NMOS tube can be close to the difference between the grid voltage of the first NMOS tube and the breakover voltage threshold value of the first NMOS tube, so that the grid-source voltage of the first NMOS tube is close to the breakover threshold value voltage of the first NMOS tube, and the voltage bearing capacity of the grid electrode of the first NMOS tube cannot be exceeded; therefore, the first NMOS tube is prevented from being burnt out, and a good electrostatic protection effect is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency circuits, and in particular to a radio frequency electrostatic protection circuit and a radio frequency electrostatic protection system. Background Art

[0002] Electrostatic discharge (ESD) is one of the main reasons for the failure of circuit components or integrated circuits. In RF circuits, due to the performance requirements of RF circuits, thin-gate transistors are generally used in chips, and the thin-gate transistors are connected to the I / O pins of the chip. The gate pressure bearing capacity of the thin-gate transistor is relatively small, which makes it easy for the thin-gate transistor to be burned when a large current appears on the gate. Therefore, the thin-gate transistor in the RF chip will be damaged by ESD, and the traditional ESD protection scheme cannot provide good ESD protection for the thin-gate transistor. Summary of the invention

[0003] The purpose of the present invention is to provide a radio frequency electrostatic protection circuit and a radio frequency electrostatic protection system to solve the problem that the traditional ESD protection scheme cannot provide good ESD protection for the thin gate tube in the radio frequency chip.

[0004] To solve the above technical problems, based on one aspect of the present invention, the present invention provides a radio frequency electrostatic protection circuit, which includes a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein the first NMOS tube is a deep N well NMOS tube;

[0005] The drain of the first NMOS tube is connected to the RF device, the gate of the first NMOS tube is connected to the signal port of the RF chip, the source of the first NMOS tube is connected to the drain of the second NMOS tube, the body end of the first NMOS tube, the source of the first NMOS tube and the source of the third NMOS tube are connected; the source of the second NMOS tube is grounded, and the gate of the second NMOS tube is connected to the first power supply voltage through the first RC network; the drain of the third NMOS tube is connected to the first power supply voltage, and the gate of the third NMOS tube is connected to the second power supply voltage through the second RC network.

[0006] Optionally, the first RC network includes a first resistor and a first capacitor, the first end of the first resistor and the first end of the first capacitor are connected together and connected to the gate of the second NMOS tube, the second end of the first resistor is connected to the power supply voltage, and the second end of the first capacitor is grounded.

[0007] Optionally, the second RC network includes a second resistor and a second capacitor, the first end of the second resistor and the first end of the second capacitor are connected together and connected to the gate of the third NMOS tube, the second end of the second resistor is connected to the power supply voltage, and the second end of the second capacitor is grounded.

[0008] Optionally, the RF device includes a first PMOS tube, a gate of the first PMOS tube is connected to a signal port of the RF chip, a drain of the first PMOS tube is connected to a drain of the first NMOS tube, and a source of the first PMOS tube is coupled to the first power supply voltage or the second power supply voltage.

[0009] Optionally, the source of the first PMOS tube and the body of the first PMOS tube are connected to the source of the third NMOS tube.

[0010] Optionally, the radio frequency electrostatic protection circuit further includes a decoupling capacitor, and the source of the third NMOS tube is grounded through the decoupling capacitor.

[0011] Optionally, the first power supply voltage and the second power supply voltage are the same power supply voltage, or the first power supply voltage and the second power supply voltage are different power supply voltages, and the second power supply voltage is provided by a linear regulator.

[0012] Based on another aspect of the present invention, the present invention also provides a radio frequency electrostatic protection system, which includes a power clamping circuit, a first diode, a second diode and the radio frequency electrostatic protection circuit as described above, wherein the power clamping circuit is connected between the first power supply voltage and ground, the anode of the first diode is grounded, the cathode of the first diode is connected to the anode of the second diode, the cathode of the second diode is connected to the first power supply voltage, and the anode of the second diode is connected to the signal port of the radio frequency chip.

[0013] Optionally, the power clamp circuit includes a third resistor, a third capacitor, an inverter, a fourth NMOS tube and a third diode, the first end of the third resistor is connected to the first power supply voltage, the second end of the third resistor is grounded through the third capacitor, the second end of the third resistor is connected to the input end of the inverter, the output end of the inverter is connected to the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the first power supply voltage, the source of the fourth NMOS tube is grounded, the anode of the third diode is grounded, and the cathode of the third diode is connected to the first power supply voltage.

[0014] Optionally, the inverter includes a second PMOS tube and a fifth NMOS tube, the source of the second PMOS tube is connected to the first power supply voltage, the source of the fifth NMOS tube is grounded, the gate of the second PMOS tube and the gate of the fifth NMOS tube are connected and serve as the input end of the inverter, and the drain of the second PMOS tube and the drain of the fifth NMOS tube are connected and serve as the output end of the inverter.

[0015] In the RF electrostatic protection circuit described above, when ESD occurs, such as electrostatic discharge from the signal port of the chip to the ground, the first power supply voltage will be clamped within a safe voltage range by the peripheral power supply clamping voltage. The existence of the first RC network can ensure that the gate voltage of the second NMOS tube is zero during the electrostatic charge discharge period, thereby ensuring that the second NMOS tube is in the off state. Therefore, there is no current return path from the gate of the first NMOS tube to the ground. Therefore, the voltage of the body terminal and the source connection point of the first NMOS tube will increase as the gate voltage of the first NMOS tube increases. Similarly, the gate voltage of the third NMOS tube is not Zero, the third NMOS tube is in the off state, the source voltage of the third NMOS tube will increase as the body voltage of the first NMOS tube increases, so that there is no current return path from the gate of the third NMOS tube to the second power supply voltage, and the voltage of the body and source connection point of the first NMOS tube will be close to the difference between the gate voltage of the first NMOS tube and the turn-on voltage threshold of the first NMOS tube. Therefore, the gate-source voltage of the first NMOS tube is close to the turn-on threshold voltage of the first NMOS tube, so that it will not exceed the pressure bearing capacity of the gate of the first NMOS tube, thereby ensuring that the first NMOS tube will not be burned, and playing a better electrostatic protection role.

[0016] It should be noted that the RF electrostatic protection system includes the RF electrostatic protection circuit, and therefore also has the technical effects brought by the RF electrostatic protection circuit, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0018] Figure 1 This is a schematic diagram of a traditional ESD electrostatic protection circuit;

[0019] Figure 2 is a schematic diagram of a power clamp circuit in the related art;

[0020] Figure 3 is a schematic diagram of a radio frequency electrostatic protection system according to an embodiment of the present invention;

[0021] Figure 4 is a schematic diagram of a radio frequency electrostatic protection circuit according to an embodiment of the present invention;

[0022] Figure 5 is another schematic diagram of a radio frequency electrostatic protection circuit according to an embodiment of the present invention;

[0023] Figure 6 FIG. 4 is another schematic diagram of an electrostatic protection system according to an embodiment of the present invention.

[0024] In the attached figure:

[0025] 10-power clamp circuit; 20-protected circuit; 30-RF device; 40-linear regulator;

[0026] D1-first diode; D2-second diode; D3-third diode;

[0027] N1-first NMOS tube; N2-second NMOS tube; N3-third NMOS tube; N4-fourth NMOS tube; N5-fifth NMOS tube; P1-first PMOS tube; P2-second PMOS tube;

[0028] R1-first resistor; R2-second resistor; R3-third resistor;

[0029] C1-first capacitor; C2-second capacitor; C3-third capacitor; C4-decoupling capacitor; DETAILED DESCRIPTION

[0030] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0031] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "the proximal end" and "the distal end" generally refer to two corresponding parts, which include not only the endpoints, and the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, as used in the present invention, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element may be in any orientation such as inside, outside, above, below or on one side of another element, unless otherwise clearly indicated in the content. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] Figure 1 This is a schematic diagram of a traditional ESD protection circuit. Figure 1 , I / O is the chip input / output pin, and the components directly connected to I / O in the protected circuit 20 need to be designed for ESD protection. Two diodes (first diode D1 and second diode D2) and a power clamp circuit 10 provide ESD protection for the protected circuit 20. The cathode of the second diode D2 is connected to the first power supply voltage, and the anode of the second diode D2 is connected to the protected circuit 20 and I / O; the cathode of the first diode D1 is connected to the protected circuit 20 and I / O, and the anode of the first diode D1 is grounded. The power clamp circuit 10 can clamp the first power supply voltage to a safe voltage (Vclamp) when ESD occurs, thereby realizing electrostatic protection for the protected circuit 20.

[0033] Figure 2 is a schematic diagram of a power clamp circuit in the related art. In one embodiment, refer to Figure 2The power clamp circuit 10 includes a third resistor R3, a third capacitor C3, an inverter, a fourth NMOS transistor N4 and a third diode D3. The first end of the third resistor R3 is connected to the first power supply voltage, the second end of the third resistor R3 is grounded through the third capacitor C3, the second end of the third resistor R3 is connected to the input end of the inverter, the output end of the inverter is connected to the gate of the fourth NMOS transistor N4, the drain of the fourth NMOS transistor N4 is connected to the first power supply voltage, the source of the fourth NMOS transistor N4 is grounded, the anode of the third diode D3 is grounded, and the cathode of the third diode D3 is connected to the first power supply voltage. When the first power supply voltage has an instantaneous high voltage due to charge accumulation, due to the presence of the third resistor R3 and the third capacitor C3, the voltage at the connection point between the third resistor R3 and the third capacitor C3 remains low and is input to the inverter, so that the inverter outputs a high voltage, so that the fourth NMOS transistor N4 is turned on, and a path is formed to discharge the charge on the first power supply voltage. Therefore, the power clamp circuit 10 can clamp the first power voltage to a safe voltage (Vclamp) when electrostatic discharge occurs, thereby protecting the internal circuit.

[0034] As an example, the inverter includes a second PMOS tube P2 and a fifth NMOS tube N5, the source of the second PMOS tube P2 is connected to the first power supply voltage, the source of the fifth NMOS tube N5 is grounded, the gate of the second PMOS tube P2 and the gate of the fifth NMOS tube N5 are connected and serve as the input end of the inverter, and the drain of the second PMOS tube P2 and the drain of the fifth NMOS tube N5 are connected and serve as the output end of the inverter.

[0035] See also Figure 1As can be understood by those skilled in the art, there are four types of charge discharge paths when ESD occurs at the I / O pin, namely, forward and reverse discharge of the I / O pin to the first power supply voltage and forward and reverse discharge of the I / O pin to the ground. Among them, the charge discharge path of the forward discharge of the I / O pin to the first power supply voltage will pass through the second diode D2, and the charge discharge path of the reverse discharge of the I / O pin to the ground will pass through the first diode D1. The conduction voltage of the first diode D1 and the conduction voltage of the second diode D2 are both set to Vdio. Therefore, the voltage generated by the forward discharge of the I / O pin to the first power supply voltage is +Vdio, and the voltage generated by the reverse discharge of the I / O pin to the ground is -Vdio. When the I / O pin discharges reversely to the first power supply voltage, the charge discharge path passes through the power clamp circuit 10 and the first diode D1. When the I / O pin discharges forward to the ground, the charge discharge path passes through the second diode D2 and the power clamp circuit 10. According to the foregoing, the power clamp circuit 10 clamps the first power supply voltage at Vclamp, so the voltage borne by the I / O pin is ±(Vclamp+Vdio).

[0036] Due to the performance requirements of the RF circuit, a thin-gate tube is generally used. The gate of the thin-gate tube is connected to the I / O pin, the source is grounded, and the drain is connected to the RF device 30 (such as an inductor, RF resistor, etc.) of the RF circuit. Therefore, the device connected to the RF input and output (I / O) will be at risk of ESD damage. If the pressure Vclamp+Vdio of the I / O pin is greater than the gate oxide breakdown voltage of the thin-gate tube, the thin-gate tube will be damaged by electrostatic discharge. Therefore, the traditional ESD protection circuit cannot well protect the thin-gate tube of advanced technology.

[0037] Therefore, the traditional ESD design cannot protect the RF I / O well, mainly because the gate pressure of the advanced process is less than Vclamp+Vdio, resulting in a large current on the gate and causing the thin gate tube to burn out. In view of this, this embodiment provides a RF electrostatic protection circuit and a RF electrostatic protection system to solve the problem that the traditional ESD protection scheme cannot provide good ESD protection for the thin gate tube in the RF chip.

[0038] Figure 3 A schematic diagram of a radio frequency electrostatic protection system according to an embodiment of the present invention, Figure 4 FIG. 1 is a schematic diagram of a radio frequency electrostatic protection circuit according to an embodiment of the present invention. Figure 3The RF electrostatic protection system includes a power clamp circuit 10, a first diode D1, a second diode D2 and a RF electrostatic protection circuit. The power clamp circuit 10 is connected between the first power supply voltage and the ground. The anode of the first diode D1 is grounded. The cathode of the first diode D1 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to the first power supply voltage. The anode of the second diode D2 is connected to the signal port of the RF chip (the signal port here is, for example, an I / O pin). Wherein, refer to Figure 4 The radio frequency electrostatic protection circuit includes a first NMOS tube N1, a second NMOS tube N2 and a third NMOS tube N3. The first NMOS tube N1 is a thin gate tube and a deep N well NMOS tube. The second NMOS tube N2 and the third NMOS tube N3 are thick gate tubes. The drain of the first NMOS tube N1 is connected to the radio frequency device 30, the gate of the first NMOS tube N1 is connected to the signal port of the radio frequency chip, the source of the first NMOS is connected to the drain of the second NMOS tube N2, the body end of the first NMOS tube, the source of the first NMOS tube N1 and the source of the third NMOS tube N3 are connected; the source of the second NMOS tube N2 is grounded, and the gate of the second NMOS tube N2 is connected to the first power supply voltage through the first RC network; the drain of the third NMOS tube N3 is connected to the first power supply voltage, and the gate of the third NMOS tube N3 is connected to the second power supply voltage through the second RC network. Further, the first RC network includes a first resistor R1 and a first capacitor C1, the first end of the first resistor R1 and the first end of the first capacitor C1 are connected together and then connected to the gate of the second NMOS transistor N2, the second end of the first resistor R1 is connected to the power supply voltage, and the second end of the first capacitor C1 is grounded, and the second RC network includes a second resistor R2 and a second capacitor C2, the first end of the second resistor R2 and the first end of the second capacitor C2 are connected together and then connected to the gate of the third NMOS transistor N3, the second end of the second resistor R2 is connected to the power supply voltage, and the second end of the second capacitor C2 is grounded. By selecting reasonable parameters of the first RC network and the second RC network, the voltages of the nodes c and d remain substantially unchanged during the occurrence of ESD.

[0039] It should be noted that the first power supply voltage is represented by VCC, and the normal value of the first power supply voltage is also represented by VCC, and the second power supply voltage is represented by VLDO, and the normal value of the second power supply voltage is also represented by VLDO. The first power supply voltage and the second power supply voltage can be the same power supply voltage, or the first power supply voltage and the second power supply voltage can be different power supply voltages, and for example, the second power supply voltage is provided by a linear regulator.

[0040] For example, see Figure 4 Taking the electrostatic discharge from I / O to ground as an example, the first power supply voltage will be clamped to Vclamp by the power clamp circuit 10. Due to the existence of the first RC network (i.e., the first resistor R1 and the first capacitor C1), during the electrostatic charge discharge period, the gate voltage of the second NMOS tube N2 (the voltage at the node c) is still 0V, and the second NMOS tube N2 is not turned on. Since the second NMOS tube N2 is equivalent to an open circuit, the current does not pass through the return path from the gate of the first NMOS tube N1 to the ground. Therefore, the node a (i.e., the body and source of the first NMOS tube N1) will rise as the gate voltage increases. The voltage at node a rises, and the voltage at node b also rises. The parasitic diode (D4) of the first NMOS tube N1 is not turned on, and the current has no return path from the gate to VCC. The voltage at node a will be close to Vclamp+Vdio-Vth1, and Vth1 is the turn-on threshold voltage of the first NMOS tube N1. Therefore, the gate-source voltage of the thin-gate first NMOS tube N1 is close to Vth1, which is less than the gate bearing voltage of the thin-gate tube, and the gate will not be burned.

[0041] When powered on and working normally (non-ESD scenario), the first power supply voltage is the normal value VCC, the voltages of nodes c and d are equal to VCC, the gate-source voltage of the second NMOS tube N2 is VCC, the second NMOS tube N2 is turned on, the third NMOS tube N3 is also turned on, and the voltage at node b is VCC-Vth3, Vth3 is the turn-on threshold voltage of the third NMOS tube N3, the sizes of the second NMOS tube N2 and the third NMOS tube N3 are reasonably selected according to the RF performance, and the first power supply voltage is reasonably selected to ensure that the first NMOS tube N1 will not be forward-conducted, so that the electrostatic protection circuit of the present invention basically does not affect the normal operation of the RF chip.

[0042] Figure 5 FIG. 1 is another schematic diagram of a radio frequency electrostatic protection circuit according to an embodiment of the present invention. Figure 5 The RF device 30 includes a first PMOS tube P1, which is a thin-gate tube. The gate of the first PMOS tube P1 is connected to the signal port of the RF chip. The drain of the first PMOS tube P1 is connected to the drain of the first NMOS tube N1. The source of the first PMOS tube P1 is coupled to the first power supply voltage or the second power supply voltage. In this way, the first PMOS tube P1 and the first NMOS tube N1 form an inverter structure. Furthermore, the source of the first PMOS tube P1 and the body of the first PMOS tube P1 are connected to the source of the third NMOS tube N3.

[0043] When the first power supply voltage is not powered on, the gate voltage of the second NMOS tube N2 is low voltage, and the second NMOS tube N2 is not turned on; the gate voltage of the third NMOS tube N3 is low voltage, and the third NMOS tube N3 is not turned on. When not powered on, nodes a, b, e, and f are all in high impedance state. When ESD occurs, the gate voltage of the first NMOS tube N1 and the first PMOS tube P1 is clamped to Vclamp+Vdio. Since the gates of the first NMOS tube N1 and the first PMOS tube P1 have no current discharge path, the voltages of nodes a, b, e, and f will all increase with the increase of the gate voltage, ensuring that the gates of the first NMOS tube N1 and the first PMOS tube P1 will not be burned by large current due to overvoltage. The gate voltage of the first NMOS tube N1 and the first PMOS tube P1 will eventually decrease with the discharge of ESD charges.

[0044] Figure 6 FIG. 2 is another schematic diagram of a radio frequency electrostatic protection system according to an embodiment of the present invention. Figure 6 , the drain of the third NMOS tube N3 is connected to the linear regulator 40, and the second power supply voltage is provided by the linear regulator 40 to achieve a better power supply rejection ratio. When the circuit is working normally, for example, VCC is 3.3V, the linear regulator 40 outputs 1V, the voltage of nodes c and d is 3.3V, the drain voltage of the first PMOS tube P1 is 1V, the first PMOS tube P1 is turned on, and because the width-to-length ratio of the first PMOS tube P1 is large, the on-resistance is small, and the voltage of node f can be approximately 1V. The voltage of node f can be used as the power supply of the RF circuit, and a decoupling capacitor C4 needs to be added to make the high-frequency power supply at node f become an AC ground, which is beneficial to improving the RF performance, that is, the source of the third NMOS tube N3 is grounded through the decoupling capacitor C4.

[0045] Continue reading Figure 6 , when the I / O pin is forwardly discharged to the ground, the charge of node g will be discharged to the ground through the second diode D2 and the power clamp circuit 10. Therefore, during discharge, the voltage of node g will be clamped to Vclamp+Vdio, and VCC will be clamped to Vclamp. According to the above analysis, when the instantaneous ESD charge arrives, due to the existence of the RC delay composed of R1, C1, R2, and C2, nodes c and d are still 0V, and the second NMOS tube N2 and the third NMOS tube N3 are not turned on. Therefore, the gates of the first NMOS tube N1 and the first PMOS tube P1 have no current discharge path to the ground, and the gates of the first NMOS tube N1 and the first PMOS tube P1 will not be burned due to the large current formed by overvoltage.

[0046] Continue reading Figure 6, when the I / O pin is discharged in reverse to VCC, the charge of node g will be discharged in reverse to VCC through the second diode D2 and the power clamp circuit 10. Therefore, when discharging, node g will be clamped to -(Vclamp+Vdio), VCC is referenced to 0V, and the ground will be clamped to -Vclamp. According to the above analysis, when the instantaneous ESD charge arrives, due to the existence of C1, C2 and the decoupling capacitor C4, the voltages of nodes c, d, and f will follow the ground to -Vclamp, and the second NMOS tube N2 and the third NMOS tube N3 are not turned on. Therefore, there is no current discharge path to VCC through the gate of the first NMOS tube N1 and the gate of the first PMOS tube P1, and the gates of the first NMOS tube N1 and the first PMOS tube P1 will not be burned due to the large current formed by overvoltage.

[0047] Although the present invention is disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A radio frequency electrostatic protection circuit, characterized in that: It includes a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein the first NMOS tube is a deep N-well NMOS tube; The drain of the first NMOS tube is connected to the RF device, the gate of the first NMOS tube is connected to the signal port of the RF chip, the source of the first NMOS tube is connected to the drain of the second NMOS tube, the body end of the first NMOS tube, the source of the first NMOS tube and the source of the third NMOS tube are connected; the source of the second NMOS tube is grounded, and the gate of the second NMOS tube is connected to the first power supply voltage through the first RC network; the drain of the third NMOS tube is connected to the first power supply voltage, and the gate of the third NMOS tube is connected to the second power supply voltage through the second RC network.

2. The radio frequency electrostatic protection circuit according to claim 1, characterized in that: The first RC network includes a first resistor and a first capacitor, the first end of the first resistor and the first end of the first capacitor are connected together and connected to the gate of the second NMOS tube, the second end of the first resistor is connected to the power supply voltage, and the second end of the first capacitor is grounded.

3. The radio frequency electrostatic protection circuit according to claim 1, characterized in that: The second RC network includes a second resistor and a second capacitor, a first end of the second resistor and a first end of the second capacitor are connected together and connected to the gate of the third NMOS tube, a second end of the second resistor is connected to the power supply voltage, and a second end of the second capacitor is grounded.

4. The radio frequency electrostatic protection circuit according to claim 1, characterized in that: The RF device includes a first PMOS tube, a gate of the first PMOS tube is connected to a signal port of the RF chip, a drain of the first PMOS tube is connected to a drain of the first NMOS tube, and a source of the first PMOS tube is coupled to the first power supply voltage or the second power supply voltage.

5. The radio frequency electrostatic protection circuit according to claim 4, characterized in that: The source of the first PMOS tube and the body of the first PMOS tube are connected to the source of the third NMOS tube.

6. The radio frequency electrostatic protection circuit according to claim 5, characterized in that: The radio frequency electrostatic protection circuit also includes a decoupling capacitor, and the source of the third NMOS tube is grounded through the decoupling capacitor.

7. The radio frequency electrostatic protection circuit according to claim 1, characterized in that: The first power supply voltage and the second power supply voltage are the same power supply voltage, or the first power supply voltage and the second power supply voltage are different power supply voltages, and the second power supply voltage is provided by a linear regulator.

8. A radio frequency electrostatic protection system, characterized in that: It includes a power clamp circuit, a first diode, a second diode and a radio frequency electrostatic protection circuit as described in any one of claims 1 to 7, wherein the power clamp circuit is connected between the first power supply voltage and ground, the anode of the first diode is grounded, the cathode of the first diode is connected to the anode of the second diode, the cathode of the second diode is connected to the first power supply voltage, and the anode of the second diode is connected to the signal port of the radio frequency chip.

9. The radio frequency electrostatic protection system according to claim 8, characterized in that: The power clamp circuit includes a third resistor, a third capacitor, an inverter, a fourth NMOS tube and a third diode. The first end of the third resistor is connected to the first power supply voltage, the second end of the third resistor is grounded through the third capacitor, the second end of the third resistor is connected to the input end of the inverter, the output end of the inverter is connected to the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the first power supply voltage, the source of the fourth NMOS tube is grounded, the anode of the third diode is grounded, and the cathode of the third diode is connected to the first power supply voltage.

10. The radio frequency electrostatic protection system according to claim 8, characterized in that: The inverter includes a second PMOS tube and a fifth NMOS tube, the source of the second PMOS tube is connected to the first power supply voltage, the source of the fifth NMOS tube is grounded, the gate of the second PMOS tube and the gate of the fifth NMOS tube are connected and serve as the input end of the inverter, and the drain of the second PMOS tube and the drain of the fifth NMOS tube are connected and serve as the output end of the inverter.

Images