Switching frequency controller, voltage conversion circuit and method for controlling switching frequency of switch

Abstract

The invention provides a switching frequency controller, a voltage conversion circuit and a method for controlling switching frequency of a switch. The switching frequency controller comprises a frequency divider, a frequency detector, an accumulation counter and an on-time controller. The frequency divider generates a frequency division signal having a frequency division frequency according to a target signal having a target frequency, wherein the target frequency is 2N times of the frequency division frequency. The frequency detector receives the frequency division signal and the switching control signal and calculates the number of cycles experienced by the switching control signal in each cycle of the frequency division signal, and the number of cycles is represented by (N + 1) bits. The accumulation counter increases or decreases the index value by a predetermined number according to the maximum ratio of the number of cycles, and the turn-on time controller adjusts the turn-on time length of the switching control signal according to the index value.

Description

Technical Field

[0001] The present invention relates to a switching frequency controller, and in particular to a switching frequency controller capable of adjusting the on-time of a control switching signal to fix the switching frequency. Background Art

[0002] In electronic products, since the supply voltages required by different electronic components may be different, a DC-DC synchronous voltage conversion circuit is often used to convert the power supply voltage into the voltage required by each electronic component. Among various DC-DC synchronous voltage conversion circuits, the voltage conversion circuit controlled by constant on-time (COT) is widely used because of its advantages such as short transient response time and simple structure. Generally speaking, the duration of each time the charging switch is turned on by the voltage conversion circuit controlled by constant on-time is fixed, and the duration of the charging switch being turned off will increase or decrease according to the difference between the current output voltage and the target voltage, so the signal frequency of the control switch is not fixed. In addition, when the electronic component switches between different operating modes, the load current of the voltage conversion circuit may also change, resulting in a change in the frequency of the control switch signal. In some cases, the frequency of the control switch signal may gradually deviate from the originally expected frequency, which may cause electromagnetic interference (EMI) between electronic components and may reduce the circuit efficiency. Therefore, how to design a controller that can maintain the switching frequency has become an urgent problem to be solved in this field.

[0003] The above description of “prior art” is only for providing background technology, and does not acknowledge that the above description of “prior art” is for the purpose of revealing the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as a part of this application. Summary of the invention

[0004] One embodiment of the present application provides a switching frequency controller. The switching frequency controller includes a frequency divider, a frequency detector, a cumulative counter, and an on-time controller. The frequency divider is used to generate a frequency-divided signal having a frequency-divided frequency according to a target signal having a target frequency, wherein the target frequency is 2 times the frequency-divided frequency. N times, where N is a positive integer. The frequency detector is coupled to the frequency divider and is used to receive the frequency-divided signal and the switching control signal generated by the control signal generator, and to count the number of cycles experienced by the switching control signal in each cycle of the frequency-divided signal.

[0005] Each cycle of the switching control signal includes a conduction time and a non-conduction time with different potentials, and the cycle number is represented by (N+1) bits. The cumulative counter is coupled to the frequency detector and is used to set the index value to a starting value at the start stage, and to increase or decrease the index value by a predetermined number according to the highest bit of the cycle number. The conduction time controller is coupled to the cumulative counter and is used to adjust the parameters of the control signal generator according to the index value to adjust the conduction time length of the switching control signal.

[0006] Another embodiment of the present application provides a voltage conversion circuit. The voltage conversion circuit includes the aforementioned switching frequency controller and a control signal generator.

[0007] Another embodiment of the present application provides a method for controlling the switching frequency of a switch, the method comprising using a control signal generator to generate a switching control signal to control the switch, wherein each cycle of the switching control signal comprises a conduction time and a non-conduction time with different potentials, and generating a frequency-divided signal having a frequency-divided frequency according to a target signal having a target frequency, wherein the target frequency is twice the frequency-divided frequency. N times, where N is a positive integer. In each cycle of the frequency-divided signal, the number of cycles experienced by the switching control signal is calculated, where the number of cycles is represented by (N+1) bits. At the initial stage, the indicator value is set to the starting value, and the indicator value is increased or decreased by a predetermined number according to the highest bit of the number of cycles. The parameters of the control signal generator are adjusted according to the indicator value to adjust the on-time length of the switching control signal.

[0008] Since the switching frequency controller, voltage conversion circuit and method for controlling the switching frequency of the switch provided in the embodiments of the present application can divide the target frequency and then compare it with the switching control frequency to monitor the frequency of the switching control signal, and can adjust the on-time length of the switching control signal accordingly, the switching control signal can be effectively controlled within a range close to the target frequency, thereby reducing the electromagnetic interference problems and circuit performance degradation problems that may be caused by the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more complete understanding of the disclosure of the present application can be obtained by referring to the embodiments and claims in conjunction with the accompanying drawings, in which the same reference numerals refer to the same elements.

[0010] Figure 1 is a schematic diagram of a voltage conversion circuit according to an embodiment of the present application.

[0011] Figure 2 It is a signal waveform diagram of a voltage conversion circuit according to an embodiment of the present application.

[0012] Figure 3It is a schematic diagram of a switching frequency controller according to an embodiment of the present application.

[0013] Figure 4 It is a waveform diagram of the target signal, frequency division signal and switching control signal.

[0014] Figure 5 It is a circuit diagram related to the on-time length in an on-time controller and a control signal generator according to an embodiment of the present application.

[0015] Figure 6 It is a flow chart of a method for controlling the switching frequency of a switch according to an embodiment of the present application.

[0016] Explanation of symbols:

[0017] 10: Voltage conversion circuit

[0018] 110: Control signal generator

[0019] 112: Comparator

[0020] 114: Ramp Generator

[0021] 120: Switching frequency controller

[0022] 122: Crossover

[0023] 124: Frequency detector

[0024] 126: Accumulation counter

[0025] 128: On-time controller

[0026] C1: Capacitor

[0027] CCS1 to CCSN: Adjusting the current source

[0028] CSW0 to CSWN: Current source switches:

[0029] C TON :capacitance

[0030] DA1 to DAN, CA1 to CAN: AND gate

[0031] DCS1 to DCSN: Adjusting the current sink

[0032] D N+1 : The highest bit of the cycle number

[0033] DSW0 to DSWN: Current sink switches

[0034] f DV : Crossover frequency

[0035] f TG : Target frequency

[0036] GND: Ground terminal

[0037] I L : Inductor current

[0038] IOUT: output current

[0039] L1: Inductor

[0040] LD: Load

[0041] P1, P2: Time period

[0042] R TON :resistance

[0043] SIG DV : Frequency division signal

[0044] SIG SW : Switching control signal

[0045] SIG SWB : Inverting signal of switching control signal

[0046] SIG TG : Target signal

[0047] SW1, SW2: switches

[0048] TOFF: Non-conduction time

[0049] TON: On time

[0050] VDD: power supply voltage

[0051] VIN: Input voltage

[0052] VLI: indicator value

[0053] VLI N+1 To VLI1: Pointer value bits

[0054] VOUT: output voltage

[0055] V RAMP : Sawtooth voltage

[0056] V REF : Reference voltage. DETAILED DESCRIPTION

[0057] The following description is in conjunction with the accompanying drawings, which are incorporated into this specification and constitute a part of this specification, and illustrate embodiments of the present application, but the present application is not limited to these embodiments. In addition, the embodiments described below can be appropriately integrated to form another embodiment.

[0058] References to "one embodiment", "an embodiment", "exemplary embodiment", "other embodiments", "another embodiment", etc. refer to the embodiment including a specific function, structure or characteristic, but not every embodiment needs to include the specific function, structure or characteristic. Furthermore, when the term "in the embodiment" is used repeatedly, it may refer to the same embodiment, but it does not necessarily refer to the same embodiment.

[0059] In order to make the application fully understood, detailed steps and structures will be provided in the following description. Obviously, the embodiments of the present application are not intended to limit the special details known to those skilled in the art. In addition, the present application will no longer describe in detail known structures and steps to avoid causing unnecessary restrictions to the present application. The preferred embodiments of the present application will be described in detail below. However, in addition to the detailed description, the present application can also be widely implemented in other embodiments. The field of the present application is not limited to these detailed descriptions, but is defined by the claims.

[0060] Figure 1 1 is a schematic diagram of a voltage conversion circuit 10 according to an embodiment of the present application. In this embodiment, the voltage conversion circuit 10 can be used to convert an input voltage VIN to a lower output voltage VOUT, that is, the voltage conversion circuit 10 can be, for example, a buck converter. The voltage conversion circuit 10 includes a control signal generator 110, switches SW1 and SW2, an inductor L1, a capacitor C1, and a switching frequency controller 120.

[0061] like Figure 1 As shown, the switch SW1 has a first terminal, a second terminal and a control terminal. The first terminal of the switch SW1 can receive an input voltage VIN, and the control terminal of the switch SW1 can receive a switching control signal SIG. SW The switch SW2 has a first end, a second end and a control end. The first end of the switch SW2 is coupled to the second end of the switch SW1. The second end of the switch SW2 is coupled to the ground end GND. The control end of the switch SW2 can receive and switch the control signal SIG. SW Inverted control signal SIG SWB The inductor L1 has a first end and a second end, the first end of the inductor L1 is coupled to the second end of the switch SW1, and the second end of the inductor L1 can output the converted voltage VOUT. The capacitor C1 has a first end and a second end, the first end of the capacitor C1 is coupled to the second end of the inductor L1, and the second end of the capacitor C1 is coupled to the ground terminal GND.

[0062] Figure 2 is a signal waveform diagram of a voltage conversion circuit 10 according to an embodiment of the present application. It should be noted that: Figure 2 The waveform shown is only used to assist in the explanation, not to limit the output voltage VOUT, inductor current I Land the waveform of the output current IOUT. In other embodiments, the output voltage VOUT, the inductor current I L The actual waveform of the output current IOUT may also be different.

[0063] In this embodiment, the control signal generator 110 can generate the switching control signal SIG SW , and if Figure 2 As shown, the switching control signal SIG SW Each cycle of may include a conduction time TON and a non-conduction time TOFF with different potentials. In this embodiment, the switching control signal SIG SW During the on-time TON, the inductor is at a logic high level. At this time, the switch SW1 is turned on, the switch SW2 is turned off, and the input voltage VIN charges the inductor L1 through the switch SW1. At this time, the inductor current I L In contrast, during the non-conduction time TOFF, the switching control signal SIG SW will be in a logic low level, at which time the switch SW1 will be turned off and the switch SW2 will be turned on. In this case, the inductor L1 can form a discharge current loop through the load LD and the switch SW2, so the inductor current I L In addition, when the inductor current I L When the inductor current I L When it is less than the output current IOUT drawn by the load LD, the output voltage VOUT will drop.

[0064] In this embodiment, when the control signal generator 110 detects that the output voltage VOUT is low, the switching control signal SIG SW The switch SW1 is turned on again from a logic low potential to a logic high potential and maintained for a fixed length of on-time TON, thereby maintaining the output voltage VOUT within a range close to the target voltage.

[0065] exist Figure 2 In the period P1, the voltage conversion circuit 10 is in a steady state, so the switching control signal SIG SWThe conduction time TON of each cycle is the same, and the non-conduction time TOFF of each cycle is also similar. However, in period P2, since the load LD of the voltage conversion circuit 10 suddenly draws a large current, that is, the output current IOUT rises, resulting in an excessively low output voltage VOUT. At this time, the control signal generator 110 will correspondingly shorten the non-conduction time TOFF while keeping the conduction time TON unchanged, so as to increase the frequency of charging the inductor L1, thereby increasing the voltage value of the output voltage VOUT. In this case, due to the switching control signal SIG SW The non-conduction time TOFF in each cycle becomes shorter, so the switching control signal SIG SW The frequency will also increase.

[0066] In this embodiment, in order to avoid the switching control signal SIG SW If the switching frequency controller 120 continues to deviate from the originally set target frequency, the switching control signal SIG SW The switching control signal SIG is adjusted by adjusting the parameters of the control signal generator 110. SW The on-time length of the switch control signal SIG SW The frequency is controlled within the preset range.

[0067] Figure 3 1 is a schematic diagram of a switching frequency controller 120 according to an embodiment of the present application. The switching frequency controller 120 may include a frequency divider 122, a frequency detector 124, an accumulation counter 126, and an on-time controller 128. Figure 3 As shown, the frequency detector 124 may be coupled to the frequency divider 122 , the accumulation counter 126 may be coupled to the frequency detector 124 , and the on-time controller 128 may be coupled to the frequency divider 122 , the accumulation counter 126 and the control signal generator 110 .

[0068] The frequency divider 122 may receive a signal having a target frequency f TG Target signal SIG TG , and can be based on the target signal SIG TG Generates a frequency with a divided frequency f DV Frequency division signal SIG DV In this embodiment, the target frequency f TG It can be the crossover frequency f DV of 2 N times, where N is a positive integer. The frequency detector 124 can receive the frequency division signal SIG DV And the switching control signal SIG SW In this embodiment, the frequency detector 124 can detect the frequency division signal SIG DV In each cycle, the switching control signal SIG is calculatedSW The number of cycles experienced. Figure 4 is the target signal SIG TG , frequency division signal SIG DV And the switching control signal SIG SW Schematic diagram of the wave pattern.

[0069] In this case, if the switching control signal SIG SW The frequency f SW Greater than the target frequency f TG , then the number of cycles calculated by the frequency detector 124 will be greater than 2 N In contrast, if the switching control signal SIG SW The frequency f SW Less than the target frequency f TG , then the number of cycles calculated by the frequency detector 124 should be less than 2 N In this embodiment, the frequency detector 124 may use (N+1) bits to represent the cycle number. In this way, the highest bit D of the cycle number is N+1 It can be used to determine the switching control signal SIG SW The frequency f SW With the target frequency f TG For example, when the highest bit D of the cycle number N+1 When it is 1, it means that the number of cycles calculated by the frequency detector 124 may be greater than 2 N , at this time, the switching control signal SIG SW The frequency f SW May be higher than the target frequency f TG . Relatively speaking, when the highest bit of the cycle number D N+1 When it is 0, it means that the number of cycles calculated by the frequency detector 124 should be less than 2 N , at this time, the switching control signal SIG SW The frequency f SW Below the target frequency f TG .

[0070] In this embodiment, the accumulation counter 126 may first set the internal index value VLI to an initial value, and then may calculate the value according to the highest bit D of the cycle number. N+1 Increase or decrease the internal index value VLI so that the difference between the index value VLI and its initial value can reflect the control signal SIG SW The frequency f SW With the target frequency f TG In this case, the on-time controller 128 can adjust the parameters of the control signal generator 110 according to the index value VLI, thereby adjusting the switching control signal SIG SWThe length of the conduction time TON and the switching control signal SIG SW The frequency f SW Can approach the target frequency f TG .

[0071] For example, the accumulation counter 126 may store the index value VLI in (N+1) individual bits VLI. N+1 To VLI1, and its initial value can be set to 2 N+1 , that is, the highest bit VLI of the index value VLI N+1 1, other bits VLI N to VLI1 are all 0. Then, the accumulation counter 126 can use the highest bit D of the cycle number to N+1 When the highest bit D of the cycle number is 1, the index value VLI is increased by a predetermined number, such as but not limited to 1. N+1 When the index value VLI is 0, the index value VLI is reduced by a predetermined number, such as but not limited to 1. In this case, when the index value VLI is greater than the starting value 2 N+1 When , it indicates the switching control signal SIG SW The frequency f SW May be greater than the target frequency f TG , at this time, the on-time controller 128 can extend the switching control signal SIG SW The conduction time length of the switching control signal SIG is reduced. SW The frequency f SW Conversely, when the indicator value VLI is less than the starting value 2 N+1 When , it indicates the switching control signal SIG SW The frequency f SW May be less than the target frequency f TG , at this time, the on-time controller 128 can shorten the switching control signal SIG SW The conduction time length of the switching control signal SIG SW The frequency f SW .

[0072] In addition, in order to avoid adjusting the switching control signal SIG too frequently SW The frequency f SW In some embodiments, when the indicator value VLI is within a predetermined range, for example, the difference between the indicator value VLI and the initial value is less than a specific value, for example, the difference between the indicator value VLI and the initial value is 2 N+1 When the difference between the values ​​of is less than 2 or 3, the on-time controller 128 may switch the control signal SIG SW The length of the conduction time remains unchanged, but the present application is not limited thereto.

[0073] In this embodiment, the accumulation counter 126 can also receive the frequency division signal SIG DV , and the frequency division signal SIG DV That is, the accumulation counter 126 operates with the divided signal SIG DV The frequency f DV To update the indicator value VLI, the on-time controller 128 is N target signal SIG TG The switching control signal SIG is adjusted accordingly. SW In this way, it is also possible to avoid adjusting the switching control signal SIG too frequently. SW The length of the conduction time affects the stability of the system.

[0074] In addition, when the indicator value VLI is greater than its initial value 2 N+1 , and the difference between the two gradually increases, indicating that the switching control signal SIG is adjusted SW After the conduction time length is several times, the switching control signal SIG SW The frequency f SW Still greater than the target frequency f TG At this time, in order to make the switching control signal SIG SW The frequency f SW Can approach the target frequency f more quickly TG , the on-time controller 128 can increase the adjustment of the switching control signal SIG SW That is, in some embodiments, the on-time controller 128 can adjust the on-time length of the indicator value VLI and the starting value 2 N+1 The larger the difference is, the greater the switching control signal SIG is adjusted. SW The length of the conduction time.

[0075] In this embodiment, the on-time controller 128 can adjust the switching control signal SIG by adjusting the parameters related to the on-time length in the control signal generator 110. SW For example, in some embodiments, the control signal generator 110 may use a sawtooth voltage and a reference voltage to generate a desired length of on-time, and may thereby generate the switching control signal SIG. SW In this case, the on-time controller 128 can adjust the switching control signal SIG by adjusting the parameters related to the sawtooth wave voltage or adjusting the reference voltage. SW The length of the conduction time.

[0076] Figure 5FIG. 1 is a schematic diagram of a circuit related to the on-time length in the on-time controller 128 and the control signal generator 110 according to an embodiment of the present application. Figure 5 As shown, the control signal generator 110 may include a comparator 112 and a ramp generator 114. The ramp generator 114 may generate a sawtooth wave voltage V RAMP , when the sawtooth voltage V RAMP When the sawtooth voltage V RAMP Reaching the reference voltage V REF , the on-time controller 128 ends the calculation of the on-time. At this time, the control signal generator 110 also turns on a discharge path to make the sawtooth voltage V RAMP Return to low voltage. That is, the sawtooth voltage V RAMP From the ground voltage VSS to the reference voltage V REF The duration of the switching control signal SIG SW It should be noted that in order to output the complete switching control signal SIG SW The control signal generator 110 may also include other elements (such as the aforementioned elements for providing a discharge path), but in order to keep the drawings and the description concise, they are not described in detail here. In some embodiments, the control signal generator 110 can be implemented according to any existing control signal generator of a voltage conversion circuit.

[0077] like Figure 5 As shown, the ramp generator 114 can utilize the input voltage VIN to pass through the resistor R TON For capacitor C TON Charge to form a sawtooth voltage V RAMP Therefore, in some embodiments, the on-time controller 128 can adjust the resistor R TON or capacitor C TON The size of the switching control signal SIG is adjusted SW However, in this embodiment, the on-time controller 128 is configured to adjust the on-time of the capacitor C TON The charging current is used to adjust the switching control signal SIG SW The length of the conduction time.

[0078] exist Figure 5 In the embodiment, the on-time controller 128 may include N adjusting current sinks DCS1 to DCSN and N adjusting current sources CCS1 to CCSN. ​​In the present embodiment, the adjusting current sinks DCS1 to DCSN may be coupled to the ground terminal GND, and may extract a portion of the current that would otherwise flow into the capacitor C TON The current of the ramp generator 114 causes the capacitor C TONThe charging current decreases. In this case, the sawtooth voltage V RAMP Rising to the reference voltage V REF The speed of the on-state will be slowed down, so the on-time will be extended. In contrast, the regulating current sources CCS1 to CCSN can be coupled to the power supply voltage VDD and can adjust the capacitor C TON The output current causes the ramp generator 114 to output the capacitor C TON The charging current increases. In this case, the sawtooth voltage V RAMP will rise faster to the reference voltage V REF , so the on-time length will be shortened.

[0079] In this embodiment, since the highest bit VLI of the indicator value VLI N+1 The value of can be used to reflect the current switching control signal SIG SW The frequency f sw With the target frequency f TG Therefore, the on-time controller 128 can be based on the highest bit VLI of the indicator value VLI. N+1 It is determined whether to enable the adjustment of the current sink DCS1 to DCSN or the adjustment of the current source CCS1 to CCSN. ​​For example, when the highest bit VLI N+1 When it is 1, it indicates the switching control signal SIG SW The frequency f sw Higher than the target frequency f TG , then the current sink switch DSW0 can be turned on to enable at least one of the current sinks DCS1 to DCSN to adjust the switching control signal SIG. SW The on-time length and the switching control signal SIG are reduced SW The frequency f sw On the contrary, when the highest bit VLI N+1 When it is 0, it indicates the switching control signal SIG SW The frequency f sw Below the target frequency f TG , then the current source switch CSW0 can be turned on to enable at least one of the adjustment current sources CCS1 to CCSN, thereby shortening the switching control signal SIG SW The on-time length and the switching control signal SIG SW The frequency f sw .

[0080] In addition, in the present embodiment, the regulating current slots DCS1 to DCSN can be used to extract currents of different magnitudes, respectively. For example, the current flowing into the regulating current slot DCSn can be twice the current flowing into the regulating current slot DCS(n-1), where n is any integer from 2 to N, for example, the current flowing into the regulating current slot DCS2 can be twice the current flowing into the regulating current slot DCS1, and the current flowing into the regulating current slot DCS3 can be twice the current flowing into the regulating current slot DCS2, and so on.

[0081] In this case, the on-time controller 128 may also be configured to calculate the value of the indicator VLI according to other bits VLI N To VLI1 to enable the corresponding regulating current sinks in DCS1 to DCSN. Figure 5 As shown, the on-time controller 128 may further include current sink switches DSW1 to DSWN, each of which may be used to control the electrical connection between a corresponding adjustment current sink among the adjustment current sinks DCS1 to DCSN and the ramp generator 114. For example, the adjustment current sink DCS1 may be coupled to the ramp generator 114 via the current sink switch DSW1, and the adjustment current sink DCS2 may be coupled to the ramp generator 114 via the current sink switch DSW2, and so on.

[0082] In this embodiment, the on-time controller 128 may further include N AND gates DA1 to DAN, each of which may receive the highest bit of the indicator value VLI and another corresponding bit to generate a control signal of a corresponding current sink switch among the current sink switches DSW1 to DSWN. For example, the AND gate DA1 may receive the highest bit VLI of the indicator value VLI. N+1 and the lowest bit VLI1, and the highest bit VLI of the indicator value VLI N+1 The AND gate DA2 performs a logic AND operation with the lowest bit VLI1 to generate a control signal of the current sink switch DSW1. Similarly, the AND gate DA2 can receive the highest bit VLI of the indicator value VLI. N+1 and the second bit VLI2, and the highest bit VLI of the index value VLI N+1 The second bit VLI2 performs a logical AND operation to generate a control signal of the current sink switch DSW2. That is, the current sink switch DSW1 will generate a control signal of the current sink switch DSW2 when the highest bit VLI of the indicator value VLI is used. N+1 The current sink switch DWS2 is turned on when the highest bit VLI of the indicator value VLI and the lowest bit VLI1 are both 1. N+1 The on-time controller 128 can conduct when the highest bit VLI of the indicator value VLI and the second bit VLI2 are both 1. N+1When it is 1, the other bits VLI according to the index value VLI N to VLI1 to enable the adjustment of current sinks DCS1 to DCSN, so that the indicator value VLI is equal to the initial value 2 N+1 When the difference is larger, the charging current of the ramp generator 114 is reduced to a greater extent, thereby increasing the switching control signal SIG to a greater extent. SW The length of the conduction time.

[0083] In addition, in this embodiment, when the index value VLI is (2 N+1 ) or (2 N+1 -1), the on-time controller 128 may not enable any current source or current sink to avoid unnecessary adjustment of the switching control signal SIG. SW In this case, the adjustment current sources CCS1 to CCSN can also be operated according to the same principle as the operation of the adjustment current sinks DCS1 to DCSN. For example, the current output by the adjustment current source CCSn can be twice the current output by the adjustment current source CCS(n-1). In this case, the on-time controller 128 can also adjust the on-time of the indicator value VLI according to other bits VLI N to VLI1 to enable the corresponding regulating current source among the regulating current sources CCS1 to CCSN.

[0084] For example, the on-time controller 128 may further include current source switches CSW1 to CSWN and AND gates CA1 to CAN, and each of the AND gates CA1 to CAN may be configured according to the highest bit VLI of the indicator value VLI. N+1 and another corresponding bit of the indicator value VLI to generate a control signal of a corresponding current source switch among the current source switches CSW1 to CSWN. In this embodiment, the on-time controller 128 only generates a control signal of a corresponding current source switch in the indicator value VLI at the highest bit VLI. N+1 When it is 0, the other bits of the indicator value VLI will be used. N To enable the adjustment current sources CCS1 to CCSN by changing the value of the indicator VLI1. Furthermore, as mentioned above, in this embodiment, when the indicator value VLI is (2 N+1 -1), (that is, except for the highest bit VLI N+1 In addition, other bits VLI N to VLI1 are all 1), the on-time controller 128 will not enable any of the regulating current sources CCS1 to CCSN, but will switch to the on-time controller 128 when the indicated value VLI is less than the initial value 2 N+1 After the difference between the current sources CCS1 and CCSN is greater than 1, the current sources CCS1 to CCSN are enabled. Figure 5In the embodiment, each of the AND gates CA1 to CAN can receive the inverted value of the highest bit of the indicator value VLI (generated by an inverter) and the inverted value of another corresponding bit (generated by an inverter) to generate a control signal of a corresponding current source switch among the current source switches CSW1 to CSWN. For example, the AND gate CA1 can receive the highest bit VLI of the indicator value VLI. N+1 The inverted value of the lowest bit VLI1 and the inverted value of the lowest bit VLI1, so the current source switch CSW1 will be at the highest bit VLI of the index value VLI. N+1 and the lowest bit VLI1 are both 0, so that the current source CCS1 can adjust the capacitor C TON Output charging current. Similarly, AND gate CA2 can receive the highest bit VLI of the indicator value VLI N+1 The inverted value of the second bit VLI2 and the inverted value of the second bit VLI2, so the current source switch CSW2 will be in the highest bit VLI of the indicator value VLI N+1 and the second bit VLI2 are both 0, so that the adjustment current source CCS2 can adjust the capacitor C TON Output charging current.

[0085] In this embodiment, the on-time controller 128 adjusts the switching control signal SIG by adjusting the current value related to the on-time length in the control signal generator 110. SW However, the present application is not limited thereto. In other embodiments of the present application, the on-time controller 128 may also adjust other parameters, such as but not limited to the reference voltage value V REF , resistor R TON The value of capacitance C TON The value of the switching control signal SIG is adjusted SW In addition, the on-time controller 128 can also adjust the switching control signal SIG by adjusting multiple parameters of the above parameters at the same time. SW The length of the conduction time.

[0086] Since the voltage conversion circuit 10 of the present application can utilize the switching frequency controller 120 therein to monitor the switching control signal SIG SW The frequency of the switching control signal SIG is adjusted accordingly. SW The on-time length can effectively switch the control signal SIG SW Controlled close to the target frequency f TG range, thereby reducing the electromagnetic interference problem and circuit performance degradation that may be caused by the previous technology.

[0087] Figure 6 FIG. 1 is a flow chart of a method M1 for controlling the switching frequency of a switch according to an embodiment of the present application. Figure 6 As shown, the method M1 may include steps S110 to S160. In some embodiments, the method M1 may be applied to the voltage conversion circuit 10. For example, the control signal generator 110 may execute step S110 to generate the switching control signal SIG SW , and the frequency divider 122 may execute step S120 to adjust the frequency according to the target signal SIG TG Generate frequency division signal SIG DV Next, in step S130, the frequency detector 124 may calculate the frequency division signal SIG DV In each cycle, the switching control signal SIG SW The cumulative counter 126 may set the internal index value VLI as the starting value in step S140, and in step S150, the highest bit D of the number of cycles calculated by the frequency detector 124 is used to calculate the number of cycles. N+1 , and correspondingly increase or decrease the internal index value VLI by a predetermined number. In this way, the on-time controller 128 can adjust the switching control signal SIG according to the index value VLI in step S160. SW The conduction time length of the switch is increased or decreased by SW frequency.

[0088] In summary, the switching frequency controller, voltage conversion circuit and method for controlling the switching frequency of a switch provided in the embodiments of the present application can divide the target frequency and then compare it with the switching control frequency to monitor the frequency of the switching control signal, and can adjust the on-time length of the switching control signal accordingly, thereby effectively controlling the switching control signal within a range close to the target frequency, thereby reducing the electromagnetic interference problem and the problem of decreased circuit performance that may be caused by the prior art.

[0089] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions or modifications may be made herein without departing from the technology of the present disclosure as defined by the appended claims. For example, many of the procedures discussed above may be implemented with different methodologies, and may be replaced by other procedures, or a combination thereof.

[0090] Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the procedures, machines, articles, compositions, devices, methods, and steps described in this specification. As will be readily appreciated by those skilled in the art from this disclosure, procedures, machines, articles, compositions, devices, methods, or steps currently existing or later developed that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present invention. Therefore, the appended claims are intended to include within their scope such processes, machines, manufactures, compositions of matter, means, methods, and steps.

Claims

1. A switching frequency controller, comprising: The frequency divider is used to generate a frequency-divided signal having a frequency-divided frequency according to a target signal having a target frequency, wherein the target frequency is twice the frequency-divided frequency. N times, N is a positive integer; a frequency detector coupled to the frequency divider, for receiving the frequency division signal and the switching control signal generated by the control signal generator, and calculating the number of cycles experienced by the switching control signal in each cycle of the frequency division signal, wherein each cycle of the switching control signal includes a conduction time and a non-conduction time with different potentials, and the number of cycles is represented by (N+1) bits; an accumulation counter, coupled to the frequency detector, for setting the indicator value to a starting value at an initial stage, and increasing or decreasing the indicator value by a predetermined number according to the highest bit of the cycle number; and The on-time controller is coupled to the accumulation counter and is used to adjust the parameters of the control signal generator according to the indicator value to adjust the on-time length of the switching control signal.

2. The switching frequency controller according to claim 1, characterized in that: The on-time controller adjusts at least one of the charging current value, the reference voltage value, the resistance value and the capacitance value of the control signal generator according to the indicator value to adjust the on-time length of the switching control signal.

3. The switching frequency controller according to claim 1 or 2, characterized in that: When the most significant bit of the cycle number is 1, the cumulative counter increases the index value by the predetermined number, and when the most significant bit of the cycle number is 0, the cumulative counter decreases the index value by the predetermined number.

4. The switching frequency controller according to claim 3, characterized in that: When the indicator value is greater than the starting value, the on-time controller extends the on-time length of the switching control signal; and When the indicator value is less than the starting value, the on-time controller shortens the on-time length of the switching control signal.

5. The switching frequency controller according to claim 3, characterized in that: When the difference between the indicator value and the starting value is larger, the on-time controller adjusts the on-time of the switching control signal to a larger extent.

6. The switching frequency controller according to claim 3, characterized in that: The index value contains (N+1) bits, and the starting value is 2 N .

7. The switching frequency controller according to claim 3, characterized in that: When the indicator value is within a predetermined range, the on-time controller maintains the on-time length of the switching control signal unchanged.

8. The switching frequency controller according to claim 3, characterized in that: The on-time controller comprises: N adjustment current sources, wherein the nth adjustment current source is used to output a current to the capacitor of the control signal generator according to the (N+1)th bit and the nth bit of the indicator value to increase a charging current to the capacitor, wherein n is any integer from 1 to N; and N adjusting current slots, wherein the nth adjusting current slot is used to draw current from the capacitor of the control signal generator according to the (N+1)th bit and the nth bit of the indicator value to reduce the charging current of the capacitor.

9. The switching frequency controller according to claim 8, characterized in that: The current output by the nth adjustment current source is twice the current output by the (n-1)th adjustment current source, the current flowing into the nth adjustment current sink is twice the current flowing into the (n-1)th adjustment current sink, and n is any integer from 2 to N.

10. The switching frequency controller according to claim 1, characterized in that: The accumulation counter is further used for receiving the frequency-divided signal, and the accumulation counter operates with the frequency-divided signal as a clock signal.

11. A voltage conversion circuit, comprising: A switching frequency controller as claimed in any one of claims 1 to 10; and The control signal generator.

12. The switching frequency controller according to claim 11, characterized in that: Also includes: The first switch has a first end for receiving an input voltage; a second end; and a control end for receiving the switching control signal; A second switch having a first end coupled to the second end of the first switch; The second terminal is coupled to the ground terminal; and the control terminal is used to receive an inverted control signal which is inverted to the switching control signal; an inductor having a first end coupled to the second end of the first switch; and a second terminal for outputting a converted output voltage; and A capacitor having a first end coupled to the second end of the inductor; and a second end coupled to the ground end.

13. A method for controlling a switching frequency of a switch, comprising: Using a control signal generator to generate a switching control signal to control the switch, wherein each cycle of the switching control signal includes a conduction time and a non-conduction time with different potentials; Generate a frequency-divided signal having a frequency-divided frequency according to a target signal having a target frequency, wherein the target frequency is twice the frequency-divided frequency. N times, N is a positive integer; In each cycle of the frequency-divided signal, the number of cycles experienced by the switching control signal is calculated, wherein the number of cycles is represented by (N+1) bits; At the initial stage, the indicator value is set to the starting value; Increasing or decreasing the indicator value by a predetermined amount according to the highest bit of the cycle number; and The parameters of the control signal generator are adjusted according to the indicator value to adjust the on-time length of the switching control signal.

14. The method according to claim 13, characterized in that The step of adjusting the parameters of the control signal generator according to the indicator value to adjust the conduction time length of the switching control signal is to adjust the conduction time length of the switching control signal by adjusting at least one of the charging current value, reference voltage value, resistance value and capacitance value of the control signal generator.

15. The method according to claim 13 or 14, characterized in that The step of increasing or decreasing the indicator value by a predetermined number according to the highest bit of the cycle number comprises: When the highest bit of the cycle number is 1, the index value is increased by a predetermined number; When the highest bit of the cycle number is 0, the index value is subtracted from the predetermined number.

16. The method according to claim 15, characterized in that The step of adjusting the on-time length of the switching control signal according to the indicator value comprises: When the indicator value is greater than the starting value, extending the on-time length of the switching control signal; and When the indicator value is smaller than the initial value, the on-time length of the switching control signal is shortened.

17. The method according to claim 16, characterized in that The step of adjusting the on-time length of the switching control signal according to the indicator value further includes: When the difference between the indicator value and the initial value is larger, the on-time length of the switching control signal is adjusted to a greater extent.

18. The method according to claim 15, characterized in that The index value contains (N+1) bits, and the starting value is 2 N .

19. The method of claim 13, wherein: The step of adjusting the on-time length of the switching control signal according to the indicator value further includes: When the indicator value is within a predetermined range, the on-time length of the switching control signal is maintained unchanged.

20. The method of claim 13, wherein: The step of increasing or decreasing the index value by the predetermined number according to the highest bit of the cycle number is performed once in each cycle of the frequency-divided signal.

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