Oscillator circuit and integrated circuit chip

Abstract

According to the oscillator circuit and the integrated circuit chip provided by the invention, by designing the zero-temperature current generation circuit, the first current with the temperature coefficient being zero can be provided for the interior of an oscillator, so that the working current of the circuit is not influenced by the temperature fundamentally, and the reference voltage which is not influenced by the temperature can be generated through the zero-temperature voltage generation circuit; the charge pump circuit can be used for generating a second voltage with a preset waveform, so that the second voltage is compared with the first voltage which is not influenced by the temperature, a comparison signal is generated at the comparator circuit, and further, the digital logic circuit performs logic operation processing on the comparison signal to generate an expected clock signal; therefore, the output of the clock signal which is not influenced by temperature is realized, and the temperature characteristic and the frequency stability of the clock signal are improved.

Description

Technical Field

[0001] The present application relates to but is not limited to an oscillator circuit and an integrated circuit chip. Background Art

[0002] An oscillator is a device that can spontaneously emit a periodic oscillation signal after being powered on. Such devices do not require input signals, only power supply. The periodic oscillation signal generated by the oscillator circuit is usually used as the internal clock signal of the chip to provide a periodic digital input signal to analog circuits such as ADC and digital circuits.

[0003] In some embodiments, an oscillator circuit can be designed by using a resistor to generate a current and a reference voltage, and the resistor generates the operating current required for the oscillator circuit to work, and the reference voltage at the input end of the comparator inside the oscillator circuit. However, the frequency-temperature characteristics of the output signal of this type of circuit are extremely poor. The temperature coefficient of the resistor is large, and the resistance value of the resistor changes greatly with the change of temperature. The temperature coefficient of the corresponding current and the reference voltage is also large, so the temperature coefficient of the frequency of the output signal generated by the oscillator is large.

[0004] In addition, in some embodiments, an oscillator circuit can be designed using an integrator and a voltage-controlled oscillator structure, and the triangular wave signal required by the circuit is generated by the integrator, and the triangular wave signal output by the integrator controls the frequency of the voltage-controlled oscillator circuit. However, the frequency-temperature characteristics and voltage characteristics of the output signal are poor, the circuit structure is complex, and the layout area is large. The frequency of the output signal changes dramatically with changes in temperature and voltage, the frequency stability is poor, and the chip area occupied is large.

[0005] In summary, the current oscillator circuit has the problem that the circuit frequency and the duty cycle of the output signal vary greatly with the working parameters such as temperature, and the output signal is unstable. Therefore, an oscillator circuit is needed to solve the problem that the output signal is greatly affected by temperature. Summary of the invention

[0006] The present application provides an oscillator circuit and an integrated circuit chip, which are used to solve the problem that the circuit frequency and the output signal duty cycle in the current oscillator circuit vary greatly with operating parameters such as temperature, and the output signal is unstable.

[0007] In a first aspect, the present application provides an oscillator circuit, the circuit comprising:

[0008] A zero-temperature current generating circuit, used for generating a first current with a zero temperature coefficient;

[0009] A zero-temperature voltage generating circuit, used for generating a first voltage with a temperature coefficient of zero;

[0010] A charge pump circuit, used for generating a second voltage of a preset waveform according to the first current;

[0011] a comparator circuit, configured to generate a comparison signal according to the first voltage and the second voltage;

[0012] The digital logic circuit is used to generate a clock signal according to the comparison signal.

[0013] As an optional implementation, the circuit further includes:

[0014] A positive temperature current generating circuit, used to generate a second current positively correlated with the temperature;

[0015] A negative temperature current generating circuit, used for generating a third current negatively correlated with temperature;

[0016] Furthermore, the zero-temperature current generating circuit is used to generate a first current with a zero temperature coefficient according to the second current and the third current.

[0017] As an optional implementation manner, the connection relationship of the circuit includes:

[0018] The output ends of the positive temperature current generating circuit and the negative temperature current generating circuit are connected to the input end of the zero temperature current generating circuit, the output end of the positive temperature current generating circuit is connected to the input end of the zero temperature voltage generating circuit, the output end of the zero temperature current generating circuit is connected to the first input end of the charge pump circuit, the output end of the zero temperature voltage generating circuit is connected to the first input end of the comparator circuit, the output end of the charge pump circuit is connected to the second input end of the comparator circuit, the output end of the comparator circuit is connected to the first end of the digital logic circuit, the second end of the digital logic circuit is connected to the second input end of the charge pump circuit, and the third end of the digital logic circuit serves as the output end of the oscillator circuit to output the clock signal.

[0019] As an optional implementation, the positive temperature current generating circuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first triode, a second triode, a third triode and a first resistor;

[0020] Wherein, the first ends of the first field effect tube and the second field effect tube are connected to the power supply voltage, the second end and the third end of the first field effect tube are connected, and are connected to the third end of the second field effect tube, the third end of the first field effect tube is connected to the first end of the third field effect tube, the second end and the third end of the third field effect tube are connected, and are connected to the third end of the fourth field effect tube, the second end of the second field effect tube is connected to the first end of the fourth field effect tube, the second end of the third field effect tube is connected to the first end of the first triode, and the second end of the fourth field effect tube is connected to the first end of the second triode and the third end of the third triode Three terminals, the third terminal of the first transistor is connected to the third terminal of the second transistor and the second terminal of the third transistor, the first terminal of the third transistor is connected to the power supply voltage, the second terminal of the first transistor is connected to the first terminal of the first resistor, the second terminal of the second transistor is connected to the second terminal of the first resistor, the second terminal of the first resistor is grounded, the connection point of the third terminal of the first field effect transistor and the third terminal of the second field effect transistor serves as the first output terminal of the positive temperature current generating circuit, and the connection point of the third terminal of the third field effect transistor and the third terminal of the fourth field effect transistor serves as the second output terminal of the positive temperature current generating circuit.

[0021] As an optional implementation, the negative temperature current generating circuit includes a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a fourth triode and a second resistor;

[0022] In addition, the first end of the fifth field effect tube is connected to the power supply voltage, the second end of the fifth field effect tube is connected to the first end of the sixth field effect tube, the second end of the sixth field effect tube is connected to the first end of the fourth transistor and the third end of the ninth field effect tube, the second end of the fourth transistor is grounded, the third end of the fourth transistor and the second end of the ninth field effect tube are connected to the first end of the second resistor, the second end of the second resistor is grounded, the third end of the fifth field effect tube is connected to the first output end of the positive temperature current generating circuit, the third end of the sixth field effect tube is connected to the second output end of the positive temperature current generating circuit, the first end of the seventh field effect tube is connected to the power supply voltage, and the second end and the third end of the seventh field effect tube are connected and connected to the first end of the eighth field effect tube, the second end and the third end of the eighth field effect tube are connected and connected to the first end of the ninth field effect tube.

[0023] As an optional implementation, the zero-temperature current generating circuit includes a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor and a fourteenth field effect transistor;

[0024] Among them, the first end of the tenth field effect tube is connected to the power supply voltage, the third end of the tenth field effect tube is connected to the second end and the third end of the seventh field effect tube, the second end of the tenth field effect tube is connected to the first end of the eleventh field effect tube, the third end of the eleventh field effect tube is connected to the second end and the third end of the eighth field effect tube, the second end of the eleventh field effect tube is connected to the first end of the twelfth field effect tube, the first end and the third end of the twelfth field effect tube are connected, the second end of the twelfth field effect tube is grounded, the first end of the thirteenth field effect tube is connected to the power supply voltage, the second end of the thirteenth field effect tube is connected to the first end of the fourteenth field effect tube, the third end of the thirteenth field effect tube is connected to the first output end of the positive temperature current generating circuit, and the third end of the fourteenth field effect tube is connected to the second output end of the positive temperature current generating circuit.

[0025] As an optional implementation, the zero-temperature voltage generating circuit includes a fifteenth field effect transistor, a sixteenth field effect transistor, a fifth triode and a third resistor;

[0026] Among them, the first end of the fifteenth field effect tube is connected to the power supply voltage, the second end of the fifteenth field effect tube is connected to the first end of the sixteenth field effect tube, the second end of the sixteenth field effect tube is connected to the first end of the third resistor, and the connection point between the second end of the sixteenth field effect tube and the first end of the third resistor serves as the output end of the zero-temperature voltage generating circuit, the second end of the third resistor is connected to the first end of the fifth triode, the second end and the third end of the fifth triode are connected and grounded, the third end of the fifteenth field effect tube is connected to the third end of the thirteenth field effect tube, and the third end of the sixteenth field effect tube is connected to the third end of the fourteenth field effect tube.

[0027] As an optional implementation manner, the charge pump circuit includes a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a twenty-first field effect transistor, a twenty-second field effect transistor and a first capacitor;

[0028] Among them, the first ends of the seventeenth field effect transistor and the eighteenth field effect transistor are connected to the power supply voltage, the second end and the third end of the seventeenth field effect transistor are connected, and are connected to the third end of the eighteenth field effect transistor, the second end of the seventeenth field effect transistor is connected to the first end of the nineteenth field effect transistor, the third end of the nineteenth field effect transistor is connected to the third end of the twelfth field effect transistor, the second end of the eighteenth field effect transistor is connected to the first end of the twentieth field effect transistor, the third end of the twentieth field effect transistor is connected to the third end of the twenty-first field effect transistor, and is connected to the second end of the digital logic circuit, the second end of the 20th field effect transistor is connected to the first end of the first capacitor and the first end of the twenty-first field effect transistor, and serves as the output end of the charge pump circuit, the second end of the first capacitor is grounded, the second end of the twenty-first field effect transistor is connected to the first end of the twenty-second field effect transistor, the third end of the twenty-second field effect transistor is connected to the third end of the nineteenth field effect transistor, and the second end of the twenty-second field effect transistor is grounded.

[0029] As an optional implementation manner, the comparator circuit uses the first voltage as a reference voltage and uses the second voltage as a comparison voltage;

[0030] The comparator circuit outputs a high-level comparison signal when the first voltage is greater than the second voltage, and outputs a low-level comparison signal when the first voltage is less than the second voltage.

[0031] As an optional implementation, the digital logic circuit includes a first inverter, a second inverter and a D flip-flop;

[0032] The input end of the first inverter is connected to the output end of the comparator circuit, the output end of the first inverter is connected to the charge pump circuit, the input end of the second inverter is connected to the output end of the first inverter, the output end of the second inverter is connected to the first end of the D flip-flop, the second end and the third end of the D flip-flop are connected, and the fourth end of the D flip-flop is used to output a clock signal with a duty cycle of a preset value.

[0033] In a second aspect, the present application provides an integrated circuit chip, wherein the chip comprises the oscillator circuit as described in the first aspect.

[0034] The oscillator circuit and integrated circuit chip provided by the present application can provide a first current with a temperature coefficient of zero inside the oscillator by designing a zero-temperature current generating circuit, thereby fundamentally making the working current of the circuit unaffected by temperature. A reference voltage unaffected by temperature can be generated by a zero-temperature voltage generating circuit. The charge pump circuit can be used to generate a second voltage of a preset waveform, which is compared with the first voltage unaffected by temperature, and a comparison signal is generated at the comparator circuit. Furthermore, the digital logic circuit generates an expected clock signal after performing logical operation on the comparison signal, thereby realizing the output of a clock signal unaffected by temperature and improving the temperature characteristics and frequency stability of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] Figure 1 is a structural schematic diagram of an oscillator circuit disclosed in an embodiment of the present invention;

[0037] Figure 2 is a structural schematic diagram of another oscillator circuit disclosed in an embodiment of the present invention;

[0038] Figure 3 is a structural schematic diagram of another oscillator circuit disclosed in an embodiment of the present invention;

[0039] Figure 4 It is a schematic diagram of the structure of an integrated circuit chip disclosed in an embodiment of the present invention.

[0040] Reference numerals:

[0041] 101-zero temperature current generating circuit; 102-zero temperature voltage generating circuit; 103-charge pump circuit; 104-comparator circuit; 105-digital logic circuit; 106-positive temperature current generating circuit; 107-negative temperature current generating circuit;

[0042] R1-first resistor; R2-second resistor; R3-third resistor; B1-first triode; B2-second triode; B3-third triode; B4-fourth triode; B5-fifth triode; M1-first transistor; M2-second transistor; M3-third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; M7-seventh transistor; M8-eighth transistor; M9-ninth transistor; M10-tenth transistor; M11-eleventh transistor; M12-twelfth transistor; M 13-the thirteenth transistor; M14-the fourteenth transistor; M15-the fifteenth transistor; M16-the sixteenth transistor; M17-the seventeenth transistor; M18-the eighteenth transistor; M19-the nineteenth transistor; M20-the twentieth transistor; M21-the twenty-first transistor; M22-the twenty-second transistor; C1-the first capacitor; C2-the second capacitor; C3-the third capacitor; C4-the fourth capacitor; Vref-reference voltage / first voltage; Vm-second voltage; Vfb-feedback voltage; CLK-clock signal.

[0043] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0044] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0045] In this application, the following terms and their abbreviations shall be understood equivalently in the same application scenarios:

[0046] PTAT, Proportional To Absolute Temperature, is proportional to absolute temperature. This voltage or current increases linearly with increasing temperature.

[0047] CTAT, Complementary To Absolute Temperature, is inversely proportional to absolute temperature. This voltage or current decreases linearly with increasing temperature.

[0048] ZTAT, Zero Temperature Coefficient, zero temperature coefficient. This voltage or current is not sensitive to temperature changes.

[0049] OSC, Oscillator, oscillator, a circuit that generates a periodic waveform.

[0050] An oscillator is a device that can spontaneously emit a periodic oscillation signal after being powered on. Such devices do not require input signals, only power supply. The periodic oscillation signal generated by the oscillator circuit is usually used as the internal clock signal of the chip to provide a periodic digital input signal to analog circuits such as ADC and digital circuits.

[0051] In some embodiments, an oscillator circuit can be designed by using a resistor to generate a current and a reference voltage, and the resistor generates the operating current required for the oscillator circuit to work, and the reference voltage at the input end of the comparator inside the oscillator circuit. However, the frequency-temperature characteristics of the output signal of this type of circuit are extremely poor. The temperature coefficient of the resistor is large, and the resistance value of the resistor changes greatly with the change of temperature. The temperature coefficient of the corresponding current and the reference voltage is also large, so the temperature coefficient of the frequency of the output signal generated by the oscillator is large.

[0052] In addition, in some embodiments, an oscillator circuit can be designed using an integrator and a voltage-controlled oscillator structure, and the triangular wave signal required by the circuit is generated by the integrator, and the triangular wave signal output by the integrator controls the frequency of the voltage-controlled oscillator circuit. However, the frequency-temperature characteristics and voltage characteristics of the output signal are poor, the circuit structure is complex, and the layout area is large. The frequency of the output signal changes dramatically with changes in temperature and voltage, the frequency stability is poor, and the chip area occupied is large.

[0053] In summary, the current oscillator circuit has the problem that the circuit frequency and the duty cycle of the output signal vary greatly with the working parameters such as temperature, and the output signal is unstable. Therefore, an oscillator circuit is needed to solve the problem that the output signal is greatly affected by temperature.

[0054] The technical concept of the present application is that, by designing a zero-temperature current generating circuit, a first current with a temperature coefficient of zero can be provided inside the oscillator, so that the working current of the circuit is fundamentally unaffected by temperature. A reference voltage that is not affected by temperature can be generated through a zero-temperature voltage generating circuit. The charge pump circuit can be used to generate a second voltage of a preset waveform, which is compared with the first voltage that is not affected by temperature, and a comparison signal is generated at the comparator circuit. Furthermore, the digital logic circuit generates an expected clock signal after performing logical operations on the comparison signal, thereby realizing the output of a clock signal that is not affected by temperature and improving the temperature characteristics and frequency stability of the clock signal.

[0055] See also Figure 1 , Figure 1 It is a structural schematic diagram of an oscillator circuit disclosed in an embodiment of the present invention.

[0056] like Figure 1 As shown, the oscillator circuit includes:

[0057] A zero-temperature current generating circuit, used for generating a first current with a zero temperature coefficient;

[0058] A zero-temperature voltage generating circuit, used for generating a first voltage with a temperature coefficient of zero;

[0059] A charge pump circuit, used for generating a second voltage of a preset waveform according to the first current;

[0060] a comparator circuit, configured to generate a comparison signal according to the first voltage and the second voltage;

[0061] The digital logic circuit is used to generate a clock signal according to the comparison signal.

[0062] By designing a zero-temperature current generating circuit, a first current with a temperature coefficient of zero can be provided inside the oscillator, so that the working current of the circuit is fundamentally unaffected by temperature. A reference voltage that is not affected by temperature can be generated through a zero-temperature voltage generating circuit. The charge pump circuit can be used to generate a second voltage of a preset waveform, which is compared with the first voltage that is not affected by temperature, and a comparison signal is generated at the comparator circuit. Furthermore, the digital logic circuit performs logical operations on the comparison signal to generate an expected clock signal, thereby achieving the output of a clock signal that is not affected by temperature and improving the temperature characteristics and frequency stability of the clock signal.

[0063] See also Figure 2 , Figure 2 FIG. 1 is a schematic diagram of the structure of another oscillator circuit disclosed in an embodiment of the present invention. Figure 2 As shown, as an optional implementation, the circuit further includes:

[0064] A positive temperature current generating circuit, used to generate a second current positively correlated with the temperature;

[0065] A negative temperature current generating circuit, used for generating a third current negatively correlated with temperature;

[0066] Furthermore, the zero-temperature current generating circuit is used to generate a first current with a zero temperature coefficient according to the second current and the third current.

[0067] By designing a positive temperature current generating circuit and a negative temperature current generating circuit, the second current and the third current can be weightedly combined to generate a first current that is not affected by temperature. This can fundamentally make the working current of the subsequent processing circuit unaffected by temperature, and further can achieve the output of a clock signal that is not affected by temperature, thereby improving the temperature characteristics and frequency stability of the clock signal.

[0068] Based on this, the connection relationship of the circuit includes:

[0069] The output ends of the positive temperature current generating circuit and the negative temperature current generating circuit are connected to the input end of the zero temperature current generating circuit, the output end of the positive temperature current generating circuit is connected to the input end of the zero temperature voltage generating circuit, the output end of the zero temperature current generating circuit is connected to the first input end of the charge pump circuit, the output end of the zero temperature voltage generating circuit is connected to the first input end of the comparator circuit, the output end of the charge pump circuit is connected to the second input end of the comparator circuit, the output end of the comparator circuit is connected to the first end of the digital logic circuit, the second end of the digital logic circuit is connected to the second input end of the charge pump circuit, and the third end of the digital logic circuit serves as the output end of the oscillator circuit to output the clock signal.

[0070] In summary, as mentioned above, the specific uses of each functional module in the circuit are as follows:

[0071] The positive temperature current generating circuit generates a current which is positively correlated with the temperature.

[0072] The negative temperature current generating circuit generates a current which is negatively correlated with the temperature.

[0073] The zero temperature current generating circuit is connected with the positive temperature current generating circuit and the negative temperature current generating circuit, and the positive temperature coefficient current and the negative temperature coefficient current are superimposed in a certain proportion to generate a current with a zero temperature coefficient.

[0074] The zero-temperature voltage generating circuit is connected to the positive temperature current generating circuit. The transistor emitter voltage is a negative temperature voltage. This voltage is superimposed on the resistor voltage through which the positive temperature current flows. By adjusting the ratio, a zero-temperature reference voltage, i.e., the first voltage, is generated.

[0075] The charge pump circuit is connected to the zero-temperature current generating circuit, and includes a capacitor and two switching field effect transistors. The capacitor is charged / discharged according to the gate voltage, and a signal of a preset waveform, such as a triangular wave, is generated at a node corresponding to the second voltage.

[0076] The comparator circuit is connected to the charge pump circuit and the zero-temperature voltage generating circuit, compares the first voltage and the second voltage, and outputs a comparison signal.

[0077] The digital logic circuit is connected to the comparator circuit and the charge pump circuit. The comparison signal is converted into a feedback signal through the first inverter and then connected to the gate of the charge pump circuit. At the same time, the feedback signal is also input into the second inverter and the D flip-flop to output a 50% clock signal CLK.

[0078] See also Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the structure of another oscillator circuit disclosed in an embodiment of the present invention. Figure 3 As shown, the division of each circuit module is based on Figure 3 Specifically, the components and principles in each circuit module are as follows:

[0079] As an optional implementation, the positive temperature current generating circuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first triode, a second triode, a third triode and a first resistor;

[0080] Wherein, the first ends of the first field effect tube and the second field effect tube are connected to the power supply voltage, the second end and the third end of the first field effect tube are connected, and are connected to the third end of the second field effect tube, the third end of the first field effect tube is connected to the first end of the third field effect tube, the second end and the third end of the third field effect tube are connected, and are connected to the third end of the fourth field effect tube, the second end of the second field effect tube is connected to the first end of the fourth field effect tube, the second end of the third field effect tube is connected to the first end of the first triode, and the second end of the fourth field effect tube is connected to the first end of the second triode and the third end of the third triode Three terminals, the third terminal of the first transistor is connected to the third terminal of the second transistor and the second terminal of the third transistor, the first terminal of the third transistor is connected to the power supply voltage, the second terminal of the first transistor is connected to the first terminal of the first resistor, the second terminal of the second transistor is connected to the second terminal of the first resistor, the second terminal of the first resistor is grounded, the connection point of the third terminal of the first field effect transistor and the third terminal of the second field effect transistor serves as the first output terminal of the positive temperature current generating circuit, and the connection point of the third terminal of the third field effect transistor and the third terminal of the fourth field effect transistor serves as the second output terminal of the positive temperature current generating circuit.

[0081] After the circuit is turned on by the enable signal (ENP), each field effect tube and transistor in the circuit module is turned on. At this time, the gate voltage and VGS voltage of the first field effect tube and the second field effect tube are equal. When designing the circuit, the size of the first field effect tube and the second field effect tube can be designed to be completely equal to simplify the circuit design, so the current of the first field effect tube and the second field effect tube is equal. The base voltages of the first transistor and the second transistor are equal, so the current of the first resistor is equal to the voltage difference of the reflected junction voltage (Vbe) of the first transistor and the second transistor divided by the resistance value of the resistor, I_PTAT=(Vbe2-Vbe1) / R. Because Vbe2-Vbe1 is positively correlated with temperature, I_PTAT is a current that is positively correlated with temperature, that is, PTAT (positive temperature coefficient) current.

[0082] As an optional implementation, the negative temperature current generating circuit includes a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a fourth triode and a second resistor;

[0083] In addition, the first end of the fifth field effect tube is connected to the power supply voltage, the second end of the fifth field effect tube is connected to the first end of the sixth field effect tube, the second end of the sixth field effect tube is connected to the first end of the fourth transistor and the third end of the ninth field effect tube, the second end of the fourth transistor is grounded, the third end of the fourth transistor and the second end of the ninth field effect tube are connected to the first end of the second resistor, the second end of the second resistor is grounded, the third end of the fifth field effect tube is connected to the first output end of the positive temperature current generating circuit, the third end of the sixth field effect tube is connected to the second output end of the positive temperature current generating circuit, the first end of the seventh field effect tube is connected to the power supply voltage, and the second end and the third end of the seventh field effect tube are connected and connected to the first end of the eighth field effect tube, the second end and the third end of the eighth field effect tube are connected and connected to the first end of the ninth field effect tube.

[0084] In this embodiment, the current of the second resistor is equal to the base voltage (Vbe4) of the fourth transistor divided by the resistance value of the resistor, I_CTAT = Vbe0 / R2. Because Vbe4 is negatively correlated with temperature, I_CTAT is a current negatively correlated with temperature, specifically, it can be the current flowing through the seventh field effect transistor and the second resistor, which is a CTAT (negative temperature coefficient) current.

[0085] As an optional implementation, the zero-temperature current generating circuit includes a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor and a fourteenth field effect transistor;

[0086] Among them, the first end of the tenth field effect tube is connected to the power supply voltage, the third end of the tenth field effect tube is connected to the second end and the third end of the seventh field effect tube, the second end of the tenth field effect tube is connected to the first end of the eleventh field effect tube, the third end of the eleventh field effect tube is connected to the second end and the third end of the eighth field effect tube, the second end of the eleventh field effect tube is connected to the first end of the twelfth field effect tube, the first end and the third end of the twelfth field effect tube are connected, the second end of the twelfth field effect tube is grounded, the first end of the thirteenth field effect tube is connected to the power supply voltage, the second end of the thirteenth field effect tube is connected to the first end of the fourteenth field effect tube, the third end of the thirteenth field effect tube is connected to the first output end of the positive temperature current generating circuit, and the third end of the fourteenth field effect tube is connected to the second output end of the positive temperature current generating circuit.

[0087] In this embodiment, the thirteenth field effect tube and the first field effect tube form a current mirror, so the current of the thirteenth field effect tube is proportional to the current of the first field effect tube, and is also a PTAT (positive temperature coefficient) current. The tenth field effect tube and the seventh field effect tube form a current mirror, so the tenth field effect tube and the seventh field effect tube are proportional to each other, and are also a CTAT (negative temperature coefficient) current. Thereafter, the currents of the tenth field effect tube and the thirteenth field effect tube are superimposed and flow through the twelfth field effect tube together. Because the current of the thirteenth field effect tube is a positive temperature coefficient and the current of the tenth field effect tube is a negative temperature coefficient, under certain proportional relationship conditions, the temperature coefficient of the current of the twelfth field effect tube is almost 0, that is, the current of the twelfth field effect tube is a ZTAT (zero temperature coefficient) current.

[0088] As an optional implementation, the zero-temperature voltage generating circuit includes a fifteenth field effect transistor, a sixteenth field effect transistor, a fifth triode and a third resistor;

[0089] Among them, the first end of the fifteenth field effect tube is connected to the power supply voltage, the second end of the fifteenth field effect tube is connected to the first end of the sixteenth field effect tube, the second end of the sixteenth field effect tube is connected to the first end of the third resistor, and the connection point between the second end of the sixteenth field effect tube and the first end of the third resistor serves as the output end of the zero-temperature voltage generating circuit, the second end of the third resistor is connected to the first end of the fifth triode, the second end and the third end of the fifth triode are connected and grounded, the third end of the fifteenth field effect tube is connected to the third end of the thirteenth field effect tube, and the third end of the sixteenth field effect tube is connected to the third end of the fourteenth field effect tube.

[0090] This embodiment also completes the calculation of zero-temperature voltage through the design of current mirror. The fifteenth field effect tube and the first field effect tube constitute a current mirror, so the current I_M15 of the fifteenth field effect tube is proportional to the current of the first field effect tube, and is also a PTAT (positive temperature coefficient) current. The emitter voltage of the fifth transistor is Vbe5, and this voltage is negatively correlated with temperature, that is, Vbe5 is a CTAT (negative temperature coefficient) voltage. The current I_M15 of the fifteenth field effect tube flows through the third resistor, so the voltage across the third resistor is equal to I_M15*R3, and this voltage is a PTAT (positive temperature coefficient) voltage. Therefore, the voltage value of the reference voltage Vref is equal to the emitter voltage of the fifth transistor plus the voltage across the third resistor, that is, Vref=Vbe5+I_M15*R3. It can be seen that under certain conditions, the reference voltage Vref can be a ZTAT (zero temperature coefficient) voltage.

[0091] As an optional implementation manner, the charge pump circuit includes a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a twenty-first field effect transistor, a twenty-second field effect transistor and a first capacitor;

[0092] Among them, the first ends of the seventeenth field effect transistor and the eighteenth field effect transistor are connected to the power supply voltage, the second end and the third end of the seventeenth field effect transistor are connected, and are connected to the third end of the eighteenth field effect transistor, the second end of the seventeenth field effect transistor is connected to the first end of the nineteenth field effect transistor, the third end of the nineteenth field effect transistor is connected to the third end of the twelfth field effect transistor, the second end of the eighteenth field effect transistor is connected to the first end of the twentieth field effect transistor, the third end of the twentieth field effect transistor is connected to the third end of the twenty-first field effect transistor, and is connected to the second end of the digital logic circuit, the second end of the 20th field effect transistor is connected to the first end of the first capacitor and the first end of the twenty-first field effect transistor, and serves as the output end of the charge pump circuit, the second end of the first capacitor is grounded, the second end of the twenty-first field effect transistor is connected to the first end of the twenty-second field effect transistor, the third end of the twenty-second field effect transistor is connected to the third end of the nineteenth field effect transistor, and the second end of the twenty-second field effect transistor is grounded.

[0093] The 12th field effect transistor, the 19th field effect transistor and the 22nd field effect transistor form a current mirror, so the current of the 19th field effect transistor and the 22nd field effect transistor is proportional to the current of the 12th field effect transistor, and is also a ZTAT (zero temperature coefficient) current. The 18th field effect transistor and the 17th field effect transistor form a current mirror, so the current of the 18th field effect transistor is proportional to the current of the 17th field effect transistor, and is also a ZTAT (zero temperature coefficient) current. The 20th field effect transistor and the 21st field effect transistor serve as switch field effect transistors.

[0094] When the feedback voltage of the gate is at a high level, the twenty-first field effect transistor is turned on and the twentieth field effect transistor is turned off. At this time, the first capacitor is discharged and the second voltage of the node VM gradually decreases.

[0095] When the feedback voltage of the gate is at a low level, the twenty-first field effect transistor is turned off and the twentieth field effect transistor is turned on. At this time, the eighteenth field effect transistor acts as a current source to charge the first capacitor, and the second voltage of the node VM gradually rises.

[0096] In addition, the circuit also includes filtering modules such as the second capacitor, the third capacitor, and the fourth capacitor to stabilize the gate voltage of the corresponding field effect tube, filter out the noise interference caused by the power supply voltage corresponding to each field effect tube, and stabilize the current of the field effect tube.

[0097] As an optional implementation manner, the comparator circuit uses the first voltage as a reference voltage and uses the second voltage as a comparison voltage;

[0098] The comparator circuit outputs a high-level comparison signal when the first voltage is greater than the second voltage, and outputs a low-level comparison signal when the first voltage is less than the second voltage.

[0099] When the negative voltage VM is greater than the positive voltage Vref, the comparator outputs a comparison signal of low level (0);

[0100] When the negative electrode voltage VM is less than the positive electrode voltage Vref, the comparator outputs a comparison signal of a high level (VDD).

[0101] The comparison signal can be used to generate a feedback signal and provided to a digital logic circuit to generate a clock signal.

[0102] As an optional implementation, the digital logic circuit includes a first inverter, a second inverter and a D flip-flop;

[0103] The input end of the first inverter is connected to the output end of the comparator circuit, the output end of the first inverter is connected to the charge pump circuit, the input end of the second inverter is connected to the output end of the first inverter, the output end of the second inverter is connected to the first end of the D flip-flop, the second end and the third end of the D flip-flop are connected, and the fourth end of the D flip-flop is used to output a clock signal with a duty cycle of a preset value.

[0104] like Figure 3As shown, in the present application, the D flip-flop input port D is connected to the output port QN to form a divider, which can double the period of the input CLK port signal, thereby reducing the frequency by half, and the output port Q outputs a periodic oscillating square wave signal CLK with a fixed frequency, and the duty cycle of the clock CLK signal can be stabilized at 50%. Therefore, this digital logic circuit uses the D flip-flop to construct a divider, which greatly improves the stability of the duty cycle of the output clock CLK signal.

[0105] In summary, when various implementation methods are combined and applied, the circuit principle is as follows:

[0106] After the circuit is turned on by the enable signal (ENP), the field effect tube and the triode of the circuit are turned on, and the entire OSC circuit starts to work. When the second voltage at the input end of the comparator (COMP) is greater than the first voltage, the comparison signal output by the comparator is a low level (0), and the comparison signal is converted by the digital logic circuit, and the output feedback signal is a high level (VDD). At this time, the gate voltages of the 20th field effect tube and the 21st field effect tube are high level (VDD), so the 21st field effect tube is turned on, the 20th field effect tube is turned off, the first capacitor is discharged, and the second voltage gradually decreases.

[0107] When the second voltage gradually decreases to be less than the first voltage, the comparison signal output by the comparator flips from a low level (0) to a high level (VDD), and the comparison signal is converted by the digital logic circuit, and the feedback signal flips from a high level (VDD) to a low level (0). At this time, the gate voltages of the twentieth field effect transistor and the twenty-first field effect transistor are low level (0), so the twentieth field effect transistor is turned on, the twenty-first field effect transistor is turned off, the first capacitor is charged, and the second voltage gradually rises.

[0108] When the second voltage gradually rises to be greater than the first voltage, the comparison signal output by the comparator flips from a high level (VDD) to a low level (0), and the comparison signal is converted by the digital logic circuit, and the feedback signal flips from a low level (0) to a high level (VDD). At this time, the gate voltages of the twentieth field effect transistor and the twenty-first field effect transistor are high level (VDD), so the twenty-first field effect transistor is turned on, the twentieth field effect transistor is turned off, the first capacitor is discharged, and the second voltage gradually decreases.

[0109] In this way, the above steps are repeated continuously, and the comparison signal output by the comparator, the feedback signal generated by the digital logic circuit, and the clock signal are continuously flipped between a low level (0) and a high level (VDD), and a periodic oscillating square wave signal with a fixed frequency can be output at the clock signal.

[0110] See also Figure 4 , Figure 4 is a schematic diagram of the structure of an integrated circuit chip disclosed in an embodiment of the present invention, such as Figure 4 As shown, the present application provides an integrated circuit chip, comprising an oscillator circuit as in any embodiment.

[0111] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0112] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An oscillator circuit, characterized in that: The circuit comprises: A zero-temperature current generating circuit, used for generating a first current with a zero temperature coefficient; A zero-temperature voltage generating circuit, used for generating a first voltage with a temperature coefficient of zero; A charge pump circuit, used for generating a second voltage of a preset waveform according to the first current; a comparator circuit, configured to generate a comparison signal according to the first voltage and the second voltage; The digital logic circuit is used to generate a clock signal according to the comparison signal.

2. The circuit according to claim 1, characterized in that The circuit further comprises: A positive temperature current generating circuit, used to generate a second current positively correlated with the temperature; A negative temperature current generating circuit, used for generating a third current negatively correlated with temperature; Furthermore, the zero-temperature current generating circuit is used to generate a first current with a zero temperature coefficient according to the second current and the third current.

3. The circuit according to claim 2, characterized in that The connection relationship of the circuit includes: The output ends of the positive temperature current generating circuit and the negative temperature current generating circuit are connected to the input end of the zero temperature current generating circuit, the output end of the positive temperature current generating circuit is connected to the input end of the zero temperature voltage generating circuit, the output end of the zero temperature current generating circuit is connected to the first input end of the charge pump circuit, the output end of the zero temperature voltage generating circuit is connected to the first input end of the comparator circuit, the output end of the charge pump circuit is connected to the second input end of the comparator circuit, the output end of the comparator circuit is connected to the first end of the digital logic circuit, the second end of the digital logic circuit is connected to the second input end of the charge pump circuit, and the third end of the digital logic circuit serves as the output end of the oscillator circuit to output the clock signal.

4. The circuit according to claim 3, characterized in that The positive temperature current generating circuit comprises a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first triode, a second triode, a third triode and a first resistor; Wherein, the first ends of the first field effect tube and the second field effect tube are connected to the power supply voltage, the second end and the third end of the first field effect tube are connected, and are connected to the third end of the second field effect tube, the third end of the first field effect tube is connected to the first end of the third field effect tube, the second end and the third end of the third field effect tube are connected, and are connected to the third end of the fourth field effect tube, the second end of the second field effect tube is connected to the first end of the fourth field effect tube, the second end of the third field effect tube is connected to the first end of the first triode, and the second end of the fourth field effect tube is connected to the first end of the second triode and the third end of the third triode Three terminals, the third terminal of the first transistor is connected to the third terminal of the second transistor and the second terminal of the third transistor, the first terminal of the third transistor is connected to the power supply voltage, the second terminal of the first transistor is connected to the first terminal of the first resistor, the second terminal of the second transistor is connected to the second terminal of the first resistor, the second terminal of the first resistor is grounded, the connection point of the third terminal of the first field effect transistor and the third terminal of the second field effect transistor serves as the first output terminal of the positive temperature current generating circuit, and the connection point of the third terminal of the third field effect transistor and the third terminal of the fourth field effect transistor serves as the second output terminal of the positive temperature current generating circuit.

5. The circuit according to claim 4, characterized in that The negative temperature current generating circuit comprises a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a fourth triode and a second resistor; In addition, the first end of the fifth field effect tube is connected to the power supply voltage, the second end of the fifth field effect tube is connected to the first end of the sixth field effect tube, the second end of the sixth field effect tube is connected to the first end of the fourth transistor and the third end of the ninth field effect tube, the second end of the fourth transistor is grounded, the third end of the fourth transistor and the second end of the ninth field effect tube are connected to the first end of the second resistor, the second end of the second resistor is grounded, the third end of the fifth field effect tube is connected to the first output end of the positive temperature current generating circuit, the third end of the sixth field effect tube is connected to the second output end of the positive temperature current generating circuit, the first end of the seventh field effect tube is connected to the power supply voltage, and the second end and the third end of the seventh field effect tube are connected and connected to the first end of the eighth field effect tube, the second end and the third end of the eighth field effect tube are connected and connected to the first end of the ninth field effect tube.

6. The circuit according to claim 5, characterized in that The zero-temperature current generating circuit comprises a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor and a fourteenth field effect transistor; Among them, the first end of the tenth field effect tube is connected to the power supply voltage, the third end of the tenth field effect tube is connected to the second end and the third end of the seventh field effect tube, the second end of the tenth field effect tube is connected to the first end of the eleventh field effect tube, the third end of the eleventh field effect tube is connected to the second end and the third end of the eighth field effect tube, the second end of the eleventh field effect tube is connected to the first end of the twelfth field effect tube, the first end and the third end of the twelfth field effect tube are connected, the second end of the twelfth field effect tube is grounded, the first end of the thirteenth field effect tube is connected to the power supply voltage, the second end of the thirteenth field effect tube is connected to the first end of the fourteenth field effect tube, the third end of the thirteenth field effect tube is connected to the first output end of the positive temperature current generating circuit, and the third end of the fourteenth field effect tube is connected to the second output end of the positive temperature current generating circuit.

7. The circuit according to claim 5, characterized in that The zero-temperature voltage generating circuit includes a fifteenth field effect transistor, a sixteenth field effect transistor, a fifth triode and a third resistor; Among them, the first end of the fifteenth field effect tube is connected to the power supply voltage, the second end of the fifteenth field effect tube is connected to the first end of the sixteenth field effect tube, the second end of the sixteenth field effect tube is connected to the first end of the third resistor, and the connection point between the second end of the sixteenth field effect tube and the first end of the third resistor serves as the output end of the zero-temperature voltage generating circuit, the second end of the third resistor is connected to the first end of the fifth triode, the second end and the third end of the fifth triode are connected and grounded, the third end of the fifteenth field effect tube is connected to the third end of the thirteenth field effect tube, and the third end of the sixteenth field effect tube is connected to the third end of the fourteenth field effect tube.

8. The circuit according to claim 6, characterized in that The charge pump circuit includes a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a twenty-first field effect transistor, a twenty-second field effect transistor and a first capacitor; Among them, the first ends of the seventeenth field effect transistor and the eighteenth field effect transistor are connected to the power supply voltage, the second end and the third end of the seventeenth field effect transistor are connected, and are connected to the third end of the eighteenth field effect transistor, the second end of the seventeenth field effect transistor is connected to the first end of the nineteenth field effect transistor, the third end of the nineteenth field effect transistor is connected to the third end of the twelfth field effect transistor, the second end of the eighteenth field effect transistor is connected to the first end of the twentieth field effect transistor, the third end of the twentieth field effect transistor is connected to the third end of the twenty-first field effect transistor, and is connected to the second end of the digital logic circuit, the second end of the 20th field effect transistor is connected to the first end of the first capacitor and the first end of the twenty-first field effect transistor, and serves as the output end of the charge pump circuit, the second end of the first capacitor is grounded, the second end of the twenty-first field effect transistor is connected to the first end of the twenty-second field effect transistor, the third end of the twenty-second field effect transistor is connected to the third end of the nineteenth field effect transistor, and the second end of the twenty-second field effect transistor is grounded.

9. The circuit according to claim 8, characterized in that The comparator circuit uses the first voltage as a reference voltage and the second voltage as a comparison voltage; The comparator circuit outputs a high-level comparison signal when the first voltage is greater than the second voltage, and outputs a low-level comparison signal when the first voltage is less than the second voltage.

10. The circuit according to any one of claims 1 to 9, characterized in that: The digital logic circuit includes a first inverter, a second inverter and a D flip-flop; The input end of the first inverter is connected to the output end of the comparator circuit, the output end of the first inverter is connected to the charge pump circuit, the input end of the second inverter is connected to the output end of the first inverter, the output end of the second inverter is connected to the first end of the D flip-flop, the second end and the third end of the D flip-flop are connected, and the fourth end of the D flip-flop is used to output a clock signal with a duty cycle of a preset value.

11. An integrated circuit chip, characterized in that: The chip comprises the oscillator circuit according to any one of claims 1-10.

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