Amplifier, snubber circuit, and semiconductor memory device

Abstract

The invention provides an amplifier, a buffer circuit and a semiconductor storage device, and belongs to the technical field of circuits. The amplifier comprises: an input circuit comprising an input transistor for receiving a differential input voltage signal and generating and outputting a differential input current signal; the amplifying circuit is used for receiving the differential input current signal and carrying out folding operational amplification so as to generate and output a control signal; the output circuit comprises a pull-up transistor and a pull-down transistor which are connected with the output end of the output circuit, and the control end of the pull-up transistor and the control end of the pull-down transistor are both connected with the output end of the amplifying circuit so as to receive the control signal; the output circuit further comprises at least one pull-up compensation current source connected with the pull-up transistor in parallel and at least one pull-down compensation current source connected with the pull-down transistor in parallel.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technology, and in particular to an amplifier, a buffer circuit and a semiconductor storage device. Background Art

[0002] The folded op amp circuit is a type of operational amplifier, which can be used as a buffer circuit to enhance the driving capability of the input signal, that is, when the input and output voltages remain unchanged, the output current is made greater than the input current, thereby improving the response speed of the output signal, including but not limited to improving the charging and discharging speed of the output load capacitance, thereby improving the response speed of the output voltage. Summary of the invention

[0003] An embodiment of the present disclosure provides an amplifier, comprising: an input circuit, comprising an input transistor, the input transistor is used to receive a differential input voltage signal, and generate and output a differential input current signal; an amplifier circuit, used to receive the differential input current signal and perform folding operational amplification to generate and output a control signal; an output circuit, comprising a pull-up transistor and a pull-down transistor connected to the output end of the output circuit, the control ends of the pull-up transistor and the pull-down transistor are both connected to the output end of the amplifier circuit to receive the control signal; wherein the output circuit also includes at least one pull-up compensation current source connected in parallel with the pull-up transistor and at least one pull-down compensation current source connected in parallel with the pull-down transistor.

[0004] The embodiment of the present disclosure further provides a buffer circuit, which includes the amplifier described in any embodiment of the present disclosure. The input transistor includes a differential input terminal, and the differential input terminal includes a first differential input terminal coupled to the output terminal of the output circuit and a second differential input terminal for receiving a reference voltage.

[0005] An embodiment of the present disclosure further provides a semiconductor storage device, comprising an amplifier or a buffer circuit according to any one of the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a schematic diagram of the circuit structure of an amplifier in the related technology.

[0007] Figure 2 Schematic diagram of a circuit structure of an amplifier according to an exemplary embodiment of the present disclosure.

[0008] Figure 3 is a circuit structure diagram of an amplifier according to another exemplary embodiment of the present disclosure.

[0009] Figure 4 4 is a circuit diagram of an amplifier according to another exemplary embodiment of the present disclosure.

[0010] Figure 5 4 is a schematic diagram of a circuit structure of an amplifier according to another exemplary embodiment of the present disclosure.

[0011] Figure 6 4 is a schematic diagram of a circuit structure of an amplifier according to another exemplary embodiment of the present disclosure.

[0012] Figure 7 4 is a schematic diagram of a circuit structure of an amplifier according to another exemplary embodiment of the present disclosure.

[0013] Figure 8 4 is a schematic diagram of a circuit structure of an amplifier according to another exemplary embodiment of the present disclosure.

[0014] Fig. 9 4 is a schematic diagram of a circuit structure of an amplifier according to another exemplary embodiment of the present disclosure.

[0015] Fig.10 4 is a schematic diagram of a circuit structure of an amplifier according to another exemplary embodiment of the present disclosure.

[0016] Fig.11 4 is a schematic diagram of a circuit structure of an amplifier according to another exemplary embodiment of the present disclosure.

[0017] Fig.12 is a circuit structure diagram of a buffer circuit according to an exemplary embodiment of the present disclosure.

[0018] Fig.13 is a circuit structure diagram of a buffer circuit according to another exemplary embodiment of the present disclosure.

[0019] Fig.14 is based on Fig.13 Simulation schematic of the buffer circuit shown.

[0020] Fig.15 is a schematic structural diagram of a semiconductor memory device according to an exemplary embodiment of the present disclosure.

[0021] Fig.16 is a schematic structural diagram of a semiconductor memory device according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The accompanying drawings are only schematic diagrams of the present disclosure. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. The memory provided in the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings.

[0023] Figure 1 It is a schematic diagram of the circuit structure of an amplifier in the related technology.

[0024] like Figure 1 As shown, the input circuit of the amplifier in the related art includes current sources Ib1 and Ib2, N-type transistors M1 and M2, and P-type transistors M3 and M4. The sources of M3 and M4 are both connected to the output terminal of Ib1. The gates of M1 and M2 are respectively connected to the second differential input terminal V+ and the first differential input terminal V-, and the gates of M3 and M4 are also respectively connected to the second differential input terminal V+ and the first differential input terminal V-. The input terminal of Ib2 is respectively connected to the source of M1 and the source of M2.

[0025] The P-type transistor mentioned in the embodiments of the present disclosure refers to a P-type metal oxide semiconductor (Positive channel-Metal-Oxide-Semiconductor, PMOS) tube, and the N-type transistor refers to an N-type metal oxide semiconductor (Negative channel-Metal-Oxide-Semiconductor, NMOS) tube.

[0026] The amplifier circuit of the amplifier includes P-type transistors M11, M12, M13, M14, M20, M21 and M22, N-type transistors M19, M15, M16, M23 and M24, current sources Ib3, Ib4, Ib5 and Ib8, and voltage sources Vb1 and Vb4. The drain of M1 is connected to the drain of M11 and the source of M13 respectively. The drain of M2 is connected to the drain of M12 and the source of M14 respectively. The drain of M3 is connected to the input of Ib3 and the source of M15 respectively. The drain of M4 is connected to the input of Ib4 and the source of M16 respectively. The gate of M21 is connected to its drain, and the gate of M22 is connected to its drain. The drain of M21 is connected to the source of M22. The drain and gate of M22 and the input of Ib5 are all connected to the gate of M20. The gate of M23 is connected to its drain, and the gate of M24 is connected to its drain. The source of M23 is connected to the drain of M24. The output terminal of Ib8, the drain and gate of M23 are all connected to the gate of M19.

[0027] The output circuit of the amplifier includes a P-type transistor M25 and an N-type transistor M26. The gate of M25 is connected to the drain of M14, the source of M20 and the drain of M19, and the gate of M26 is connected to the drain of M16, the source of M19 and the drain of M20. The drain of M25 and the drain of M26 are both connected to the output end of the output circuit to output the output signal Vo.

[0028] The input terminal of Ib1, the source of M11, the source of M12, the input terminal of Vb1, the source of M21, the input terminal of Ib8, and the source of M25 are all connected to the positive power supply signal VDD. The output terminal of Ib2, the output terminal of Ib3, the output terminal of Ib4, the output terminal of Vb4, the output terminal of Ib5, the source of M24, and the source of M26 are all connected to the ground voltage VSS.

[0029] Figure 1 It is a typical Class AB operational amplifier (Class AB Amplifier), which is used in some scenarios with large input range and high speed requirements. Its working principle is: (Ib1 / M3 / M4)+(M11~M16) constitutes a folding operational amplifier with PMOS input, which can amplify smaller input voltages (for example, the power supply is 0.9V (volts), and PMOS can handle a voltage range of 0~0.5V); (Ib2 / M1 / M2)+(M11~M16) constitutes a folding operational amplifier with NMOS input, which can amplify larger input voltages (for example, the power supply is 0.9V, and NMOS can handle a voltage range of 0.4V~0.9V); M19 and M20 are equivalent to a PMOS switch and an NMOS respectively. switch, which are biased by M21 and M22, M23 and M24 respectively, and are all turned on during normal operation; the gates of M25 and M26 are connected through the turned-on M19 and M20, so that when the gate voltage of M25 is lower, M25 provides more current to the load, and M26 is gradually turned off. When the gate voltage of MP25 is higher, M25 is gradually turned off, and M26 discharges more charge on the load, so that the class AB amplifier can effectively cope with rail-to-rail input voltage changes. The current mirror M11-M14 and the folded common source and common gate M15 and M16 form an adding circuit, which adds the signals from the complementary input stage.

[0030] However, the amplifier in the above related technology has the following problems:

[0031] First, with the development of integrated circuits, in order to reduce the power consumption of integrated circuits (such as semiconductor storage devices), the value of the positive power signal VDD has been reduced from 3V to 1.8V, and then gradually reduced to about 1.0V. Taking into account the IR Drop (power supply voltage drop), the value inside the chip may be reduced to 0.95V or even 0.9V in some application scenarios. Under this condition, the over-drive voltage of M12, M14, M20, M19, M16 and Ib4 is insufficient, because there are five transistors in the current path, which causes the operational amplifier to fail to work normally. At the same time, the static power consumption of Ib5 and Ib8 will increase.

[0032] Second, the output impedance of the above amplifier is relatively large, which results in insufficient stability of the amplifier.

[0033] Figure 2 Schematic diagram of a circuit structure of an amplifier according to an exemplary embodiment of the present disclosure.

[0034] like Figure 2 As shown, the amplifier 20 provided in the embodiment of the present disclosure includes an input circuit 21, an amplifier circuit 22 and an output circuit 23. The input circuit 21 may include an input transistor 211. The input transistor 211 may be used to receive a differential input voltage signal and generate and output a differential input current signal. The amplifier circuit 22 may be used to receive a differential input current signal and perform a folding operational amplifier to generate and output a control signal o1. The output circuit 23 includes a pull-up transistor MP9 and a pull-down transistor MN7 connected to the output terminal Nout of the output circuit 23. The control terminals of the pull-up transistor MP9 and the pull-down transistor MN7 are both connected to the output terminal of the amplifier circuit 22 to receive the control signal o1. Among them, the output circuit 23 also includes at least one pull-up compensation current source connected in parallel with the pull-up transistor MP9 and at least one pull-down compensation current source connected in parallel with the pull-down transistor MN7.

[0035] Figure 2 , a pull-up compensation current source Ibu1 and a pull-down compensation current source Ibd1 are shown, but the present disclosure is not limited thereto. In some embodiments, the pull-up transistor of the output circuit is connected in parallel with multiple pull-up compensation current sources, and the pull-down transistor is connected in parallel with multiple pull-down compensation current sources.

[0036] like Figure 3 As shown above Figure 2 The difference of the embodiment is that it is assumed here that the pull-up transistor MP9 of the output circuit 23 is connected in parallel with n pull-up compensation current sources, which are represented as Ibu1 to Ibun, respectively, and n is a positive integer greater than 1. The pull-down transistor MN7 of the output circuit 23 is connected in parallel with n pull-down compensation current sources, which are represented as Ibd1 to Ibdn.

[0037] The amplifier provided in the embodiment of the present disclosure can provide a larger output current and a stronger current driving capability when the load capacitance of the amplifier increases by connecting multiple pull-up compensation current sources in parallel to the pull-up transistor of the output circuit, and connecting multiple pull-down compensation current sources in parallel to the pull-down transistor of the output circuit, thereby achieving the same charging and discharging speed as with a smaller load capacitance.

[0038] Continue to refer Figure 3The output circuit 23 may further include a control switch connected in series with each pull-up compensation current source, and a control switch connected in series with each pull-down compensation current source, for example, a control switch ku1 connected in series with Ibu1, a control switch kun connected in series with Ibun, a control switch kd1 connected in series with Ibd1, and a control switch kdn connected in series with Ibdn.

[0039] When the load capacitance of the amplifier is larger, in order to achieve the same charging and discharging speed, a larger output current is required. At this time, more pull-up compensation current sources and pull-down compensation current sources can be connected in parallel, that is, the size of the load capacitance is positively correlated with the number of pull-up compensation current sources and pull-down compensation circuit sources connected in parallel. For example, when the load capacitance is 200pf (picofarads), one pull-up compensation current source and one pull-down compensation current source can be selected to be connected in parallel. When the load capacitance is 400pf, two pull-up compensation current sources and two pull-down compensation current sources can be selected to be connected in parallel. The specific number of pull-up compensation current sources and pull-down compensation current sources connected in parallel can be set according to actual needs, and the present disclosure is not limited to this, and is only used for illustration here.

[0040] The disclosed embodiment provides compensation between output loads (such as load capacitance) by connecting the output MOS tubes (including pull-up transistors and pull-down transistors) of the class AB amplifier in parallel with current sources (including pull-up compensation current sources and pull-down compensation current sources). By adding parallel current sources, the total current of the output load can be averaged to different output transistors, thereby obtaining a larger output current, resulting in a higher overall power level, thereby increasing the current driving capability.

[0041] The amplifier provided in the embodiment of the present disclosure can choose to turn on or off the corresponding number of pull-up compensation current sources and pull-down compensation current sources according to changes in the size of the load capacitance of the amplifier through a control switch connected in series with each pull-up compensation current source and a control switch connected in series with each pull-down compensation current source.

[0042] In the following embodiments, a pull-up transistor is connected in parallel with a pull-up compensation current source and a pull-down transistor is connected in parallel with a pull-down compensation current source for example, but the present disclosure is not limited thereto.

[0043] like Figure 4 As shown, it is Figure 2 The difference of the embodiment is that each pull-up compensation current source includes a seventh P-type transistor MP7 and an eighth P-type transistor MP8. The second end of the seventh P-type transistor MP7 can be coupled to the first power input terminal Pit1 for receiving the power signal VCC, and the control end of the seventh P-type transistor MP7 can receive the first P bias voltage Biasp1.

[0044] The second end of the eighth P-type transistor MP8 can be coupled to the first end of the seventh P-type transistor MP7, the first end of the eighth P-type transistor MP8 can be coupled to the output end Nout of the output circuit 23, and the control end of the eighth P-type transistor MP8 can be used to receive the second P bias voltage Biasp2.

[0045] Continue to refer Figure 4 , each pull-down compensation current source may include a sixth N-type transistor MN6 and a fifth N-type transistor MN5. The first end of the sixth N-type transistor MN6 may be coupled to the output end Nout of the output circuit 23, and the control end of the sixth N-type transistor MN6 may receive the first N bias voltage Biasn1. The first end of the fifth N-type transistor MN5 may be coupled to the second end of the sixth N-type transistor MN6, the second end of the fifth N-type transistor MN5 may be coupled to the second power input end Pit2 for receiving another power signal, and the control end of the fifth N-type transistor MN5 may receive the second N bias voltage Biasn2. The other power signal may be a negative power voltage or a ground voltage VSS. In this embodiment, the ground voltage VSS is taken as an example.

[0046] The amplifier provided in the embodiment of the present disclosure can reduce the output impedance of the output circuit by connecting at least one pull-up compensation current source in parallel to the pull-up transistor MP9 of the output circuit and at least one pull-down compensation current source in parallel to the pull-down transistor MN7 of the output circuit, thereby solving the problem of stability of the class AB amplifier.

[0047] In some embodiments, the “connection” between the control terminals of the pull-up transistor MP9 and the pull-down transistor MN7 refers to a direct connection, that is, there is no other component between the two connected to each other. For example, there is no connection between the control terminals of the pull-up transistor MP9 and the pull-down transistor MN7. Figure 1 However, it should be noted that the term "connection" is limited to the control terminal of the pull-up transistor MP9 and the control terminal of the pull-down transistor MN7 in some embodiments, and does not limit the positional relationship and electrical properties between other nodes.

[0048] The amplifier provided by the embodiment of the present disclosure allows the control ends of the pull-up transistor and the pull-down transistor of the output circuit to be directly connected to the output end of the amplifier circuit, thereby eliminating the two transistors M19 and M20 in the amplifier circuit, so that the number of transistors connected in series in the current path in the amplifier circuit is reduced, thereby solving the problem of insufficient overdrive voltage in the amplifier, so that the amplifier can work normally. In addition, by eliminating the two transistors M19 and M20 in the amplifier circuit, the path of Ib8, M23 and M24 that provide bias for M19 can also be omitted, and the path of Ib5, M21 and M22 that provide bias for M20 can also be omitted, thereby saving the static power consumption of the amplifier and saving the circuit area of ​​the amplifier.

[0049] refer to Figure 2 , the input transistor 211 may include: a tenth P-type transistor MP10 and an eleventh P-type transistor MP11. The second end of the tenth P-type transistor MP10 is coupled to the second end of the eleventh P-type transistor MP11. The control end of the tenth P-type transistor MP10 and the control end of the eleventh P-type transistor MP11 can be used to receive the first voltage signal vinneg and the second voltage signal vinpos in the differential input voltage signal, respectively. The first end of the tenth P-type transistor MP10 and the first end of the eleventh P-type transistor MP11 can be used to output the first current signal Iinneg and the second current signal Iinpos in the differential input current signal to the amplifier circuit 22, respectively. It should be noted that the coupling in the embodiments of the present disclosure includes direct connection and indirect connection, and indirect connection means that other components may exist between the two mutually coupled components.

[0050] In some embodiments, the first end of the pull-up transistor MP9 and the first end of the pull-down transistor MN7 are coupled to the output end Nout of the output circuit 23 to output the output signal Vout. An inverter is provided between the control signal o1 and the output signal Vout to invert the voltage.

[0051] In some embodiments, the pull-up transistor MP9 is a PMOS transistor, and the pull-down transistor MN7 is an NMOS transistor. The control terminals of the pull-up transistor MP9 and the pull-down transistor MN7 are their gates, the first terminals can be drains, and the second terminals can be sources. It can be understood that in some embodiments, the source and drain of the PMOS transistor and the NMOS transistor can be interchangeable; in parallel, in some embodiments, the pull-up transistor and the pull-down transistor are the same type of transistors, that is, both are PMOS transistors or NMOS transistors.

[0052] The amplifier shown in the embodiment of the present disclosure may be a Class AB Amplifier, and specifically may be a folded cascode operational amplifier, but the present disclosure is not limited thereto.

[0053] Continue to refer Figure 4 The output circuit 23 may further include a first capacitor C1 and a second capacitor C2. The first end of the first capacitor C1 may be coupled to the output terminal Nout of the output circuit 23, and the second end of the first capacitor C1 may be coupled to the control terminal of the pull-down transistor MN7. The first end of the second capacitor C2 may be coupled to the control terminal of the pull-up transistor MP9, and the second end of the second capacitor C2 may be coupled to the output terminal Nout of the output circuit 23.

[0054] The amplifier provided in the embodiment of the present disclosure can eliminate the oscillation of the amplifier, reduce the nonlinearity and distortion of the amplifier, and improve the efficiency, noise ratio and frequency response of the amplifier by adding a second capacitor coupled to the control end of the pull-up transistor of the output circuit and a first capacitor coupled to the control end of the pull-down transistor.

[0055] like Figure 5 As shown, it is Figure 4 The difference between the embodiments is that each pull-up compensation current source may include only one PMOS transistor, and each pull-down compensation current source may include only one NMOS transistor.

[0056] For example, each pull-up compensation current source may include only the seventh P-type transistor MP7. The second end of the seventh P-type transistor MP7 may be coupled to the first power input terminal Pit1 for receiving the power signal VCC, the control end of the seventh P-type transistor MP7 may receive the first P bias voltage Biasp1, and the first end of the seventh P-type transistor MP7 may be coupled to the output terminal Nout of the output circuit 23.

[0057] For example, each pull-down compensation current source may include only a sixth N-type transistor MN6. A first terminal of the sixth N-type transistor MN6 may be coupled to the output terminal Nout of the output circuit 23, a control terminal of the sixth N-type transistor MN6 may receive the first N bias voltage Biasn1, and a second terminal of the sixth N-type transistor MN6 may be coupled to the second power input terminal Pit2 for receiving another power signal.

[0058] The amplifier provided by the embodiment of the present disclosure can also reduce the output impedance, avoid the problem of insufficient over-driving voltage, and improve the stability of the amplifier by setting each pull-up compensation current source to include only one PMOS tube and each pull-down compensation current source to include only one NMOS tube. At the same time, since the number of transistors included in each pull-up compensation current source and pull-down compensation current source is reduced, the circuit area of ​​the amplifier can be reduced.

[0059] like Figure 6 As shown, the amplifier provided by the embodiment of the present disclosure is Figure 2The difference of the embodiment is that the amplifier circuit 22 includes: a third current source Ib3, a fourth current source Ib4, a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3 and a fourth N-type transistor MN4. The input terminals of the third current source Ib3 and the fourth current source Ib4 are both coupled to the first power input terminal Pit1 to receive the power signal VCC. The first terminal of the second N-type transistor MN2 is coupled to the output terminal of the third current source Ib3, and the control terminal of the second N-type transistor MN2 is coupled to the control terminal of the fourth N-type transistor MN4 and receives the first N bias voltage Biasn1. The first terminal of the first N-type transistor MN1 and the second terminal of the second N-type transistor MN2 are coupled to the first node N1 to receive the first current signal Iinneg in the differential input current signal. The first terminal of the fourth N-type transistor MN4 and the second terminal of the third N-type transistor MN3 are coupled to the second node N2 to receive the second current signal Iinpos in the differential input current signal. That is, the first node N1 and the second node N2 can be used to receive the first current signal Iinneg and the second current signal Iinpos in the differential input current signal, respectively. The control end of the first N-type transistor MN1 and the control end of the third N-type transistor MN3 are both coupled to the first end of the second N-type transistor MN2 (i.e., the output end of the third current source Ib3) to receive the second N bias voltage Biasn2. The first end of the fourth N-type transistor MN4 is coupled to the output end of the fourth current source Ib4. The second ends of the first N-type transistor MN1 and the third N-type transistor MN3 are both coupled to the second power supply input terminal Pit2 to receive the ground voltage VSS. The first N-type transistor MN1, the second N-type transistor MN2, the third N-type transistor MN3 and the fourth N-type transistor MN4 form a mirror constant current source, whose controlled current is equal to the input reference current, that is, the input-output current transfer ratio is equal to 1.

[0060] In an exemplary embodiment, the first power input terminal Pit1 is used to receive a power signal VCC, and a voltage value of the power signal VCC is between 0.9V and 1.1V.

[0061] from Figure 6It can be seen that the pull-up transistor MP9 and the pull-down transistor MN7 of the output circuit 23 are directly connected to the output end of the amplifier circuit 22 to receive the same control signal o1. On the two current paths of the amplifier circuit 22, a current source and two transistors are connected in series on each current path, and the two transistors connected in series on the same current path are NMOS tubes. Compared with the PMOS tube, the threshold voltage of the NMOS tube is lower. For example, the threshold voltage of the PMOS tube is about 0.5V, and the threshold voltage of the NMOS tube is about 0.3V. The over-driving voltage is negatively correlated with the sum of the threshold voltages of multiple transistors connected in series on the same current path. Therefore, when the NMOS tube is used to replace the PMOS tube for self-biasing, and M19 and M20 are omitted, when the voltage value of the power supply signal VCC drops to between 0.9V and 1.1V, the over-driving voltage on each current path of the amplifier circuit 22 can still be greater than 0, that is, the amplifier can still work normally. At the same time, since the power supply of the amplifier drops from a larger VDD (about 3.3V) to a smaller VCC (for example, about 1.0V), the overall power consumption of the amplifier can be reduced.

[0062] like Figure 7 As shown, it is Figure 6 The difference of the embodiment is that the third current source Ib3 includes a third P-type transistor MP3 and a fourth P-type transistor MP4. The second end of the third P-type transistor MP3 is coupled to the first power input end to receive the power signal VCC, and the control end of the third P-type transistor MP3 is used to receive the first P bias voltage Biasp1. The second end of the fourth P-type transistor MP4 is coupled to the first end of the third P-type transistor MP3, the first end of the fourth P-type transistor MP4 is coupled to the first end of the second N-type transistor MN2, and the control end of the fourth P-type transistor MP4 is used to receive the second P bias voltage Biasp2. Continue to refer to Figure 7 , the fourth current source Ib4 includes a fifth P-type transistor MP5 and a sixth P-type transistor MP6. The second end of the fifth P-type transistor MP5 is coupled to the first power input end to receive the power signal VCC. The control end of the fifth P-type transistor MP5 receives the first P bias voltage Biasp1. The second end of the sixth P-type transistor MP6 is coupled to the first end of the fifth P-type transistor MP5, and the first end of the sixth P-type transistor MP6 is coupled to the first end of the fourth N-type transistor MN4. The control end of the sixth P-type transistor MP6 is used to receive the second P bias voltage Biasp2.

[0063] The amplifier provided by the embodiment of the present disclosure includes four transistors connected in series in the same current path in the amplification circuit, including two PMOS tubes and two NMOS tubes. Since the self-bias of the folded operational amplifier is changed from the PMOS tube to the NMOS tube, the threshold voltage of the NMOS tube is usually smaller than the threshold voltage of the PMOS tube, so that the over-drive voltage consumed by the self-bias is relatively small, so that when the power supply signal drops to about 1.0V, the over-drive voltage can still be greater than 0, and therefore it can still work normally.

[0064] like Figure 8 As shown, the amplifier provided by the embodiment of the present disclosure is Figure 7 Compared with the embodiment, the difference is that the amplifier also includes a bias voltage circuit 24. The bias voltage circuit 24 includes a twenty-first P-type transistor M21 and a twenty-second P-type transistor M22. The second end of the twenty-first P-type transistor M21 is coupled to the first power input end to receive the power signal VCC, and the control end of the twenty-first P-type transistor M21 is coupled to the first end of the twenty-first P-type transistor M21 for outputting the first P bias voltage Biasp1 to provide to the control end of the third P-type transistor MP3 and the control end of the fifth P-type transistor MP5 of the amplifier circuit 22. The second end of the twenty-second P-type transistor M22 can be coupled to the first end of the twenty-first P-type transistor M21, and the control end of the twenty-second P-type transistor M22 can be coupled to the first end of the twenty-second P-type transistor M22 for outputting the second P bias voltage Biasp2 to provide to the control end of the fourth P-type transistor MP4 and the control end of the sixth P-type transistor MP6 of the amplifier circuit 22.

[0065] In the embodiment of the present disclosure, the first P bias voltage Biasp1 comes from the twenty-first P-type transistor M21, and the second P bias voltage Biasp2 comes from the twenty-second P-type transistor M22. Both the twenty-first P-type transistor M21 and the twenty-second P-type transistor M22 are connected by diodes so that the voltage difference between the first P bias voltage Biasp1 and the second P bias voltage Biasp2 is equivalent to the voltage drop of a diode, which is approximately 0.3V.

[0066] It should be noted that the acquisition of the first P bias voltage Biasp1 and the second P bias voltage Biasp2 is not limited to the above examples. For example, in other embodiments, independent bias voltage circuits can be provided for the third current source and the fourth current source to provide bias voltages for the third current source and the fourth current source respectively.

[0067] The amplifier provided in the embodiment of the present disclosure can improve the accuracy of the bias voltage and simplify the circuit structure by setting a bias voltage circuit of the same structure for the third current source and the fourth current source in the amplifier circuit to obtain the required bias voltage (including the first P bias voltage Biasp1 and the second P bias voltage Biasp2).

[0068] like Fig. 9 As shown, the amplifier provided by the embodiment of the present disclosure is Figure 6 The difference between the embodiments is that the third current source and the fourth current source each include only one MOS tube.

[0069] For example, the third current source Ib3 only includes a third P-type transistor MP3. The second end of the third P-type transistor MP3 is coupled to the first power input end to receive the power signal VCC, and the control end of the third P-type transistor MP3 is used to receive the first P bias voltage Biasp1. The first end of the third P-type transistor MP3 is coupled to the first end of the second N-type transistor MN2.

[0070] For example, the fourth current source Ib4 only includes a fifth P-type transistor MP5. A second terminal of the fifth P-type transistor MP5 is coupled to the first power input terminal to receive the power signal VCC, and a control terminal of the fifth P-type transistor MP5 is used to receive the first P bias voltage Biasp1. A first terminal of the fifth P-type transistor MP5 is coupled to a first terminal of the fourth N-type transistor MN4.

[0071] The amplifier provided by the embodiment of the present disclosure reduces the number of transistors in the third current source and the fourth current source, so that the same current path in the amplifier circuit includes three transistors connected in series, including one PMOS tube and two NMOS tubes, thereby further reducing the consumed overdrive voltage, so that when the power supply signal drops to about 1.0V, the overdrive voltage can still be greater than 0, so it can still work normally. At the same time, the reduction in the number of transistors can also reduce the circuit area of ​​the amplifier.

[0072] like Fig.10 As shown, the amplifier provided by the embodiment of the present disclosure is Figure 2The difference of the embodiment is that the input circuit 21 further includes a first current source Ib1. The input terminal of the first current source Ib1 is coupled to the first power input terminal to receive the power signal VCC. The second terminal of the tenth P-type transistor MP10 is coupled to the output terminal of the first current source Ib1. The second terminal of the eleventh P-type transistor MP11 is coupled to the output terminal of the first current source Ib1. The control terminal of the eleventh P-type transistor MP11 and the control terminal of the tenth P-type transistor MP10 can be used to receive the first voltage signal vinneg and the second voltage signal vinpos in the differential input voltage signal, respectively, and the first terminal of the eleventh P-type transistor MP11 and the first terminal of the tenth P-type transistor MP10 can be used to output the first current signal Iinneg and the second current signal Iinpos in the differential input current signal, respectively.

[0073] The amplifier provided in the embodiment of the present disclosure, when the power supply of the amplifier is 3.3V, the voltage originally obtained by the voltage division circuit and input to Figure 1 The voltage value of the second differential input terminal V+ is about 500-700mV, and the NMOS tube M2 can be turned on. When the power signal of the amplifier drops to about 1.1V, the voltage value divided to the second differential input terminal V+ is about 300mV. Figure 1 The M2 tube in the circuit cannot be turned on due to insufficient overdrive voltage, and the M1 and M2 tubes are cut off. The M2 tube cannot play its original role, so it can be omitted. Figure 1 The M1 and M2 tubes in the amplifier save the area and power consumption of the amplifier.

[0074] Fig.11 4 is a schematic diagram of a circuit structure of an amplifier according to another exemplary embodiment of the present disclosure.

[0075] like Fig.11 As shown, Fig.10 The first current source Ib1 in the embodiment includes a first P-type transistor MP1 and a second P-type transistor MP2. The second end of the first P-type transistor MP1 is coupled to the first power input end to receive the power signal VCC, and the control end of the first P-type transistor MP1 is used to receive the first P bias voltage Biasp1. The second end of the second P-type transistor MP2 is coupled to the first end of the first P-type transistor MP1, and the first end of the second P-type transistor MP2 is coupled to the second ends of the tenth P-type transistor MP10 and the eleventh P-type transistor MP11. The control end of the second P-type transistor MP2 is used to receive the second P bias voltage Biasp2.

[0076] In some embodiments, the first current source Ib1 includes only a first P-type transistor MP1. A second terminal of the first P-type transistor MP1 is coupled to a first power input terminal to receive a power signal VCC. A control terminal of the first P-type transistor MP1 is used to receive a first P bias voltage Biasp1. A first terminal of the first P-type transistor MP1 is coupled to second terminals of the tenth P-type transistor MP10 and the eleventh P-type transistor MP11.

[0077] Fig.11 In the embodiment, when the second voltage signal vinpos increases, the current on the second node N2 on MN4 decreases, and the potential of the control signal o1 decreases accordingly, so that the pull-up capability of the pull-up transistor MP9 is stronger. The voltage values ​​of the first N bias voltage Biasn1 and the second N bias voltage Biasn2 can be the same or different.

[0078] Continue to refer Fig.11 In the embodiment of the present disclosure, the first current source in the input circuit 21, the third current source and the fourth current source in the amplifier circuit 22, and the seventh P-type transistor MP7 and the eighth P-type transistor MP8 connected in parallel to the pull-up transistor MP9 in the output circuit 23 all adopt Figure 8 The same bias voltage circuit 24 in the embodiment is used to provide the bias voltage, and the same bias voltage circuit can simplify the circuit structure. However, the present disclosure is not limited thereto, and in other embodiments, an independent bias voltage circuit can be provided for each of the first current source, the third current source, the fourth current source, the seventh P-type transistor MP7, and the eighth P-type transistor MP8.

[0079] Fig.11 In the embodiment, the bias voltages of the sixth N-type transistor MN6 and the fourth N-type transistor MN4 are the same, which are the first N bias voltage Biasn1. The fifth N-type transistor MN5 and the seventh P-type transistor MP7 are configured in conjunction with the first capacitor C1 and the second capacitor C2 to implement Miller compensation and eliminate the influence of the parasitic capacitance of the output end (output control signal o1) of the amplifier circuit on the voltage of the output signal Vout.

[0080] In some embodiments, by improving the buffer circuit as above, on the one hand, by allowing the control ends of the pull-up transistor and the pull-down transistor of the output circuit to be directly connected to the output end of the amplifier circuit at the same time, M19 and M20 can be omitted, thereby solving the problem of insufficient overdrive voltage of the amplifier due to the voltage drop of the power supply signal, so that the amplifier can also work normally under a smaller power supply signal, and the smaller power supply signal reduces the overall power consumption of the amplifier. On the other hand, when M19 and M20 are omitted, Ib5 and Ib8 can be omitted, thereby saving the static power consumption of the amplifier. At the same time, due to the drop of the power supply signal, M1 and M2 are almost cut off, so M1, M2 and Ib2 can be omitted, thereby saving the area and power consumption of the amplifier. In addition, the self-bias of the folded operational amplifier is changed from PMOS to NMOS, because the threshold voltage of NMOS is usually less than the threshold voltage of PMOS, so the overdrive voltage consumed by the self-bias is also relatively small. On the other hand, by connecting at least one pull-up compensation current source in parallel to the pull-up transistor and at least one pull-down compensation current source in parallel to the pull-down transistor, the output impedance can be reduced and the stability of the amplifier can be improved.

[0081] like Fig.12 As shown, the embodiment of the present disclosure further provides a buffer circuit 30, the buffer circuit 30 includes the above Figures 2 to 11 Amplifier 20 in any embodiment. The input transistor in amplifier 20 includes a differential input terminal, and the differential input terminal includes a first differential input terminal (e.g., corresponding to the control terminal of MP10) and a second differential input terminal (e.g., corresponding to the control terminal of MP11), the first differential input terminal is used to receive the first voltage signal vinneg in the differential input voltage signal, and the second differential input terminal is used to receive the second voltage signal vinpos in the differential input voltage signal. The output terminal Nout of the output circuit 23 of the amplifier 20 is coupled to the first differential input terminal of the input circuit 21 to form a buffer circuit 30, so that the voltage magnitudes of the second voltage signal vinpos and the output signal Vout are the same, that is, the voltage value of the output signal Vout follows the second voltage signal vinpos, but the driving capability is improved, that is, the driving current magnitude is different. When Fig.12 When the buffer circuit 30 provided in the embodiment is used to provide a reference voltage for a semiconductor memory device, the second differential input terminal can be used to receive the reference voltage.

[0082] Fig.13 Example and Fig.11 The difference of the embodiment lies in that the output terminal Nout of the output circuit 23 of the amplifier 20 is coupled to the first differential input terminal of the input transistor of the input circuit 21 to form a buffer circuit 30 .

[0083] The amplifier or buffer circuit in any of the above embodiments can be used to generate a reference voltage V for a semiconductor memory device. REF For example, VREFDQ and VREFCA are generated for the DQ (data signal) pin and the CA (command address signal) pin in the semiconductor memory device, that is, Vout in the above embodiment can be used as VREFDQ and VREFCA, respectively. In addition, the load capacitance at the output end of the output circuit is to prevent the voltage change of the CA and DQ terminals from generating a kick-back effect on the VREFDQ and VREFCA terminals.

[0084] The semiconductor storage device in the embodiment of the present disclosure may be, for example, a DRAM (Dynamic Random Access Memory), such as LPDDR5 / 5X, but the present disclosure does not limit the type of semiconductor storage device. When the output signal Vout is connected to the first voltage signal vinneg to form a buffer circuit, it can be used as an input buffer in the DRAM. LPDDR4 began to introduce the VREFDQ / VREFCA training function because the speed of DQ IO (input and output, which is the Rx circuit (receiving circuit) on the LPDDR4 side) is getting faster and faster. Due to the existence of parasitic RC, different VREFDQ / VREFCA values ​​need to be set for signals of different speeds on Rx in order to better receive the data transmitted by the controller. With LPDDR5 / 5X, the IO speed reaches a higher level (for example, 8533M), which puts higher requirements on VREFDQ / VREFCA.

[0085] JESD209-5B makes some provisions for VREFDQ, puts forward some requirements for the range of VREFDQ, and the accuracy of VREFDQ, and also has clear requirements for VREFDQ in terms of timing. The amplifier or buffer circuit provided in the embodiment of the present disclosure can be adaptively changed or optimized according to different processes, devices, etc. in actual applications, so as to meet the requirements of the spec. Fig.13 As shown, when Vout and vinneg are connected, Fig.13A buffer circuit is formed, and the gates of MP7 and MP8 are connected to Biasp1 and Biasp2 respectively, and the gates of MN5 and MN6 are connected to Biasn1 and Biasn2 respectively, wherein Biasn2 is generated by the self-bias of the class AB amplifier. MP7, MP8, MN5, and MN6 can be adjusted online through testmode (test circuit), that is, the aspect ratio and size of MP7, MP8, MN5, and MN6 are adjusted according to the output load capacitance of Vout, or the number of parallel pull-up compensation current sources and pull-down compensation current sources are adjusted as in the above embodiment. Using this buffer circuit, combined with MR14 in JESD209-5B, MR14 is one of the mode registers, which can be used to adjust parameters, and then adjust the voltage of the second voltage signal vinpos. The voltage of the output signal Vout is adjusted following the adjustment of the voltage of vinpos. The technical effect that can be achieved is shown in FIG. Fig.14 .

[0086] Fig.14 The horizontal axis represents time in ns (nanoseconds), and the vertical axis is the voltage value of the output signal vinpos in mV (millivolts). After being connected into a buffer circuit, Vout and vinneg are connected into a negative feedback form, and Vout follows vinpos. Therefore, the voltage shapes of vinpos and Vout are almost exactly the same. Fig.13 In the embodiment, the current of vinpos is relatively small and the current of Vout is relatively large. When the output load capacitance is relatively large, a relatively fast charging and discharging speed can be provided, so that the output voltage can respond to changes quickly.

[0087] like Fig.15 As shown, the semiconductor memory device 150 of the embodiment of the present disclosure may include the amplifier 20 described in any of the above embodiments. Fig.16 As shown, the semiconductor memory device 150 of the embodiment of the present disclosure may include the buffer circuit 30 described in any of the above embodiments.

[0088] The present disclosure is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. An amplifier, characterized in that: include: An input circuit, comprising an input transistor, the input transistor being configured to receive a differential input voltage signal and generate and output a differential input current signal; an amplifier circuit, used for receiving the differential input current signal and performing folding operational amplification to generate and output a control signal; An output circuit comprises a pull-up transistor and a pull-down transistor connected to the output end of the output circuit, wherein the control ends of the pull-up transistor and the pull-down transistor are both connected to the output end of the amplifier circuit to receive the control signal; wherein the output circuit also comprises at least one pull-up compensation current source connected in parallel with the pull-up transistor and at least one pull-down compensation current source connected in parallel with the pull-down transistor.

2. The amplifier according to claim 1, characterized in that Each pull-up compensation current source includes: a seventh P-type transistor, wherein a second terminal of the seventh P-type transistor is coupled to the first power input terminal, and a control terminal of the seventh P-type transistor receives a first P bias voltage; an eighth P-type transistor, wherein a second terminal of the eighth P-type transistor is coupled to a first terminal of the seventh P-type transistor, a first terminal of the eighth P-type transistor is coupled to an output terminal of the output circuit, and a control terminal of the eighth P-type transistor receives a second P bias voltage; Each pull-down compensation current source includes: a sixth N-type transistor, a first terminal of the sixth N-type transistor being coupled to the output terminal of the output circuit, and a control terminal of the sixth N-type transistor receiving a first N bias voltage; A fifth N-type transistor, wherein a first terminal of the fifth N-type transistor is coupled to the second terminal of the sixth N-type transistor, a second terminal of the fifth N-type transistor is coupled to the second power input terminal, and a control terminal of the fifth N-type transistor receives a second N bias voltage.

3. The amplifier according to claim 1, characterized in that The amplifying circuit comprises: A third current source and a fourth current source, wherein input terminals of the third current source and the fourth current source are both coupled to the first power input terminal; a second N-type transistor, wherein a first terminal of the second N-type transistor is coupled to the output terminal of the third current source, and a control terminal of the second N-type transistor is coupled to the control terminal of the fourth N-type transistor and receives a first N bias voltage; a first N-type transistor, wherein a first terminal of the first N-type transistor and a second terminal of the second N-type transistor are coupled to a first node, a first terminal of the fourth N-type transistor and a second terminal of the third N-type transistor are coupled to a second node, the first node and the second node are respectively used to receive a first current signal and a second current signal in the differential input current signal, and a control terminal of the first N-type transistor and a control terminal of the third N-type transistor are both coupled to a first terminal of the second N-type transistor to receive a second N bias voltage; The fourth N-type transistor, a first terminal of the fourth N-type transistor is coupled to the output terminal of the fourth current source; The second ends of the third N-type transistor, the first N-type transistor and the third N-type transistor are all coupled to the second power input end.

4. The amplifier according to claim 3, characterized in that The third current source comprises: a third P-type transistor, wherein a second terminal of the third P-type transistor is coupled to the first power input terminal, and a control terminal of the third P-type transistor receives a first P bias voltage; a fourth P-type transistor, wherein a second terminal of the fourth P-type transistor is coupled to a first terminal of the third P-type transistor, a first terminal of the fourth P-type transistor is coupled to a first terminal of the second N-type transistor, and a control terminal of the fourth P-type transistor receives a second P bias voltage; The fourth current source comprises: a fifth P-type transistor, wherein a second terminal of the fifth P-type transistor is coupled to the first power input terminal, and a control terminal of the fifth P-type transistor receives the first P bias voltage; A sixth P-type transistor, wherein the second end of the sixth P-type transistor is coupled to the first end of the fifth P-type transistor, the first end of the sixth P-type transistor is coupled to the first end of the fourth N-type transistor, and the control end of the sixth P-type transistor receives the second P bias voltage.

5. The amplifier according to claim 4, characterized in that Also includes: A bias voltage circuit, the bias voltage circuit comprising: a twenty-first P-type transistor, a second terminal of the twenty-first P-type transistor being coupled to the first power input terminal, and a control terminal of the twenty-first P-type transistor being coupled to the first terminal of the twenty-first P-type transistor for outputting the first P bias voltage; A twenty-second P-type transistor, the second end of the twenty-second P-type transistor is coupled to the first end of the twenty-first P-type transistor, and the control end of the twenty-second P-type transistor is coupled to the first end of the twenty-second P-type transistor for outputting the second P bias voltage.

6. The amplifier according to any one of claims 3 to 5, characterized in that The first power input terminal is used to receive a power signal, and the voltage value of the power signal is between 0.9V and 1.1V.

7. The amplifier according to claim 1, characterized in that The input circuit further comprises: A first current source, wherein an input terminal of the first current source is coupled to a first power input terminal; The input transistor comprises: a tenth P-type transistor, a second terminal of the tenth P-type transistor being coupled to the output terminal of the first current source; An eleventh P-type transistor, the second end of the eleventh P-type transistor is coupled to the output end of the first current source, the control end of the eleventh P-type transistor and the control end of the tenth P-type transistor are respectively used to receive the second voltage signal and the first voltage signal in the differential input voltage signal, and the first end of the eleventh P-type transistor and the first end of the tenth P-type transistor are respectively used to output the second current signal and the first current signal in the differential input current signal.

8. The amplifier according to claim 7, characterized in that The first current source comprises: a first P-type transistor, wherein a second terminal of the first P-type transistor is coupled to the first power input terminal, and a control terminal of the first P-type transistor is used to receive a first P bias voltage; A second P-type transistor, the second end of the second P-type transistor is coupled to the first end of the first P-type transistor, the first end of the second P-type transistor is coupled to the second ends of the tenth P-type transistor and the eleventh P-type transistor, and the control end of the second P-type transistor receives a second P bias voltage.

9. A buffer circuit, characterized in that: include: An amplifier as claimed in any one of claims 1 to 8; The input transistor includes a differential input terminal, and the differential input terminal includes a first differential input terminal coupled to the output terminal of the output circuit and a second differential input terminal for receiving a reference voltage.

10. A semiconductor storage device, characterized in that: The method comprises the amplifier according to any one of claims 1 to 8 or the buffer circuit according to claim 9.

Images