Film surface acoustic wave filter and packaging method

Abstract

The invention provides a thin film surface acoustic wave filter and a packaging method, the filter comprises a first wafer and a second wafer, the first wafer comprises a first substrate layer and an electrode layer, and the electrode layer is arranged on the first substrate layer; the second wafer is arranged on one side of the first wafer, the second wafer comprises a second substrate layer and a bonding layer, the bonding layer is arranged on the second substrate layer, the bonding layer is bonded with the electrode layer, and the bonding layer surrounds between the first wafer and the second wafer to form a sealed cavity; a part of the surface of the electrode layer of the first wafer and a part of the surface of the second substrate layer of the second wafer are exposed out of the sealed cavity. According to the invention, the second wafer replaces a cavity formed by an existing dry film, the area occupied by the original dry film is reduced, the miniaturization of the filter is realized, the stability of the cavity structure is further improved, the first wafer of the module packaging type can bear higher pressure, the collapse condition in the module packaging process is reduced, and the packaging quality of the module is improved. And the quality of the filter is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of thin film filters, and in particular relates to a thin film surface acoustic wave filter and a packaging method. Background Art

[0002] At present, commonly used RF filters include surface acoustic wave filters SAW (Surface Acoust i cWave, SAW) and bulk acoustic wave filters BAW (Bulk Acoust ic Wave, BAW). Among them, surface acoustic wave filters include ordinary surface acoustic wave filters, temperature compensated surface acoustic wave filters TC-SAW and thin film surface acoustic wave filters TF-SAW.

[0003] There are two main types of semiconductor packaging methods: traditional packaging and wafer-level packaging. Traditional packaging involves first cutting the wafer into chips and then packaging the chips; while wafer-level packaging involves first performing partial or full packaging on the wafer and then cutting it into individual pieces.

[0004] In the wafer-level packaging process, using dry film to create a cavity structure of predetermined shape and size on the surface of the silicon wafer helps to improve the beam steering and mode control of the filter. However, when the cavity structure is formed only by dry film, the dry film itself is weak in strength and can withstand less pressure, so it may collapse during the module packaging process, which may cause quality problems in the filter. Summary of the invention

[0005] To solve the above problems, the present disclosure provides a thin film surface acoustic wave filter and a packaging method. By selecting a second wafer instead of a dry film to form a cavity, the filter can withstand a greater pressure during subsequent module assembly, thereby ensuring the quality of the filter.

[0006] A first aspect of the present disclosure provides a thin film surface acoustic wave filter, the filter comprising: a first wafer, the first wafer comprising a first substrate layer and an electrode layer, the electrode layer being arranged on the first substrate layer;

[0007] A second wafer is arranged on one side of the first wafer, the second wafer includes a second substrate layer and a bonding layer, the bonding layer is arranged on the second substrate layer, the bonding layer is bonded to the electrode layer, the bonding layer surrounds and forms a sealed cavity between the first wafer and the second wafer, and a partial surface of the electrode layer of the first wafer and a partial surface of the second substrate layer of the second wafer are exposed in the sealed cavity.

[0008] In this way, the second wafer is bonded to the electrode layer of the first wafer through the bonding layer, and the bonding layer is formed in a sealed cavity between the first wafer and the second wafer, which helps to improve transmission efficiency and filtering accuracy. The cavity formed by the existing dry film is replaced by the second wafer, thereby reducing the area occupied by the original dry film, realizing the miniaturization of the filter, and then increasing the stability of the cavity structure, which helps the first wafer in the module packaging type to withstand greater pressure and reduce collapse during the module packaging process, thereby ensuring the quality of the filter.

[0009] In some embodiments, a via is formed on a side of the first wafer facing away from the second wafer, and the electrode layer of the first wafer is exposed through the via.

[0010] This arrangement allows the first wafer to be electrically connected to an external device through the via hole.

[0011] In some embodiments, a metal layer is provided on a side of the first wafer facing away from the second wafer, and the metal layer is provided along the surface of the first wafer, the surface of the via hole wall, and the surface where the electrode layer is exposed in the via hole, and the metal layer contacts the electrode layer through the via hole.

[0012] Such arrangement enables the metal layer to form a reflective delay line on the first wafer, thereby increasing the selectivity of the filter and thus improving the quality of the received signal.

[0013] In some embodiments, a protection layer is provided on a side of the first wafer facing away from the second wafer, and the protection layer covers the metal layer and the via hole.

[0014] Such configuration can protect the first wafer and help reduce the damage to the first wafer caused by electrostatic discharge generated by other components in the circuit during use.

[0015] In some embodiments, a plurality of conductive balls are disposed on a side of the protective layer facing away from the first wafer, and the conductive balls are disposed in contact with the protective layer and the metal layer avoiding the via holes.

[0016] Such an arrangement enables the conductive ball to contact the electrode layer through the metal layer, thereby achieving efficient coupling between the acoustic wave signal and the electrical signal, so that the electrode layer can be electrically connected to an external device through the conductive ball.

[0017] The second aspect of the present disclosure provides a thin-film surface acoustic wave filter packaging method, which is applicable to the thin-film surface acoustic wave filter described in the first aspect, and the packaging method comprises: obtaining a first wafer, the first wafer comprising a first substrate layer and an electrode layer, and the electrode layer is arranged on the first substrate layer; obtaining a second wafer, the second wafer comprising a second substrate layer and a bonding layer, and the bonding layer is arranged on the second substrate layer; bonding the second wafer to the first wafer, the bonding layer bonding to the electrode layer, the bonding layer surrounding the first wafer and the second wafer to form a sealed cavity, and a partial surface of the electrode layer of the first wafer and a partial surface of the second substrate layer of the second wafer are exposed in the sealed cavity.

[0018] In the present disclosure, the first wafer and the second wafer are bonded using a wafer-level packaging method, and the sealed cavity formed by the second wafer on the first wafer is used to replace the cavity formed by the dry film, so that a greater pressure can be withstood during the subsequent module assembly, and the stability of the cavity structure is increased, which helps the first wafer in the module packaging type to withstand a greater pressure. At the same time, due to the high strength of the cavity structure of the first wafer, only a circle of dry film is required around the edge of the first wafer, replacing the original two-layer dry film structure, which helps to achieve the miniaturization of the thin film surface acoustic wave filter.

[0019] In some embodiments, the packaging method further includes: forming a via hole on a side of the first wafer facing away from the second wafer, wherein the via hole exposes the electrode layer of the first wafer.

[0020] With such arrangement, a hole in the form of a via hole is formed inside the first wafer, so as to facilitate electrical connection between wafers or between a wafer and an external device through the hole.

[0021] In some embodiments, the opening of a via on the side of the first wafer facing away from the second wafer includes: forming a metal layer on the side of the first wafer facing away from the second wafer, the metal layer being arranged along the surface of the first wafer, the surface of the via hole wall, and the surface where the electrode layer is exposed in the via, and the metal layer is in contact with the electrode layer through the via.

[0022] With such a configuration, the metal layer can be composed of metal lines, capacitors and inductors, which are mainly used to delay signals and reflect signals to increase filter selectivity. It can also be used for interconnection between wafers or between wafers and external devices.

[0023] In some embodiments, forming the metal layer on the side of the first wafer facing away from the second wafer includes: forming a protective layer on the side of the first wafer facing away from the second wafer, wherein the protective layer covers the metal layer and the via.

[0024] With such configuration, the first wafer is protected by the protective layer to reduce damage to the first wafer.

[0025] In some embodiments, forming a protective layer on a side of the first wafer facing away from the second wafer includes: forming a plurality of conductive balls on a side of the protective layer facing away from the first wafer, wherein the conductive balls are arranged away from the via holes.

[0026] By configuring in this way, adding a layer of conductive balls on the first wafer can improve the coupling efficiency between the metal layer and the electrode layer, thereby improving the performance of the filter.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] By using a second wafer to replace the dry film to form a cavity, the area occupied by the original dry film is reduced, the filter can be miniaturized, and the stability of the cavity structure is increased. It can withstand greater pressure during subsequent module assembly, thereby ensuring the quality of the filter.

[0029] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The purpose and other advantages of the present disclosure can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 It is a top view schematic diagram of wafer and chip dry film bonding to silicon wafer in the prior art;

[0032] Figure 2 A schematic top view of a second wafer provided by the present disclosure;

[0033] Figure 3 A schematic cross-sectional view of a thin film surface acoustic wave filter provided by the present disclosure;

[0034] Figure 4 A schematic diagram of a packaging method for a thin film surface acoustic wave filter provided by the present invention;

[0035] Figure 5 A flow chart of structural changes in bonding between a first wafer and a second wafer provided in the present disclosure;

[0036] Figure 6 A flow chart of structural changes of opening holes and implanting balls on a first wafer provided in the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0038] The following is a brief introduction to some concepts that may be involved in the embodiments of the present disclosure.

[0039] Dry film: relative to wet film, dry film is a polymer material that can produce a polymerization reaction after being irradiated by ultraviolet rays to form a stable substance attached to the board surface, thereby achieving the function of blocking electroplating and etching.

[0040] Thin film surface acoustic wave filter: A metal film is evaporated on a substrate with piezoelectric effect, and two groups of cross-finger metal electrodes with energy conversion function are made through photolithography, which are called input interdigital transducer and output interdigital transducer respectively. When the input interdigital transducer is connected to an AC voltage signal, the surface of the piezoelectric crystal substrate vibrates and excites sound waves with the same frequency as the external signal. This sound wave mainly propagates along the surface of the substrate and the direction where the interdigital metal electrodes rise, so it is called surface acoustic wave filtering. The sound waves in one direction are absorbed by the divisor sound-absorbing material, and the sound waves in the other direction are transmitted to the output interdigital transducer and converted into electrical signals for output.

[0041] Wafer Level Chip Scale Packaging (WLCSP): A miniaturized integrated circuit packaging technology that packages the entire chip directly on a single silicon wafer instead of placing the chip in an external package as is traditionally done.

[0042] In the existing wafer-level chip packaging process, refer to Figure 1 , Figure 1 It is a top view schematic diagram of wafer and chip dry film bonding silicon wafer in the prior art, and the dry film is Figure 1 The two strips side by side in the figure indicate that two layers of dry film are bonded to the silicon wafer to create a cavity structure of predetermined shape and size. Such a cavity structure helps in the beam manipulation and mode control of the filter subsequently formed on the high-altitude silicon wafer.

[0043] Then, on the one hand, such two layers of dry film add a dry film wall in the wafer, which increases the volume of the wafer and thus increases the volume of the wafer chip; on the other hand, when the cavity structure is formed only by dry film, since the dry film itself is weak in strength and withstands less pressure, it may collapse during the module packaging process, which may cause quality problems in the filter.

[0044] To this end, the present disclosure provides a thin film surface acoustic wave filter 1000, see Figure 2 and Figure 3 , Figure 2 is a schematic top view of a second wafer provided in the present disclosure, Figure 3 A schematic cross-sectional view of a thin film surface acoustic wave filter provided by the present disclosure. The filter includes a first wafer 100 and a second wafer 200. The first wafer 100 includes a first substrate layer 110 and an electrode layer 120. The electrode layer 120 is disposed on a side of the first substrate layer 110 close to the second wafer 200. The second wafer 200 is disposed on one side of the first wafer 100 in the thickness direction. The second wafer 200 includes a second substrate layer 210 and a bonding layer 220. The bonding layer 220 is disposed on the second substrate layer 210. The bonding layer 220 is bonded to the electrode layer 120. The bonding layer 220 surrounds the space between the first wafer 100 and the second wafer 200 and forms a sealed cavity 300. Part of the surface of the electrode layer 120 of the first wafer 100 and part of the surface of the second substrate layer 210 of the second wafer 200 are exposed in the sealed cavity 300.

[0045] In the present disclosure, the bonding layer 220 on the second substrate layer 210 of the second wafer 200 is hollow and forms a circle around the edge of the second wafer 200 so as to form a hollow space on the second wafer 200, which helps the bonding layer 220 to form a sealed cavity 300 between the second wafer 200 and the first wafer 100.

[0046] For example, the bonding layer 220 includes a dry film made of organic materials such as polyimide Pi, benzocyclobutene (BCB), epoxy resin, etc. Figure 2The circular dry film around the upper surface of the second substrate layer 210 is shown in the figure, so that a hollow space is formed on the upper surface of the second wafer 200 by surrounding the dry film in a circle. On the one hand, the dry film in a circle in the second wafer 200 replaces the existing two-layer dry film structure, reducing the area occupied by the original dry film and realizing the miniaturization of the filter. On the other hand, since only two layers of dry film are used for support in the module packaging process in the prior art, and the present embodiment is supported by the dry film in the second wafer 200 and the second substrate 210, the dry film in a circle in the second wafer 200 can increase the stability of the sealed cavity 300, which helps the first wafer 100 to withstand greater pressure during module packaging, and reduces the collapse in the module packaging process, thereby ensuring the quality of the filter.

[0047] For example, the second substrate layer 210 is a high-resistance silicon substrate 1101, glass or other materials, and the thickness of the second substrate layer 210 may be 675 μm, and the thickness of the bonding layer 220 may be 20 μm.

[0048] In some embodiments, Figure 3 As shown, the first wafer 100 is bonded on the second wafer 200, the first substrate layer 110 is far away from the second substrate layer 210, and the electrode layer 120 is close to the second substrate layer 210 and bonded to the bonding layer 220. The first substrate layer 110 includes a silicon substrate 1101, polysilicon 1102 (Poly-sil icon), a low temperature oxide layer (Low Temperature, LT), and silicon dioxide 1103 stacked in sequence in the direction close to the electrode layer 120. The LT layer is not shown in the figure. The electrode layer 120 includes an aluminum gasket 121 and a forked electrode 122, wherein the aluminum gasket 121 is located on both sides of the forked electrode 122, and the forked electrode 122 is located in the sealed cavity 300 surrounded by the bonding layer 220, and the aluminum gasket 121 is bonded to the bonding layer 220 formed by the dry film.

[0049] Exemplarily, the thickness of the silicon substrate 1101 may be 675 μm, the thickness of the polycrystalline silicon 1102 (Poly Si) may be 1 μm, the thickness of the silicon dioxide 1103 may be 0.5 μm, the thickness of the LT layer may be 0.6 μm, the thickness of the aluminum spacer 121 may be 2 μm, and the thickness of the interdigital electrode 122 may be 0.5 μm.

[0050] In some embodiments, a via 111 is provided on a side of the first wafer 100 facing away from the second wafer 200, and the via 111 exposes the electrode layer 120 of the first wafer 100. The via 111 penetrates the surface of the first substrate layer 110 facing away from the electrode layer 120, so as to expose the aluminum pad 121 in the electrode layer 120, and further facilitate electrical connection with external devices through the exposed aluminum pad 121.

[0051] Exemplarily, the opening of the via 111 away from the aluminum gasket 121 is larger than the opening close to the aluminum gasket 121, so that the opening of the via 111 in the first substrate layer 110 gradually expands in the direction away from the aluminum gasket 121, which can reduce the reflection of sound waves at the edge of the via 111, reduce the insertion loss of the filter, and improve signal integrity.

[0052] In some embodiments, a metal layer 112 is provided on the side of the first wafer 100 facing away from the second wafer 200. The metal layer 112 is provided along the surface of the first wafer 100, the surface of the wall of the via hole 111, and the surface where the electrode layer 120 is exposed in the via hole 111. The metal layer 112 contacts the electrode layer 120 through the via hole 111, so that the aluminum gasket 121 in the via hole 111 can be electrically connected to an external device through the metal layer 112 on the side of the first substrate layer 110 facing away from the second substrate layer 210. On the other hand, a reflective delay line is formed on the first wafer 100 to increase the selectivity of the filter, thereby improving the quality of the received signal.

[0053] For example, the metal layer 112 may include titanium and copper metals. The combination of copper and titanium can achieve good acoustic coupling, which is beneficial to the effective propagation of sound waves.

[0054] In some embodiments, a protective layer 113 is provided on the side of the first wafer 100 facing away from the second wafer 200, and the protective layer 113 covers the metal layer 112 and the via 111. The protective layer 113 protects the metal layer 112 and the via 111, thereby protecting the first wafer 100 and reducing damage to the first wafer 100.

[0055] Exemplarily, the protection layer 113 includes polyimide Pi to increase the high heat resistance and chemical stability of the first wafer 100 .

[0056] In some embodiments, a plurality of conductive balls 114 are provided on a side of the protective layer 113 facing away from the first wafer 100. The conductive balls 114 avoid the vias 111, and the conductive balls pass through the protective layer 113 to contact the metal layer 112. The conductive balls 114 are located on the surface of the first substrate between the vias 111, so as to avoid the vias 111 and the conductive balls 114 are formed on the metal layer 112, and pass through the protective layer 113, so that the conductive balls 114 are electrically connected to the aluminum pads 121 through the metal layer 112.

[0057] Exemplarily, the conductive balls 114 include solder balls, which are formed by applied solder paste so as to solder the first wafer 100 , thereby facilitating the electrical connection of the filter with external devices through the conductive balls 114 .

[0058] Based on the contents described in the above embodiments, the present disclosure also provides a packaging method for a thin film surface acoustic wave filter 1000. Figure 4 , Figure 4 FIG. 1 is a flow chart of a packaging method of a thin film surface acoustic wave filter 1000 provided in the present disclosure, as shown in FIG. Figure 5-Figure 6 As shown, Figure 5 The structural change flow chart of the bonding between the first wafer 100 and the second wafer 200 provided in the present disclosure is as follows: Figure 6 A flow chart of structural changes of opening holes and implanting balls on the first wafer 100 provided in the present disclosure.

[0059] The packaging method of the embodiment of the present disclosure includes:

[0060] S1. Obtain a first wafer 100.

[0061] In this embodiment, see Figure 4 and Figure 5 (a), the first wafer 100 includes a first substrate layer 110 and an electrode layer 120. The electrode layer 120 is disposed on the first substrate layer 110. The first substrate layer 110 includes a silicon substrate 1101, polysilicon 1102 (Poly Si), a low temperature oxide layer (Low Temperature, LT), and silicon dioxide 1103 stacked in sequence. The LT layer is not shown in the figure. The electrode layer 120 includes an aluminum pad 121 and a forked electrode 122, wherein the aluminum pad 121 is located on both sides of the forked electrode 122.

[0062] S2. Obtain a second wafer 200.

[0063] In this embodiment, see Figure 4 and Figure 5 (b), the second wafer 200 includes a second substrate layer 210 and a bonding layer 220, and the bonding layer 220 is arranged on the periphery of the second substrate layer 210; the second substrate layer 210 is a high-resistance silicon substrate 1101, glass and other materials, and the bonding layer 220 includes a dry film, and the material is polyimide Pi, epoxy resin and other organic materials.

[0064] It can be understood that a dry film (made of polyimide) is first laminated on the bare wafer of the second wafer 200, and then patterned after exposure and development to expose the interdigitated electrode 122 area of ​​the first wafer 100, so that the interdigitated electrode 122 and a portion of the surface of the second substrate layer 210 are located within the sealed cavity 300.

[0065] S3 , bonding the second wafer 200 and the first wafer 100 .

[0066] In this embodiment, see Figure 4 and Figure 5(c) The first wafer 100 and the second wafer 200 are bonded together through a dry film using a wafer-level bonding device (temperature 250° C., pressure 5000 N), that is, the aluminum gasket 121 is bonded to the dry film of the bonding layer 220 .

[0067] S4 , forming a via hole 111 on a side of the first wafer 100 facing away from the second wafer 200 .

[0068] In this embodiment, see Figure 4 and Figure 6 (a), first use a grinder to grind the first wafer 100 to a target thickness of 100 μm; then use exposure and puddle development to expose the via 111 area, use a dry etcher to etch away the silicon in the exposed area of ​​the first wafer 100 facing away from the second wafer 200, then perform oxide etching to remove silicon dioxide 1103, and finally remove the photoresist on the surface of the first wafer 100 to form the via 111. Oxide etching usually uses a specific chemical solution or plasma, which can selectively dissolve oxides without affecting the underlying materials.

[0069] S5 , forming a metal layer 112 on a side of the first wafer 100 facing away from the second wafer 200 .

[0070] In this embodiment, see Figure 4 and Figure 6 (b) First, titanium and copper metals are deposited on the surface of the first wafer 100, and the metal parts determined based on the mask positioning image are etched away by exposure and development to expose part of the surface of the first wafer 100 for subsequent ball planting; then, wet etching solutions of Cu and Ti are used for wet removal to interconnect the flat areas (pads) on the first wafer 100 through the metal layer 112.

[0071] Metal layer 112 is also called redistribution layer (RDL). At the wafer level, contact redistribution can be performed very efficiently. The redistribution layer is used to re-plan the connection path and obtain a higher contact density. The redistribution process actually adds one or more layers to the original wafer.

[0072] S6 . Form a protection layer 113 and a plurality of conductive balls 114 on a side of the first wafer 100 facing away from the second wafer 200 .

[0073] In this embodiment, see Figure 6(c) and (d), polyimide Pi photoresist is coated on the first wafer 100, and a protective layer 113 (Passivation) is formed by exposure, development, and baking. Finally, ball planting and reflow are performed, firstly, the ball is planted on the UBM surface by a ball planting machine, and then the flux is cleaned to form solder balls, where UBM (Under-Bump Metallization) refers to the bottom metallization process, which is usually used to form electrical contact points between chips (integrated circuits) and external connectors.

[0074] S7. Grind and cut the entire wafer body.

[0075] In this embodiment, the participants Figure 4 and Figure 6 The second wafer 200 is thinned to 70-100 μm on the back side away from the first wafer 100, and then cut to form dies. A die is a small piece on the wafer, which is a chip wafer body, scientifically known as a die, and becomes a particle after packaging.

[0076] Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A thin film surface acoustic wave filter, characterized in that: The filter comprises: A first wafer, wherein the first wafer comprises a first substrate layer and an electrode layer, wherein the electrode layer is disposed on the first substrate layer; A second wafer is arranged on one side of the first wafer, the second wafer includes a second substrate layer and a bonding layer, the bonding layer is arranged on the second substrate layer, the bonding layer is bonded to the electrode layer, the bonding layer surrounds and forms a sealed cavity between the first wafer and the second wafer, and a partial surface of the electrode layer of the first wafer and a partial surface of the second substrate layer of the second wafer are exposed in the sealed cavity.

2. The thin film surface acoustic wave filter according to claim 1, characterized in that: A via is provided on a side of the first wafer facing away from the second wafer, and the electrode layer of the first wafer is exposed through the via.

3. The thin film surface acoustic wave filter according to claim 2, characterized in that: A metal layer is provided on the side of the first wafer facing away from the second wafer. The metal layer is provided along the surface of the first wafer, the wall surface of the via hole and the surface where the electrode layer is exposed in the via hole. The metal layer contacts the electrode layer through the via hole.

4. The thin film surface acoustic wave filter according to claim 3, characterized in that: A protective layer is provided on a side of the first wafer facing away from the second wafer, and the protective layer covers the metal layer and the via hole.

5. The thin film surface acoustic wave filter according to claim 4, characterized in that: A plurality of conductive balls are arranged on a side of the protective layer facing away from the first wafer, and the conductive balls are arranged to contact the protective layer and the metal layer avoiding the via holes.

6. A method for packaging a thin film surface acoustic wave filter, applicable to the thin film surface acoustic wave filter according to claims 1-5, characterized in that: The packaging method comprises: Obtaining a first wafer, wherein the first wafer comprises a first substrate layer and an electrode layer, wherein the electrode layer is disposed on the first substrate layer; Obtaining a second wafer, wherein the second wafer comprises a second substrate layer and a bonding layer, wherein the bonding layer is disposed on the second substrate layer; The second wafer is bonded to the first wafer, the bonding layer is bonded to the electrode layer, the bonding layer surrounds and forms a sealed cavity between the first wafer and the second wafer, and a partial surface of the electrode layer of the first wafer and a partial surface of the second substrate layer of the second wafer are exposed in the sealed cavity.

7. The packaging method according to claim 6, characterized in that: The packaging method further comprises: A via hole is formed on a side of the first wafer facing away from the second wafer, and the electrode layer of the first wafer is exposed through the via hole.

8. The packaging method according to claim 7, characterized in that: The step of opening a via hole on a side of the first wafer facing away from the second wafer comprises: A metal layer is formed on the side of the first wafer facing away from the second wafer. The metal layer is arranged along the surface of the first wafer, the wall surface of the via hole and the surface where the electrode layer is exposed in the via hole. The metal layer contacts the electrode layer through the via hole.

9. The packaging method according to claim 8, characterized in that: The forming of a metal layer on a side of the first wafer facing away from the second wafer comprises: A protection layer is formed on a side of the first wafer facing away from the second wafer, wherein the protection layer covers the metal layer and the via hole.

10. The packaging method according to claim 9, characterized in that: The forming of a protective layer on a side of the first wafer facing away from the second wafer comprises: A plurality of conductive balls are formed on a side of the protection layer facing away from the first wafer, and the conductive balls are arranged away from the via holes.

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