A self-recovering single-event multi-bit flip-over resistant latch circuit structure

Abstract

The present invention discloses a self-recovering single-particle multi-bit upset resistant latch circuit structure, comprising: a clock-controlled inverter circuit, a latch unit, an SEU monitoring unit, an output control unit, and an inverter circuit. The output of the first clock-controlled inverter circuit is connected to the input of the first latch unit and the input of the SEU monitoring unit; the output of the second clock-controlled inverter circuit is connected to the input of the first latch unit and the input of the SEU monitoring unit; the output of the first latch unit is connected to the input of the SEU monitoring unit and the input of the output control unit; the output of the third clock-controlled inverter circuit and the fourth clock-controlled inverter circuit are respectively connected to the two inputs of the second latch unit; the output of the second latch unit is connected to the input of the output control unit; and the output of the SEU monitoring unit is connected to the input of the output control unit. The present invention has good single-particle hardening capabilities and can achieve hardening against single-particle multi-bit upsets.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and in particular relates to a self-recovering single-particle resistant multi-bit flip latch circuit structure. Background Art

[0002] A single-event upset (SEU) occurs when a sensitive area of ​​an integrated circuit device is bombarded by a single high-energy particle, causing the device's logic state to flip. SEUs primarily occur in sequential circuits. When a high-energy particle strikes a sensitive node in a sequential circuit, the charged particle interacts with the semiconductor material, generating electron-hole pairs. These carriers, influenced by concentration gradients and electric fields, migrate and accumulate at the sensitive node. When these charge carriers reach a certain level, they alter the voltage level at the node, changing the storage state of the sequential circuit, resulting in a single-event upset. The erroneous data generated by a SEU can lead to incorrect instructions and system dysfunction, potentially causing catastrophic failures.

[0003] Latch circuits are one of the most fundamental elements in integrated circuit design, and their inherent radiation hardening is crucial and important. With decreasing process geometries, issues such as reduced charge storage at sensitive nodes and the presence of single-event incident trajectories across multiple devices are impacting the IC's ability to withstand single-event upsets (SEEs). Consequently, radiation hardening technologies to combat SEEs are becoming a key research focus.

[0004] Currently, widely used circuit structures to improve SEE resistance, such as DICE, triple-mode redundancy, and transistor stacking, have proven effective in combating SEE. However, with advancements in process technology and shrinking device sizes, the reinforcement effectiveness of these structures has become increasingly poor, making them inadequate for SEE multi-bit upsets. They are therefore unsuitable for SEE hardening under advanced nanotechnology. Summary of the Invention

[0005] The technology of the present invention solves the problem: overcomes the shortcomings of the existing technology, provides a self-recovering single-particle multi-bit upset resistant latch circuit structure, and aims to achieve multi-bit single-particle upset resistance reinforcement.

[0006] In order to solve the above technical problems, the present invention discloses a self-recovering single-event multi-bit upset resistant latch circuit structure, comprising: a clock-controlled inverter circuit, a latch unit, an output control unit, an SEU monitoring unit and an inverter circuit; wherein the clock-controlled inverter circuit comprises: a first clock-controlled inverter circuit, a second clock-controlled inverter circuit, a third clock-controlled inverter circuit and a fourth clock-controlled inverter circuit; the latch unit comprises: a first latch unit and a second latch unit;

[0007] An output terminal of the first clock-controlled inverter circuit is connected to an input terminal in1 of the first latch unit and an input terminal in1 of the SEU monitoring unit;

[0008] An output terminal of the second clock-controlled inverter circuit is connected to an input terminal in2 of the first latch unit and an input terminal in3 of the SEU monitoring unit;

[0009] An output terminal of the third clock-controlled inverter circuit is connected to an input terminal in1 of the second latch unit;

[0010] An output terminal of the fourth clock-controlled inverter circuit is connected to an input terminal in2 of the second latch unit;

[0011] The output terminal out1 of the first latch unit is connected to the input terminal in1 of the output control unit and the input terminal in2 of the SEU monitoring unit; the output terminal out2 of the first latch unit is connected to the input terminal in4 of the SEU monitoring unit;

[0012] The output terminal out1 of the second latch unit is connected to the input terminal in2 of the output control unit;

[0013] The output terminal S1 and the output terminal S1N of the SEU monitoring unit are connected to the input terminal S1 and the input terminal S1N of the output control unit respectively;

[0014] The inverter circuit is used to provide a clock signal CK1 and a clock signal CK2 to the clock control inverter circuit, the latch unit and the SEU monitoring unit.

[0015] In the above-mentioned self-recovery single-event multi-bit upset resistant latch circuit structure, the inverter circuit includes: a first inverter circuit and a second inverter circuit; wherein the first inverter circuit and the second inverter circuit are connected in series; the first inverter circuit is used to provide a clock signal CK1 for the clock-controlled inverter circuit, the latch unit and the SEU monitoring unit; the second inverter circuit is used to provide a clock signal CK2 for the clock-controlled inverter circuit, the latch unit and the SEU monitoring unit.

[0016] In the above-mentioned self-recovery single-event resistant multi-bit flip latch circuit structure, the input end of the first inverter circuit is connected to the input clock signal CLK; the first inverter circuit outputs the clock signal CK1, and the second inverter circuit outputs the clock signal CK2; wherein, the clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is the inverted signal of the clock signal CLK, and the clock signal CK2 is the inverted signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of the data signal in the latch circuit.

[0017] In the above self-recovery single-event multi-bit upset latch circuit structure, the clock-controlled inverter circuit is an inverter circuit controlled by a set of complementary clock signals, including: a PMOS transistor P21, a PMOS transistor P22, an NMOS transistor N22 and an NMOS transistor N21;

[0018] The PMOS transistor P21, the PMOS transistor P22, the NMOS transistor N22 and the NMOS transistor N21 are connected in series in sequence;

[0019] The gate of the PMOS transistor P22 is connected to the clock signal CK2;

[0020] The gate of the NMOS transistor N22 is connected to the clock signal CK1;

[0021] The gate of the PMOS transistor P21 and the gate of the NMOS transistor N21 serve together as the input end of the clock control inverter circuit for receiving an input signal.

[0022] In the above-mentioned self-recovery single-event multi-bit upset resistant latch circuit structure, the latch unit is a DICE structure, including: inverter D31, inverter D32, inverter D33 and inverter D34; wherein, inverter D31 includes: PMOS transistor P31 and NMOS transistor N31 connected in series; inverter D32 includes: PMOS transistor P32, PMOS transistor P33, NMOS transistor N33 and NMOS transistor N32 connected in series in sequence; inverter D33 includes: PMOS transistor P34 and NMOS transistor N34 connected in series; inverter D34 includes: PMOS transistor P35, PMOS transistor P36, NMOS transistor N36 and NMOS transistor N35 connected in series in sequence;

[0023] The input signal in1 is connected to the drain of the PMOS transistor P33, the drain of the NMOS transistor N33, the gate of the PMOS transistor P34 and the gate of the NMOS transistor N31;

[0024] The input signal in2 is connected to the drain of the PMOS transistor P36, the drain of the NMOS transistor N36, the gate of the PMOS transistor P31 and the gate of the NMOS transistor N34;

[0025] The output signal out1 is connected to the drain of the PMOS transistor P34, the drain of the NMOS transistor N34, the gate of the PMOS transistor P35 and the gate of the NMOS transistor N32;

[0026] The output signal out2 is connected to the drain of the PMOS transistor P31, the drain of the NMOS transistor N31, the gate of the PMOS transistor P32, and the gate of the NMOS transistor N35;

[0027] The gates of the PMOS transistor P33 and the PMOS transistor P36 are connected to the clock signal CK1;

[0028] The gates of the NMOS transistor N33 and the NMOS transistor N36 are connected to the clock signal CK2.

[0029] In the above-mentioned self-recovery single-event multi-bit flip-proof latch circuit structure, the output control unit includes: an inverter D41, an inverter D42, and an inverter D43; wherein the inverter D41 includes: a PMOS transistor P41, a PMOS transistor P42, an NMOS transistor N42, and an NMOS transistor N41 connected in series in sequence; the inverter D42 includes: a PMOS transistor P43, a PMOS transistor P44, an NMOS transistor N44, and an NMOS transistor N43 connected in series in sequence; the inverter D43 includes: a PMOS transistor P45 and an NMOS transistor N45 connected in series;

[0030] The input signal in1 is connected to the gate of the PMOS transistor P41 and the gate of the NMOS transistor N41;

[0031] The input signal in2 is connected to the gate of the PMOS transistor P43 and the gate of the NMOS transistor N43;

[0032] The gate of the PMOS transistor P42 and the gate of the NMOS transistor N44 are connected to the input control signal S1;

[0033] The gate of the NMOS transistor N42 and the gate of the PMOS transistor P44 are connected to the input control signal S1N;

[0034] The output end of the inverter D41 and the output end of the inverter D42 are commonly connected to the input end of the inverter D43;

[0035] The output terminal of the inverter D43 serves as the output terminal out of the output control unit.

[0036] In the above-mentioned self-recovery single-event multi-bit flip-resistant latch circuit structure, for the output control unit, when the input control signal S1 is a low level "0" and the input control signal S1N is a high level "1", the PMOS transistor P42 and the NMOS transistor N42 are in the on state, the PMOS transistor P44 and the NMOS transistor N44 are in the off state, and the state of the input signal in1 is transmitted to the output terminal out through the inverter D41 and the inverter D43; conversely, when the input control signal S1 is a high level "1" and the input control signal S1N is a low level "0", the PMOS transistor P42 and the NMOS transistor N42 are in the off state, the PMOS transistor P44 and the NMOS transistor N44 are in the on state, and the state of the input signal in2 is transmitted to the output terminal out through the inverter D42 and the inverter D43.

[0037] In the above self-recovery single-event multi-bit upset latch circuit structure, the SEU monitoring unit includes: an exclusive OR gate XOR1, an exclusive OR gate XOR2, an exclusive OR gate XOR3, an inverter D51, an inverter D52, an inverter D53, an inverter D54, an inverter D55, an inverter D56 and an OR gate OR1; wherein the inverter D51 includes: a PMOS transistor P51, an NMOS transistor N51 and an NMOS transistor N53; the drain of the PMOS transistor P51, the drain of the NMOS transistor N51 and the drain of the NMOS transistor N53 serve as the output end of the inverter D51; the inverter D52 includes: a PMOS transistor P51, an NMOS transistor N51 and an NMOS transistor N53; the drain of the PMOS transistor P51, the drain of the NMOS transistor N51 and the drain of the NMOS transistor N53 serve as the output end of the inverter D51; 2. NMOS transistor N52 and NMOS transistor N54; the drain of PMOS transistor P52, the drain of NMOS transistor N52, and the drain of NMOS transistor N54 collectively serve as the output end of inverter D52; inverter D53 includes: PMOS transistor P55, PMOS transistor P56, NMOS transistor N56, and NMOS transistor N55 connected in series in sequence; inverter D54 includes: PMOS transistor P57 and NMOS transistor N57 connected in series; inverter D55 includes: PMOS transistor P58 and NMOS transistor N58 connected in series; inverter D56 includes: PMOS transistor P59 and NMOS transistor N59 connected in series;

[0038] Input signals in1 and in2 are connected to the two input terminals of the XOR gate XOR1 respectively; the output terminal of the XOR gate XOR1 is connected to the input terminal of the inverter D51, that is, the gate of the PMOS transistor P51;

[0039] Input signals in3 and in4 are connected to the two input terminals of the XOR gate XOR2 respectively; the output terminal of the XOR gate XOR2 is connected to the input terminal of the inverter D52, that is, the gate of the PMOS transistor P52;

[0040] The input signals in2 and in4 are connected to the two input terminals of the exclusive OR gate XOR3 respectively;

[0041] The output terminal of the inverter D51 is connected to the gate of the PMOS transistor P55 and the gate of the NMOS transistor N55;

[0042] The output terminal of the inverter D52 is connected to the gate of the PMOS transistor P56 and the gate of the NMOS transistor N56;

[0043] The output end of the inverter D53 and the output end of the XOR gate XOR3 are connected to the two input ends of the OR gate OR1 respectively; in addition, the output end of the inverter D53 is connected to the input end of the inverter D54;

[0044] The output terminal of the inverter D54 is connected to the gate of the NMOS transistor N51 and the gate of the NMOS transistor N52;

[0045] The output terminal of the OR gate OR1 is connected to the gate of the PMOS tube P58;

[0046] The gates of the NMOS transistor N53, N54, and N58 serve as the clock input terminal of the SEU monitoring unit, and are used to receive the clock signal CK1.

[0047] Inverter D55 outputs a control signal S1 , and inverter D56 outputs a control signal S1N. The control signal S1 and the control signal S1N are complementary signals, that is, the signal S1N is an inverted signal of the signal S1 .

[0048] In the above-mentioned self-recovery single-event multi-bit flip-flop latch circuit structure, for the SEU monitoring unit, when the clock signal CK1 is at a high level "1", the NMOS transistor N53, the NMOS transistor N54 and the NMOS transistor N58 are in the on state, the output control signal S1 remains at a low level "0", and the output control signal S1N remains at a high level "1". At this time, the SEU monitoring unit is in a functionally disabled state; when the clock signal CK1 is at a low level "0", the NMOS transistor N53, the NMOS transistor N54 and the NMOS transistor N58 are in a disabled state, and the SEU monitoring unit function is enabled.

[0049] In the above-mentioned self-recovering single-event multi-bit upset resistant latch circuit structure, the latch adopts a combination of circuit reinforcement technology and layout reinforcement technology to achieve single-event upset resistant reinforcement of internal nodes.

[0050] The present invention has the following advantages:

[0051] (1) The present invention discloses a self-recovering single-particle upset resistant multi-bit latch circuit structure, which determines whether an irreversible single-particle upset occurs in a latch unit through an SEU monitoring unit. If so, the output control unit circuit automatically switches to a spare latch unit to achieve single-particle upset reinforcement.

[0052] (2) The present invention discloses a self-recovering single-particle multi-bit flip-resistant latch circuit structure, in which the latch unit has the ability to self-recover from soft errors and has a good reinforcement effect against single-particle flips occurring at a single node.

[0053] (3) The present invention discloses a self-recovering single-particle-resistant multi-bit flip latch circuit structure, which can achieve single-particle flip reinforcement of up to three nodes.

[0054] (4) The present invention discloses a self-recovering single-particle anti-flip multi-bit latch circuit structure, which adopts a combination of circuit design and layout design to achieve good reinforcement effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Schematic diagram of a self-recovering single-event multi-bit upset latch circuit structure in an embodiment of the present invention;

[0056] Figure 2 is a circuit structure diagram of a clock-controlled inverter circuit in an embodiment of the present invention;

[0057] Figure 3 is a circuit structure diagram of a latch unit in an embodiment of the present invention;

[0058] Figure 4 is a circuit structure diagram of an output control unit in an embodiment of the present invention;

[0059] Figure 5 This is a circuit structure diagram of an SEU monitoring unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments disclosed in the present invention will be described in further detail below with reference to the accompanying drawings.

[0061] The present invention discloses a self-recovering single-event multi-bit upset-resistant latch circuit structure, which primarily includes a clock-controlled inverter circuit, a latch unit, an output control unit, an SEU monitoring unit, and an inverter circuit. The latch unit has the ability to self-recover from soft errors. The SEU monitoring unit is used to monitor whether a single-event upset has occurred in the latch unit. The output control unit is used to control the on / off switching of the outputs of the two latch units based on the monitoring results of the SEU monitoring unit. The inverter circuit is used to invert the clock input signal CLK. The latch structure implemented by the present invention has strong single-event multi-bit upset resistance.

[0062] like Figure 1As shown, in this embodiment, the self-recovering single event multi-bit upset resistant latch circuit structure includes: a clocked inverter circuit, a latch unit, an output control unit 107, an SEU monitoring unit 108, and an inverter circuit. The clocked inverter circuit includes: a first clocked inverter circuit 101, a second clocked inverter circuit 102, a third clocked inverter circuit 103, and a fourth clocked inverter circuit 104; the latch unit includes: a first latch unit 105 and a second latch unit 106. The output terminal of the first clock-controlled inverter circuit 101 is connected to the input terminal in1 of the first latch unit 105 and the input terminal in1 of the SEU monitoring unit 108; the output terminal of the second clock-controlled inverter circuit 102 is connected to the input terminal in2 of the first latch unit 105 and the input terminal in3 of the SEU monitoring unit 108; the output terminal of the third clock-controlled inverter circuit 103 is connected to the input terminal in1 of the second latch unit 106; the output terminal of the fourth clock-controlled inverter circuit 104 is connected to the input terminal in2 of the second latch unit 106; the output terminal out1 of the first latch unit 105 is connected to the output control The input terminal in1 of the unit 107 and the input terminal in2 of the SEU monitoring unit 108; the output terminal out2 of the first latch unit 105 is connected to the input terminal in4 of the SEU monitoring unit 108; the output terminal out1 of the second latch unit 106 is connected to the input terminal in2 of the output control unit 107; the output terminal S1 and the output terminal S1N of the SEU monitoring unit 108 are respectively connected to the input terminal S1 and the input terminal S1N of the output control unit 107; the inverter circuit is used to provide clock signals CK1 and clock signals CK2 to the clock control inverter circuit, the latch unit and the SEU monitoring unit 108.

[0063] In this embodiment, the inverter circuit includes: a first inverter circuit 109 and a second inverter circuit 110. The first inverter circuit 109 and the second inverter circuit 110 are connected in series; the first inverter circuit 109 is used to provide a clock signal CK1 to the clock-controlled inverter circuit, the latch unit, and the SEU monitoring unit 108; and the second inverter circuit 110 is used to provide a clock signal CK2 to the clock-controlled inverter circuit, the latch unit, and the SEU monitoring unit 108.

[0064] Preferably, the input end of the first inverter circuit 109 is connected to the input clock signal CLK; the first inverter circuit 109 outputs the clock signal CK1, and the second inverter circuit 110 outputs the clock signal CK2; wherein, the clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is the inverted signal of the clock signal CLK, and the clock signal CK2 is the inverted signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of the data signal in the latch circuit.

[0065] In this embodiment, the clock-controlled inverter circuit is an inverter circuit controlled by a set of complementary clock signals. Figure 2 The clock-controlled inverter circuit includes a PMOS transistor P21, a PMOS transistor P22, an NMOS transistor N22, and an NMOS transistor N21. The PMOS transistors P21, PMOS transistor P22, NMOS transistor N22, and NMOS transistor N21 are connected in series. The gate of the PMOS transistor P22 is connected to the clock signal CK2; the gate of the NMOS transistor N22 is connected to the clock signal CK1. The gates of the PMOS transistor P21 and the NMOS transistor N21 serve as input terminals of the clock-controlled inverter circuit for receiving input signals.

[0066] In this embodiment, the latch unit is a DICE structure, which is composed of a pair of cross-coupled inverter structures and is mainly used to realize the function of storing data according to the timing signal. Figure 3 The latch unit includes an inverter D31, an inverter D32, an inverter D33, and an inverter D34. Inverter D31 includes a PMOS transistor P31 and an NMOS transistor N31 connected in series. Inverter D32 includes a PMOS transistor P32, a PMOS transistor P33, an NMOS transistor N33, and an NMOS transistor N32 connected in series. Inverter D33 includes a PMOS transistor P34 and an NMOS transistor N34 connected in series. Inverter D34 includes a PMOS transistor P35, a PMOS transistor P36, an NMOS transistor N36, and an NMOS transistor N35 connected in series. The input signal in1 is connected to the drain of the PMOS transistor P33, the drain of the NMOS transistor N33, the gate of the PMOS transistor P34, and the gate of the NMOS transistor N31; the input signal in2 is connected to the drain of the PMOS transistor P36, the drain of the NMOS transistor N36, the gate of the PMOS transistor P31, and the gate of the NMOS transistor N34; the output signal out1 is connected to the drain of the PMOS transistor P34, the drain of the NMOS transistor N34, the gate of the PMOS transistor P35, and the gate of the NMOS transistor N32; the output signal out2 is connected to the drain of the PMOS transistor P31, the drain of the NMOS transistor N31, the gate of the PMOS transistor P32, and the gate of the NMOS transistor N35; the gates of the PMOS transistor P33 and the PMOS transistor P36 are connected to the clock signal CK1; the gates of the NMOS transistor N33 and the NMOS transistor N36 are connected to the clock signal CK2.

[0067] Preferably, for the latch unit, when the clock signal CK1 is at a high level "1" and the clock signal CK2 is at a low level "0", the PMOS transistor P33, NMOS transistor N33, PMOS transistor P36, and NMOS transistor N36 are all in the off state. Because a cross-coupled inverter structure is not formed, a single-event bombardment of any single node within the latch unit will only generate a SET, not an SEU. When the clock signal CK1 is at a low level "0" and the clock signal CK2 is at a high level "1", the PMOS transistor P33, NMOS transistor N33, PMOS transistor P36, and NMOS transistor N36 are all in the on state, enabling the latching of the data signal.

[0068] Preferably, for the latch unit, when the clock signal CK1 is at a low level "0" and the clock signal CK2 is at a high level "1," the memory cell will only flip if the data of a pair of sensitive nodes are simultaneously changed. However, if the data of only one sensitive node is changed, the latch unit will not flip. The dual-mode redundant structure of the internal nodes enables self-recovery from soft errors and provides excellent reinforcement against single-event upsets at a single node.

[0069] Preferably, for the latch unit, combined with layout reinforcement technology, by increasing the distance between the sensitive node pair in1 and in2, or increasing the distance between the sensitive node pair out1 and out2, the probability of being simultaneously flipped is reduced, thereby achieving the purpose of enhancing resistance to single-event upsets.

[0070] In this embodiment, the output control unit has two data input terminals, two control signal input terminals and one data signal output terminal. Figure 4 As shown, the output control unit includes an inverter D41, an inverter D42, and an inverter D43. Inverter D41 includes a PMOS transistor P41, a PMOS transistor P42, an NMOS transistor N42, and an NMOS transistor N41 connected in series. Inverter D42 includes a PMOS transistor P43, a PMOS transistor P44, an NMOS transistor N44, and an NMOS transistor N43 connected in series. Inverter D43 includes a PMOS transistor P45 and an NMOS transistor N45 connected in series. The input signal in1 is connected to the gate of the PMOS transistor P41 and the gate of the NMOS transistor N41; the input signal in2 is connected to the gate of the PMOS transistor P43 and the gate of the NMOS transistor N43; the gate of the PMOS transistor P42 and the gate of the NMOS transistor N44 are connected to the input control signal S1; the gate of the NMOS transistor N42 and the gate of the PMOS transistor P44 are connected to the input control signal S1N; the output end of the inverter D41 and the output end of the inverter D42 are commonly connected to the input end of the inverter D43; the output end of the inverter D43 serves as the output end out of the output control unit.

[0071] Preferably, for the output control unit, when the input control signal S1 is a low level "0" and the input control signal S1N is a high level "1", the PMOS tube P42 and the NMOS tube N42 are in the on state, the PMOS tube P44 and the NMOS tube N44 are in the off state, and the state of the input signal in1 is transmitted to the output end out through the inverter D41 and the inverter D43; conversely, when the input control signal S1 is a high level "1" and the input control signal S1N is a low level "0", the PMOS tube P42 and the NMOS tube N42 are in the off state, the PMOS tube P44 and the NMOS tube N44 are in the on state, and the state of the input signal in2 is transmitted to the output end out through the inverter D42 and the inverter D43.

[0072] In this embodiment, the SEU monitoring unit has four data input terminals, one clock signal input terminal and two control signal output terminals. Figure 5As shown, the SEU monitoring unit includes: XOR gate XOR1, XOR gate XOR2, XOR gate XOR3, inverter D51, inverter D52, inverter D53, inverter D54, inverter D55, inverter D56 and OR gate OR1. Inverter D51 includes: PMOS transistor P51, NMOS transistor N51 and NMOS transistor N53; the drain of PMOS transistor P51, the drain of NMOS transistor N51 and the drain of NMOS transistor N53 serve as the output end of inverter D51; inverter D52 includes: PMOS transistor P52, NMOS transistor N52 and NMOS transistor N54; the drain of PMOS transistor P52, the drain of NMOS transistor N52 and the drain of NMOS transistor N54 serve as the output end of inverter D51. The drain electrodes serve together as the output end of the inverter D52; the inverter D53 includes: a PMOS transistor P55, a PMOS transistor P56, an NMOS transistor N56, and an NMOS transistor N55 connected in series in sequence; the inverter D54 includes: a PMOS transistor P57 and an NMOS transistor N57 connected in series; the inverter D55 includes: a PMOS transistor P58 and an NMOS transistor N58 connected in series; the inverter D56 includes: a PMOS transistor P59 and an NMOS transistor N59 connected in series. Input signals in1 and in2 are connected to the two input terminals of XOR gate XOR1 respectively; the output terminal of XOR gate XOR1 is connected to the input terminal of inverter D51, that is, the gate of PMOS transistor P51; input signals in3 and in4 are connected to the two input terminals of XOR gate XOR2 respectively; the output terminal of XOR gate XOR2 is connected to the input terminal of inverter D52, that is, the gate of PMOS transistor P52; input signals in2 and in4 are connected to the two input terminals of XOR gate XOR3 respectively; the output terminal of inverter D51 is connected to the gate of PMOS transistor P55 and the gate of NMOS transistor N55; the output terminal of inverter D52 is connected to the gate of PMOS transistor P56 and the gate of NMOS transistor N56; the output terminal of inverter D53 is connected to the gate of XOR gate XOR2; The output of OR gate XOR3 is connected to the two inputs of OR gate OR1 respectively. In addition, the output of inverter D53 is connected to the input of inverter D54. The output of inverter D54 is connected to the gates of NMOS transistor N51 and N52. The output of OR gate OR1 is connected to the gate of PMOS transistor P58. The gates of NMOS transistors N53, N54, and N58 serve as the clock input of the SEU monitoring unit for receiving clock signal CK1. Inverter D55 outputs control signal S1, and inverter D56 outputs control signal S1N. Control signal S1 and control signal S1N are complementary signals, that is, signal S1N is the inverted signal of signal S1.

[0073] Preferably, for the SEU monitoring unit, when the clock signal CK1 is at a high level "1," NMOS transistors N53, N54, and N58 are in an on state. Nodes d, e, and S2 within the SEU monitoring unit maintain a low level "0," the output control signal S1 maintains a low level "0," and the output control signal S1N maintains a high level "1." At this point, the SEU monitoring unit is functionally disabled. This is intended to shield against false detections during normal changes in the state of the data input signal D.

[0074] Preferably, for the SEU monitoring unit, when the clock signal CK1 is at a low level “0”, the NMOS transistor N53 , the NMOS transistor N54 and the NMOS transistor N58 are in a closed state, and the SEU monitoring unit function is turned on.

[0075] Preferably, for the SEU monitoring unit, its internal node changes and SEU detection principles are as follows:

[0076] XOR1 monitors sensitive nodes N1 and N2 of the first latch unit 105. If it detects that nodes N1 and N2 have the same logic state for a short period of time, it indicates that an SEU has occurred at either node N1 or N2. Node a within the SEU monitoring unit changes from a high level "1" to a low level "0," turning PMOS transistor P51 on. Since node S2 is initially at a low level "0," NMOS transistor N51 is off, and node d changes from its initial low level "0" to a high level "1" and remains at that level until the state of internal node S2 or the clock signal CK1 changes. Similarly, XOR2 monitors sensitive nodes N3 and N4 of the first latch unit 105. If it detects that nodes N3 and N4 have the same logic state for a short period of time, it indicates that an SEU has occurred at either node N3 or N4. Node b within the SEU monitoring unit changes from a high level "1" to a low level "0," turning PMOS transistor P52 on. Since node S2 is initially at low level “0”, NMOS transistor N52 is in the off state, and node e changes from the initial low level “0” to high level “1” and remains there until the internal node S2 or the clock signal CK1 changes state.

[0077] When nodes d and e are both at low level "0", it indicates that no sensitive nodes inside the first latch unit have changed, all internal nodes of the SEU monitoring unit remain unchanged, the SEU monitoring unit output control signal S1 remains at low level "0", and the output control signal S1N remains at high level "1".

[0078] When the states of nodes d and e differ (one is low level "0" and the other is high level "1"), this indicates that only the data at a sensitive node within the first latch unit has changed, and the latch unit will not flip. The dual-mode redundant structure of the internal nodes enables self-recovery from soft errors. In inverter D53, one of the PMOS and NMOS transistors (PMOS transistor P55 and NMOS transistor N56, or PMOS transistor P56 and NMOS transistor N55) must be off, and inverter D53 is non-conductive. Node f within the SEU monitoring unit remains high level "1," OR gate OR1 outputs a high level "1," PMOS transistor P58 is off, and the SEU monitoring unit output control signal S1 remains low level "0," while output control signal S1N remains high level "1."

[0079] When both nodes d and e are high level “1”, NMOS transistors N56 and N55 are in the on state, and node f changes from high level “1” to low level “0”. At this time, XOR gate XOR3 detects the sensitive node pair N2 and N4 of the first latch unit 105.

[0080] When the logical states of nodes N2 and N4 differ, this indicates that the data at the two sensitive nodes within first latch unit 105 has changed, but the previous sensitive node has recovered from its previous flip, and first latch unit 105 will not flip. At this point, XOR gate XOR3 outputs a high level "1," and OR gate OR1 outputs a high level "1." PMOS transistor P58 is off, and the SEU monitoring unit's output control signal S1 remains low at "0," while its output control signal S1N remains high at "1."

[0081] When the logical states of nodes N2 and N4 are the same, it indicates that the data at both sensitive nodes within first latch unit 105 have changed, and a single-event upset (SING) has occurred in first latch unit 105. At this point, XOR gate XOR3 outputs a low-level "0," and OR gate OR1 outputs a low-level "0." PMOS transistor P58 is turned on, and the SEU monitoring unit's output control signal S1 becomes a high-level "1," while the output control signal S1N becomes a low-level "0." Furthermore, the output control unit switches the data transmission channel from first latch unit 105 to second latch unit 106, achieving SINGLE-EVENT MULTI-BIT UGS resistance.

[0082] When nodes d and e are both high level "1," NMOS transistors N56 and N55 are turned on, node f changes from high level "1" to low level "0," and node S2 changes from low level "0" to high level "1." At this point, NMOS transistors N51 and N52 turn on, resetting nodes d and e to low level "0." Node f changes to high level "1," and node S2 changes to low level "0." NMOS transistors N51 and N52 turn off again, and node g changes to high level "1." At this point, the SEU monitoring unit's internal nodes d, e, f, g, and S2 are all reset, and SEU detection resumes.

[0083] In this embodiment, the self-recovering single-event upset-resistant multi-bit latch circuit structure uses a combination of circuit reinforcement technology and layout reinforcement technology to achieve single-event upset-resistant reinforcement of internal nodes.

[0084] In this embodiment, the self-recovering single-particle multi-bit upset resistant latch circuit structure can achieve single-particle upset resistance in all cases except when single-particle upset occurs in all the first latch unit and the second latch unit, and has a strong single-particle multi-bit upset resistance characteristic.

[0085] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

[0086] The contents not described in detail in the specification of the present invention belong to the common knowledge of professionals in this field.

Claims

1. A self-recovering single-event multi-bit flip-over resistant latch circuit structure, characterized in that: include: A clock-controlled inverter circuit, a latch unit, an output control unit (107), an SEU monitoring unit (108), and an inverter circuit; wherein the clock-controlled inverter circuit includes: a first clock-controlled inverter circuit (101), a second clock-controlled inverter circuit (102), a third clock-controlled inverter circuit (103), and a fourth clock-controlled inverter circuit (104); and the latch unit includes: a first latch unit (105) and a second latch unit (106); The output terminal of the first clock-controlled inverter circuit (101) is connected to the input terminal in1 of the first latch unit (105) and the input terminal in1 of the SEU monitoring unit (108); The output terminal of the second clock-controlled inverter circuit (102) is connected to the input terminal in2 of the first latch unit (105) and the input terminal in3 of the SEU monitoring unit (108); The output terminal of the third clock-controlled inverter circuit (103) is connected to the input terminal in1 of the second latch unit (106); The output terminal of the fourth clock-controlled inverter circuit (104) is connected to the input terminal in2 of the second latch unit (106); The output terminal out1 of the first latch unit (105) is connected to the input terminal in1 of the output control unit (107) and the input terminal in2 of the SEU monitoring unit (108); the output terminal out2 of the first latch unit (105) is connected to the input terminal in4 of the SEU monitoring unit (108); The output terminal out1 of the second latch unit (106) is connected to the input terminal in2 of the output control unit (107); The output terminal S1 and the output terminal S1N of the SEU monitoring unit (108) are connected to the input terminal S1 and the input terminal S1N of the output control unit (107) respectively; The inverter circuit is used for providing a clock signal CK1 and a clock signal CK2 to a clock control inverter circuit, a latch unit and an SEU monitoring unit (108).

2. The self-recovering single-event multi-bit upset latch circuit structure according to claim 1, characterized in that: The inverter circuit comprises: a first inverter circuit (109) and a second inverter circuit (110); wherein the first inverter circuit (109) and the second inverter circuit (110) are connected in series; the first inverter circuit (109) is used to provide a clock signal CK1 for the clock-controlled inverter circuit, the latch unit and the SEU monitoring unit (108); and the second inverter circuit (110) is used to provide a clock signal CK2 for the clock-controlled inverter circuit, the latch unit and the SEU monitoring unit (108).

3. The self-recovering single-event multi-bit upset latch circuit structure according to claim 2, characterized in that: The input terminal of the first inverter circuit (109) is connected to the input clock signal CLK; the first inverter circuit (109) outputs a clock signal CK1, and the second inverter circuit (110) outputs a clock signal CK2; wherein the clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is an inverted signal of the clock signal CLK, and the clock signal CK2 is an inverted signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of the data signal in the latch circuit.

4. The self-recovering single-event multi-bit upset latch circuit structure according to claim 1, characterized in that: The clock-controlled inverter circuit is an inverter circuit controlled by a set of complementary clock signals, including: a PMOS transistor P21, a PMOS transistor P22, an NMOS transistor N22, and an NMOS transistor N21; The PMOS transistor P21, the PMOS transistor P22, the NMOS transistor N22 and the NMOS transistor N21 are connected in series in sequence; The gate of the PMOS transistor P22 is connected to the clock signal CK2; The gate of the NMOS transistor N22 is connected to the clock signal CK1; The gate of the PMOS transistor P21 and the gate of the NMOS transistor N21 serve together as the input end of the clock control inverter circuit for receiving an input signal.

5. The self-recovering single event multi-bit upset resistant latch circuit structure according to claim 1, characterized in that: The latch unit has a DICE structure and includes an inverter D31, an inverter D32, an inverter D33, and an inverter D34. Inverter D31 includes a PMOS transistor P31 and an NMOS transistor N31 connected in series. Inverter D32 includes a PMOS transistor P32, a PMOS transistor P33, an NMOS transistor N33, and an NMOS transistor N32 connected in series. Inverter D33 includes a PMOS transistor P34 and an NMOS transistor N34 connected in series. Inverter D34 includes a PMOS transistor P35, a PMOS transistor P36, an NMOS transistor N36, and an NMOS transistor N35 connected in series. The input signal in1 is connected to the drain of the PMOS transistor P33, the drain of the NMOS transistor N33, the gate of the PMOS transistor P34 and the gate of the NMOS transistor N31; The input signal in2 is connected to the drain of the PMOS transistor P36, the drain of the NMOS transistor N36, the gate of the PMOS transistor P31 and the gate of the NMOS transistor N34; The output signal out1 is connected to the drain of the PMOS transistor P34, the drain of the NMOS transistor N34, the gate of the PMOS transistor P35 and the gate of the NMOS transistor N32; The output signal out2 is connected to the drain of the PMOS transistor P31, the drain of the NMOS transistor N31, the gate of the PMOS transistor P32, and the gate of the NMOS transistor N35; The gates of the PMOS transistor P33 and the PMOS transistor P36 are connected to the clock signal CK1; The gates of the NMOS transistor N33 and the NMOS transistor N36 are connected to the clock signal CK2.

6. The self-recovering single event multi-bit upset resistant latch circuit structure according to claim 1, characterized in that: The output control unit includes an inverter D41, an inverter D42, and an inverter D43. Inverter D41 includes a PMOS transistor P41, a PMOS transistor P42, an NMOS transistor N42, and an NMOS transistor N41 connected in series. Inverter D42 includes a PMOS transistor P43, a PMOS transistor P44, an NMOS transistor N44, and an NMOS transistor N43 connected in series. Inverter D43 includes a PMOS transistor P45 and an NMOS transistor N45 connected in series. The input signal in1 is connected to the gate of the PMOS transistor P41 and the gate of the NMOS transistor N41; The input signal in2 is connected to the gate of the PMOS transistor P43 and the gate of the NMOS transistor N43; The gate of the PMOS transistor P42 and the gate of the NMOS transistor N44 are connected to the input control signal S1; The gate of the NMOS transistor N42 and the gate of the PMOS transistor P44 are connected to the input control signal S1N; The output end of the inverter D41 and the output end of the inverter D42 are commonly connected to the input end of the inverter D43; The output terminal of the inverter D43 serves as the output terminal out of the output control unit.

7. The self-recovering single-event multi-bit upset latch circuit structure according to claim 6, characterized in that: For the output control unit, when the input control signal S1 is at a low level "0" and the input control signal S1N is at a high level "1", the PMOS transistor P42 and the NMOS transistor N42 are in an on state, the PMOS transistor P44 and the NMOS transistor N44 are in an off state, and the state of the input signal in1 is transmitted to the output terminal out through the inverter D41 and the inverter D43; conversely, when the input control signal S1 is at a high level "1" and the input control signal S1N is at a low level "0", the PMOS transistor P42 and the NMOS transistor N42 are in an off state, the PMOS transistor P44 and the NMOS transistor N44 are in an on state, and the state of the input signal in2 is transmitted to the output terminal out through the inverter D42 and the inverter D43.

8. The self-recovering single event multi-bit upset resistant latch circuit structure according to claim 1, characterized in that: The SEU monitoring unit includes: an exclusive OR gate XOR1, an exclusive OR gate XOR2, an exclusive OR gate XOR3, an inverter D51, an inverter D52, an inverter D53, an inverter D54, an inverter D55, an inverter D56 and an OR gate OR1; wherein the inverter D51 includes: a PMOS transistor P51, an NMOS transistor N51 and an NMOS transistor N53; the drain of the PMOS transistor P51, the drain of the NMOS transistor N51 and the drain of the NMOS transistor N53 serve as the output end of the inverter D51; the inverter D52 includes: a PMOS transistor P52, an NMOS transistor N52 and an NMOS transistor MOS transistor N54; the drain of PMOS transistor P52, the drain of NMOS transistor N52, and the drain of NMOS transistor N54 collectively serve as the output end of inverter D52; inverter D53 includes: PMOS transistor P55, PMOS transistor P56, NMOS transistor N56, and NMOS transistor N55 connected in series in sequence; inverter D54 includes: PMOS transistor P57 and NMOS transistor N57 connected in series; inverter D55 includes: PMOS transistor P58 and NMOS transistor N58 connected in series; inverter D56 includes: PMOS transistor P59 and NMOS transistor N59 connected in series; Input signals in1 and in2 are connected to the two input terminals of the XOR gate XOR1 respectively; the output terminal of the XOR gate XOR1 is connected to the input terminal of the inverter D51, that is, the gate of the PMOS transistor P51; Input signals in3 and in4 are connected to the two input terminals of the XOR gate XOR2 respectively; the output terminal of the XOR gate XOR2 is connected to the input terminal of the inverter D52, that is, the gate of the PMOS transistor P52; The input signals in2 and in4 are connected to the two input terminals of the exclusive OR gate XOR3 respectively; The output terminal of the inverter D51 is connected to the gate of the PMOS transistor P55 and the gate of the NMOS transistor N55; The output terminal of the inverter D52 is connected to the gate of the PMOS transistor P56 and the gate of the NMOS transistor N56; The output end of the inverter D53 and the output end of the XOR gate XOR3 are connected to the two input ends of the OR gate OR1 respectively; in addition, the output end of the inverter D53 is connected to the input end of the inverter D54; The output terminal of the inverter D54 is connected to the gate of the NMOS transistor N51 and the gate of the NMOS transistor N52; The output terminal of the OR gate OR1 is connected to the gate of the PMOS tube P58; The gates of the NMOS transistor N53, N54, and N58 serve as the clock input terminal of the SEU monitoring unit, and are used to receive the clock signal CK1. Inverter D55 outputs a control signal S1 , and inverter D56 outputs a control signal S1N. The control signal S1 and the control signal S1N are complementary signals, that is, the signal S1N is an inverted signal of the signal S1 .

9. The self-recovering single event resistant multi-bit upset latch circuit structure according to claim 8, characterized in that: For the SEU monitoring unit, when the clock signal CK1 is at a high level "1", the NMOS transistor N53, the NMOS transistor N54 and the NMOS transistor N58 are in the on state, the output control signal S1 remains at a low level "0", and the output control signal S1N remains at a high level "1". At this time, the SEU monitoring unit is in a functionally disabled state; when the clock signal CK1 is at a low level "0", the NMOS transistor N53, the NMOS transistor N54 and the NMOS transistor N58 are in a disabled state, and the SEU monitoring unit function is enabled.

10. The self-recovering single event resistant multi-bit upset latch circuit structure according to claim 1, characterized in that: The latch adopts a combination of circuit reinforcement technology and layout reinforcement technology to achieve single-event upset resistance of internal nodes.

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