Electronic circuit, memory and method for compensating data distortion caused by channel loss

Abstract

The invention discloses an electronic circuit, a memory and a method for compensating data distortion caused by channel loss. In one embodiment, an electronic circuit includes a conversion circuit to convert an input signal into a digital signal, and a compensation circuit coupled to the conversion circuit. The conversion circuit includes a sampling circuit for receiving a digital signal and generating an output signal. The output signal includes a stream of bits to be transmitted in a plurality of consecutive pulse periods. The conversion circuit also includes one or more equalizer circuits coupled to the sampling circuit. Each equalizer circuit is configured to receive a bit of an output feedback signal in a corresponding one of consecutive pulse periods. The sampling circuit is configured to generate an output signal according to the digital signal and a sum of one or more equalized outputs output by the one or more equalizer circuits.

Description

Technical Field

[0001] The present invention relates to the related technology of decision feedback equalization (DFE) in semiconductor devices, and more particularly to an electronic circuit, a memory and a method for compensating data distortion caused by channel loss. Background Art

[0002] Integrated circuit memories are widely used in electronic products to store and transmit data. In recent years, the demand for memories with high storage capacity and high data transmission rate has been increasing. Summary of the invention

[0003] The present invention provides techniques related to decision feedback equalization in semiconductor devices.

[0004] In one embodiment, the present invention describes an electronic circuit, including a conversion circuit and a compensation circuit. The conversion circuit is used to convert an input signal into a digital signal. The compensation circuit is coupled to the conversion circuit and includes a sampling circuit. The sampling circuit is used to receive the digital signal and generate an output signal. The output signal includes a bit stream, which is used to be transmitted in multiple consecutive pulse cycles. The compensation circuit also includes one or more equalizer circuits, which are coupled to the sampling circuit. Each of the equalizer circuits is used to receive a bit of an output feedback signal in a corresponding one of the consecutive pulse cycles and generate a corresponding equalized output. The sampling circuit is used to generate an output signal based on the sum of the digital signal and one or more equalized outputs output by the equalizer circuit.

[0005] In one embodiment, the sum of the one or more equalized outputs comprises a weighted sum.

[0006] In one embodiment, the electronic circuit further comprises one or more capacitors. The capacitor is coupled to the sampling circuit and connected in parallel with the equalizer circuit. The one or more capacitors comprise at least one of the following: one or more metal-insulator-metal (MIM) capacitors, one or more metal-oxide-semiconductor capacitors (MOSCAPs), or one or more multilayer ceramic capacitors (MLCC). The electronic circuit further comprises one or more switching elements coupled to the one or more capacitors.

[0007] In one embodiment, the pulse width of the output signal is different from the pulse width of the input signal. The electronic circuit includes a receiving circuit, the receiving circuit is used to receive a data signal from a data channel, and output the input signal. The pulse width of the input signal is smaller than the pulse width of the data signal. The compensation circuit is used to make the pulse width of the output signal substantially the same as the pulse width of the data signal.

[0008] In one embodiment, the electronic circuit includes a latch circuit, wherein the latch circuit is configured to receive an output signal and output a latch output.

[0009] In some embodiments, the digital signal includes a complementary metal-oxide-semiconductor (CMOS) signal in a digital format.

[0010] In one embodiment, the conversion circuit includes a current mode logic (CML) circuit and a current mode logic to digital conversion circuit (CML-to-digital converter circuit). The current mode logic circuit is used to generate a current mode logic signal according to an input signal. The current mode logic to digital conversion circuit is used to convert the current mode logic signal into a digital signal. The current mode logic circuit includes a bias current source, a first switch and a second switch. The first switch is controlled by the input signal and the second switch is controlled by the reference signal. The current mode logic to digital conversion circuit includes a digital analog-to-digital converter (ADC) and an amplifier circuit. The digital analog-to-digital converter is used to output a logic "0" or "1" according to the voltage level of the current mode logic signal. The amplifier circuit is used to adjust the voltage level of the logic "0" or "1" to generate a digital signal.

[0011] In one embodiment, the sampling circuit includes a first N-type metal-oxide-semiconductor (NMOS). The sampling circuit is used to receive a digital signal from a gate terminal of the first NMOS. One or more equalizer circuits are coupled to a drain terminal of the first NMOS. The electronic circuit further includes one or more capacitors, and one or more capacitors are coupled to the drain terminal of the first NMOS.

[0012] In one embodiment, the sampling circuit further includes a second N-type metal oxide semiconductor switch. The sampling circuit is used to receive the inverted digital signal from the gate terminal of the second N-type metal oxide semiconductor switch.

[0013] In one embodiment, the sampling circuit includes an N-type charge sharing metal oxide semiconductor switch (chargesharing NMOS switch). The gate terminal of the N-type charge sharing metal oxide semiconductor switch is coupled to a constant voltage source. The first terminal of the N-type charge sharing metal oxide semiconductor switch is coupled to the drain terminal of the first N-type metal oxide semiconductor switch. The second terminal of the N-type charge sharing metal oxide semiconductor switch is coupled to the drain terminal of the second N-type metal oxide semiconductor switch. The first terminal is one of the drain terminal or the source terminal of the N-type charge sharing metal oxide semiconductor switch, and the second terminal is the other of the drain terminal or the source terminal of the N-type charge sharing metal oxide semiconductor switch.

[0014] In one embodiment, the sampling circuit includes one or more reset switches. The gate terminal of each of the one or more reset switches is driven by a pulse signal. The drain terminal of each of the one or more reset switches is coupled to the first N-type metal oxide semiconductor switch. The source terminal of each of the one or more reset switches is coupled to a constant voltage source or a ground terminal.

[0015] In one embodiment, each equalizer circuit includes a first feedback switch, a second feedback switch, and one or more weighted control switches. The first feedback switch is used to receive a bit of an output feedback signal. The second feedback switch is used to receive the inverted logic value (logic opposite) of the bit of the output feedback signal. The one or more weighted control switches are used to receive the weighted control signal.

[0016] In one embodiment, one or more weighted control switches are used to connect the first feedback switch and the second feedback switch to a plurality of weighted switches according to a weighted control signal.

[0017] In one embodiment, one or more weighted control switches are used to connect the first feedback switch and the second feedback switch to one or more current mirror circuits according to a weighted control signal.

[0018] In one embodiment, the compensation circuit is a first compensation circuit, and the sampling circuit is a first sampling circuit. The electronic circuit further includes a second compensation circuit, and the second compensation circuit includes a second sampling circuit. The second sampling circuit is used to receive a digital signal and generate an output feedback signal in a continuous pulse cycle.

[0019] In one embodiment, the electronic circuit further comprises a first latch circuit and a second latch circuit. The first latch circuit is coupled to the first compensation circuit. The second latch circuit is coupled to the second compensation circuit. The first latch circuit is used to output a first latch output (first latch output), and the second latch circuit is used to output a second latch output (second latch output).

[0020] In one embodiment, the electronic circuit further includes a third compensation circuit and a fourth compensation circuit. The first compensation circuit is driven by the first pulse signal, the second compensation circuit is driven by the second pulse signal, the third compensation circuit is driven by the third pulse signal, and the fourth compensation circuit is driven by the fourth pulse signal. The first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal have the same cycle length. The first pulse signal is earlier than the second pulse signal by one quarter of the cycle length. The second pulse signal is earlier than the third pulse signal by one quarter of the cycle length. The third pulse signal is earlier than the fourth pulse signal by one quarter of the cycle length.

[0021] In one embodiment, the present invention further provides a memory, comprising a memory interface circuit, a memory cell array, a data buffer circuit and a control logic circuit. The memory interface circuit is coupled to the data channel. The control logic circuit is coupled to the memory interface circuit, the memory cell array and the data buffer circuit. The memory buffer circuit comprises a conversion circuit and a compensation circuit. The conversion circuit is used to receive an input signal from the memory interface circuit and convert the input signal into a digital signal. The compensation circuit is coupled to the conversion circuit. The compensation circuit comprises a sampling circuit and one or more equalizer circuits. The sampling circuit is used to receive a digital signal and generate an output signal. The output signal comprises a bit stream, which is used to be transmitted in a plurality of consecutive pulse cycles. One or more equalizer circuits are coupled to the sampling circuit, each equalizer circuit being used to receive a bit of an output feedback signal in a corresponding one of the consecutive pulse cycles and generate a corresponding balanced output. The sampling circuit is used to generate an output signal according to the sum of the digital signal and one or more balanced outputs output by the one or more equalizer circuits.

[0022] In one embodiment, the data buffer circuit includes a plurality of compensation circuits, and the compensation circuits include the compensation circuit, each compensation circuit includes a respective sampling circuit and at least one respective equalizer circuit. The respective equalizer circuit in each compensation circuit is used to receive an output feedback signal from an output in another different compensation circuit.

[0023] In one embodiment, the data buffer circuit further includes a plurality of latch circuits, each latch circuit being coupled to a corresponding compensation circuit among the compensation circuits and configured to receive an output signal from the corresponding compensation circuit and output a latch output signal.

[0024] In one embodiment, the present invention also provides a method for compensating for data distortion caused by channel loss, comprising: receiving an input signal from a data channel; converting the input signal into a digital signal; generating a sampled output signal, wherein the sampled output signal comprises a bit stream, the bit stream being used to be transmitted in a plurality of consecutive pulse cycles; and providing a bit of an output feedback signal to each of one or more equalizer circuits in a corresponding one of the consecutive pulse cycles, wherein the sampled output signal is used to be generated based on the sum of the digital signal and one or more equalized outputs output by the one or more equalizer circuits.

[0025] The following paragraphs and drawings describe one or more implementation details of the present invention so as to clearly present various features, aspects and advantages in the embodiments, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a memory according to some embodiments of the present invention.

[0027] Figure 2 A schematic diagram of a memory according to some embodiments of the present invention.

[0028] Figure 3A FIG. 1 is a schematic diagram of a receiver with decision feedback equalization according to some embodiments of the present invention.

[0029] Figure 3B FIG. 1 is a schematic diagram of pulse width reduction caused by inter-symbol interference (ISI) and compensation of pulse width reduction according to some embodiments of the present invention.

[0030] Figure 4 FIG. 1 is a schematic diagram of a receiver of decision feedback equalization (DFE) according to some embodiments of the present disclosure.

[0031] Figure 5 FIG. 1 is a schematic diagram of a current mode logic (CML) circuit according to some embodiments of the present disclosure.

[0032] Figure 6 FIG. 1 is a schematic diagram of a strong arm latch comparator with a compensation circuit according to some embodiments of the present disclosure.

[0033] Fig. 7A FIG. 1 is a schematic diagram of pulse width reduction caused by inter-symbol interference (ISI) and compensation for pulse width reduction according to some embodiments of the present invention.

[0034] Figure 7BFIG. 4 is a schematic diagram of pattern effect of pulse width compensation according to some embodiments of the present invention.

[0035] Figure 8 FIG. 1 is a table diagram showing the compensation effect of pulse width reduction in some embodiments according to the present invention.

[0036] Fig.9A FIG. 1 is a schematic diagram of a quarter-rate and one-tap decision feedback equalization (DFE) circuit with latched output according to some embodiments of the present disclosure.

[0037] Fig. 9B According to some embodiments of the present invention Fig.9A Timing diagram of quarter-rate and single-stage decision feedback equalization circuits.

[0038] Fig.10 The present invention is a flowchart of a method according to some embodiments of the present invention.

[0039] The drawings are not drawn to scale, and the same reference numerals are used to represent the same or similar elements.

[0040] Description of Reference Numerals

[0041] 100: System

[0042] 110: Installation

[0043] 112: Device controller

[0044] 113: Processor

[0045] 114: Internal memory

[0046] 116: Memory

[0047] 120: Host device

[0048] 122: Host controller

[0049] 200: Memory

[0050] 202: Memory Interface

[0051] 204: Control Logic

[0052] 206: X Decoder

[0053] 210: Memory cell array

[0054] 215: Bit line

[0055] 220: Page buffer circuit

[0056] 230: Data cache circuit

[0057] 240: Data buffer

[0058] 242: Data input buffer

[0059] 244: Data output buffer

[0060] 300: Architecture

[0061] 304: Adder

[0062] 306: Sum

[0063] 308: Sampling and latching circuit

[0064] 310: Sample output

[0065] 312-1: Bit

[0066] W1-W n : Weight value

[0067] 314-2: Trigger

[0068] 352 Curve

[0069] 354: Curve

[0070] 400: Receiver

[0071] 401: Current Mode Logic Circuit

[0072] 402: Current Mode Logic to Digital Conversion Circuit

[0073] 403: Compensation circuit

[0074] REF: Reference signal

[0075] 411: Input signal

[0076] 412: Current Mode Logic Signal

[0077] 413: Digital Signal

[0078] 414: Output signal

[0079] 415: Feedback signal

[0080] 500: Current Mode Logic Circuit

[0081] 501: Bias current source

[0082] 503: First switch

[0083] 505: Second switch

[0084] IN: Input signal

[0085] I bias : Current

[0086] 600: Compensation circuit

[0087] 610: Sampling Circuit

[0088] 620-1: Equalizer circuit

[0089] 620-n: Equalizer circuit

[0090] 613: Digital Signal

[0091] 614: Output signal

[0092] L: Node

[0093] R: Node

[0094] MEQ: N-type charge sharing metal oxide semiconductor switch

[0095] MSWL: NMOS switch

[0096] MSWR: NMOS switch

[0097] MN2: N-type metal oxide semiconductor switch

[0098] MN3: N-type metal oxide semiconductor switch

[0099] MP4: P-type metal oxide semiconductor reset switch

[0100] MP5: P-type metal oxide semiconductor reset switch

[0101] VDD: voltage

[0102] OUT0: Output terminal

[0103] OUT0B: Output terminal

[0104] OUT1: Output terminal

[0105] OUT1B: Output terminal

[0106] OUT PREV1 :Signal

[0107] OUT PREVn :Signal

[0108] OUTB PREV1 :Signal

[0109] OUTB PREVn :Signal

[0110] Q0-Q3: Latch output

[0111] MFBR1: Switch

[0112] MFBL1: Switch

[0113] W[2:0]: weighted control signal

[0114] MWL1[2:0]: Weighted switch

[0115] MWR1[2:0]: Weighted switch

[0116] 617: Capacitor

[0117] 700A: Situation

[0118] 700B: Situation

[0119] 700C: Situation

[0120] 750A-750C: Waveform

[0121] 800: Table

[0122] 900: Decision Feedback Equalization Circuit

[0123] 903-0: Compensation Circuit

[0124] 903-3: Compensation Circuit

[0125] 901: Digital Signal

[0126] 950: Timing diagram

[0127] 1000: Processing flow

[0128] 1002: Steps

[0129] 1004: Steps

[0130] 1006: Steps

[0131] 1008: Steps DETAILED DESCRIPTION

[0132] The following will disclose multiple embodiments of the present invention with drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are not necessary. In addition, for the purpose of simplifying the drawings, some conventional structures and components will be depicted in a simple schematic manner in the drawings.

[0133] In this document, when an element is referred to as "connected" or "coupled", it may refer to "electrical connection" or "electrical coupling". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish between elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present invention.

[0134] A semiconductor device (e.g., a memory) can receive data from a host device (e.g., a personal computer). Data transmission is often susceptible to noise and interference, resulting in distortion of the data waveform sampled by the semiconductor device. One type of interference is "inter-symbol interference (ISI)". With ISI, a first data symbol (e.g., a bit) sampled in an earlier pulse cycle has a voltage level (e.g., logic "0") that may cause a second data symbol used in a later pulse cycle to have a different voltage level (e.g., logic "1"). A reduction in the pulse width of the second data symbol will increase the probability of a data error rate.

[0135] In order to mitigate the effects of inter-symbol interference (ISI), in some cases, semiconductor devices are used to implement equalizer circuits, such as decision feedback equalization (DFE) circuits, which are used to feed back one or more earlier symbols of an output signal to a receiver circuit. Accordingly, the later symbol of the output signal can take into account the earlier symbol and compensate for the reduction in pulse width. In some cases, the decision feedback equalization (DFE) circuit feeds back the earlier symbol to a current mode logic (CML) circuit, which is used to compensate for the reduction in pulse width of the input signal and generate a pair of differential analog signals. The sampling circuit converts the analog signal into a digital signal and feeds it back to the next stage of input signal compensation. Therefore, the feedback path in these decision feedback equalization (DFE) circuits will cause a considerable delay from the current mode logic (CML) circuit to the sampling circuit. Since "feedback" requires compensation and sampling to be completed within one pulse cycle, it will be difficult to meet the timing requirements when using the decision feedback equalization (DFE) circuit in a memory supporting high-speed data transmission.

[0136] Implementations of the present invention provide techniques for addressing the above challenges. In some embodiments, the architecture of decision feedback equalization (DFE) is used to improve the performance of decision feedback equalization (DFE) through small feedback delay and compensation space tuning. This architecture can also reduce the inter-symbol interference (ISI) of the post-cursor of the long tail, thereby reducing the bit error rate. As described below, these techniques can reduce the feedback delay in the decision feedback equalization (DFE) circuit. For example, some embodiments of the present technology can directly feed back the output signal to the sampling circuit without passing through the current mode logic (CML) circuit, thereby reducing the feedback delay and making the implemented decision feedback equalization (DFE) circuit suitable for high-speed memory. In addition, the present technology can support adjustable pulse width compensation space. Using one or more of the features described later, each implementation of the present invention can improve the quality of data reception and the flexibility of decision feedback equalization (DFE).

[0137] The present technology can be applied to any suitable circuit or device, such as a semiconductor device. For illustrative purposes, a memory is described herein as a semiconductor device as an example. For example, the present technology can be applied to various types of non-volatile memories, such as: NOR flash memory, NAND flash memory, erasable programmable read-only memory (EPROM), static random access memory (SRAM), resistive random-access memory (RRAM), ferroelectric random access memory (FeRAM) and magnetoresistive random access memory (MRAM). The present technology can also be applied to various types of memories, such as: single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), penta-level cell (PLC). In addition, the present technology can be applied to various types of devices and systems, such as secure digital cards, embedded multimedia cards (eMMC), solid-state drives (SSDs), embedded systems, and computing network devices.

[0138] Figure 1 1 is a schematic diagram of a system 100 according to some embodiments of the present disclosure, including a memory. The system 100 includes a device 110 and a host device 120. The device 110 includes a device controller 112 and a memory 116. The device controller 112 includes a processor 113 and an internal memory 114. In some embodiments, the device 110 includes a plurality of memories 116 coupled to the device controller 112.

[0139] In some embodiments, the device 110 is a memory. For example, the device 110 may be an embedded multimedia card (eMMC), a memory card (sSD), a solid state drive device (SSD), or other suitable storage devices. In some embodiments, the device 110 is a smart watch, a digital camera, or a multimedia player. In some embodiments, the device 110 is a user-end device coupled to a host-end device. For example, the device 110 is a memory card in a host-end device (digital camera or multimedia player).

[0140] The device controller 112 may be a general-purpose microprocessor or a dedicated microcontroller. In some embodiments, the device controller 112 is a memory controller of the device 110. Various techniques are described below based on an implementation in which the device controller 112 is a memory controller. However, the techniques described below will also be applicable to other implementations in which the device controller 112 is other than a memory controller.

[0141] The processor 113 is used to execute instructions and process data. Instructions include firmware instructions and / or other program instructions stored in the auxiliary memory as firmware code and / or other program codes. Data includes program data corresponding to the firmware and / or processor executed, and other suitable data. In some embodiments, the processor 113 is a general-purpose microprocessor or a dedicated microcontroller. The processor 113 can also be a central processing unit.

[0142] The processor 113 accesses instructions and data from the internal memory 114. In some embodiments, the internal memory 114 may be a static random access memory (SRAM) or a dynamic random access memory (DRAM). For example, in some embodiments, when the device 110 is an eMMC, an SD card, or a smart watch, the internal memory 114 is an SRAM. In some embodiments, when the device 110 is a digital camera or a multimedia player, the internal memory 114 is a DRAM.

[0143] In some embodiments, the internal memory is a cache memory included in the device controller 112, as shown in FIG1A. The internal memory 114 stores instruction codes corresponding to instructions executed by the processor 113 and / or data requested by the processor 113 in the runtime.

[0144] The device controller 112 transfers the instruction code and / or data from the memory 116 to the internal memory 114. The memory 116 may be a semiconductor device. In some embodiments, the memory 116 is a non-volatile memory for long-term storage of instructions and / or data, such as a NAND flash memory device, or other applicable non-volatile memory. In an embodiment where the memory 116 is a NAND flash memory, the device 110 is a flash memory device, such as a flash memory card. The device controller 112 is a NAND flash memory controller. For example: In some embodiments, when the device 110 is an eMMC or a memory card, the memory 116 is a MAND flash memory. In some embodiments, when the device 110 is a digital camera, the memory 116 is a memory card. In some embodiments, when the device 110 is a multimedia player, the memory 116 is a hard disk.

[0145] The memory 116 includes a plurality of memory blocks. The memory 116 may be a two-dimensional memory including a plurality of two-dimensional memory blocks. The memory 116 may also be a three-dimensional memory including a plurality of three-dimensional memory blocks.

[0146] Figure 2 FIG. 2 is a schematic diagram of a memory 200 according to some embodiments of the present invention. The memory 200 may be implemented as Figure 1 The memory 116 is shown. The memory 200 includes a memory cell array 210. The memory cell array 210 may include a plurality of memory cells, which are coupled in series to a plurality of word lines in rows and a plurality of bit lines in columns.

[0147] The memory cell includes a memory transistor as a storage element. The memory transistor includes a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating gate metal oxide semiconductor field effect transistor (floating gate transistor), a nitride read only memory (NROM) transistor, or any suitable non-volatile memory metal-oxide-silicon (MOS) device that can store charge.

[0148] The memory 200 includes a memory interface 202 having a plurality of input / output terminals for receiving data, for example, from a Figure 1 The device controller 112 shown receives data, or receives data from Figure 1The host controller 122 shown receives data or outputs data from the memory cell array 210. The memory 200 includes a data buffer 240, which is used to buffer data through the memory interface 202. The data buffer 240 includes a data input buffer 242, which is used to receive data from a controller (e.g., Figure 1 The device controller 112 shown, or Figure 1 The host controller 122 shown in the figure buffers / transmits data to the memory cell array 210. The data buffer 240 also includes a data output buffer 244 for buffering / transmitting data from the memory cell array 210 through the memory interface 202, for example, to Figure 1 The host device 120 is shown.

[0149] In some embodiments, the memory 200 further includes an X decoder 206 (column decoder) and an optional Y decoder (not shown). Each memory cell is coupled to the X decoder 206 via its own word line and to the Y decoder via its own bit line 215. Accordingly, each memory cell can be selected by the X decoder 206 and the Y decoder for read or write operations via its own word line and bit line 215.

[0150] The memory 200 includes a page buffer circuit 220, which includes a plurality of page buffers. Each page buffer is connected to the memory cell array 210 via a respective bit line 215. In some embodiments, the page buffer is connected to a Y decoder via a data line associated with a corresponding bit line 215, which is connected to a corresponding line of a plurality of memory cells in the memory cell array 210. The page buffer is used to control a voltage on a corresponding word line to perform an operation on a memory cell (coupled to a corresponding bit line), such as reading, writing / programming, or clearing. The page buffer may include at least one latch circuit.

[0151] In some embodiments, the memory 200 further includes a data buffer circuit 230. The data buffer circuit 230 is coupled between the page buffer circuit 220 and the data buffer 240. In a programming or clearing operation, the data buffer circuit 230 is used to store data from the data buffer 240 (e.g., from the data input buffer 242) and / or output data to the memory cell array 210 through the page buffer 220. In a read operation, the data buffer circuit 230 is used to store data from the memory cell array through the page buffer circuit 220 and / or output data to the data buffer 240 (e.g., the data output buffer 244).

[0152] In some embodiments, the memory 200 further includes a control logic 204, which is coupled to multiple components in the memory 200 (including the X decoder 206 and the Y decoder, the data buffer 240, the page buffer circuit 220, and the data cache circuit 230). The control logic 204 is used to receive commands, address information, and / or data through the memory interface 202, for example, from a memory controller (such as Figure 1 The control logic 204 may also access commands, address information, and / or data, such as to generate physical address information (e.g., memory blocks / memory pages in the memory cell array 210). The control logic 204 may include a circuit system, such as an integrated circuit that combines multiple logic, circuits, and / or components.

[0153] In some embodiments, the control logic 204 includes a data register, an SRAM buffer, an address generator, a mode logic, and a state machine. The mode logic is used to determine whether there is a read or write operation and provide the determination result to the state machine.

[0154] In a write operation, the data register of the control logic 204 can temporarily store the input data of the memory interface 202. The address generator of the control logic 204 can generate a corresponding physical address to store the input data of the designated memory cell in the memory cell array 210. The address generator is connected to the X decoder 206 and the Y decoder, and is controlled to select the designated memory cell through the corresponding word line and bit line. When powered, the SRAM buffer is used to maintain the input data of the data register of the memory. The state machine can process the write signal of the SRAM buffer and provide a control signal to the voltage generator to provide a write voltage to the X decoder 206 and the Y decoder. The Y decoder is used to output a write voltage to the bit line to store the input data of the designated memory cell.

[0155] In a read operation, the state machine may provide control signals to the voltage generator and the page buffer circuit 220. The voltage generator may provide a read voltage to the X decoder 206 and the Y decoder to select a memory cell. The page buffer may sense a small electrical signal (e.g., a current signal) stored in the selected memory cell and used to represent a data bit (e.g., "1" or "0") by coupling the bit line 215 of the page buffer or the selected memory cell. The sense amplifier may amplify the swing of the small electrical signal to a recognizable logic level so that the data bit can be correctly interpreted by logic inside or outside the memory 200. In some embodiments, the page buffer circuit 220 and / or the data buffer circuit 230 are included in the sense amplifier. The data buffer 240 (e.g., the data output buffer 244) may receive the amplified voltage from the sense amplifier and output the amplified electrical signal to logic outside the memory 200 through the memory interface 202.

[0156] Figure 3A FIG. 3 is a schematic diagram of a receiver architecture 300 of decision feedback equalization (DFE) according to some embodiments of the present disclosure. The architecture 300 may be implemented as Figure 2 Data is shown as being input to a buffer 242 to mitigate inter-symbol interference (ISI).

[0157] In some embodiments, the architecture 300 includes an input node for receiving data from a channel, such as a cable or a flat cable, or a wireless communication channel. The received data is input to an adder 304 to output a sum 306.

[0158] In some embodiments, the architecture 300 further includes a sampling and latching circuit 308 driven by the pulse signal. During each pulse cycle of the pulse signal, the sampling and latching circuit 308 can sample each bit of the sum 306 and latch (e.g., for long-term storage) the output to obtain a sampled output 310 for further processing.

[0159] In some embodiments, the architecture 300 further includes N feedback loops from the sample output 310 to the adder 304, where N is a positive integer greater than or equal to 1. Each feedback loop is referred to as a tap. In a set pulse cycle, a bit of the sample output 310 is weighted according to a weight value and fed back to the adder 304 through each feedback loop. For example, in the first feedback loop, the last bit 312-1 of the sample output 310 is weighted by the weight value W1 and fed back to the adder 304. In the same pulse cycle, in the second feedback loop, the penultimate bit 312-2 output by the sample and latch circuit 308 in the previous pulse cycle and delayed by the flip-flop 314-2 is weighted by the weight value W2 and fed back to the adder 304. Similarly, in the same pulse cycle, in the nth feedback loop, the inverse nth bit 312-n of "the sampling and latch circuit 308 outputs in the first n pulse cycles" and "delayed by n-1 flip-flops 314-2 to 314-n" is weighted by the weight value W. n The weighted values ​​W1 are fed back to the adder 304. Through these feedback loops, the sampling of the sampling and latching circuit 308 can take into account the influence of the previous bit on the data and compensate for the pulse width variation caused by the inter-symbol interference (ISI) accordingly. Because the inter-symbol interference (ISI) generally decreases with the increase of the time gap between symbols, the weight value W1 can be the maximum value of all the weight values ​​in the n feedback loops.

[0160] Figure 3B FIG. 2 is a schematic diagram showing waveform distortion caused by the mitigation effect of inter-symbol interference (ISI) and decision feedback equalization (DFE) according to some embodiments of the present invention. Figure 3B In FIG. 3 , curve 352 shows the waveform distortion caused by inter-symbol interference (ISI), and curve 354 shows the mitigation effect of decision feedback equalization (DFE). The waveform diagram covers four consecutive bits in the data, whose logic values ​​are "0, 1, 1 and 0" respectively.

[0161] As shown in curve 352, in the first pulse cycle, the data is at a low voltage level and corresponds to logic "0" without distortion. In the second pulse cycle, since the logic value of the second bit is "1", ideally, the voltage of the data should immediately rise to a high level corresponding to logic "1" at the beginning of the second pulse cycle. However, due to the inter-symbol interference (ISI) of the first bit, the voltage of the second bit of data cannot immediately rise to the level of logic "1". On the contrary, throughout the second pulse cycle, the data voltage will gradually rise and will not reach the high level corresponding to logic "1", thereby presenting an obvious distorted waveform on curve 352. Similarly, in the third pulse cycle, the inter-symbol interference (ISI) of the first bit will continue to cause the third bit to be distorted, but the degree is less than that of the second bit. Throughout the third pulse cycle, the data voltage continues to rise to the level corresponding to logic "1", but will not reach that level. Similar to the distortion of the second and third bits, when the data of the fourth bit becomes logic “0”, inter-symbol interference (ISI) slows down the voltage drop in the fourth pulse cycle.

[0162] Distortion between the second pulse period and the fourth pulse period may result in a reduction in pulse width. For example, a typical one-bit sampling circuit compares the data voltage with the reference voltage and outputs a sampling result of "1" if the data voltage is higher than the reference voltage. As shown in curve 352, since the voltage gradually rises (ramp-up) during the first pulse period, the data voltage is higher than the reference voltage only during a portion of the first pulse period. Accordingly, the sampling circuit will output "1" during a portion of the pulse period and will inaccurately output "0" during the rest of the pulse period. This will significantly reduce the pulse width of the first bit of data.

[0163] Decision feedback equalization (DFE) is a method to mitigate the distortion caused by inter-symbol interference (ISI). Figure 3A As shown by curve 354 in FIG. 3 , the decision feedback equalization (DFE) circuit can take into account the earlier bits affected by the inter-symbol interference (ISI). The decision feedback equalization (DFE) circuit can also provide a mechanism to compensate for the reduction in pulse width caused by the inter-symbol interference (ISI). The implementation details of the decision feedback equalization (DFE) circuit will be described below.

[0164] Figure 4 FIG. 4 is a reference diagram of a receiver 400 of a decision feedback equalization (DFE) circuit according to some embodiments of the present invention. The feedback equalizer circuit (ie, the receiver 400) may have a Figure 3A The architecture 300 is similar to the architecture of FIG. Figure 2 data input buffer 242.

[0165] In some embodiments, a receiver 400 of a decision feedback equalization (DFE) circuit includes a current mode logic (CML) circuit 401. The current mode logic circuit receives an input signal 411 from a data channel. And receives a reference signal REF. The reference signal REF may have a fixed voltage level. In some embodiments, this fixed voltage level is set according to an intermediate value between "a high voltage level corresponding to a logic '1' in the input data signal" and "a low voltage level corresponding to a logic '0' in the input signal". For example, when the input signal uses 0.4 volts as a logic "1" and uses 0 volts to represent a logic "0", the reference signal REF may have a fixed voltage level of approximately 0.2 volts. In some embodiments, the fixed voltage of the reference signal REF may be configured to be a value other than the intermediate value between logic "1" and "0".

[0166] According to the input signal 411 and the reference signal REF, the current mode logic circuit 401 outputs a current mode logic signal 412. The current mode logic signal 412 can be output in a differential mode on two paths with opposite voltage levels. For example, when the first path has a high voltage level, the other path will have a low voltage level, and vice versa.

[0167] In some embodiments, the receiver 400 of the decision feedback equalization (DFE) circuit includes a current mode logic to digital converter circuit (CML-to-digital converter circuit) 402. The CML-to-digital converter circuit 402 receives a current mode logic signal 412 and converts the current mode logic signal 412 into a digital signal 413. For example, the CML-to-digital converter circuit 402 may include a digital analog-to-digital converter to output a digital value “0” or “1” according to the current mode logic signal 412.

[0168] In addition, the current mode logic to digital conversion circuit 402 further includes an amplifier circuit, which is used to adjust the voltage level representing the digital "0" or "1". For example, when the input signal 411 uses 0 volts and 0.4 volts to represent the logic "0" and "1" respectively, the current mode logic to digital conversion circuit 402 is used to output the digital signal 413, using 0 volts and 1.2 volts to represent the logic "0" and "1" respectively. As the difference between the logic "0" and "1" increases, the digital signal 413 can be applied to a CMOS circuit, which can have a faster operation. In this case, the digital signal 413 can be a CMOS signal.

[0169] The current mode logic to digital conversion circuit 402 receives the current mode logic signal 412 through a single input terminal. Alternatively, when the current mode logic circuit 401 provides the current mode logic signal 412 in a differential mode, the current mode logic to digital conversion circuit 402 receives two paths from the current mode logic signal 412 through two differential input terminals, such as Figure 4 As shown. The current mode logic to digital conversion circuit 402 can output the digital signal 413 through a single output terminal. Alternatively, the current mode logic to digital conversion circuit 402 can output the digital signal in a differential mode through two output terminals, such as Figure 4 The current mode logic circuit 401 and the current mode logic to digital conversion circuit 402 together form a conversion circuit to convert an input signal 411 into a digital signal 413 .

[0170] In some embodiments, the receiver 400 of the decision feedback equalization (DFE) circuit further includes one or more strong arm latch comparators, which have multiple compensation circuits such as 403-1, 403-2, etc., which can be collectively referred to as strong arm latch comparators with multiple compensation circuits 403, and individually referred to as strong arm latch comparators with one compensation circuit 403. The strong arm latch comparator with compensation circuit 403 receives the digital signal 413 from the current mode logic to digital conversion circuit 402, either as a single-ended input or as a differential input, such as the IN and INB labels in the figure (such as Figure 4 As shown). Each strong-arm latch comparator with compensation circuit 403 generates an output signal 414. Each strong-arm latch comparator with compensation circuit 403 may also receive a corresponding output signal 414 as a feedback signal 415 from a corresponding output terminal (e.g., OUT0 / OUT0B or OUT1 / OUT1B). Each strong-arm latch comparator with compensation circuit 403 receives its own output signal 414 from its own output terminal as an output feedback signal 415, or receives other output signals 414 from the output terminals of other compensation circuits 403 as output feedback signals. The strong-arm latch comparator with compensation circuit 403 may operate similarly to the combination of adder 304, sampling and latch circuit 308, and feedback loop in architecture 300.

[0171] Figure 5 FIG. 5 is a schematic diagram of a current mode logic circuit 500 according to some embodiments of the present disclosure. The current mode logic circuit 500 may be implemented as Figure 4 Current mode logic circuit 401.

[0172] In some embodiments, the current mode logic circuit 500 includes a bias current source 501, a first switch 503, and a second switch 505. The first switch 503 is controlled by an input signal IN, and the second switch 505 is controlled by a reference signal REF. Each of the first switch 503 and the second switch 505 can be a transistor, such as a MOS transistor. The first switch 503 and the second switch 505 are coupled in parallel to each other, providing two alternative paths 511 and 513 to allow the current I bias When the voltage of the input signal IN is greater than the reference signal REF, the current I bias The current I flows to the path 511 through the first switch 503. When the voltage of the input signal IN is lower than the reference signal REF, the current I bias The current flows to the path 513 through the second switch 505. Therefore, the current mode logic circuit 500 outputs a current mode logic signal in a differential mode through the two paths 511 and 513.

[0173] Figure 6 A schematic diagram of a strong arm latch comparator with a compensation circuit 600 in some embodiments for illustrating the content of the present invention. The strong arm latch comparator with the compensation circuit 600 can be implemented as Figure 4 A single compensation circuit 403 or a combination of one or more compensation circuits 403 is shown.

[0174] In some embodiments, the strong-arm latch comparator with compensation circuit 600 includes a sampling circuit 610. The function of sampling circuit 610 may be similar to the sampling of sampling and latch circuit 308 in architecture 300. The strong-arm latch comparator with compensation circuit 600 may also include n equalizer circuits 620-1 to 620-n (which may be individually or collectively referred to as equalizer circuits 620) connected in parallel to each other. The n equalizer circuits 620-1 to 620-n may operate similarly to the n feedback loops of architecture 300.

[0175] The sampling circuit 610 receives a digital signal 613. The digital signal 613 may be a single-port input, such as labeled IN, or may include a pair of differential digital signals, such as labeled IN and INB. The digital signal 613 may be Figure 4 The sampling circuit 610 also outputs an output signal 614, which can be Figure 4The output signal 414 is shown. The output signal 614 can be a single-port output, such as labeled OUT, or can include a pair of differential output signals, such as labeled OUT, OUTB. The following description assumes that both the digital signal 613 and the output signal 614 include a pair of differential signals. Under this assumption, the one or more equalizer circuits 620 that provide weighted output feedback signals to the sampling circuit 610 can also be formed in a differential mode.

[0176] The sampling of the digital signal 613 can be synchronized with the pulse signal CLK and connected to the gate terminals of the NMOS switches MN4 and MN5. At each rising edge of the pulse signal, a pair of differential digital signals IN and INB connected to the gate terminals of the NMOS switches MN2 and MN3 will cause the NMOS switches MN2 and MN3 to be turned on or off, thereby controlling the current path from IN and INB to OUTB and OUT, respectively. Accordingly, the voltage values ​​of IN and INB will be sampled at OUT and OUTB.

[0177] In order to provide a discharge path for nodes L and R to avoid flipping of output data, the sampling circuit 610 has an N-type charge sharing metal oxide semiconductor switch MEQ. The N-type charge sharing metal oxide semiconductor switch MEQ is connected between the drain terminals of the N-type metal oxide semiconductor (NMOS) switches MN2 and MN3. The gate terminal of the N-type charge sharing metal oxide semiconductor switch MEQ is connected to the voltage VDD of the high voltage level. The sampling circuit 610 may also include one or more P-type metal oxide semiconductor (PMOS) reset switches MP4 and MP5 driven by the falling edge of the pulse signal CLK. When the pulse signal CLK is a low level voltage, sampling will stop and the PMOS reset switches MP4 and MP5 will be turned on to allow the high voltage VDD to be transferred to the nodes L and R. This will ensure that the voltages of the nodes L and R are reset to the voltage VDD at the beginning of each pulse cycle.

[0178] Each equalizer circuit 620 is used to form a feedback loop. Taking the equalizer circuit 620-1 as an example, in the differential mode, the equalizer circuit 620-1 receives the previous bit of each of OUT and OUTB as input, which are represented as OUT PREVl and OUTB PREVlBy controlling the NMOS switches MFBL1, MFBR1, MWL1[2:0], and MWR1[2:0], the equalizer circuit 620-1 generates an output feedback signal 615-1, which may include a pair of differential feedback signals. OUT PREV1 and OUTB PREV1 The reception of the output feedback signal 615-1 and the generation of the output feedback signal 615-1 are synchronized with the pulse signal CLK. The output feedback signals 615-1 to 615-n from the n equalizer circuits 620 are added at the nodes L and R of the sampling circuit 610. The addition of the output feedback signals 615-1 to 615-n at the nodes L and R can be similar to Figure 3A The functionality of adder 304 in architecture 300.

[0179] As with architecture 300, equalizer circuit 620 may weight its respective output feedback signals 615-1 to 615-n before outputting them. Weighting may be implemented by one or more weighting switches. Taking equalizer circuit 620-1 as an example, in each pulse cycle, signal OUT PREV1 and OUTB PREVl The NMOS switches MFBR1 and MFBL1 are controlled to be turned on or off, thereby controlling the current flowing through the switches MFBR1 and MFBL1. At the same time, according to the value of the weighted control signal W[2:0], the current flows through one or more weighted switches MWL1[2:0] and MWR1[2:0]. The weighted switches MWL1[2:0] and MWR1[2:0] can each include three NMOS switches of different sizes (for example: 1x, 2x and 4x), and can output currents of different sizes. Accordingly, by adjusting the weighted control signal W[2:0], the user of the equalizer circuit 620-1 can adjust the weight applied to the output feedback signal 615-1. This weighting mechanism can be similar to Figure 3A In the architecture 300, W1, W2, ... W n weighted.

[0180] In other embodiments, the equalizer circuit 620 may use a current mirror circuit to replace the weighted switches MWL1[2:0] and MWR1[2:0] to weight the output feedback signals 615-1 to 615-n according to the weighted control signal W[2:0], for example, to adjust the feedback gain. Since those skilled in the art can understand the structure and operation of the current mirror circuit, it is not further described here.

[0181] In some embodiments, the strong arm latch comparator with compensation circuit 600 further includes one or more capacitors 617, which can increase the hold time of typical corners and fast corners and provide compensation space for channel loss. One or more capacitors 617 can be coupled to the sampling circuit 610 at nodes L and R and connected in parallel with the equalizer circuit 620. One or more capacitors 617 can be metal-insulator-metal (MIM) capacitors, multilayer ceramic capacitors (MLCC), one or more metal oxide semiconductor (MOSCAP) capacitors, or other types of capacitors. Each of the one or more capacitors 617 is coupled to NMOS switches MSWL and MSWR. Each of the NMOS switches MSWL and MSWR is controlled by a capacitor switching signal SWC, which couples or decouples one or more capacitors 617 to the sampling circuit 610.

[0182] The equalizer circuit 620 and one or more capacitors 617 can help mitigate the distortion of the digital signal 613 caused by inter-symbol interference (ISI). As discussed in subsequent Figures 7 and 8, the equalizer circuit 620 can compensate for the pulse width reduction of the input data signal 613, and the one or more capacitors 617 can help increase the compensation headroom.

[0183] Fig. 7A Used to illustrate the reduction in pulse width caused by intersymbol interference (ISI). Fig. 7A The above diagram shows an ideal situation 700A, where the input data is not distorted after being transmitted through the data channel. Therefore, after sampling, a bit pulse corresponding to a logic "1" will maintain the same width (e.g., 250 picoseconds in this embodiment) throughout a complete pulse cycle.

[0184] Compared with the ideal case 700A, the non-ideal case 700B shows that the width of a bit pulse is reduced to 180ps. Specifically, since the input data of the sampling circuit needs a certain holding time (such as 70ps in this embodiment) after the rising edge of the sampling pulse signal CLK, the actual CLK window frame needs to be 70ps ahead of the input signal.

[0185] Please refer to Figure 6 , the output feedback signals 615-1 to 615-n can help slow down the delay of the sampling circuit. For example, when the digital signal 613 switches from logic "0" to logic "1", the signal OUTB PREV1 Has a logic "1" value. Signal OUTB PREV1The high voltage corresponding to the logic "1" of the NMOS switch MFBL1 causes the current to flow from the NMOS switch MFBL1 to the node L after being weighted. With the additional current, the time required for the voltage at the node L to reach 0 volts is reduced, thereby reducing the delay of the output signal OUT to become the voltage of logic "1". Using the feedback loop to reduce the delay can be regarded as similar to reducing the holding time of the sampling circuit, which is equivalent to the pulse width stretching of the input signal (assuming that the holding time is fixed to 70ps). The result after compensation is shown in the case 700C in Figure 7.

[0186] Figure 7B The figure shows the pattern effect of pulse width compensation according to some embodiments of the present invention. The compensation with pattern effect can be applied to the situation 700B where the pulse width is reduced from the ideal 250ps to 180ps due to inter-symbol interference (ISI).

[0187] exist Figure 7B In FIG. 7 , waveform 750A shows that the pulse width is reduced from 250 ps to 180 ps. This reduction is caused by the most severe inter-symbol interference (ISI).

[0188] Compared to waveform 750B, waveform 750C shows that the pulse width is increased to 200 ps because the inter-symbol interference (ISI) only comes from the first two bits (with a logic "0" value). Therefore, the third bit of the compensated waveforms 750A, 750B, and 750C has an overlap width of 230 ps, ​​which is 20 ps less than the ideal width of 250 ps.

[0189] Although the feedback loop can effectively compensate for the reduction in pulse width, this mechanism also has limitations. For example, since the actual decision feedback equalization (DFE) circuit usually cannot have an infinite number of feedback loops, the compensation provided by the feedback loop usually cannot cover the full range (such as 70ps in case 700B). In addition, the production of components in the sampling circuit will also affect the compensation space. In particular, components produced at typical corners and fast corners can have smaller hold time margins than components produced at slow corners. Therefore, components produced at typical corners and fast corners can reduce the range of potential compensation, making it more challenging for the compensation circuit 600 to compensate for the reduction in pulse width.

[0190] The use of one or more capacitors 617 can improve the compensation performance at typical corners and fast corners. For example, by enabling the NMOS switches MSWL and MSWR with the capacitor switching signal SWC, the one or more capacitors 617 can be connected to the sampling circuit 610. The charge storage effect of the one or more capacitors 617 can increase the margin of the holding time of the sampling circuit 610, thereby increasing the space for potential compensation.

[0191] Figure 8 A table 800 is shown to illustrate the compensation effect of pulse width reduction. The compensation effect in table 800 can be achieved by applying a strong arm latch comparator with a single-stage (1-tap) compensation circuit 600 to a variety of situations (including: a full pulse period of 250 ps and a worst-case pulse width of 180 ps without compensation).

[0192] According to Table 800, the connection of capacitor 617 to sampling circuit 610 can improve the compensation effect for both fast corner components and typical corner components. Specifically, when capacitor 617 is connected to sampling circuit 610 (i.e., SWC=1), the pulse width increases from 205ps to 230ps in the fast corner component and from 210ps to 230ps in the typical corner component. For the slow corner component, the pulse width is 230ps, where capacitor 617 is disconnected from sampling circuit 610 (i.e., SWC=0). In all cases, one equalizer circuit 620 and one capacitor 617 can improve the pulse width from 180ps to 230ps. When more equalizer circuits 620 are available, the reduction in pulse width can be further compensated. Therefore, after the memory circuit for implementing "strong arm latch comparator with compensation circuit of decision feedback equalization (DFE)" is manufactured, the user can control the capacitor switching signal SWC according to the corner where the memory is located to achieve the desired pulse width compensation.

[0193] Fig.9A FIG. 1 is a schematic diagram of a quarter-rate and one-tap decision feedback equalization (DFE) circuit 900 with latched outputs according to some embodiments of the present invention. The quarter-rate one-tap decision feedback equalization (DFE) circuit 900 may be similar to Figure 3A The sampling and latching circuit 308 in the architecture 300 operates.

[0194] In some embodiments, a quarter rate and single-stage decision feedback equalization (DFE) circuit 900 has four strong arm latch comparators with compensation circuits 903-0 to 903-3 (collectively referred to as strong arm latch comparators with multiple compensation circuits 903, or individually referred to as strong arm latch comparators with a single compensation circuit 903). Each strong arm latch comparator with compensation circuit 903 can be identical or similar to circuit 600. The four strong arm latch comparators with compensation circuit 903 are used to receive the same digital signal 901, which includes a pair of differential digital signals IN and INB. The four strong arm latch comparators with compensation circuit 903 generate output signals OUT0 to OUT3 respectively. The output signal generated by one strong arm latch comparator with compensation circuit 903 will be fed back to another strong arm latch comparator with compensation circuit 903. That is, the signal OUT0 is fed back to the strong arm latch comparator 903-1 with the compensation circuit 903; the signal OUT1 is fed back to the strong arm latch comparator 903-2 with the compensation circuit 903; the signal OUT2 is fed back to the strong arm latch comparator 903-3 with the compensation circuit 903; and the signal OUT3 is fed back to the strong arm latch comparator 903-4 with the compensation circuit 903. The four strong arm latch comparators with the compensation circuit 903 can also generate inverted output signals OUT0B to OUT3B, which correspond to the output signals OUT0 to OUT3.

[0195] The operation of the strong-arm latch comparator with compensation circuit 903 can be synchronized with the pulse signals CLK0-CLK3, and each pulse signal is used to drive the corresponding compensation circuit 903. The pulse signals CLK0-CLK3 have the same pulse cycle length, but the phase difference is 90 degrees. For example: the pulse signal CLK0 is earlier than the pulse signal CLK1 by one-quarter of the cycle length; the pulse signal CLK1 is earlier than the pulse signal CLK2 by one-quarter of the cycle length; the pulse signal CLK2 is earlier than the pulse signal CLK3 by one-quarter of the cycle length. The frequency of the pulse signals CLK0-CLK3 is one-quarter of the data rate of the digital signal 901. Therefore, each strong-arm latch comparator with compensation circuit 903 performs sampling and compensation in every four bits of the digital signal 901.

[0196] The output signals OUT0-OUT3 of the compensation circuit 903 may be latched for a period of time by four latch circuits 905-0-905-3 (collectively referred to as latch circuits 905, or individually by latch circuits 905) to stabilize. The latch circuits 905-0-905-3 each output latch outputs Q0-Q3, respectively. In some embodiments, each latch circuit 905 includes a set / reset latch having two inputs for receiving two mutually inverted signals OUT and OUTB, and two outputs for receiving two mutually inverted signals Q and QB. The quarter-rate and single-stage decision feedback equalization (DFE) circuit 900 may use a quarter pulse rate to bypass the delay of the SR latch and improve the feedback delay.

[0197] Fig. 9B Shown are some embodiments according to the present invention Fig.9A A timing diagram 950 of a quarter rate and single stage decision feedback equalization circuit is shown. The timing diagram 950 assumes that the digital signal IN has a rate of one bit per time unit (1U).

[0198] As mentioned above, the pulse signals CLK0-CLK3 each have a frequency equal to one-fourth of the data rate of the digital signal IN. Therefore, the pulse signals CLK0-CLK3 each have a cycle length equal to 4U (logic "1" is 2U, logic "0" is 2U). The pulse signal CLK0 is one time unit (1U) earlier than the pulse signal CLK1; the pulse signal CLK1 is one time unit earlier than the pulse signal CLK2; the pulse signal CLK2 is one time unit earlier than CLK3.

[0199] Driven by the pulse signals CLK0-CLK3, each strong arm latch comparator with compensation circuit 903 samples the digital signal IN at a rate of "one bit per 4U", and outputs the sampled data on the output signals OUT0-OUT3 respectively. Since sampling only occurs when the pulse signals CLK0-CLK3 are at a high level, the signals OUT0-OUT3 have 2U of valid sampled data in one pulse cycle, and are reset during the other 2U periods in the same pulse cycle (for example: through the reset switches MP4 and MP5 in the compensation circuit 600). As shown in the timing diagram 950, the signals OUT0-CLK0 are sampled with data D0 during the 2U period of the pulse cycle, and are reset during the other 2U period in the same pulse cycle. In the next pulse cycle, the signal OUT0 has been sampled with data D4, which is the 4 bits sampled after D0. Similarly, during the 2U period of the pulse cycle of the pulse signal CLK1, the signal OUT1 is sampled to obtain data D1 and reset at 2U; then, data D5 is sampled in the next pulse cycle of the pulse signal CLK1. The data in the output signals OUT2 and OUT3 can also be obtained in a similar manner.

[0200] Next, the output signals OUT0 to OUT3 are latched and become latch outputs Q0 to Q3, respectively. In the timing diagram 950, the latch uses 4U for each bit of data. Accordingly, latch 905-0 outputs data D0 on latch output Q0 of 4U, and then outputs data D4 in another 4U. Similarly, latch 905-1 outputs data D1 on latch output Q1 of 4U, and then outputs data D5 in another 4U. The data of latch outputs Q2 and Q3 can also be obtained in a similar manner.

[0201] The quarter rate and single stage decision feedback equalization (DFE) circuit 900 can help compensate for data distortion in high-speed applications. Because after the rising edge of the next pulse signal, the feedback signal needs a certain holding time when it is transmitted to the next strong arm latch comparator with the compensation circuit 903, and after the rising edge of the next pulse signal, the output signal of the circuit 903 has valid sampled data within at least 1U, therefore, the quarter rate and single stage decision feedback equalization (DFE) circuit 900 can use the output signal of the circuit 903 for feedback without passing through the latch 905, and has a shorter feedback delay. In the case of lower feedback delay requirements, the compensation circuit can use more taps to improve compensation performance.

[0202] Although FIGS. 9A and 9B illustrate a circuit design of a quarter rate and single-stage decision feedback equalization (DFE) circuit, other embodiments may have other rates. For example, some embodiments may have two, eight, or sixteen strong arm latch comparators with compensation circuits driven by a pulse signal having a frequency equal to one-half, one-eighth, or one-sixteenth of the data rate.

[0203] Fig.10 1 is a flowchart of a method of processing flow 1000 according to some embodiments of the present invention. Processing flow 1000 may be performed by a receiver 400 such as a decision feedback equalization (DFE) circuit of a memory. By executing processing flow 1000, the memory may compensate for data distortion caused by channel loss (e.g., inter-symbol interference ISI).

[0204] In step 1002, an input signal is received from a data channel. The input signal may be Figure 4 The input signal 411 is the same or similar.

[0205] In step 1004, the input signal is converted into a digital signal. The digital signal can be Figure 4 Digital signal 413, Figure 6 The digital signal 613 or Fig.9A The digital signal 901 is the same or similar.

[0206] In step 1006, a sampled output signal is generated. The sampled output signal may include a bit stream transmitted in a plurality of consecutive pulse cycles. The sampled output signal may be Figure 4 The output signal 414, Figure 6 The output signal 614, or Fig.9A The output signals OUT0-OUT3 of the equalizer circuit 620 are the same or similar. The transmission of the bit stream can be fed back to the equalizer circuit 620 as the signal OUT PREV1 ~OUT PREVn OUTB PREV1 ~OUTB PREVn .

[0207] In step 1008, during one of the consecutive pulse cycles, one or more equalizer circuits provide a bit of an output feedback signal. The bit of the output feedback signal provided may be Figure 6 The equalizer circuit 620 provides the OUT PREVl ~OUT PREVn and OUTBPREV1~OUTB PREVn The sum of the output of one or more equalizer circuits and the digital signal may be used to generate a sampled output signal.

[0208] The various embodiments of the present invention may be implemented as one or more computer program products, such as one or more computer program instruction modules programmed in a computer-readable medium for executing or controlling the operation of a data processing device. The computer-readable medium may be a machine-readable device, a machine-readable substrate, a memory, or a combination of one or more of the above. The aforementioned "data processing device" includes various types of equipment, devices, and machines for processing data, such as a programmable processor, a single computer, or multiple processors and computers. In addition to hardware, the aforementioned equipment may also include code for creating an execution environment for the aforementioned computer program, such as: constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of the above.

[0209] The system may include all devices, equipment and machines for processing data, including a programmable processor, a single computer or multiple processors or multiple computers. In addition to hardware, the system may also include code for creating an execution environment for the aforementioned computer program, for example: constituting processor firmware, protocol stack, database management system, operating system or a combination of one or more of the above.

[0210] A computer program (or program, software, software application APP, script or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a standalone program or as a module, component, subroutine or other unit suitable for application in a computer environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a part of an archive or data that stores other programs (such as one or more scripts stored in a markup language document), in a single file dedicated to the aforementioned program, or in multiple coordinated files (e.g., storing one or more modules, subroutines or partial codes). A computer program can be deployed on a single computer or multiple computers for execution, which can be located at a single site or distributed at multiple sites and interconnected by a communication network.

[0211] The processing procedures and logic flows described in the present invention can be performed by executing one or more programmed processors, which are used to execute one or more computer programs to perform the aforementioned functions. The processing procedures and logic flows can also be performed by dedicated logic circuits, and the device can also be implemented as a dedicated logic circuit, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0212] For example, processors suitable for executing computer programs include general and special purpose microprocessors, and one or more processors of any type of digital computer. Generally speaking, the processor will receive instructions and data from a read-only memory and / or a random access memory. The basic elements of a computer may include a processor for executing instructions and one or more memories for storing instructions and data. Generally speaking, a computer may also include, or be operatively coupled to receive data from and / or transmit data to one or more mass storage devices (such as magnetic disks, magneto-optical disks, or optical disks) for storing data. However, a computer may not require these devices. Computer-readable media are suitable for storing computer program instructions and data, including various forms of non-volatile memory, media and storage, such as semiconductor memories or magnetic disks such as EPROMs and EEPROMs. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0213] Although the content of the present invention describes many details, these details should not be interpreted as limitations on the claims or the content claimed for protection, but should be interpreted as a description of the unique features of a specific embodiment. The specific features described in the different embodiments of the content of the present invention may also be combined or implemented in a single embodiment. On the other hand, the various features described in a single embodiment may also be implemented in multiple embodiments or in any suitable sub-combination. In addition, although some of the aforementioned features are described as being implemented in a specific combination, in some embodiments, some features may be deleted from the combination, and the combination claimed for protection may be for changes in sub-combinations or each sub-combination. Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be understood as limiting a specific order or a continuous order, and should not be understood as having to follow the operations of the diagrams to achieve the desired effect.

[0214] The above only discloses some embodiments of the present invention. The present invention can be varied, modified or improved on each embodiment according to the disclosed content.

Claims

1. An electronic circuit, characterized in that: Include: a conversion circuit for converting an input signal into a digital signal; and A compensation circuit is coupled to the conversion circuit and comprises: a sampling circuit for receiving the digital signal and generating an output signal, wherein the output signal comprises a bit stream, and the bit stream is used to be transmitted in a plurality of consecutive pulse cycles; as well as One or more equalizer circuits coupled to the sampling circuit, wherein each of the one or more equalizer circuits is configured to receive a bit of an output feedback signal in a corresponding one of the consecutive pulse cycles and generate a corresponding equalized output; The sampling circuit is used to generate the output signal according to a sum of the digital signal and one or more equalized outputs output by the one or more equalizer circuits.

2. The electronic circuit according to claim 1, characterized in that The sum of the one or more equalized outputs comprises a weighted sum.

3. The electronic circuit according to claim 1, characterized in that Also includes: One or more capacitors are coupled to the sampling circuit and connected in parallel with the one or more equalizer circuits.

4. The electronic circuit according to claim 1, characterized in that A pulse width of the output signal is different from a pulse width of the input signal.

5. The electronic circuit according to claim 1, characterized in that Also includes: A latch circuit is used to receive the output signal and output a latch output.

6. The electronic circuit according to claim 1, characterized in that The conversion circuit includes: a current mode logic circuit for generating a current mode logic signal according to the input signal; and A current mode logic to digital conversion circuit is used to convert the current mode logic signal into the digital signal.

7. The electronic circuit according to claim 1, characterized in that: The sampling circuit includes a first N-type metal oxide semiconductor switch; The sampling circuit is used for receiving the digital signal from a gate terminal of the first N-type metal oxide semiconductor switch; The one or more equalizer circuits are coupled to a drain terminal of the first NMOS switch; and The electronic circuit further includes one or more capacitors, and the one or more capacitors are coupled to the drain terminal of the first N-type metal oxide semiconductor switch.

8. The electronic circuit according to claim 7, characterized in that: The sampling circuit further includes a second N-type metal oxide semiconductor switch; and The sampling circuit is used for receiving an inverted digital signal from a gate terminal of the second N-type metal oxide semiconductor switch.

9. The electronic circuit according to claim 8, characterized in that: The sampling circuit includes an N-type charge sharing metal oxide semiconductor switch; A gate terminal of the N-type charge sharing metal oxide semiconductor switch is coupled to a certain voltage source; A first terminal of the N-type charge sharing metal oxide semiconductor switch is coupled to the drain terminal of the first N-type metal oxide semiconductor switch; as well as A first terminal of the N-type charge sharing metal oxide semiconductor switch is coupled to a drain terminal of the first N-type metal oxide semiconductor switch; The first end is one of a drain end or a source end of the N-type charge sharing metal oxide semiconductor switch, and the second end is the other of the drain end or the source end of the N-type charge sharing metal oxide semiconductor switch.

10. The electronic circuit according to claim 9, characterized in that: The sampling circuit includes one or more reset switches; A gate terminal of each of the one or more reset switches is driven by a pulse signal; A drain terminal of each of the one or more reset switches is coupled to the first N-type metal oxide semiconductor switch; and A source terminal of each of the one or more reset switches is coupled to the constant voltage source or a ground terminal.

11. The electronic circuit according to claim 1, characterized in that Each of the one or more equalizer circuits comprises: a first feedback switch, configured to receive the bit of the output feedback signal; a second feedback switch for receiving an inverted logic value of the bit of the output feedback signal; as well as One or more weighted control switches are used to receive a weighted control signal.

12. The electronic circuit according to claim 11, characterized in that The one or more weighted control switches are used to connect the first feedback switch and the second feedback switch to a plurality of weighted switches according to the weighted control signal.

13. The electronic circuit according to claim 11, characterized in that The one or more weighted control switches are used to connect the first feedback switch and the second feedback switch to one or more current mirror circuits according to the weighted control signal.

14. The electronic circuit according to claim 1, characterized in that The compensation circuit is a first compensation circuit, and the sampling circuit is a first sampling circuit; and The electronic circuit further includes a second compensation circuit, which includes a second sampling circuit. The second sampling circuit is used to receive the digital signal and generate the output feedback signal in these multiple continuous pulse cycles.

15. The electronic circuit according to claim 14, characterized in that Also includes: a first latch circuit coupled to the first compensation circuit; and A second latch circuit is coupled to the second compensation circuit, wherein the first latch circuit is used to output a first latch output, and the second latch circuit is used to output a second latch output.

16. The electronic circuit according to claim 15, characterized in that It also includes a third compensation circuit and a fourth compensation circuit, wherein: The first compensation circuit is driven by a first pulse signal, the second compensation circuit is driven by a second pulse signal, the third compensation circuit is driven by a third pulse signal, and the fourth compensation circuit is driven by a fourth pulse signal; The first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal have the same cycle length; The first pulse signal is earlier than the second pulse signal by one quarter of the cycle length; The second pulse signal is earlier than the third pulse signal by one quarter of the cycle length; and The third pulse signal is earlier than the fourth pulse signal by one quarter of the cycle length.

17. A memory, characterized in that: Include: a memory interface circuit coupled to a data channel; a memory cell array; a data buffer circuit; and A control logic circuit is coupled to the memory interface circuit, the memory cell array and the data buffer circuit, wherein the memory buffer circuit comprises: a conversion circuit for receiving an input signal from the memory interface circuit and converting the input signal into a digital signal; and A compensation circuit is coupled to the conversion circuit, wherein the compensation circuit comprises: a sampling circuit for receiving the digital signal and generating an output signal, wherein the output signal comprises a bit stream, and the bit stream is used to be transmitted in a plurality of consecutive pulse cycles; as well as One or more equalizer circuits coupled to the sampling circuit, wherein each of the one or more equalizer circuits is configured to receive a bit of an output feedback signal in a corresponding one of the consecutive pulse cycles and generate a corresponding equalized output; The sampling circuit is used to generate the output signal according to a sum of the digital signal and one or more equalized outputs output by the one or more equalizer circuits.

18. The memory according to claim 17, characterized in that: The data buffer circuit includes a plurality of compensation circuits, and the compensation circuits include the compensation circuit, each of the compensation circuits includes a respective sampling circuit and at least a respective equalizer circuit; The at least one respective equalizer circuit of each of the compensation circuits is configured to receive the output feedback signal from an output of another of the compensation circuits.

19. The memory according to claim 18, characterized in that: The data buffer circuit further includes a plurality of latch circuits, each of which is coupled to a corresponding compensation circuit among the compensation circuits and is used to receive an output signal from the corresponding compensation circuit and output a latched output signal.

20. A method for compensating for data distortion caused by channel loss, characterized in that: Include: receiving an input signal from a data channel; Converting the input signal into a digital signal; Generating a sampled output signal, wherein the sampled output signal comprises a bit stream, and the bit stream is used to be transmitted in a plurality of consecutive pulse periods; as well as In a corresponding one of these consecutive pulse cycles, one bit of an output feedback signal is provided to each of one or more equalizer circuits, wherein the sampled output signal is generated based on a sum of the digital signal and one or more equalized outputs output by the one or more equalizer circuits.

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