Filter data processing method, device and electronic equipment

Abstract

The embodiments of the present application disclose a method, device and electronic device for processing filtered data, and relate to the field of computer technology. The method comprises: performing frequency division processing on a sampling clock signal based on a preset filtering frequency division number to obtain a filtered clock signal; within any cycle of the filtered clock signal, storing a set of sampled data collected in a first sub-area of ​​a cache area, and transferring another set of sampled data stored in the first sub-area of ​​the previous cycle to a second sub-area of ​​the cache area; if within any cycle of the filtered clock signal, it is detected that the number of sampled data in the cache area is equal to a preset number threshold, then filtering and calculating the earliest set of sampled data stored in the cache area based on a preset filtering order to obtain a plurality of filtered sampled data corresponding to any cycle. Through this method, the reliability of filtered data processing can be improved and the cost can be reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a filtering data processing method, device and electronic equipment. Background Art

[0002] The sampling rate of current analog digital converters (ADCs) is getting higher and higher, and high-speed data sampling can be performed, for example, data sampling can be performed at a sampling rate of 3.2GSPS. In addition, the sampled data needs to be filtered to remove noise and interference.

[0003] In related technologies, in order to ensure the synchronous generation of sampled data, filtering and data sampling need to work under the same frequency clock signal. However, the multipliers and adders used in chip filtering have large delays. When the clock signal frequency is too high, it will be difficult to ensure that accurate filtered sampled data is output in each cycle, resulting in unreliable filtering data processing.

[0004] Therefore, how to improve the reliability of filtering data processing is an urgent problem to be solved. Summary of the invention

[0005] To solve the above technical problems, embodiments of the present application provide a filtering data processing method, apparatus, device and computer-readable storage medium.

[0006] Among them, the technical solution adopted in the present application is: a filtering data processing method, comprising: dividing a sampling clock signal based on a preset filtering frequency division number to obtain a filtering clock signal; within any period of the filtering clock signal, storing a group of collected sampling data in a first sub-area of ​​a cache area, and transferring another group of sampling data stored in the first sub-area of ​​the previous period to a second sub-area of ​​the cache area; wherein the number of sampling data in each group of sampling data is the same as the preset filtering frequency division number; if within any period of the filtering clock signal, it is detected that the number of sampling data in the cache area is equal to a preset number threshold, then filtering and calculating the earliest group of sampling data stored in the cache area based on the preset filtering order to obtain multiple filtered sampling data corresponding to any period.

[0007] A filtering data processing device comprises: a processing unit, which is used to perform frequency division processing on a sampling clock signal based on a preset filtering frequency division number to obtain a filtering clock signal; a storage unit, which is used to store a group of sampled data collected in a first sub-area of ​​a cache area within any cycle of the filtering clock signal, and transfer another group of sampled data stored in the first sub-area of ​​the previous cycle to a second sub-area of ​​the cache area; wherein the number of sampled data in each group of sampled data is the same as the preset filtering frequency division number; and a calculation unit, which is used to perform filtering calculation on the earliest group of sampled data stored in the cache area based on a preset filtering order if it is detected within any cycle of the filtering clock signal that the number of sampled data in the cache area is equal to a preset number threshold, to obtain a plurality of filtered sampled data corresponding to the any cycle.

[0008] In one embodiment of the present application, based on the aforementioned scheme, the processing unit is further used to write a group of newly collected sampling data into an intermediate cache area based on the sampling clock signal; wherein the intermediate cache area is used to store at least one group of sampling data; within any cycle of the filtering clock signal, the earliest group of sampling data stored in the intermediate cache area is stored in the first sub-area of ​​the cache area.

[0009] In one embodiment of the present application, based on the aforementioned scheme, the device also includes an acquisition unit for writing a set of newly collected sampling data into the intermediate cache area if it is detected based on the sampling clock signal that a period equal to the preset filter division number has passed since the last trigger to write the sampling data into the intermediate cache area.

[0010] In one embodiment of the present application, based on the aforementioned scheme, the acquisition unit is further used to respectively acquire multiple sampling data associated with each sampling data in the earliest stored group of sampling data; wherein the number of the multiple sampling data is the same as the preset filtering order; the calculation unit is further used to calculate the filtered sampling data corresponding to the sampling data based on the multiple sampling data corresponding to each sampling data; the processing unit is further used to simultaneously output the filtered sampling data corresponding to each sampling data in the earliest stored group of sampling data to obtain the multiple filtered sampling data.

[0011] In one embodiment of the present application, based on the aforementioned scheme, the processing unit is further used to detect the target serial number corresponding to the target sampling data; wherein the target sampling data is any one of the earliest stored group of sampling data; the calculation unit is further used to calculate the termination serial number based on the preset filtering order; starting from the target serial number, each sampling data is obtained in the order of increasing serial numbers until the sampling data corresponding to the termination serial number is obtained, thereby obtaining multiple sampling data associated with the target sampling data.

[0012] In one embodiment of the present application, based on the aforementioned scheme, the cache area also includes a third sub-area, and the third sub-area is used to store the earliest stored set of sampling data; the processing unit is also used to delete the sampling data stored in the third sub-area if it is detected within any cycle of the filtering clock signal that the third sub-area in the cache area has stored sampling data, and the sampling data stored in other sub-areas are to be transferred to the third sub-area; and transfer the sampling data stored in the other sub-areas to the third sub-area.

[0013] In one embodiment of the present application, based on the aforementioned scheme, the processing unit is further used to detect the sampling frequency corresponding to the sampling clock signal; calculate the filtering frequency based on the sampling frequency and the preset filtering frequency division number; and generate the filtering clock signal based on the filtering frequency.

[0014] An electronic device, one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, the electronic device implements the above filtering data processing method.

[0015] A computer-readable storage medium stores a computer program, which implements the above-mentioned filtering data processing method when executed by a processor.

[0016] In the above technical solution: the sampling clock signal can be divided based on the preset filter frequency division number to obtain the filter clock signal. Due to the frequency division process, the frequency of the filter clock signal is lower than the sampling clock signal. Next, in any cycle of the filter clock signal, a group of sampled data collected is stored in the first sub-area of ​​the cache area, and another group of sampled data stored in the first sub-area of ​​the previous cycle is transferred to the second sub-area of ​​the cache area; wherein the number of sampled data in each group of sampled data is the same as the preset filter frequency division number. In this way, different groups of sampled data can be stored in different sub-areas of the cache area in a rolling manner. If in any cycle of the filter clock signal, it is detected that the number of sampled data in the cache area is equal to the preset number threshold, the earliest stored group of sampled data in the cache area is filtered and calculated based on the preset filter order to obtain a plurality of filtered sampled data corresponding to the any cycle.

[0017] On the one hand, this method reduces the frequency of the filter clock signal by dividing the sampling clock signal, so that the chip can complete the processing of the filter data at a lower frequency. In each filter clock cycle, multiple filtered sampled data can be processed and output, so even if the filter clock frequency is reduced, the amount of output filter data remains the same as when there is no frequency division. In addition, the filter cycle is longer after frequency division, which improves the processing accuracy of the filter data in each cycle, thereby improving the accuracy and reliability of the filter processing.

[0018] On the other hand, since the frequency of the filter clock signal is reduced, there is no need to use a chip that supports high-frequency processing, but a lower-cost chip that meets the frequency requirements after frequency division can be selected. High-frequency chips are usually expensive, and this method effectively avoids this high-cost requirement, significantly reducing the cost of filter data processing while ensuring the efficiency and accuracy of filter processing.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings.

[0021] Figure 1 It is a schematic diagram of an implementation environment involved in this application.

[0022] Figure 2The figure is a flow chart of a method for processing filtered data according to an exemplary embodiment.

[0023] Figure 3 This is a schematic diagram of the relationship between a sampling clock signal and a filtering clock signal involved in the present application.

[0024] Figure 4 It is a timing diagram of signals and data involved in this application.

[0025] Figure 5 This is a timing diagram of a cache area storing sampled data involved in the present application.

[0026] Figure 6 It is a schematic diagram of a filtering calculation method corresponding to 11-tap involved in this application.

[0027] Figure 7 It is a block diagram of a filtering data processing device according to an exemplary embodiment.

[0028] Figure 8 It is a structural diagram of a computer system of a filtering data processing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0029] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments that are the same as the present application. Instead, they are only examples of devices and methods that are the same as some aspects of the present application as detailed in the attached claims.

[0030] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0031] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, while some operations / steps can be integrated or partially integrated, so the actual execution order may change according to actual conditions.

[0032] It should be noted that the "multiple" mentioned in this application refers to two or more than two. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship.

[0033] It should be noted that in the specific implementation of the present application, when the user-related data is involved, when the embodiment of the present application is applied to a specific product or technology, the user's permission or consent is required, and the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. At the same time, the formulas involved in the embodiments of the present application can be flexibly adjusted, such as increasing or decreasing the corresponding parameters.

[0034] See also Figure 1 , Figure 1 It is a schematic diagram of an implementation environment involved in this application.

[0035] Figure 1 The illustrated implementation environment includes an analog signal 110 , a processing chip 120 , an intermediate buffer area 130 , and a buffer area 140 .

[0036] Among them, the analog signal 110 is an unprocessed original signal, which refers to information expressed by continuously changing physical quantities, such as temperature, humidity, pressure, length, current, voltage, etc. Analog signals are usually called continuous signals, which can have infinite different values ​​within a certain time range.

[0037] The processing chip 120 can sample the analog signal 110, and it can be an analog digital converter (ADC) chip, so that the analog signal 110 can be converted into a digital signal. In addition, in the present application, the processing chip 120 can receive a sampling clock signal, so as to perform data sampling on the analog signal 110 according to the sampling clock signal. Among them, the sampling clock signal is a periodic clock signal, and its frequency can be different according to different processing chip types, for example, it can be 1GSPS, 3.2GSPS, etc., which is not limited in the embodiments of the present application. The processing chip 120 can store the collected sampled data in the intermediate storage area 130 and the cache area 140.

[0038] The intermediate storage area 130 may be a first-in first-out (FIFO) memory. This means that the sampled data that first enters the FIFO memory may be first output from the FIFO memory. In this way, each sampled data collected may be output from the FIFO memory in the order in which it was originally collected.

[0039] The cache area 140 is an area used by the processing chip 120 to store a plurality of sampled data. The cache area 140 includes a plurality of sub-areas, such as a sub-area 141, a sub-area 142, a sub-area 143, and a sub-area 144. It should be noted that the number of sub-areas included in the cache area 140 can be set by a person skilled in the art, for example, it can also be 2 sub-areas, 3 sub-areas, or 4 or more sub-areas.

[0040] In the embodiment of the present application, a sub-region may also store multiple sampling data. For example, the first sub-region 141 may store four sampling data, such as sampling data 0, sampling data 1, sampling data 2, and sampling data 3, and so on.

[0041] See also Figure 2 , Figure 2 is a flowchart of a method for processing filtered data according to an exemplary embodiment. The method can be applied to Figure 1 The implementation environment shown is specifically executed by the processing chip 120. Of course, the method can also be applied to other implementation environments, and the execution subject of the method is not limited here.

[0042] The following will use the processing chip 120 as an exemplary execution subject to describe the filtering data processing method in detail. Figure 2 As shown, in an exemplary embodiment, the method comprises at least the following steps:

[0043] S210 , performing frequency division processing on the sampling clock signal based on a preset filtering frequency division number to obtain a filtering clock signal.

[0044] The preset filter frequency division number can be determined by a person skilled in the art according to the properties of the processing chip. For example, the processing chip can perform data sampling with a sampling clock signal of 3.2 GSPS. However, if the processing chip performs filtering data processing at 3.2 GSPS, it will lead to problems such as incomplete processing and processing errors. Therefore, a preset filter frequency division number can be set to make the filtering clock signal lower in frequency than the sampling clock signal.

[0045] For example, the preset filter frequency division number can be set to 2. If the frequency of the sampling clock signal is 3.2 GHz, a filter clock signal with a frequency of 1.6 GHz can be obtained after dividing by two. For another example, the preset filter frequency division number can be set to 4. If the frequency of the sampling clock signal is 3.2 GHz, a filter clock signal with a frequency of 800 MHz can be obtained after dividing by four, and so on.

[0046] Specifically, the processing chip can detect the sampling frequency corresponding to the sampling clock signal, and then calculate the filtering frequency based on the sampling frequency and the preset filtering frequency division number. When calculating, the sampling frequency can be divided by the preset filtering frequency division number to obtain the filtering frequency. Finally, the filtering clock signal can be generated based on the filtering frequency. It should be noted that the filtering clock signal is generated by dividing the sampling clock signal, so the multiple between the sampling clock signal and the filtering clock signal is the same as the preset filtering frequency division number. In addition, the filtering clock signal and the sampling clock signal are aligned in time. If the filtering clock signal has a level switch (such as a high level switching to a low level, or a low level switching to a high level), then the sampling clock signal will also have a level switch.

[0047] For example, Figure 3 The figure shows a schematic diagram of the relationship between a sampling clock signal and a filtering clock signal involved in the present application. Figure 3 In the example, assuming that the filtering clock signal is obtained by dividing the sampling clock signal by four, the period difference between the two is four times, but the two are aligned in time.

[0048] S220. Within any cycle of the filtering clock signal, a group of sampled data collected is stored in a first sub-area of ​​the cache area, and another group of sampled data stored in the first sub-area of ​​the previous cycle is transferred to a second sub-area of ​​the cache area; wherein the number of sampled data in each group of sampled data is the same as the preset filtering frequency division number.

[0049] Specifically, the processing chip can write a group of newly collected sampled data into the intermediate cache area based on the sampling clock signal. In an embodiment of the present application, the number of sampled data in each group of sampled data is the same as the preset filter number. For the sake of example, the present application takes the preset filter division number as 4 as an example, that is, each group of sampled data contains 4 sampled data. Next, the processing chip needs to store the earliest group of sampled data stored in the intermediate cache area in the first sub-area of ​​the cache area within any cycle of the filter clock signal. The intermediate cache area can be a FIFO memory, which can store at least one group of sampled data.

[0050] In one embodiment of the present application, when the processing chip writes a group of newly collected sampling data into the intermediate cache area based on the sampling clock signal, it is specifically necessary to first generate a write enable signal (fifo_wen) based on the sampling clock signal. Figure 4 The following is a timing diagram of a signal and data involved in this application. Figure 4In the example, it is assumed that the sampling clock signal (clk_sys) is a 3.2Ghz ADC sampling clock signal, and the sampling data (sys_data) is a 3.2Ghz 16-bit wide sampling data. That is to say, in one cycle of the sampling clock signal, the processing chip can collect a 16-bit sampling data, such as Data0, Data1, Data2, etc. Next, the processing chip can combine every 4 sampling data into a 64-bit wide sampling data × 4 (sys_data × 4). For example, Data0, Data1, Data2, and Data3 are combined into Data3210. Then, every 4 cycles of the sampling clock signal, fifo_wen can be enabled so that each sys_data × 4 can be written into the intermediate cache area. For example, in Figure 4 In the process, at the first rising edge of fifo_wen, the processing chip will write Data3210 into the intermediate cache area.

[0051] In one embodiment of the present application, if the processing chip detects that the period from the last trigger to write the sampled data into the intermediate cache area has passed the same period as the preset filter division number based on the sampling clock signal, the latest set of sampled data collected will be written into the intermediate cache area. That is, the processing chip will write the latest set of sampled data collected into the intermediate cache area every time it detects that the fifo_wen signal appears in a high level interval, so that the latest set of sampled data will be continuously stored in the intermediate cache area.

[0052] Since the filtering clock signal is a frequency division process of the sampling clock signal ( Figure 4 The figure shows a four-frequency division process), so we can get Figure 4 clk_d4 in the buffer is an 800M clock signal. When the filter clock signal has a rising edge and the sampled data is stored in the intermediate cache area, the read enable signal (fifo_ren) will also have a rising edge accordingly. Therefore, the processing chip will read the earliest set of sampled data stored in the intermediate cache area and obtain the read data (fifo_rdata) [63:0], where [63:0] represents a 64-bit wide data, such as Data3210, Data7654, etc. Next, the processing chip will split the read data (fifo_rdata) to obtain multiple sampled data, namely sampled data 0 / 1 / 2 / 3 (sample_data0 / 1 / 2 / 3).

[0053] However, in different cycles of the filter clock signal, the sampled data 0 / 1 / 2 / 3 will be different groups of sampled data. For example, Figure 4In the example, the sampling data 0 / 1 / 2 / 3 is Data0~Data3 in a certain cycle, and becomes Data4~Data7 in the next cycle.

[0054] When the filtering clock signal reaches a high level, the processing chip will read the earliest stored set of sampling data in the intermediate cache area, and at the same time, delete the earliest stored set of sampling data from the intermediate cache area to ensure that the intermediate cache area can store other updated sampling data.

[0055] Next, see Figure 5 , Figure 5 This is a timing diagram of a cache area storing sampled data involved in this application. Figure 5 As shown, the cache area includes 4 sub-areas, namely sub-area 1 to sub-area 4, and each sub-area includes 4 cache data bits. The number of cache data bits can be determined by a person skilled in the art based on a preset filter order and a preset filter frequency division number. The number of cache data bits needs to be a multiple of the preset filter frequency division number and is greater than the sum of the preset filter order and the preset filter frequency division number. Therefore, in the present application, assuming that the preset filter order is 11 and the preset filter frequency division number is 4, the cache data bits can be 16, 20, 24, etc. Figure 5 The above is obtained by taking the cache data bit as 16 as an example.

[0056] exist Figure 5 In the case of a filter clock signal at a high level, the processing chip will store a set of sample data corresponding to sample data 0 to sample data 3 in the buffer area. Figure 5 In cycle 1 of the filtering clock signal, the processing chip can store a group of sampled data (Data0~Data3) corresponding to data 0~sampled data 3 in sub-area 1 in the cache area, and store them in sub-area 1 in ascending order, for example, Data0 is stored in cache data bit 12 (buffer_data12), Data1 is stored in cache data bit 13 (buffer_data13), and so on.

[0057] Next, when the filter clock signal enters cycle 2, the sampled data stored in sub-area 1 needs to be transferred to sub-area 2. In this way, sub-area 1 can store new sampled data read from the intermediate cache area, namely Data4~Data7, which are also stored in ascending order. For example, Data4 is stored in cache data bit 12 (buffer_data12), Data5 is stored in cache data bit 13 (buffer_data13), and so on.

[0058] In this way, it is possible to store a group of sampled data collected in the first sub-area of ​​the cache area in any cycle of the filter clock signal, and transfer another group of sampled data stored in the first sub-area in the previous cycle to the second sub-area of ​​the cache area. The first sub-area is used to store the latest sampled data read from the intermediate cache area, and the second sub-area is used to store the sampled data stored in the first sub-area in the previous cycle.

[0059] In one embodiment of the present application, within any cycle of the filtering clock signal, if no sampling data is stored in the first sub-region at this time, there is no need to perform the above-mentioned operation of transferring another set of sampling data stored in the first sub-region in the previous cycle to the second sub-region of the cache area.

[0060] In one embodiment of the present application, if, within any cycle of the filtering clock signal, it is detected that the third sub-area in the cache area has stored sampling data, and the sampling data stored in other sub-areas are to be transferred to the third sub-area, the sampling data stored in the third sub-area is deleted, and the sampling data stored in other sub-areas is transferred to the third sub-area.

[0061] The third sub-region refers to a sub-region in the cache region whose sequence number is the same as the preset filter frequency division number, and the sampling data stored in the third sub-region is the earliest stored in the multiple sub-regions in the cache region. Figure 5 In the buffer area shown, sub-area 4 is the sub-area with the largest sequence number, and it stores the earliest stored sampling data in the four sub-areas. If sampling data is stored in sub-area 4, it means that the buffer area is full of sampling data at this time. If the filter clock signal enters the next cycle, the sampling data in sub-area 4 needs to be deleted and the sampling data of other sub-areas (sub-area 3) needs to be stored.

[0062] It is understandable that in Figure 5In cycle 1 of the filtering clock signal, the processing chip stores Data0~Data3 in sub-area 1; in cycle 2, the processing chip transfers Data0~Data3 to sub-area 2, and stores Data4~Data7 in sub-area 1; in cycle 3, the processing chip transfers Data0~Data3 to sub-area 3, transfers Data4~Data7 to sub-area 2, and stores Data8~Data11 in sub-area 1; in cycle 4, the processing chip transfers Data0~Data3 to sub-area 4, transfers Data4~Data7 to sub-area 3, transfers Data8~Data11 to sub-area 2, and stores Data12~Data15 in sub-area 1; in cycle 5, the processing chip deletes Data0~Data3 from sub-area 4, transfers Data4~Data7 to sub-area 4, transfers Data8~Data11 to sub-area 3, transfers Data12~Data15 to sub-area 2, and stores Data16~Data19 in sub-area 1. In this way, the sampled data in the cache area is updated in rolling groups.

[0063] S230. If, within any period of the filtering clock signal, it is detected that the number of sampling data in the cache area is equal to a preset number threshold, filtering calculation is performed on the earliest set of sampling data stored in the cache area based on a preset filtering order to obtain multiple filtered sampling data corresponding to any period.

[0064] In one embodiment of the present application, in the filtering data processing in the present application, it is necessary to use multiple sampled data for multiplication and addition operations to obtain filtered data. And according to the different preset filter orders, the number of sampled data required to be used is also different. For example, assuming that the preset filter order is 11, the processing chip needs to perform 11-tap filtering calculations, and 11 sampled data are required.

[0065] like Figure 6 The figure shows a schematic diagram of a filtering calculation method corresponding to 11-tap involved in this application. Figure 6 In the figure, 14 sampled data (Data) are displayed. Among them, by filtering Data0~Data10, the filtered sampled data 0 (Data_out0) can be obtained, by filtering Data1~Data11, the filtered sampled data 1 (Data_out1) can be obtained, by filtering Data2~Data12, the filtered sampled data 2 (Data_out2) can be obtained, and so on.

[0066] In any cycle of the filter clock signal, the processing chip detects whether the number of sampled data in the cache area is equal to a preset number threshold, wherein the preset number threshold can be set by a person skilled in the art, for example, the number of cached data bits in the cache area. For example, if the cached data bits are 16, then the preset number threshold can be 16. Because the sampled data are stored in the cache area in the form of a group, the number of sampled data in the cache area is a multiple of the preset filter division number.

[0067] If the number of sampled data in the cache area is equal to the preset number threshold, it means that there are enough sampled data in the cache area for the preset filter order, and filtering calculation can be performed. Specifically, the processing chip needs to obtain multiple sampled data associated with each sampled data in the earliest group of sampled data stored in the cache area; wherein the number of multiple sampled data is the same as the preset filter order. The earliest group of sampled data stored may be stored in the third sub-area, so it can be understood that filtering processing is performed on multiple sampled data in the third sub-area.

[0068] Specifically, when acquiring multiple sample data associated with each sample data, the processing chip detects the target sequence number corresponding to the target sample data; wherein the target sample data is any sample data in the earliest stored set of sample data. Next, the termination sequence number is calculated based on the preset filter order, and the calculation formula is as follows.

[0069] End sequence number = target sequence number + preset filter order - 1.

[0070] For example, if the target sampling signal is Data0, the target sequence number is 0, and the preset filter order is 11, then the termination sequence number can be obtained as 0+11-1=10. If the target sampling signal is Data2, the target sequence number is 2, and the preset filter order is 11, then the termination sequence number can be obtained as 2+11-1=12.

[0071] Next, the processing chip starts from the target sequence number and obtains each sampling data in the order of increasing sequence numbers until the sampling data corresponding to the termination sequence number is obtained, and multiple sampling data associated with the target sampling data are obtained. For example, in the above example, if the target sequence number is 0 and the termination sequence number is 10, the processing chip will obtain Data0~Data10 in the cache area, a total of 11 sampling data, as multiple sampling data associated with Data0. If the target sequence number is 2 and the termination sequence number is 12, the processing chip will obtain Data2~Data12 in the cache area, a total of 11 sampling data, as multiple sampling data associated with Data2.

[0072] Finally, the processing chip calculates the filtered sampling data corresponding to each sampling data based on the multiple sampling data corresponding to the sampling data, and simultaneously outputs the filtered sampling data corresponding to each sampling data in the earliest stored group of sampling data, thereby obtaining multiple filtered sampling data. In other words, the processing chip calculates the corresponding filtered data for each sampling data in the earliest stored group of sampling data, and simultaneously outputs the filtered sampling data corresponding to each sampling data, thereby obtaining multiple filtered sampling data corresponding to the group of sampling data.

[0073] For example, in the above example, the multiple sampled data associated with Data0 are Data0~Data10, then the processing chip will perform filtering operation on Data0~Data10 to obtain the filtered sampled data corresponding to Data0, recorded as Data_out0. For another example, the multiple sampled data associated with Data2 are Data2~Data12, then the processing chip will perform filtering operation on Data2~Data12 to obtain the filtered sampled data corresponding to Data2, recorded as Data_out2, and so on.

[0074] The calculation process of the filtered sampled data may include an algorithm for multiplication and addition, and the specific algorithm is set by a person skilled in the art, and is not limited in the embodiment of the present application. In addition, the filtering calculation of each sampled data in a group of sampled data may be performed in parallel, that is, the processing chip may perform filtering calculations on multiple sampled data at the same time.

[0075] When a group of sampled data in the current cycle of the filter clock signal has calculated and output the corresponding filtered sampled data, the filter clock signal will enter the next cycle, and the "earliest stored sampled data" in the cache area will be updated, so that the processing chip can perform filtering calculations on the updated earliest stored sampled data. This cycle continues, and in each cycle, the sampled data in the cache area is rolling updated according to the group, and the processing chip is also performing rolling filtering calculations on the sampled data of each group.

[0076] In the relevant technology, in chip implementation, high-precision nanotechnology (such as 7 nanometers, 5 nanometers) can handle high-frequency data sampling and digital filtering functions, for example, data sampling and digital filtering can be completed at a rate of 3.2GSPS. However, when the chip process accuracy is reduced (such as 22 nanometers, 28 nanometers), the chip can complete data sampling at a rate of 3.2GSPS, but it is difficult to complete digital filtering at a rate of 3.2GSPS. The reasons include many aspects, such as the large calculation delay of the multiplier and adder, and the inability to complete the filtering calculation of the 16-bit wide sampling data within 0.3125 nanoseconds (i.e., the length of a cycle corresponding to 3.2GSPS), which will cause the filtering calculation result to be inaccurate or erroneous.

[0077] And through the method of the present application, on the one hand, the method reduces the frequency of the filter clock signal by dividing the sampling clock signal, so that the chip can complete the processing of the filter data at a lower frequency. In each filter clock cycle, multiple filtered sampled data can be processed and output, so even if the filter clock frequency is reduced, the amount of filter data output remains consistent with that when there is no frequency division. In addition, the filter cycle is longer after frequency division, so that the processing accuracy of the filter data in each cycle is improved, thereby improving the accuracy and reliability of the filter processing. For example, the present application can reduce the rate of 3.2GSPS to 800MSPS. At this rate, the length of a cycle is 1.25 nanoseconds. The delay of the multiplier and adder is within this cycle length, and 4 filtering calculations with a bit width of 16 bits (a total of 64 bits) can be completed.

[0078] On the other hand, since the frequency of the filter clock signal is reduced, there is no need to use a chip that supports high-frequency processing, but a lower-cost chip that meets the frequency requirements after frequency division can be selected. High-frequency chips are usually expensive, and this method effectively avoids this high-cost requirement, significantly reducing the cost of filter data processing while ensuring the efficiency and accuracy of filter processing.

[0079] Figure 7 FIG. 1 is a block diagram of a filtering data processing device according to an embodiment of the present application. Figure 7As shown, the device includes: a filtering data processing device, including: a processing unit 710, used to perform frequency division processing on a sampling clock signal based on a preset filtering frequency division number to obtain a filtering clock signal; a storage unit 720, used to store a group of collected sampling data in a first sub-area of ​​a cache area within any cycle of the filtering clock signal, and transfer another group of sampling data stored in the first sub-area of ​​the previous cycle to a second sub-area of ​​the cache area; wherein the number of sampling data in each group of sampling data is the same as the preset filtering frequency division number; a calculation unit 730, used to perform filtering calculation on a group of sampling data stored earliest in the cache area based on a preset filtering order if it is detected that the number of sampling data in the cache area is equal to a preset number threshold within any cycle of the filtering clock signal, so as to obtain a plurality of filtered sampling data corresponding to any cycle.

[0080] In one embodiment of the present application, based on the aforementioned scheme, the processing unit 710 is further used to write a group of newly collected sampling data into an intermediate cache area based on a sampling clock signal; wherein the intermediate cache area is used to store at least one group of sampling data; within any cycle of the filtering clock signal, the group of sampling data stored earliest in the intermediate cache area is stored in the first sub-area of ​​the cache area.

[0081] In one embodiment of the present application, based on the aforementioned scheme, the device also includes an acquisition unit 740, which is used to write a set of newly collected sampling data into the intermediate cache area if it is detected based on the sampling clock signal that the period from the last trigger to write the sampling data into the intermediate cache area is the same as the preset filter division number.

[0082] In one embodiment of the present application, based on the aforementioned scheme, the acquisition unit 740 is also used to obtain multiple sampling data associated with the sampling data for each sampling data in the earliest stored group of sampling data; wherein the number of the multiple sampling data is the same as the preset filtering order; the calculation unit 730 is also used to calculate the filtered sampling data corresponding to the sampling data based on the multiple sampling data corresponding to each sampling data; the processing unit 710 is also used to simultaneously output the filtered sampling data corresponding to each sampling data in the earliest stored group of sampling data to obtain multiple filtered sampling data.

[0083] In one embodiment of the present application, based on the aforementioned scheme, the processing unit 710 is also used to detect the target sequence number corresponding to the target sampling data; wherein the target sampling data is any one of a group of sampling data stored earliest; the calculation unit 730 is also used to calculate the termination sequence number based on a preset filtering order; starting from the target sequence number, each sampling data is obtained in the order of increasing sequence numbers until the sampling data corresponding to the termination sequence number is obtained, thereby obtaining multiple sampling data associated with the target sampling data.

[0084] In one embodiment of the present application, based on the aforementioned scheme, the cache area also includes a third sub-area, and the third sub-area is used to store the earliest stored set of sampling data; the processing unit 710 is also used to delete the sampling data stored in the third sub-area if it is detected within any cycle of the filtering clock signal that the third sub-area in the cache area has stored sampling data, and the sampling data stored in other sub-areas are to be transferred to the third sub-area; and transfer the sampling data stored in other sub-areas to the third sub-area.

[0085] In one embodiment of the present application, based on the aforementioned scheme, the processing unit 710 is further used to detect the sampling frequency corresponding to the sampling clock signal; calculate the filtering frequency based on the sampling frequency and the preset filtering frequency division number; and generate the filtering clock signal based on the filtering frequency.

[0086] It should be noted that the apparatus provided in the aforementioned embodiment and the method provided in the aforementioned embodiment belong to the same concept, wherein the specific manner in which each module and unit performs the operation has been described in detail in the method embodiment.

[0087] An embodiment of the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by one or more processors, the electronic device implements the above filtering data processing method.

[0088] An embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the above-mentioned filtering data processing method is implemented.

[0089] Figure 8 It is a structural diagram of a computer system suitable for implementing the filtering data processing device of the embodiment of the present application.

[0090] It should be noted that Figure 8 The computer system 800 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0091] like Figure 8As shown, the computer system 800 includes a central processing unit (CPU) 801, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 802 or the program loaded from the storage part 808 to the random access memory (RAM) 803, such as executing the method in the above embodiment. In the RAM 803, various programs and data required for system operation are also stored. The CPU 801, the ROM 802 and the RAM 803 are connected to each other through the bus 804. The input / output (I / O) interface 805 is also connected to the bus 804.

[0092] The following components are connected to the I / O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed so that a computer program read therefrom is installed into the storage section 808 as needed.

[0093] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 809, and / or installed from a removable medium 811. When the computer program is executed by a central processing unit (CPU) 801, various functions defined in the system of the present application are executed.

[0094] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable medium may be any tangible medium containing or storing a program, which may be used by an instruction execution system, device or device or used in combination with it. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier, in which a computer-readable computer program is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0095] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0096] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not constitute limitations on the units themselves in some cases.

[0097] Another aspect of the present application further provides a computer readable medium having a computer program stored thereon, which implements the above-mentioned filtering data processing method when the computer program is executed by a processor. The computer readable medium may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device.

[0098] Another aspect of the present application also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable medium. A processor of a computer device reads the computer instruction from the computer-readable medium, and the processor executes the computer instruction, so that the computer device executes the filtering data processing method provided in each of the above embodiments.

[0099] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. A person skilled in the art can easily make corresponding changes or modifications based on the main concept and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

Claims

1. A filtering data processing method, characterized in that: include: Perform frequency division processing on the sampling clock signal based on a preset filtering frequency division number to obtain a filtering clock signal; In any cycle of the filtering clock signal, a group of sampled data collected is stored in a first sub-area of ​​the buffer area, and another group of sampled data stored in the first sub-area of ​​the previous cycle is transferred to a second sub-area of ​​the buffer area; wherein the number of sampled data in each group of sampled data is the same as the preset filtering frequency division number; If it is detected that the number of sampled data in the cache area is equal to a preset number threshold in any cycle of the filtering clock signal, filtering calculation is performed on the earliest group of sampled data stored in the cache area based on a preset filtering order to obtain a plurality of filtered sampled data corresponding to any cycle; The filtering calculation is performed on the earliest stored set of sampling data in the cache area based on the preset filtering order to obtain a plurality of filtered sampling data corresponding to any one period, including: For each sampled data in the earliest stored set of sampled data, a plurality of sampled data associated with the sampled data are respectively acquired; wherein the number of the plurality of sampled data is the same as the preset filter order; Calculate filtered sampling data corresponding to each sampling data based on multiple sampling data corresponding to the sampling data; The filtered sampling data corresponding to each sampling data in the earliest stored set of sampling data are outputted simultaneously to obtain the plurality of filtered sampling data.

2. The method according to claim 1, characterized in that The storing of a set of sampled data collected in any cycle of the filtering clock signal into the first sub-area of ​​the buffer area comprises: Based on the sampling clock signal, a group of newly collected sampling data is written into the intermediate buffer area; wherein the intermediate buffer area is used to store at least one group of sampling data; In any cycle of the filtering clock signal, a group of sampling data stored earliest in the intermediate buffer area is stored in the first sub-area of ​​the buffer area.

3. The method according to claim 2, characterized in that The step of writing a group of newly acquired sampling data into the intermediate buffer area based on the sampling clock signal comprises: If it is detected based on the sampling clock signal that a period equal to the preset filter division number has passed since the last trigger to write the sampling data into the intermediate cache area, the latest set of sampling data collected will be written into the intermediate cache area.

4. The method according to claim 1, characterized in that: The step of respectively acquiring a plurality of sampling data associated with each sampling data in the earliest stored set of sampling data comprises: Detecting a target serial number corresponding to target sampling data; wherein the target sampling data is any one of the earliest stored set of sampling data; Calculating a termination sequence number based on the preset filter order; Starting from the target sequence number, each sampling data is acquired in the order of increasing sequence numbers until the sampling data corresponding to the termination sequence number is acquired, thereby obtaining a plurality of sampling data associated with the target sampling data.

5. The method according to claim 1, characterized in that The cache area also includes a third sub-area, and the third sub-area is used to store the earliest stored set of sampling data; the method also includes: If, within any cycle of the filtering clock signal, it is detected that the third sub-region in the cache region has stored sampling data, and the sampling data stored in other sub-regions are to be transferred to the third sub-region, the sampling data stored in the third sub-region is deleted; The sampling data stored in the other sub-areas are transferred to the third sub-area.

6. The method according to claim 1, characterized in that The frequency division process of the sampling clock signal based on the preset filtering frequency division number to obtain the filtering clock signal includes: Detecting a sampling frequency corresponding to the sampling clock signal; Calculating a filtering frequency based on the sampling frequency and the preset filtering frequency division number; The filtered clock signal is generated based on the filtered frequency.

7. A filtering data processing device, characterized in that: include: A processing unit, configured to perform frequency division processing on the sampling clock signal based on a preset filtering frequency division number to obtain a filtering clock signal; A storage unit, used to store a group of sampled data collected in a first sub-area of ​​a cache area in any cycle of the filter clock signal, and transfer another group of sampled data stored in the first sub-area of ​​a previous cycle to a second sub-area of ​​the cache area; wherein the number of sampled data in each group of sampled data is the same as the preset filter frequency division number; a calculation unit, configured to, if it is detected that the number of sampled data in the cache area is equal to a preset number threshold within any period of the filter clock signal, perform filtering calculation on a group of sampled data stored earliest in the cache area based on a preset filter order to obtain a plurality of filtered sampled data corresponding to the any period; The filtering calculation is performed on the earliest stored set of sampling data in the cache area based on the preset filtering order to obtain a plurality of filtered sampling data corresponding to any one period, including: For each sampled data in the earliest stored set of sampled data, a plurality of sampled data associated with the sampled data are respectively acquired; wherein the number of the plurality of sampled data is the same as the preset filter order; Calculate filtered sampling data corresponding to each sampling data based on multiple sampling data corresponding to the sampling data; The filtered sampling data corresponding to each sampling data in the earliest stored set of sampling data are outputted simultaneously to obtain the plurality of filtered sampling data.

8. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enables the electronic device to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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