Analog-to-digital conversion method, device, equipment, acquisition system and storage medium

Abstract

The present application provides an analog-to-digital conversion method, device, equipment, acquisition system and storage medium, which relates to the field of wireless communication technology, including a sampling module, an analog-to-digital conversion module, a phase shift module and a processing module; the sampling module is used to sample the input signal to obtain a sampled signal. The phase shift module is used to determine all clock phases of the analog-to-digital conversion module under the control of the processing module, and the analog-to-digital conversion module is used to convert the sampled signal into a corresponding digital signal at each clock phase. The processing module is used to determine the target phase of the analog-to-digital conversion module according to the signal power of the digital signal corresponding to the clock phase, and determine the target phase as the working phase of the analog-to-digital conversion module; wherein the target clock phase is the clock phase corresponding to the maximum signal power of the digital signal. The present application can provide a technical solution to solve the problem that the high-frequency attenuation of the link between the sampling module and the analog-to-digital conversion module is too large, and the power consumption overhead is high.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to analog-to-digital conversion methods, devices, equipment, acquisition systems and storage media. Background Art

[0002] With the widespread application of data communications and the rapid growth of data traffic, the information transmission rate is getting higher and higher. At present, the international advanced high-speed serial signal rate has reached 112Gbps (Gigabits per second). High-speed signals put forward higher requirements on the bandwidth of data systems.

[0003] The core of the data acquisition system is the analog-to-digital conversion module, and the sampler is an important part of the analog-to-digital conversion module. As the signal transmission rate increases, the sampling rate and bandwidth of the sampler are also increasing. However, as the bandwidth of the sampler becomes higher and higher, due to the skin effect of the transmission medium and its own loss, the transmission link of the sampler usually exhibits a low-pass characteristic, which is manifested as large high-frequency loss.

[0004] In order to compensate for the high-frequency loss of the sampler transmission link, equalization technology can be used. The current equalization technology mainly includes linear equalization and nonlinear equalization. The former can be implemented in analog links or with digital filters; while the latter is a digital equalization filter and cannot be used in the circuit. Compared with nonlinear equalization, linear equalization has real-time performance and can guarantee a certain signal-to-noise ratio. However, traditional linear equalization compensates for high-frequency loss by reducing low-frequency signals. In order to compensate for high-frequency loss, linear equalization requires a larger bandwidth and therefore a larger static current, which will lead to a larger power consumption overhead, which brings challenges to the design and use of samplers. Summary of the invention

[0005] The present application provides an analog-to-digital conversion method, device, equipment, acquisition system and storage medium, which are used to provide a technical solution to solve the problem of excessive high-frequency attenuation and high power consumption of the link between the sampling module and the analog-to-digital conversion module.

[0006] In a first aspect, the present application provides an analog-to-digital conversion device, including a sampling module, an analog-to-digital conversion module, a phase shift module, and a processing module;

[0007] The sampling module is used to sample the input signal to obtain a sampled signal.

[0008] The phase shift module is used to determine all clock phases of the analog-to-digital conversion module under the control of the processing module;

[0009] The analog-to-digital conversion module is used to convert the sampled signal into a corresponding digital signal under the control of the processing module at different clock phases.

[0010] The processing module is used to determine the target clock phase of the analog-to-digital conversion module according to the signal power of the digital signal corresponding to the clock phase, and determine the target clock phase as the working phase of the analog-to-digital conversion module; wherein the target clock phase is the clock phase corresponding to the maximum signal power of the digital signal.

[0011] In the case of adopting the above technical solution, the processing module controls the phase shift module to determine all the clock phases of the analog-to-digital conversion module, and controls the analog-to-digital conversion module to convert the sampling signal into the corresponding digital signal at each clock phase, and determines the target clock phase of the analog-to-digital conversion module according to the signal power of the digital signal corresponding to all the clock phases, wherein the target clock phase is the clock phase corresponding to the maximum signal power among the signal powers of the digital signals corresponding to different clock phases. The target phase is determined as the working clock phase of the analog-to-digital conversion module, that is, the analog-to-digital conversion module is aligned with the clock phase of the sampling module at the target clock phase. It should be understood that when the signal power of the digital signal is the maximum, the clock phase alignment of the analog-to-digital conversion module and the sampling module is achieved. At this time, the signal analog-to-digital conversion module can collect the level of the peak position of the sampling module signal, and the image frequency outside the signal band is folded into the band by the analog-to-digital conversion module, so that the analog-to-digital conversion device can have the best signal quality and gain, and the self-equalization gain of the analog-to-digital conversion device is the maximum.

[0012] Self-equalizing gain refers to the ability of the analog-to-digital conversion device to use its own high-frequency gain to compensate for attenuation and distortion during signal transmission. Therefore, when the working phase of the analog-to-digital conversion module is the target phase, the analog-to-digital conversion device can compensate for high-frequency attenuation. Therefore, the present application does not need to compensate for high-frequency attenuation by reducing low-frequency signals, and can solve the problem of excessive high-frequency attenuation between the sampling module and the analog-to-digital conversion module. And because the technical solution of the present application does not require a larger bandwidth, it does not require a larger static current, and will not lead to a larger power consumption overhead.

[0013] In an optional implementation, the analog-to-digital conversion device further includes: a buffer module; the buffer module is used to smooth the sampled signal, or to store the sampled signal, or to smooth the sampled signal and store the smoothed sampled signal.

[0014] When adopting the above technical solution, the buffer module can not only be used to temporarily store the sampling signal output by the sampling module to optimize signal transmission and processing, but also smooth the instantaneous fluctuation of the sampling signal and reduce the noise and interference that may be introduced during the signal transmission process, thereby improving the input signal quality of the analog-to-digital conversion module.

[0015] In an optional implementation, the analog-to-digital conversion device further includes: a clock signal generating module;

[0016] The clock signal generation module is used to provide the same source clock signal to the sampling module, the analog-to-digital conversion module and the phase shift module respectively.

[0017] When the above technical solution is adopted, the clock signal generation module can be used to provide the same source clock signal to the sampling module, the analog-to-digital conversion module and the phase shift module respectively, thereby improving the overall synchronization of the analog-to-digital conversion and the accuracy of data processing.

[0018] In an optional implementation, the analog-to-digital conversion device further includes: a low-pass filtering module, and the low-pass filtering module is used to suppress the image frequency signal in the sampling signal.

[0019] In an optional implementation, the sampling module includes a voltage-type sample-and-hold device, and the low-pass filtering module includes any one of a Butterworth filter, a Chebyshev filter, an elliptic filter, a Bessel filter, or a Gaussian filter.

[0020] In an optional implementation, the voltage-type sample-and-hold device includes a buffer, a first switch unit, and a first storage unit;

[0021] One end of the buffer is used to receive an input signal, and the other end is connected to the first end of the first switch unit;

[0022] The second end of the first switch unit is connected to the first storage unit, and the control end of the first switch unit is connected to the clock signal generating module, and is used to be turned on or off under the control of the clock signal generated by the clock signal generating module to implement sampling of the input signal.

[0023] In an optional implementation, the bandwidth of the sampling module is greater than the bandwidth of the low-pass filter, and the bandwidth of the low-pass filter is greater than the bandwidth of the analog-to-digital conversion module.

[0024] In the case of adopting the above technical solution, the bandwidth of the sampling module is greater than the bandwidth of the low-pass filter, which can effectively suppress the image frequency and ensure the normal operation of the analog-to-digital conversion device. The bandwidth of the low-pass filter is greater than the bandwidth of the analog-to-digital converter, so that the filtered signal can be completely converted by the analog-to-digital converter.

[0025] In an optional implementation, the sampling module includes a current-type sample-and-hold device, and the low-pass filter includes any one of a Bessel filter, a Chebyshev filter, or a Butterworth filter.

[0026] In an optional implementation, the current-type sample-and-hold device includes a current-to-voltage converter, a second switch unit, and a second storage unit;

[0027] One end of the current-to-voltage converter is used to receive an input signal, and the other end is connected to the first end of the second switch unit;

[0028] The second end of the second switch unit is connected to the second storage unit, and the control end of the second switch unit is connected to the clock signal generating module, and is used to be turned on or off under the control of the clock signal generated by the clock signal generating module to implement sampling of the input signal.

[0029] In an optional implementation, the input signal is a single tone signal or a square wave signal;

[0030] The frequency of the input signal is the Nyquist frequency of the sampling module.

[0031] In a second aspect, the present application provides a data acquisition system, comprising the analog-to-digital conversion device of the first aspect of claim 1.

[0032] In a third aspect, the present application provides an analog-to-digital conversion method, which is applied to the analog-to-digital conversion device of any one of the first aspects, and the method includes:

[0033] Acquire a sampling signal obtained by sampling the input signal by the sampling module;

[0034] Controlling the phase shift module to determine all clock phases of the analog-to-digital conversion module;

[0035] Obtaining a corresponding digital signal obtained by converting the sampled signal by the analog-to-digital conversion module at each clock phase;

[0036] The target phase of the analog-to-digital conversion module is determined according to the signal power of the digital signal corresponding to the clock phase, and the target phase is determined as the working phase of the analog-to-digital conversion module.

[0037] In an optional embodiment, the method further includes:

[0038] Provide the same source clock signal to the sampling module, analog-to-digital conversion module and phase shift module.

[0039] In an optional embodiment, the method further includes:

[0040] Based on the low-pass filter module, the sampling signal is filtered to obtain a filtered sampling signal;

[0041] The analog-to-digital conversion module obtains the corresponding digital signal obtained after converting the sampled signal at each clock phase, including:

[0042] The analog-to-digital conversion module obtains a corresponding digital signal after converting the filtered sampling signal at each clock phase.

[0043] In an optional implementation, the input signal is a single tone signal or a square wave signal;

[0044] The frequency of the input signal is the Nyquist frequency of the sampling module.

[0045] In a fourth aspect, the present application also provides an analog-to-digital conversion device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the program is executed by the processor, any one of the methods in the third aspect is implemented.

[0046] In a fifth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in any one of the third aspects is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0048] Figure 1 A schematic diagram of an application scenario provided for an embodiment of the present application;

[0049] Figure 2 A schematic diagram of the structure of an analog-to-digital conversion device provided in an embodiment of the present application;

[0050] Figure 3 A schematic diagram of the specific structure of an analog-to-digital conversion device provided in an embodiment of the present application;

[0051] Figure 4 A circuit diagram of a Butterworth filter provided in an embodiment of the present application;

[0052] Figure 5 A schematic diagram of an output signal power corresponding to a clock phase of an analog-to-digital conversion device provided in an embodiment of the present application;

[0053] Figure 6 A graph showing a spectrum gain result of a self-equalization of an analog-to-digital conversion device provided in an embodiment of the present application;

[0054] Figure 7 A schematic diagram of the specific structure of another analog-to-digital conversion device provided in an embodiment of the present application;

[0055] Figure 8 A schematic diagram of a 4th-order Bessel filter provided in an embodiment of the present application;

[0056] Fig. 9 A flowchart of an analog-to-digital conversion method is provided for an embodiment of the present application;

[0057] Fig.10 A structural diagram of an analog-to-digital conversion device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. It is understood that the terms "first", "second", etc. used in the present application can be used to describe various information or data in this article, but these elements are not limited by these terms. These terms are only used to distinguish the first information from another information. For example, without departing from the scope of the present application, the first action information can be referred to as the second action information, and similarly, the second action information can be referred to as the first action information. Both the first action information and the second action information are action information, but they are not the same action information.

[0060] The analog-to-digital conversion device provided in this application can be applied to Figure 1 In the data acquisition system shown in Figure 1 As shown in the figure, the data acquisition system includes an analog-to-digital converter and a sampler. As the signal transmission rate of the data acquisition system increases, the sampling rate and bandwidth of the sampler are also getting higher and higher, which makes the transmission link between the sampler and the analog-to-digital converter exhibit low-pass characteristics and increase high-frequency loss. Currently, high-frequency attenuation is compensated by reducing low-frequency signals, but this will cause the data acquisition system to have a large power consumption overhead.

[0061] In response to the above problems, the present application proposes: through the clock phase alignment technology of the sampling module and the analog-to-digital conversion module, the high-frequency gain of the analog-to-digital conversion device is achieved to be greater than the low-frequency gain, thereby providing a technical problem of excessive high-frequency attenuation in the link between the sampling module and the analog-to-digital conversion module without reducing the low-frequency signal to compensate for the high-frequency attenuation.

[0062] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0063] Reference Figure 2An embodiment of the present application provides an analog-to-digital conversion device, including a sampling module, an analog-to-digital conversion module, a phase shift module and a processing module; the sampling module is connected to the analog-to-digital conversion module, and the phase shift module is connected to the analog-to-digital conversion module and the processing module.

[0064] The sampling module is used to sample the input signal to obtain a sampled signal.

[0065] In practice, the sampling module samples the input signal according to a predetermined sampling frequency, wherein the input signal is generally an analog signal. The predetermined sampling frequency can be controlled by a clock signal to ensure synchronization and stability of the sampling process.

[0066] In some examples, the sampling module may include a sampler, which may be any type of sampler and is not particularly limited in the embodiments of the present application.

[0067] The sampler may include a zero-order hold sampler, an ideal sampler or a natural sampler.

[0068] The phase shift module is used to determine all clock phases of the analog-to-digital conversion module under the control of the processing module.

[0069] For example, under the control of the processing module, the phase shifting module may traverse all clock phases of the analog-to-digital conversion module to determine all clock phases of the analog-to-digital conversion module.

[0070] Optionally, the phase shifting module may be a phase shifter.

[0071] In this embodiment, the phase shifter can traverse the 360° phase of the analog-to-digital conversion module clock under the control of the control module to determine the 360° phase of the analog-to-digital conversion module clock.

[0072] The above-mentioned phase shifter may include an analog phase shifter, a digital phase shifter or a variable phase shifter, and the embodiments of the present application do not impose any special limitation on this.

[0073] The analog-to-digital conversion module is used to convert the sampling signal into a corresponding digital signal in a clock phase under the control of the processing module.

[0074] Optionally, the above-mentioned analog-to-digital conversion module can be an analog-to-digital converter. Based on this, the processing module controls the analog-to-digital converter to convert the sampling signal into a corresponding digital signal in each clock phase. Afterwards, the analog-to-digital converter determines the optimal clock phase alignment point with the sampler according to the clock phase determined by the above-mentioned phase shifter, and uses the optimal clock phase as the target clock phase.

[0075] In some examples, the processing module can be used to determine the target clock phase of the analog-to-digital conversion module based on the signal power of the digital signals corresponding to all the clock phases, and determine the target clock phase as the working clock phase of the analog-to-digital conversion module. The target clock phase is the clock phase corresponding to the maximum signal power of the digital signal. In other words, the processing module can select the clock phase corresponding to the maximum signal power from the signal power of the digital signals corresponding to all the clock phases as the target clock phase.

[0076] In the embodiment of the present application, the processing module is used to control the clock phase adjustment, signal power calculation and target clock phase determination of the analog-to-digital conversion module. The processing module can be a microprocessor, a digital signal processor or an application-specific integrated circuit, and the embodiment of the present application does not make any special limitation on this.

[0077] Based on the above description, the analog-to-digital conversion module is aligned with the clock phase of the sampling module at the target clock phase. It should be understood that when the signal power of the digital signal is the maximum, the analog-to-digital conversion module and the sampling module are aligned, so that the analog-to-digital conversion device can have the best signal quality and gain, and the self-equalization gain of the analog-to-digital conversion device is the maximum.

[0078] Self-balancing gain refers to the ability of the analog-to-digital conversion device to use its own high-frequency gain to compensate for the attenuation and distortion during signal transmission. Therefore, when the working phase of the analog-to-digital conversion module is the target phase, the analog-to-digital conversion device can achieve the maximum self-balancing gain to compensate for the high-frequency attenuation. The present application does not need to compensate for the high-frequency attenuation by reducing the low-frequency signal, so as to solve the problem of excessive high-frequency attenuation between the sampling module and the analog-to-digital conversion module. And because the present application does not require a larger bandwidth, it does not require a larger static current and will not lead to a larger power consumption overhead.

[0079] In some examples, the maximum self-equalization gain of the analog-to-digital conversion device may be 6 dB.

[0080] In an optional embodiment, the processing module is specifically used for:

[0081] The signal power of the digital signal corresponding to each of the clock phases is calculated.

[0082] The signal power may be obtained by calculating the root mean square (RMS) of the digital signal or other power indicators, and the embodiments of the present application do not impose any special limitation on this.

[0083] The clock phase corresponding to the maximum power among the signal powers of the corresponding digital signals is determined as the target phase, and the target phase is determined as the working phase of the analog-to-digital conversion module.

[0084] It should be understood that since the clock phase alignment of the analog-to-digital conversion module and the sampling module is achieved when the signal power is maximum, the analog-to-digital conversion device can have the best signal quality and gain. At this time, the self-equalization gain of the analog-to-digital conversion device is maximum. Therefore, the clock phase corresponding to the maximum power in the signal power of the digital signal is determined as the working phase of the analog-to-digital conversion module, which can ensure that the analog-to-digital conversion device performs sampling and conversion at the optimal clock phase, and the self-equalization gain of the analog-to-digital conversion device can be maximized.

[0085] In some examples, in order to ensure that the modules of the analog-to-digital conversion device in this embodiment operate under the same time reference, the analog-to-digital conversion device may further include: a clock signal generating module.

[0086] The clock signal generating module is respectively connected to the sampling module, the analog-to-digital conversion module and the phase shifting module, and is used to provide the same source clock signal to the sampling module, the analog-to-digital conversion module and the phase shifting module, so as to improve the overall synchronization of the analog-to-digital conversion and the accuracy of data processing.

[0087] Optionally, a frequency divider or frequency multiplier can be set between the clock signal generation module and the sampling module, the analog-to-digital conversion module and the phase shift module, so that the clock signal provided by the clock signal generation module to the sampling module, the analog-to-digital conversion module and the phase shift module can meet the needs of the corresponding modules. The frequency divider or frequency multiplier is used to adjust the frequency of the clock signal. Specifically, the frequency divider can reduce the frequency of the clock signal to adapt to the module that requires a lower frequency clock signal; while the frequency multiplier can increase the frequency of the clock signal to meet the module that requires a higher frequency clock signal. In this way, each module can operate at its optimal operating frequency, thereby improving the overall performance and reliability of the system.

[0088] In some examples, the analog-to-digital conversion device may further include: a buffer module, wherein the buffer module is disposed between the sampling module and the analog-to-digital conversion module.

[0089] The buffer module may be a buffer, which may be used to temporarily store the sampling signal output by the sampling module to optimize signal transmission and processing.

[0090] Specifically, the buffer module can smooth the instantaneous fluctuation of the sampling signal and reduce the noise and interference that may be introduced during the signal transmission process, thereby improving the input signal quality of the analog-to-digital conversion module.

[0091] Furthermore, by providing a buffer between the sampling module and the analog-to-digital conversion module, the stability and integrity of the signal can be ensured, thereby improving the overall performance of the device and the accuracy of data processing.

[0092] In some examples, in order to suppress the image frequency signal of the sampling signal output by the sampling module, the analog-to-digital conversion device provided by the embodiment of the present application further includes a low-pass filter. The low-pass filter is arranged between the sampling module and the analog-to-digital conversion module.

[0093] Optionally, the low-pass filter may be a low-pass filter with an out-of-band roll-off characteristic. Out-of-band roll-off refers to the rate at which the signal attenuates in the frequency range outside the filter's cutoff frequency. The cutoff frequency is the boundary of the filter's passband, and at the cutoff frequency point, the filter begins to significantly attenuate the amplitude of the input signal.

[0094] It should be understood that the spectrum of the input signal will produce image frequencies at integer multiples of the sampling frequency of the sampling module. Through proper design, these image frequencies can be used to enhance high-frequency signals. The low-pass filter allows low-frequency signals to pass while attenuating high-frequency signals. By designing a low-pass filter with an out-of-band roll-off characteristic, the desired frequency response can be achieved within the band of the low-pass filter. The out-of-band roll-off can help suppress low-frequency signals while allowing high-frequency signals to pass.

[0095] Based on this, the embodiments of the present application can achieve the desired frequency response by determining the cutoff frequency, order and other parameters of the filter. By reasonably selecting the sampling frequency and filter parameters, the mirror frequency generated during the sampling process can be used to enhance the gain of the high-frequency signal. The out-of-band roll-off characteristics of the filter can achieve the high-frequency gain of the analog-to-digital conversion device being greater than the low-frequency gain.

[0096] Optionally, the embodiment of the present application can select the cutoff frequency of the filter so that the filter can provide a higher gain in the high frequency range. The order of the filter determines the steepness of the out-of-band roll-off. A higher order can more effectively suppress unwanted frequency components. Therefore, the low-frequency part of the signal can be suppressed by selecting the order of the filter. It is also possible to select the sampling frequency of the filter so that the filter produces a favorable image frequency during the sampling process. Among them, the image frequency can be combined with the frequency response of the filter to enhance the gain of the high-frequency signal.

[0097] In this embodiment, the sampling module is used to sample the input signal to obtain a sampled signal. The sampling module may include a voltage-type sample-and-hold device or a current-type sample-and-hold device. The following describes the case where the sampling module is a voltage-type sample-and-hold device and the sampling module is a current-type sample-and-hold device using different embodiments.

[0098] In one embodiment, referring to Figure 3When the sampling module is a voltage-type sample-and-hold device, the low-pass filter may be a Butterworth filter, a Chebyshev filter, an elliptic filter, a Bessel filter or a Gaussian filter, or other analog filters with similar roll-off.

[0099] The voltage type sample-and-hold device is usually a tracking-and-hold type sampler. Inside, the input voltage signal passes through the input buffer and then the clock-controlled switch tube charges and discharges the capacitor to realize the sampling process of the input signal. Its structure is a charging and discharging of the capacitor by the input voltage.

[0100] Optionally, the voltage type sample and hold device may include a buffer, a first switch unit and a first storage unit. One end of the buffer is used to receive the input signal, and the other end is connected to the first end of the first switch unit. The second end of the first switch unit is connected to the first storage unit, and the control end is connected to the clock signal generating module, and is used to be turned on or off under the control of the clock signal generated by the clock signal generating module to achieve sampling of the input signal.

[0101] Reference Figure 3 The first switch unit may use a switch tube Q1 to control the sampling time according to the clock signal generated by the clock generation module. The first storage unit may use a capacitor element C1 to store the sampled voltage signal. The buffer may be used to isolate the capacitor element from the subsequent circuit to prevent the voltage on the capacitor element from changing due to the load effect.

[0102] The specific functions implemented by the voltage-type sample-and-hold device may include: in the sampling phase, the first switch unit is turned on, the input signal is added to the first storage unit through the first switch unit, and the first storage unit is charged to the voltage value of the input signal. In the holding phase, the first switch unit is turned off, and the voltage stored in the first storage unit is output through the buffer and remains unchanged until the next sampling.

[0103] It should be understood that the above-mentioned first switch unit and first storage unit can be virtual units or logical function units, and are not used to limit the actual circuit structure. Other circuit structures with the same functions as these devices can also be applied to the embodiments of the present application.

[0104] The low-pass filter has a preset bandwidth and out-of-band roll-off characteristics to suppress the image frequency of the output signal from the sampling module, and the size of the out-of-band roll-off is adjusted by designing different inductance and capacitance values ​​and orders, thereby achieving different balanced frequency ranges and gains. The capacitance, inductance and order are preset parameters of the filter, which can be determined in combination with the requirements of the analog-to-digital conversion device.

[0105] It should be understood that the narrower the bandwidth of the filter, the faster it can suppress the image frequency from the output signal of the sampling module, and the steeper the out-of-band roll-off of the low-pass filter, the more effectively it can suppress the image frequency. Therefore, the embodiment of the present application can reasonably set the bandwidth and out-of-band roll-off characteristics of the low-pass filter according to actual needs.

[0106] Optional, see Figure 4 , shows a circuit diagram of a Butterworth filter, wherein Rs is the input load resistance, RL is the output load resistance; C1, L2, C3, L4, and C5 are cascaded to form a 5th-order π-type Butterworth filter.

[0107] In some examples, the bandwidth of the sampling module is greater than the bandwidth of the low-pass filter, and the bandwidth of the low-pass filter is greater than the bandwidth of the analog-to-digital conversion module.

[0108] It should be understood that the voltage type sample-and-hold device is a tracking-and-hold type sampler, and its output waveform has a large number of image frequencies due to the first-order hold. The image frequencies are generated by the spectrum aliasing effect during the sampling process, and these frequency components will affect the quality of the signal and the performance of the device.

[0109] In order to effectively suppress the image frequency and ensure the normal operation of the analog-to-digital converter, the sampling rate of the voltage-type sample-and-hold device should be at least twice the bandwidth of the low-pass filter (i.e., satisfy the Nyquist sampling theorem). In addition, the bandwidth of the voltage-type sample-and-hold device must be greater than the bandwidth of the low-pass filter so that the voltage-type sample-and-hold device can accurately capture all required signal components. The bandwidth of the low-pass filter is greater than the bandwidth of the analog-to-digital converter, so that the filtered signal can be completely converted by the analog-to-digital converter.

[0110] In this embodiment, the sampling module is phase-aligned with the analog-to-digital conversion module clock. The input signal is a single-tone signal or a square wave signal with a frequency close to the Nyquist frequency. The control module controls the phase shift module to traverse the 360° phase of the analog-to-digital conversion module clock. At the same time, the analog-to-digital conversion module collects signals at different phases and calculates the signal power. When the signal power is maximum, the phase alignment is completed. At this time, the self-equalization gain can reach a maximum of 6dB.

[0111] Figure 5 When the delay of the phase shifter changes in the range of 0~75ps, the power curve of the signal collected by the analog-to-digital conversion device changes at different delays, where the horizontal axis represents the delay and the vertical axis represents the amplitude ratio of the signal gain. It can be seen that the amplitude ratio of the signal gain will also change corresponding to different delays of the same signal, so that the delay position with the maximum signal power can be determined, and then the delay position is converted to the frequency domain to obtain the clock phase when the signal power is maximum.

[0112] Reference Figure 6, the Butterworth filters are 3rd, 7th, and 8th order, respectively. Under the condition of capacitor and inductor as preset parameters, the self-equalized spectrum gain results show that the 3rd, 7th, and 8th order Butterworth filters achieve self-equalizing gains at Nyquist frequency positions of 2.5dB, 1.5dB, and 2.8dB, respectively. This shows that different gains can be achieved at Nyquist frequency positions by designing low-pass filters of different orders. Among them, the preset parameters can be set according to specific circumstances, and the embodiments of the present application do not make specific limitations on this.

[0113] In another embodiment, referring to Figure 7 When the sampling module is a current-type sample-and-hold device, the low-pass filter may be any one of a Bessel filter, a Chebyshev filter or a Butterworth filter.

[0114] A current sample-and-hold device is a device that samples a current signal and holds its value. It has the characteristics of high input impedance and low output impedance and can effectively capture and hold transient current signals.

[0115] The Bessel filter is a low-pass filter with a linear phase response. Its main feature is to provide a constant group delay within the passband, thereby preserving the waveform characteristics of the signal. Due to this characteristic of the Bessel filter, it is more effective in processing applications that need to maintain the integrity of the signal waveform, and is suitable for the output signal processing of the current-type sample-and-hold device. Specifically, the Bessel filter can be used to filter out high-frequency noise and interference in the output signal of the current-type sample-and-hold device, while retaining the waveform characteristics and phase information of the signal. In this way, the quality of the analog-to-digital converter input signal can be improved, ensuring the overall performance of the device and the accuracy of data processing. The Bessel filter has an out-of-band roll-off characteristic, and the desired out-of-band roll-off characteristic can be obtained by setting the order of the Bessel filter.

[0116] The Chebyshev filter has a fast roll-off characteristic in the frequency response and is suitable for applications that require fast out-of-band attenuation and can tolerate passband fluctuations. The desired out-of-band roll-off characteristic can be obtained by setting the order of the Chebyshev filter.

[0117] Butterworth filter is a commonly used filter type. Compared with Chebyshev filter, Butterworth filter has a slower out-of-band roll-off. In order to obtain a steeper roll-off, the order of the filter can be increased. In addition, the embodiment of the present application can also adjust the parameters of the selected low-pass filter according to the specific application requirements to optimize the filtering effect and performance.

[0118] For example, refer to Figure 8 , the Bessel filter in this application is a 4th-order Bessel filter.

[0119] Specifically, the current sampler converts the input voltage signal into a current signal through a transconductance amplifier, and charges and discharges the capacitor through a clock-controlled switch tube, that is, the current sampler charges and discharges the capacitor with a current signal. The output waveform of the current sampler is slightly different from that of the voltage sampler, but both have mirror frequencies. After passing through the Bessel filter, the waveforms of the two are basically the same.

[0120] Optionally, the current-type sample-and-hold device includes a current-to-voltage converter (eg, a transconductance amplifier), a second switch unit, and a second storage unit.

[0121] One end of the current-to-voltage converter is used to receive the input signal, and the other end is connected to the first end of the second switch unit; the current-to-voltage converter can be a transconductance amplifier, which is used to convert the input analog voltage signal into an analog current signal.

[0122] The second end of the second switch unit is connected to the second storage unit, and the control end of the second switch unit is connected to the clock signal generating module, and is used to be turned on or off under the control of the clock signal generated by the clock signal generating module to achieve sampling of the input signal.

[0123] Reference Figure 7 The second switch unit may be a transistor Q2, which is used to control the sampling time according to the clock signal generated by the clock generation module. The second storage unit may be a capacitor element C2, which is used to store the sampled current signal.

[0124] The specific functions implemented by the current-type sample-and-hold device may include: in the sampling phase, the second switch unit is turned on, the analog current signal enters the second storage unit through the second switch unit, and the voltage of the second storage unit begins to change with the current. In the holding phase, the second switch unit is turned off, the voltage of the second storage unit is locked, and the transconductance amplifier outputs a current signal proportional to the voltage of the second storage unit, keeping the value of the input current signal unchanged.

[0125] It should be understood that the above-mentioned second switch unit and second storage unit can be a specific representation of the abstract circuit structure and is not used to limit the actual circuit structure. Other circuit structures with the same functions as these devices can also be applied to the embodiments of the present application.

[0126] In another embodiment, the analog-to-digital conversion device may not need to be configured with a low-pass filter, and the out-of-band image frequency may be suppressed through high-speed interconnection such as on-board wiring or the attenuation of the coaxial cable itself, thereby improving the high-frequency gain.

[0127] The present application also provides a data acquisition system, comprising the aforementioned Figure 1-Figure 7 An analog-to-digital conversion device is provided in any of the embodiments shown.

[0128] It should be understood that the data acquisition system includes the above-mentioned analog-to-digital conversion device, and the beneficial effects achieved by the data acquisition system are the same as those of the above-mentioned Figure 2-Figure 8 The beneficial effects of the analog-to-digital conversion device provided in the illustrated embodiment are the same and will not be described in detail here.

[0129] Reference Fig. 9 The present application also provides an analog-to-digital conversion method, which can be applied to the aforementioned Figure 1-Figure 7 The analog-to-digital conversion device in any of the embodiments shown includes the following steps:

[0130] S100, obtaining a sampled signal obtained by a sampling module by sampling an input signal.

[0131] The description of the sampling module and the sampling signal can refer to the analog-to-digital conversion device, and will not be repeated here.

[0132] S200, controlling the phase shift module to determine all clock phases of the analog-to-digital conversion module;

[0133] S300, obtaining a corresponding digital signal obtained by an analog-to-digital conversion module after performing analog-to-digital conversion on a sampling signal at each clock phase.

[0134] Similarly, the description of the shift module and the analog-to-digital conversion module here can refer to the analog-to-digital conversion device, and will not be repeated here.

[0135] S400, determining the target phase of the analog-to-digital conversion module according to the signal power of the digital signal corresponding to the above clock phase, and determining the target phase as the working phase of the analog-to-digital conversion module. In some examples, the method can be used to determine the target clock phase of the analog-to-digital conversion module according to the signal power of the digital signal corresponding to each clock phase, and determine the target clock phase as the working clock phase of the analog-to-digital conversion module. The above target clock phase is the clock phase corresponding to the maximum signal power of the digital signal.

[0136] In an embodiment of the present application, the method is used to control the clock phase adjustment, signal power calculation and target clock phase determination of the analog-to-digital conversion module.

[0137] Based on the above description, the analog-to-digital conversion module is aligned with the clock phase of the sampling module at the target clock phase. It should be understood that when the signal power of the digital signal is the maximum, the analog-to-digital conversion module and the sampling module are aligned, so that the analog-to-digital conversion device can have the best signal quality and gain, and the self-equalization gain of the analog-to-digital conversion device is the maximum.

[0138] Self-balancing gain refers to the ability of the analog-to-digital conversion device to have its own high-frequency gain to compensate for attenuation and distortion during signal transmission. Therefore, when the working phase of the analog-to-digital conversion module is the target phase, the analog-to-digital conversion device can achieve the maximum self-balancing gain to compensate for high-frequency attenuation. Therefore, this application does not need to compensate for high-frequency attenuation by reducing low-frequency signals, and can solve the problem of excessive high-frequency attenuation between the sampling module and the analog-to-digital conversion module. And because this application does not require a larger bandwidth, it does not require a larger static current, and will not lead to a larger power consumption overhead.

[0139] Optionally, determining a target phase of the analog-to-digital conversion module according to the signal power of the digital signal corresponding to the different clock phases, and determining the target phase as the working phase of the analog-to-digital conversion module may include:

[0140] The signal power of the digital signal corresponding to different clock phases is calculated. The signal power can be obtained by calculating the mean square value or other power index of the digital signal, and the embodiment of the present application does not make any special limitation on this.

[0141] The clock phase corresponding to the maximum power among the signal powers of the corresponding digital signals is determined as the target phase, and the target phase is determined as the working phase of the analog-to-digital conversion module.

[0142] It should be understood that since the clock phase alignment of the analog-to-digital conversion module and the sampling module is achieved when the signal power is maximum, the analog-to-digital conversion device can have the best signal quality and gain. At this time, the self-equalization gain of the analog-to-digital conversion device is maximum. Therefore, the method determines the target phase as the working phase of the analog-to-digital conversion module, which can ensure that sampling and conversion are performed at the optimal clock phase of the analog-to-digital conversion device, and the self-equalization gain of the analog-to-digital conversion device can be maximized.

[0143] In some examples, reference Fig. 9 In order to ensure that the modules of the analog-to-digital conversion device in this embodiment operate under the same time reference, before step S100, the method further includes:

[0144] S101, providing a homologous clock signal to a sampling module, an analog-to-digital conversion module, and a phase shift module.

[0145] Based on this, the overall synchronization of the method and the accuracy of data processing can be improved.

[0146] Optionally, the method can divide or multiply the homologous clock signal and provide it to the sampling module, analog-to-digital conversion module and phase shift module to meet the needs and structures of each module. In this way, each module can operate at its optimal operating frequency, thereby improving the overall performance and reliability of the system.

[0147] In one example, in order to suppress the mirror frequency signal of the sampling signal output by the sampling module, after acquiring the sampling signal obtained by the sampling module sampling the input signal, the method also includes: filtering the sampling signal based on a low-pass filtering module to obtain a filtered sampling signal; wherein the low-pass filtering module includes a low-pass filtering module with out-of-band roll-off.

[0148] In this example, the above step S300 may specifically include:

[0149] The analog-to-digital conversion module obtains a corresponding digital signal after converting the filtered sampling signal under different clock phases.

[0150] It should be understood that the spectrum of the input signal will generate image frequencies at integer multiples of the sampling frequency of the sampling module. And through reasonable design, these image frequencies can be used to enhance high-frequency signals. The low-pass filter module allows low-frequency signals to pass through while attenuating high-frequency signals. By designing a low-pass filter module with an out-of-band roll-off characteristic, the required frequency response can be achieved within the band of the low-pass filter module. The out-of-band roll-off can help suppress low-frequency signals while allowing high-frequency signals to pass. Based on this, the image frequencies generated during the sampling process can be used to enhance the gain of high-frequency signals, and the out-of-band roll-off characteristics of the low-pass filter can achieve the high-frequency gain of the above method to be greater than the low-frequency gain.

[0151] In one example, the input signal is a single tone signal or a square wave signal.

[0152] The frequency of the input signal is the Nyquist frequency of the sampling module.

[0153] Specifically, a single tone signal is a sine wave signal with a single frequency component, while a square wave signal contains multiple harmonic components. The Nyquist frequency is half the sampling rate.

[0154] For example, if the sampling rate of the sampling module is 100 MHz, the Nyquist frequency is 50 MHz. In this case, if the input signal is a single-tone signal, its frequency is 50 MHz; if the input signal is a square wave signal, its fundamental frequency is 50 MHz.

[0155] It should be understood that since the single tone signal is a sine wave signal with a single frequency component, its power is concentrated at the frequency point, so it can accurately reflect the signal power of the frequency point, and thus accurately obtain the clock phase of the maximum signal power of the single tone signal.

[0156] The power of the square wave signal is distributed at multiple frequency points, such as the fundamental frequency and harmonic frequency points. Therefore, the square wave signal can better reflect the signal power at a specific frequency point, and thus accurately obtain the clock phase of the maximum signal power of the single-tone signal.

[0157] The present application also provides an analog-to-digital conversion device, Fig.10 This is a schematic diagram of the structure of the analog-to-digital conversion device provided in the embodiment of the present application. Fig.10 As shown, the analog-to-digital conversion device may include: a transceiver 121 , a processor 122 , and a memory 123 .

[0158] The processor 122 executes the computer-executable instructions stored in the memory, so that the processor 122 executes the scheme in the above-mentioned analog-to-digital conversion method embodiment. The processor 122 can be a general-purpose processor, including a central processing unit CPU, a network processor (network processor, NP), etc.; it can also be a digital signal processor DSP, an application-specific integrated circuit ASIC, a field programmable gate array FPGA or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0159] The memory 123 is connected to the processor 122 via a system bus and completes communication between them. The memory 123 is used to store computer program instructions.

[0160] The transceiver 121 may be used to obtain tasks to be executed and configuration information of the tasks to be executed.

[0161] The system bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The system bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The transceiver is used to realize the communication between the database access device and other computers (such as clients, read-write libraries, and read-only libraries). The memory may include random access memory (RAM) and may also include non-volatile memory.

[0162] An embodiment of the present application also provides a chip for running instructions, which is used to execute the technical solution of the analog-to-digital conversion method in the above embodiment.

[0163] An embodiment of the present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the computer executes the technical solution of the analog-to-digital conversion method in the above embodiment.

[0164] An embodiment of the present application also provides a computer program product, which includes a computer program stored in a computer-readable storage medium. At least one processor can read the computer program from the computer-readable storage medium. When at least one processor executes the computer program, the technical solution of the analog-to-digital conversion method in the above embodiment can be implemented.

[0165] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0166] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to implement the solution of this embodiment.

[0167] In addition, each functional module in each embodiment of the present application can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The above-mentioned module-composed unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

[0168] The above-mentioned integrated module implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform some steps of the methods of various embodiments of the present application.

[0169] It should be understood that the above processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the invention can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0170] The memory may include a high-speed RAM memory, and may also include a non-volatile storage NVM, such as at least one disk memory, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a magnetic disk or an optical disk, etc.

[0171] The above storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0172] An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the storage medium can also exist as discrete components in an electronic control unit or a main control device.

Claims

1. An analog-to-digital conversion device, characterized in that: It includes a sampling module, an analog-to-digital conversion module, a phase shift module and a processing module; The sampling module is used to sample the input signal to obtain a sampled signal; The phase shift module is used to determine all clock phases of the analog-to-digital conversion module under the control of the processing module; The analog-to-digital conversion module is used to convert the sampled signal into a corresponding digital signal in each clock phase under the control of the processing module; The processing module is used to determine the target clock phase of the analog-to-digital conversion module according to the signal power of the digital signal corresponding to the clock phase, and determine the target clock phase as the working clock phase of the analog-to-digital conversion module; The target clock phase is a clock phase corresponding to the maximum signal power of the digital signal.

2. The analog-to-digital conversion device according to claim 1, characterized in that: The analog-to-digital conversion device further includes: a buffer module; The buffer module is used to smooth the sampled signal, or to store the sampled signal, or to smooth the sampled signal and store the smoothed sampled signal.

3. The analog-to-digital conversion device according to claim 1, characterized in that: The analog-to-digital conversion device further includes: a clock signal generating module; The clock signal generating module is used to provide the same source clock signal to the sampling module, the analog-to-digital conversion module and the phase shifting module respectively.

4. The analog-to-digital conversion device according to claim 3, characterized in that: The analog-to-digital conversion device further includes: a low-pass filtering module; The low-pass filtering module is used to suppress the image frequency signal in the sampling signal.

5. The analog-to-digital conversion device according to claim 4, characterized in that: The sampling module includes a voltage type sample and hold device, and the low-pass filtering module includes any one of a Butterworth filter, a Chebyshev filter, an elliptic filter, a Bessel filter or a Gaussian filter.

6. The analog-to-digital conversion device according to claim 5, characterized in that: The voltage type sample and hold device comprises a buffer, a first switch unit and a first storage unit; One end of the buffer is used to receive the input signal, and the other end is connected to the first end of the first switch unit; The second end of the first switch unit is connected to the first storage unit, and the control end of the first switch unit is connected to the clock signal generating module, and is used to be turned on or off under the control of the clock signal generated by the clock signal generating module to realize sampling of the input signal.

7. The analog-to-digital conversion device according to claim 5, characterized in that: The bandwidth of the sampling module is greater than the bandwidth of the low-pass filtering module, and the bandwidth of the low-pass filtering module is greater than the bandwidth of the analog-to-digital conversion module.

8. The analog-to-digital conversion device according to claim 4, characterized in that: The sampling module includes a current-type sample-and-hold device, and the low-pass filtering module includes any one of a Bessel filter, a Chebyshev filter or a Butterworth filter.

9. The analog-to-digital conversion device according to claim 8, characterized in that: The current-type sample-and-hold device comprises a current-to-voltage converter, a second switch unit and a second storage unit; One end of the current-to-voltage converter is used to receive the input signal, and the other end is connected to the first end of the second switch unit; The second end of the second switch unit is connected to the second storage unit, and the control end of the second switch unit is connected to the clock signal generating module, and is used to be turned on or off under the control of the clock signal generated by the clock signal generating module to realize sampling of the input signal.

10. The analog-to-digital conversion device according to any one of claims 1 to 9, characterized in that: The input signal is a single tone signal or a square wave signal; The frequency of the input signal is the Nyquist frequency of the sampling module.

11. A data acquisition system, characterized in that: The analog-to-digital conversion device comprises any one of claims 1-10.

12. An analog-to-digital conversion method, characterized in that: Applied to the analog-to-digital conversion device according to any one of claims 1 to 10, the method comprises: Acquire a sampling signal obtained by the sampling module sampling an input signal; Controlling the phase shift module to determine all clock phases of the analog-to-digital conversion module; Acquire a corresponding digital signal obtained by the analog-to-digital conversion module after performing analog-to-digital conversion on the sampling signal at each clock phase; According to the signal power of the digital signal corresponding to the clock phase, the target phase of the analog-to-digital conversion module is determined, and the target phase is determined as the working phase of the analog-to-digital conversion module, wherein the target clock phase is the clock phase corresponding to the maximum signal power of the digital signal.

13. The method according to claim 12, characterized in that The method further comprises: The sampling module, the analog-to-digital conversion module and the phase shift module are provided with the same clock signal respectively.

14. The method according to claim 12 or 13, characterized in that The method further comprises: Based on the low-pass filtering module, filtering the sampled signal to obtain a filtered sampled signal; The obtaining module converts the sampled signal at each clock phase to obtain a corresponding digital signal, which includes: A corresponding digital signal is obtained after the analog-to-digital conversion module converts the filtered sampling signal at each clock phase.

15. The method according to claim 12 or 13, characterized in that The input signal is a single tone signal or a square wave signal; The frequency of the input signal is the Nyquist frequency of the sampling module.

16. An analog-to-digital conversion device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the program implements the method according to any one of claims 12 to 15 when executed by the processor.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 12 to 15 is implemented.

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