Low-power, high-precision single-slope analog-to-digital conversion circuit for image sensors

Abstract

The present invention discloses a low-power, high-precision single slope analog-to-digital conversion circuit for an image sensor, comprising a slope generation circuit, a comparator circuit, a rising edge detection circuit, a falling edge detection circuit, a clock generation circuit, a coarse counting circuit, a fine counting circuit, a phase comparison circuit and a data processing circuit. The present invention combines a coarse counting clock with a fine counting clock for counting, reduces the number of bits required, and thus reduces the power consumption of the circuit; by adopting a fractional frequency division phase-locked loop structure to divide the coarse counting clock and the fine counting clock, the synchronization of the state conversion of the coarse counting clock and the fine counting clock is achieved, and the double-edge triggering technology is adopted to improve the processing efficiency of the circuit; and by combining the coarse counting clock and the fine counting clock, the output result of the circuit is quantized, so that the accuracy of the final readout is improved by 4 orders of magnitude, and finally low-power consumption, high-precision and high-speed readout at a lower clock frequency is achieved.

Description

Technical Field

[0001] The invention relates to a low-power consumption, high-precision single-slope analog-to-digital conversion circuit for an image sensor, belonging to the technical field of electronics. Background Art

[0002] Single Slope Analog Digital Converter (SS-ADC) is widely used in image sensors because of its simple circuit structure, strong anti-interference ability and low power consumption. Its working principle is to compare a ramp signal whose voltage increases linearly with time with the output signal of the pixel in a comparator. When the ramp voltage is equal to the pixel signal value, the output state of the comparator changes. At this time, the counter records the time required for the ramp voltage to reach the pixel signal value and locks it in the memory. This time represents the analog value of the pixel signal. Finally, the value is read out through the readout circuit to realize the conversion of analog signal to digital signal.

[0003] However, the single-slope analog-to-digital converter in the prior art requires the counter to run at an extremely high clock frequency when realizing high-speed analog-to-digital conversion, which will cause the internal digital logic gate to switch frequently, thereby increasing dynamic power consumption. Maintaining high-speed analog-to-digital conversion requires higher power supply voltage and current, which will also increase the power consumption of the circuit. In addition, the counter must traverse from the minimum value to the maximum value. As the bit width increases, the conversion time will also increase, which leads to a significant increase in power consumption. If the clock frequency of the counter is reduced, the number of sampling times will be reduced, resulting in an increase in the minimum time interval that the counter can distinguish, and the high level time of the comparator cannot be accurately measured, so that the number of times the counter can count per unit time is reduced, resulting in a reduction in the quantization bit width, thereby affecting the conversion accuracy.

[0004] Currently, there is no technology that can achieve both low power consumption and high precision. As the pixel size of image sensors continues to expand, the demand for low power consumption and high precision is becoming increasingly urgent, and corresponding solutions need to be studied. Summary of the invention

[0005] In order to solve the defects existing in the above-mentioned prior art, the present invention proposes a low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor. By combining a coarse counting clock and a fine counting clock, the circuit can achieve low-power, high-precision, high-speed readout at a lower clock frequency against the background of the continuous expansion of the pixel scale of the image sensor.

[0006] According to one aspect of the present invention, the present invention proposes a low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor, the circuit comprising: a ramp generating circuit, a comparator circuit, a rising edge detection circuit, a falling edge detection circuit, a clock generating circuit, a coarse counting circuit, a fine counting circuit, a phase comparison circuit and a data processing circuit.

[0007] The ramp generating circuit is configured to output a ramp signal VRP with an initial voltage of VB, a termination voltage of VE and a slope of VS, and an output end thereof is connected to an inverting input end of the comparator circuit;

[0008] The comparator circuit is configured to have a positive input terminal connected to a signal to be measured VCP, an inverting input terminal connected to a ramp signal VRP, an output terminal outputting a comparator signal CMP and connected to both an input terminal of a rising edge detection circuit and an input terminal of a falling edge detection circuit. When the signal to be measured VCP is higher than the ramp signal VRP, a high level is output, otherwise a low level is output;

[0009] A rising edge detection circuit, wherein the input end is connected to the comparator signal CMP output by the comparator circuit, and the output end outputs the enable signal ENU connected to the input end of the coarse counting circuit; the state of the output enable signal ENU is controlled according to the state of the comparator signal CMP; if a rising edge is detected, the enable signal ENU is at a high level, otherwise it is at a low level;

[0010] A falling edge detection circuit, wherein the input end is connected to a comparator signal CMP output by a comparator circuit, and the output end output enable signal END is connected to the input end of a fine counting circuit; the state of the output enable signal END is controlled according to the state of the comparator signal CMP; if a falling edge is detected, the enable signal END is at a high level, otherwise it is at a low level;

[0011] A clock generating circuit outputs a coarse counting clock FCE and a fine counting clock FFE according to an input reference clock FRF; wherein the coarse counting clock FCE is connected to a coarse counting circuit and a phase comparison circuit, and the fine counting clock FFE is connected to a fine counting circuit and a phase comparison circuit;

[0012] The coarse counting circuit uses an N-bit counter to count the coarse counting clock FCE according to the state of the input enable signal ENU, and the output terminal outputs the count value CCE connected to the data processing circuit; when the enable signal ENU is at a high level, the coarse counting circuit starts counting;

[0013] A fine counting circuit uses an N-bit counter to count the fine counting clock FFE according to the state of the input enable signal END. The output terminal outputs the count value CFE connected to the data processing circuit. When the enable signal END is at a high level, the fine counting circuit starts counting;

[0014] The phase comparison circuit compares the coarse counting clock FCE and the fine counting clock FFE and outputs a comparison signal POL; the state of the comparison signal POL is controlled according to the comparison result of the coarse counting clock FCE and the fine counting clock FFE, when the rising edges of the coarse counting clock FCE and the fine counting clock FFE coincide, the comparison signal POL is output as a high level, otherwise it is a low level;

[0015] The data processing circuit calculates and outputs a quantization result CNT according to the input coarse count value CCE, fine count value CFE and phase comparison signal POL.

[0016] In one embodiment, the coarse counting clock FCE and the fine counting clock FFE satisfy 2 N-1 ×FCE=(2 N-1 +1)×FFE.

[0017] In one embodiment, the clock generation circuit adopts a fractional frequency phase-locked loop structure, the coarse counting clock FCE is in phase with the reference clock FRF after integer division, and the fine counting clock FFE is in phase with the reference clock FRF after fractional division.

[0018] In one implementation, the coarse counting clock FCE and the fine counting clock FFE determine whether to start counting according to the states of the enable signals ENU and END; when the enable signal ENU is at a high level, the coarse counting clock FCE starts counting, and when the enable signal END is at a high level, the fine counting clock FFE starts counting.

[0019] In one implementation, the count value when the rising edges of the coarse counting clock FCE and the fine counting clock FFE coincide for the first time is selected for calculation.

[0020] In one embodiment, the calculation method of the quantization result CNT is CCE / FCE-CFE / FFE.

[0021] In one implementation, double-edge triggering is adopted for the coarse counting clock FCE and the fine counting clock FFE.

[0022] The beneficial effects of the present invention are:

[0023] The present invention combines a coarse counting clock with a fine counting clock for counting, reduces the required number of bits, and thus reduces the power consumption of the circuit; by adopting a fractional frequency division phase-locked loop structure to divide the coarse counting clock and the fine counting clock, the synchronization of the state conversion of the coarse counting clock and the fine counting clock is realized, and the double-edge triggering technology is adopted to improve the processing efficiency of the circuit; by combining the coarse counting clock and the fine counting clock, the output result of the circuit is quantized, so that the accuracy of the final readout is improved by 4 orders of magnitude, and finally low power consumption, high-precision and high-speed readout at a lower clock frequency is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is a low-power, high-precision single-slope analog-to-digital conversion circuit architecture diagram for an image sensor provided by the present invention;

[0026] Figure 2 It is a schematic diagram of the structure of a clock generating circuit in a low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor provided by the present invention;

[0027] Figure 3 It is a schematic diagram of the structure of a rising edge detection circuit in a low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor provided by the present invention;

[0028] Figure 4 It is a schematic diagram of the structure of a falling edge detection circuit in a low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor provided by the present invention;

[0029] Figure 5 It is a schematic diagram of the 8-bit counting circuit in the low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor provided by the present invention;

[0030] Figure 6 It is a schematic diagram of the structure of a phase comparison circuit in a low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor provided by the present invention;

[0031] Figure 7 The invention provides a key signal timing diagram in a low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0033] Embodiment 1

[0034] The circuit of the present invention is exemplarily described below in conjunction with the accompanying drawings and specific embodiments.

[0035] This embodiment provides a low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor. Figure 1As shown, the circuit includes: a ramp generating circuit, a comparator circuit, a rising edge detecting circuit, a falling edge detecting circuit, a clock generating circuit, a coarse counting circuit, a fine counting circuit, a phase comparison circuit and a data processing circuit. In the circuit, both the coarse counting circuit and the fine counting circuit adopt an 8-bit counter.

[0036] The ramp generating circuit is configured to output a ramp signal VRP with an initial voltage of VB, a termination voltage of VE and a slope of VS, and an output end thereof is connected to an inverting input end of the comparator circuit;

[0037] The comparator circuit is configured such that the non-inverting input terminal is connected to the signal to be tested VCP, the inverting input terminal is connected to the ramp signal VRP, the output terminal outputs the comparator signal CMP and is simultaneously connected to the input terminal of the rising edge detection circuit and the input terminal of the falling edge detection circuit. When the signal to be tested VCP is higher than the ramp signal VRP, the comparator circuit outputs a high level, otherwise the comparator circuit outputs a low level.

[0038] A rising edge detection circuit, wherein the input end is connected to the comparator signal CMP of the comparator circuit, and the output end output enable signal ENU is connected to the input end of the coarse counting circuit; the state of the output enable signal ENU is controlled according to the state of the comparator signal CMP; if a rising edge is detected, the enable signal ENU is high level, otherwise it is low level;

[0039] A falling edge detection circuit, wherein the input end is connected to the comparator signal CMP of the comparator circuit, and the output end is connected to the input end of the fine counting circuit; the state of the output enable signal END is controlled according to the state of the comparator signal CMP; if a falling edge is detected, the enable signal END is at a high level, otherwise it is at a low level;

[0040] A clock generating circuit outputs a coarse counting clock FCE and a fine counting clock FFE according to an input reference clock FRF; wherein the coarse counting clock FCE is connected to a coarse counting circuit and a phase comparison circuit, and the fine counting clock FFE is connected to a fine counting circuit and a phase comparison circuit;

[0041] The coarse counting circuit uses an N-bit counter to count the coarse counting clock FCE according to the state of the input enable signal ENU, and the output terminal outputs the count value CCE connected to the data processing circuit; when the enable signal ENU is at a high level, the coarse counting circuit starts counting;

[0042] A fine counting circuit uses an N-bit counter to count the fine counting clock FFE according to the state of the input enable signal END. The output terminal outputs the count value CFE connected to the data processing circuit. When the enable signal END is at a high level, the fine counting circuit starts counting;

[0043] The phase comparison circuit compares the coarse counting clock FCE and the fine counting clock FFE and outputs a comparison signal POL; the state of the comparison signal POL is controlled according to the comparison result of the coarse counting clock FCE and the fine counting clock FFE, when the rising edges of the coarse counting clock FCE and the fine counting clock FFE coincide, the comparison signal POL is output as a high level, otherwise it is a low level;

[0044] The data processing circuit calculates and outputs a quantization result CNT according to the input coarse count value CCE, fine count value CFE and phase comparison signal POL.

[0045] If the coarse count clock FCE is set to 5MHz, the fine count clock FFE needs to be set to:

[0046]

[0047] Its time measurement accuracy is:

[0048]

[0049] Figure 2 The schematic diagram of the clock generation circuit is given, which consists of two phase-locked loops. Each phase-locked loop consists of a phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider. Assuming that the reference clock FRF is 1MHz, the frequency division ratio of the frequency divider CE is set to 5, then the coarse counting clock is 5MHz; the frequency division ratio of the frequency divider FE is set to 128 / 129, then the fine counting clock is 4.961240310MHz; at the same time, since the coarse counting clock and the fine counting clock are both generated by the reference clock, the above two clocks are in phase.

[0050] Figure 3 A rising edge detection circuit is given, whose input signals are the clock signal CLK, the reset signal RST, the comparator signal CMP, and the output signal is ENU; when the reset signal RST is at a low level, the output signal ENU is at a low level, and registers F0, F1, F2 and F3 are set to zero; when the reset signal RST is at a high level, after each cycle of the clock signal CLK, F2 is set to F1, F1 is set to F0, and F0 is set to CMP; if F1 is at a high level and F2 is at a low level, the output signal ENU is at a high level.

[0051] Figure 4A falling edge detection circuit is given, whose input signals are the clock signal CLK, the reset signal RST, the comparator signal CMP, and the output signal is END; when the reset signal RST is at a low level, the output signal END is at a low level, and registers F0, F1, F2 and F3 are set to zero; when the reset signal RST is at a high level, after each cycle of the clock signal CLK, F2 is set to F1, F1 is set to F0, and F0 is set to CMP; if F1 is at a low level and F2 is at a high level, the output signal END is at a high level.

[0052] Figure 5 The circuit diagram of 8-bit coarse counting and fine counting is given. Its input signals are the clock signal CLK, the reset signal RST, and the enable signal EN, and the output signal is Q<7:0>; when the reset signal RST is at a low level, the output signal Q<7:0> is 0, and registers F0~F7 are set to zero. When the enable signal EN is at a high level, the output signal Q<7:0> is incremented by 1 after each cycle of the clock signal CLK to realize the counting function.

[0053] Figure 6 A phase comparison circuit diagram is given, whose input signals are the coarse count clock FCE, the fine count clock FFE and the reference voltage VL, and the output signal is POL; by adjusting the reference voltage VL so that when the rising edges of FCE and FFE coincide, POL outputs a low level, otherwise it outputs a high level, thus realizing the phase comparison function.

[0054] Figure 7 The key signal timing diagram is given. Assume that the starting voltage VB of VRP is 0V, the ending voltage VE is 4V, and the slope VS is , the signal to be measured VCP is , the high level duration of the corresponding comparator signal CMP is When the falling edge of the comparator signal CMP arrives, the count value CCE of the coarse counter is 22. If the traditional solution is used, the sampling result is , the corresponding voltage value is 2.2V, and the error is 39.1055mV. If the solution proposed by the present invention is adopted, the fine counter starts counting, and when the rising edges of the coarse counting clock FCE and the fine counting clock FFE overlap, the count value CCE of the coarse counter is 72, and the count value CFE of the fine counter is 50. The final quantization result is:

[0055]

[0056] The corresponding voltage value is The quantization error is 0.043mV, which is 4 orders of magnitude higher than the traditional scheme.

[0057] Obviously, the described embodiments are only some embodiments of the present disclosure, rather than all embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the above detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure claimed for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

Claims

1. A low-power, high-precision single-slope analog-to-digital conversion circuit for an image sensor, characterized in that: The circuit comprises: a ramp generating circuit, a comparator circuit, a rising edge detecting circuit, a falling edge detecting circuit, a clock generating circuit, a coarse counting circuit, a fine counting circuit, a phase comparing circuit and a data processing circuit; The ramp generating circuit is used to generate a ramp signal VRP with an initial voltage of VB, a termination voltage of VE and a slope of VS; The comparator circuit is used to compare the ramp signal VRP with the signal to be tested VCP and output a comparator signal CMP; The rising edge detection circuit outputs an enable signal ENU according to the comparator signal CMP. If a rising edge is detected, ENU is at a high level, otherwise it is at a low level; The falling edge detection circuit outputs an enable signal END according to the comparator signal CMP. If a falling edge is detected, END is at a high level, otherwise it is at a low level; The clock generating circuit outputs a coarse counting clock FCE and a fine counting clock FFE according to the input reference clock FRF; The coarse counting circuit uses an N-bit counter to count the coarse counting clock FCE according to the state of the input enable signal ENU, and the output count value is CCE. When the enable signal ENU is at a high level, the coarse counting circuit starts counting; The fine counting circuit uses an N-bit counter to count the fine counting clock FFE according to the state of the input enable signal END, and the output count value is CFE. When the enable signal END is at a high level, the fine counting circuit starts counting; The phase comparison circuit compares the coarse count clock FCE and the fine count clock FFE, and outputs a comparison signal POL. When the rising edges of the coarse count clock FCE and the fine count clock FFE coincide, the comparison signal POL is output as a high level, otherwise it is a low level. The data processing circuit calculates and outputs a quantization result CNT according to the input coarse count value CCE, fine count value CFE and comparison signal POL; The output end of the ramp generating circuit outputs a ramp signal VRP connected to the inverting input end of the comparator circuit; the non-inverting input end of the comparator circuit is connected to the signal to be measured VCP, and the output end outputs a comparator signal CMP connected to the input ends of the rising edge detection circuit and the falling edge detection circuit; the output end of the rising edge detection circuit outputs an enable signal ENU connected to the input end of the coarse counting circuit; the output end of the falling edge detection circuit outputs an enable signal END connected to the input end of the fine counting circuit; the clock generating circuit outputs a coarse counting clock FCE and a fine counting clock FFE according to the input reference clock FRF, and the coarse counting clock FCE is connected to the coarse counting circuit at the same time. The input end of the circuit and the phase comparison circuit, the fine counting clock FFE is connected to the input end of the fine counting circuit and the phase comparison circuit at the same time; the output end of the coarse counting circuit outputs the coarse counting circuit count value CCE and is connected to the data processing circuit; the output end of the fine counting circuit outputs the fine counting circuit count value CFE and is connected to the data processing circuit; the output end of the phase comparison circuit outputs a comparison signal POL and is connected to the data processing circuit; the input end of the data processing circuit is connected to the coarse counting value CCE output by the coarse counting circuit, the fine counting value CFE output by the fine counting circuit and the comparison signal POL output by the phase comparison circuit, and the output end outputs a quantization result CNT.

2. The circuit according to claim 1, characterized in that The clock generating circuit adopts a fractional frequency division phase locked loop structure. The coarse counting clock FCE is in phase with the reference clock FRF after integer frequency division, and the fine counting clock FFE is in phase with the reference clock FRF after fractional frequency division.

3. The circuit according to claim 2, characterized in that The coarse count clock FCE and the fine count clock FFE satisfy 2 N-1 ×FCE=(2 N-1 +1)×FFE.

4. The circuit according to claim 3, characterized in that The coarse count clock starts counting when the enable signal ENU is at a high level, and the fine count clock starts counting when the enable signal END is at a high level.

5. The circuit according to claim 4, characterized in that The calculation method of the quantization result CNT is CCE / FCE-CFE / FFE.

6. The circuit according to claim 5, characterized in that The coarse counting clock FCE and the fine counting clock FFE are triggered by double edges.

7. An analog-to-digital converter, characterized in that: The analog-to-digital converter is implemented based on the circuit described in any one of claims 1-6.

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