A current comparator module for high-precision digital-to-analog converter calibration circuit

Abstract

The present invention discloses a current comparator module for a high-precision digital-to-analog converter calibration circuit, the current comparator module for the high-precision digital-to-analog converter calibration circuit includes a current-to-voltage conversion module, a dynamic comparator and a common-mode feedback circuit module, the current-to-voltage conversion module includes a differential-mode current signal unit and a common-mode current signal unit, the differential-mode current signal unit is respectively connected to the current-to-voltage conversion module and the dynamic comparator; the common-mode current signal unit is connected to the current-to-voltage conversion module; the common-mode feedback circuit module is respectively connected to the common-mode current signal unit and the dynamic comparator. The current comparator module for the high-precision digital-to-analog converter calibration circuit proposed by the present invention can be applied to the calibration of a current steering DAC with more than three segments, solving the problem that the current comparator circuit in the prior art is difficult to be generalized and applied to a three-segment DAC.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a current comparator module for a high-precision digital-to-analog converter calibration circuit. Background Art

[0002] High-speed and high-precision current-steering DACs (digital-to-analog converters) are widely used in broadband communications, direct digital synthesis, radar and other fields. Their static performance, dynamic performance and signal bandwidth are one of the key factors limiting system performance. Integral nonlinearity (INL) and differential nonlinearity (DNL) are key indicators for measuring the static performance of DACs, which are limited by the matching accuracy between different current sources in the DAC. Although increasing the size of the current source tube can reduce the mismatch between current sources and improve INL and DNL, ​​an overly large current source size will increase the chip area, which will not only aggravate the impact of the gradient effect of the current source array, but also increase the capacitance parasitics on the current branch nodes and traces, thereby reducing the maximum conversion rate of the DAC and worsening the spurious-free dynamic range (SFDR) of the DAC's high-frequency output.

[0003] like Figure 1 As shown, Figure 1 The invention discloses an existing current comparator circuit used in the current source calibration of two-segment 14-bit DAC. The circuit is composed of three parts: a current-to-voltage converter, an offset cancellation amplifier and a dynamic comparator. Figure 1 There are two problems with the current comparator structure shown. First, the common-mode current and differential-mode current of the input current signal flow through the same current branch. Therefore, when the common-mode current increases, the differential-mode signal gain decreases, making it difficult to apply to the current source calibration process of a three-segment DAC with higher precision. Second, when the current comparator is working, the common-mode feedback function is turned off, so continuous calibration cannot be performed. Each time a current comparison is performed, the common-mode feedback process must be repeated. This repetitive process undoubtedly reduces the calibration speed.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a current comparator module and a digital-to-analog converter for a high-precision digital-to-analog converter calibration circuit, so as to at least solve the problem that the current comparator circuit is difficult to be generalized and applied to a three-segment DAC.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a current comparator module for a high-precision digital-to-analog converter calibration circuit, comprising a current-to-voltage conversion module and a dynamic comparator connected to the current-to-voltage conversion module, wherein the current-to-voltage conversion module comprises:

[0008] A differential mode current signal unit, wherein the differential mode current signal unit is connected to the current-voltage conversion module and the dynamic comparator respectively;

[0009] A common mode current signal unit, the common mode current signal unit is connected to the current-voltage conversion module;

[0010] Furthermore, the current comparator module for the high-precision digital-to-analog converter calibration circuit further includes:

[0011] A common-mode feedback circuit module is connected to the common-mode current signal unit and the dynamic comparator respectively.

[0012] Furthermore, the common-mode feedback circuit module is a switched capacitor common-mode feedback circuit, the common-mode voltage information of the common-mode feedback circuit module is extracted from the high-resistance node on the differential-mode current signal unit, and the feedback point of the common-mode feedback circuit module is at the tail current source of the common-mode current signal unit.

[0013] Furthermore, the operating phase of the common-mode feedback circuit module does not overlap with the phase of the current comparator module for the high-precision digital-to-analog converter calibration circuit comparing the input current, and during the operation of the current comparator module for the high-precision digital-to-analog converter calibration circuit, the switch in the common-mode feedback circuit module stops switching.

[0014] Furthermore, the current-voltage conversion module further includes:

[0015] The first PMOS tube has a source connected to the input voltage VDD, and a drain connected to the input current I IN , the differential mode current signal unit and the common mode current signal unit are connected;

[0016] A second PMOS tube, wherein the source of the second PMOS tube is connected to the input voltage VDD, and the drain of the second PMOS tube is connected to the input current I IP , the differential mode current signal unit and the common mode current signal unit are connected, and the gate of the second PMOS tube is connected to the gate of the first PMOS tube;

[0017] a third PMOS tube, wherein a source of the third PMOS tube is connected to the input voltage VDD, and a drain of the third PMOS tube is respectively connected to the differential mode current signal unit and the common mode current signal unit;

[0018] A fourth PMOS tube, wherein the source of the fourth PMOS tube is connected to the input voltage VDD, the drain of the fourth PMOS tube is respectively connected to the differential mode current signal unit and the common mode current signal unit, and the gate of the fourth PMOS tube is connected to the gate of the third PMOS tube.

[0019] Furthermore, the differential mode current signal unit includes:

[0020] The fifth PMOS tube, the source of the fifth PMOS tube is respectively connected to the input current I IN , the current-voltage conversion module is connected, and the drain of the fifth PMOS tube is connected to the negative input terminal of the dynamic comparator;

[0021] The sixth PMOS tube, the source of the sixth PMOS tube is respectively connected to the input current I IP , the current-voltage conversion module is connected, and the gate of the sixth PMOS tube is connected to the gate of the fifth PMOS tube, and the drain of the fifth PMOS tube is connected to the positive input terminal of the dynamic comparator;

[0022] a first switch, wherein two ends of the first switch are respectively connected to the drain of the fifth PMOS tube and the drain of the sixth PMOS tube;

[0023] a first NMOS transistor, wherein a drain of the first NMOS transistor is respectively connected to the first end of the first switch and the drain of the fifth PMOS transistor;

[0024] a second NMOS transistor, wherein a drain of the second NMOS transistor is respectively connected to the second end of the first switch and the drain of the sixth PMOS transistor, and a gate of the second NMOS transistor is connected to the gate of the first NMOS transistor;

[0025] A third NMOS tube, wherein the drain of the third NMOS tube is respectively connected to the source of the first NMOS tube and the source of the second NMOS tube, and the source of the third NMOS tube is connected to the output voltage VSS.

[0026] Furthermore, the gate of the third NMOS tube is connected to the output port V BN1 connect.

[0027] Furthermore, it is characterized in that the common mode current signal unit comprises:

[0028] The fourth NMOS tube, the drain of the fourth NMOS tube is respectively connected to the current-voltage conversion module and the input current I IN connect;

[0029] A fifth NMOS tube, the drain of which is connected to the current-voltage conversion module and the input current IIP The gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube;

[0030] A sixth NMOS tube, wherein the drain of the sixth NMOS tube is respectively connected to the source of the fourth NMOS tube and the source of the fifth NMOS tube, the gate of the sixth NMOS tube is connected to the common-mode feedback circuit module, and the source of the sixth NMOS tube is connected to the output voltage VSS.

[0031] Furthermore, the common mode feedback circuit module includes:

[0032] a first capacitor, wherein a first end of the first capacitor is connected to the common-mode current signal unit, and a second end of the first capacitor is connected to the differential-mode current signal unit;

[0033] A second capacitor, wherein a first end of the second capacitor is connected to the common-mode current signal unit, and a second end of the first capacitor is connected to the differential-mode current signal unit;

[0034] a second switch, wherein a first end of the second switch is connected to the common mode current signal unit;

[0035] a third capacitor, a first end of the third capacitor being connected to the second end of the second switch;

[0036] a third switch, wherein a first end of the third switch is connected to the second end of the first capacitor, and a second end of the third switch is connected to the second end of the third capacitor;

[0037] a fourth switch, wherein a first end of the fourth switch is connected to a second end of the second capacitor;

[0038] a fourth capacitor, wherein a first end of the fourth capacitor is connected to the second end of the fourth switch, and a second end of the fourth capacitor is connected to the second end of the second switch;

[0039] a fifth switch, wherein a first end of the fifth switch is connected to the second end of the fourth capacitor, and a second end of the fifth switch is connected to the output port VBN2;

[0040] a sixth switch, wherein a first end of the sixth switch is connected to a second end of the third switch, and a second end of the sixth switch is connected to an output port VCMO;

[0041] A seventh switch, wherein a first end of the seventh switch is connected to the first end of the fourth capacitor, and a second end of the seventh switch is connected to the output port VCMO.

[0042] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0043] A current comparator module for a high-precision digital-to-analog converter calibration circuit of the present invention sets a differential-mode current signal unit and a common-mode current signal unit in a current-to-voltage conversion module, so that the bias current in the differential-mode current signal unit is fixed by a third NMOS tube of a tail current source, and uses a common-mode feedback circuit module to provide a DC current for the common-mode circuit signal unit, so that when the input current common mode changes, the changed common-mode current will all flow through the common-mode current signal unit, and the current-to-voltage conversion gain from the differential-mode current signal unit to the differential input end of the dynamic comparator remains almost unchanged, so that the minimum resolvable current of the current comparator module for the high-precision digital-to-analog converter calibration circuit will not change with the input common-mode current change, so that the current comparator module for the high-precision digital-to-analog converter calibration circuit proposed by the present invention can be applied to the calibration of current-steering DACs with more than three segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 The following is a simplified diagram of the existing N-bit DAC MSB current source calibration circuit;

[0046] Figure 2 A schematic diagram of an existing current comparator for DAC current source calibration;

[0047] Figure 3 It is a timing diagram of the existing comparator in DAC current source calibration;

[0048] Figure 4 A schematic diagram of a current comparator module for a high-precision digital-to-analog converter calibration circuit according to an embodiment of the present invention;

[0049] Figure 5 The timing diagram of the current comparator module in the DAC current source calibration of the high-precision digital-to-analog converter calibration circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0051] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0052] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0053] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0055] High-speed and high-precision current-steering DACs (digital-to-analog converters) are widely used in broadband communications, direct digital synthesis, radar and other fields. Their static performance, dynamic performance and signal bandwidth are one of the key factors limiting system performance. Integral nonlinearity (INL) and differential nonlinearity (DNL) are key indicators for measuring the static performance of DACs, which are limited by the matching accuracy between different current sources in the DAC. Although increasing the size of the current source tube can reduce the mismatch between current sources and improve INL and DNL, ​​an overly large current source size will increase the chip area, which will not only aggravate the impact of the gradient effect of the current source array, but also increase the capacitance parasitics on the current branch nodes and traces, thereby reducing the maximum conversion rate of the DAC and worsening the spurious-free dynamic range (SFDR) of the DAC high-frequency output.

[0056] In order to solve the mismatch problem between DAC current sources and improve the static performance of DAC, a common practice is to introduce digital calibration technology. The binary DAC is segmented into two parts: the high-order segment current source (MSBs) and the low-order segment current source (LSBs). The high-order segment current source array is first temperature-coded and then digitally calibrated.

[0057] Figure 1 A simplified diagram of the current source mismatch calibration of a two-segment N-bit P-terminal output current steering DAC is given. The number of bits in the high-bit segment and the low-bit segment are N1 and N2 respectively. The high-bit segment has a total of 2N1-1 MSB unit current sources with the same weight, recorded as MSB , where i = {1,2,3,…,2N1-1}, and the tail current source tube of each MSB current source is connected in parallel with a small binary M-bit calibration current DAC (cal-DAC). There are a total of N2 binary weighted LSB current sources in the low-order segment, denoted as LSB , where i = {1,2,3,…,N2}, and an additional INT current source is introduced, whose current is equal to the lowest bit LSB current source LSB <1> The current source calibration circuit uses the sum of all LSB current sources and the INT current source current as the reference current. Based on the comparison result of the current comparator, the successive approximation (SAR) logic adjusts each MSB current source current to be equal to the reference current to complete the calibration. The calibration timing is as follows:

[0058] 1. Ground the gates of NM5 tubes of all LSB current sources and INT current source, connect the gate of NM6 tube to bias voltage, and let the current of the tail current source tube NM4 of all LSB current sources flow into the positive input terminal of the current comparator.

[0059] 2. Set the MSB of the current source to be calibrated The gate of NM2 is grounded, and the gate of NM3 is connected to the bias voltage, so that all the current of the tail current source tube NM1 flows through the NM3 tube to reach the negative input terminal of the current comparator. At the same time, the gate of the remaining MSB current source NM2 tube remains biased, the gate of NM3 tube is grounded, and all the current of the tail current source remains connected to the output current bus IOUTP / IOUTN.

[0060] 3. The current comparator compares the current at the positive and negative input terminals and outputs the comparison result. The SAR logic adjusts the control word D of the cal-DAC from high to low based on the comparison result. <m-1:0>, making the MSB The current size is close to the reference current. After M steps of adjustment, the MSB is completed. Current mismatch calibration.

[0061] 4. When all MSB current source units in the MSBs are calibrated, the current source calibration of the DAC is completed.

[0062] like Figure 2 As shown, Figure 2 The present invention provides a solution to the problem of DAC current source adaptation in the prior art. Specifically, Figure 2 An existing current comparator circuit for two-segment 14-bit DAC current source calibration is presented. The circuit consists of three parts: a current-to-voltage converter (I2V), an offset cancellation amplifier (OCA), and a dynamic comparator. The principle is as follows: IP / I IN After flowing through the NM1 tube, it is folded into the PM3 tube, NM3 tube, and NM2 tube branches, and converted into a voltage signal at the high resistance point OP / ON. Then the voltage signal will be converted into a digital signal by the dynamic comparator at the rising edge of CLK.

[0063] Figure 3 Given Figure 2 The current comparator works in the DAC calibration sequence. ENCAL is the calibration enable signal, CAL <1> , CAL <2> MSB <1> 、MSB <2> In the P1 phase, switches K1 and K3 are closed, and the OP / ON two-point OCA inputs form a closed loop with I2V and OCA. OCA adjusts PM 2A With PM 2B The gate voltage difference is used to force the voltages at OP and ON to be equal. When the loop is stable, the information of the offset current of I2V and the differential input current of the current amplifier is stored on capacitor C1. At the same time, the NM4 tube and the tail current source IB form a source follower circuit topology and form a common-mode feedback loop with the NM2 tube to stabilize the common-mode voltage at OP and ON at the sum of the gate-source voltages of the NM2 tube and the NM4 tube. In the P2 phase, the switch K3 is disconnected, OCA is disconnected from I2V, the current comparator input is reversed, and the offset of I2V itself is offset at the differential input of the dynamic comparator. The differential output of OP and ON is equal to the conversion result of twice the actual input differential current.

[0064] From the above content, we can know Figure 2 The current comparator in has the following three disadvantages:

[0065] 1. The common-mode feedback loop of I2V is disconnected at P2 phase, and during the calibration process of MSB, the common-mode current of the current comparator input will change with the cal-DAC control word D <m-1:0>This will cause the output common-mode voltage of I2V to deviate from the preset value. Therefore, in the calibration timing design, each step of the M-step comparison process of a single MSB current source requires an offset storage and common-mode establishment process. From a circuit perspective, this process is a closed-loop steady-state establishment process of a two-pole system, and the establishment time is much longer than the open-loop establishment time of the conversion from the comparator input current signal to the OP / ON voltage signal (in the actual circuit, the time required for the P1 phase is much longer than the time required for the P2 phase), which seriously increases the time required for calibration.

[0066] 2. The common-mode current and differential-mode current of the input current signal flow through the same current branch, making it difficult for the current comparator to be applied to three-segment DACs. Note that the common-mode feedback loop maintains the balance of the upper and lower currents by adjusting the currents of the PM3, NM3, and NM2 branches. When the input common-mode current of the comparator increases by several times or even dozens of times from the current size of a USB unit to the current size of an MSB unit, all of these additional common-mode currents will flow through the PM3, NM3, and NM2 branches, and the current-to-voltage conversion gain of the input differential current to the differential input terminal of the dynamic comparator will decrease, and the minimum discernible current of the comparator will decrease.

[0067] 3. The offset cancellation amplifier can only eliminate the offset of I2V, but cannot handle the offset of the offset cancellation amplifier itself and the dynamic comparator. This problem is more serious in the calibration of high-precision DACs, because the maximum input range and minimum resolution current ratio required by the current comparator are larger, and it is difficult to allocate a higher current voltage gain to I2V to suppress the offset of the offset cancellation amplifier and the dynamic comparator while ensuring the input range.

[0068] For higher precision DAC, in order to reduce the number of temperature codes, it is generally necessary to perform a second segmentation in the high-order segment, dividing the original high-order segment current source into the high-order segment and the middle-order segment current source (USBs), and both segments are decoded using temperature codes. For this three-segment DAC, the calibration of the current source will be divided into two steps. First, all USB current sources are calibrated through the above steps, and then the sum of all USBs, LSBs, and INT current sources is set again as the MSB reference current, and the calibration of the MSB current source is completed by adjusting the current of each MSB current source to approach the reference current.

[0069] The current comparator is the core component of the entire DAC calibration circuit system. Its input current offset, minimum resolvable current, and comparison speed will directly determine the DAC's calibrable accuracy and calibration time. For a typical 16-bit, 20mA full-scale DAC, its LSB current is about 300nA, and the calibration accuracy is generally set to 0.25LSB. When using a typical 6-4-6 three-segment segment, the current comparator needs to be able to input a current amplitude greater than 300uA while meeting the minimum resolution current of 75nA. It is quite difficult to design a current comparator with such a large input range, high resolution, and fast response speed.

[0070] Based on this, this specification embodiment proposes a processing solution: Figure 4 As shown, a current comparator module for a high-precision digital-to-analog converter calibration circuit of the present invention separates the branches through which the differential-mode input current signal and the common-mode input current signal flow in the current-voltage conversion module, so that the minimum resolvable current of the comparator does not change with the change of the common-mode input current; and the switch capacitor common-mode feedback and related timing are reasonably inserted, so that during the calibration process, the comparator can adjust the bias current in real time to ensure the stability of the common-mode voltage of the internal high-resistance node when the input common-mode current changes, which enables the comparator to have the ability to make multiple comparisons continuously. The current comparator proposed by the present invention is very suitable for use in the calibration of high-speed and high-precision DAC current sources using a segmented structure, especially using more than three segments, and has the advantages of a small minimum resolvable current, a large input current range, and a fast calibration speed.

[0071] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0072] Example 1

[0073] like Figure 4 As shown, an embodiment of the present invention provides a current comparator module for a high-precision digital-to-analog converter calibration circuit, including a current-to-voltage conversion module and a dynamic comparator connected to the current-to-voltage conversion module.

[0074] The dynamic comparator includes a comparator unit.

[0075] The current-voltage conversion module includes a differential-mode current signal unit and a common-mode current signal unit, wherein the differential-mode current signal unit is connected to the current-voltage conversion module and the dynamic comparator respectively; and the common-mode current signal unit is connected to the current-voltage conversion module.

[0076] Furthermore, the current comparator module for the high-precision digital-to-analog converter calibration circuit also includes a common-mode feedback circuit module, and the common-mode feedback circuit module is respectively connected to the common-mode current signal unit and the dynamic comparator.

[0077] Among them, the DC bias current of the differential-mode current signal unit is fixed, and the bias current of the common-mode current signal unit is controlled by the common-mode feedback circuit module to continuously track the change of the input common-mode current, so as to separate the flow branches of the differential-mode input current signal and the common-mode input current signal in the current-voltage conversion module, so that the minimum resolvable current of the comparator does not change with the change of the common-mode input current.

[0078] Compared with the prior art, a current comparator module for a high-precision digital-to-analog converter calibration circuit in an embodiment of the present invention removes the offset compensation amplifier and the input point cross-coupling switch, and adds a common-mode feedback circuit module, so that the current voltage gain from the input differential-mode current signal to the differential input terminal of the dynamic comparator remains almost unchanged, and the minimum resolvable current of the comparator does not change with the change of the input common-mode current, thereby making the current comparator proposed in the present invention very suitable for the calibration of current-steering DACs with more than three segments.

[0079] Furthermore, if Figure 4 As shown, the current-voltage conversion module includes a first PMOS tube PM 1B , the second PMOS tube PM 1A 、The third PMOS tube PM 2B And the fourth PMOS tube PM 2A Among them, the first PMOS tube PM 1B , the first PMOS tube PM 1B The source of the first PMOS tube PM is connected to the input voltage VDD. 1B The drain of the IN , differential mode current signal unit, and common mode current signal unit are connected; the second PMOS tube PM 1A The source of the second PMOS tube PM is connected to the input voltage VDD. 1A The drain and input current I IP , differential mode current signal unit, common mode current signal unit connected, the second PMOS tube PM 1A The gate of the first PMOS tube PM 1B The gate connection of the third PMOS tube PM 2B The source of the third PMOS tube PM is connected to the input voltage VDD. 2B The drain of the fourth PMOS tube PM is connected to the differential mode current signal unit and the common mode current signal unit respectively; 2A The source of the fourth PMOS tube PM is connected to the input voltage VDD. 2A The drain of the fourth PMOS tube PM is connected to the differential mode current signal unit and the common mode current signal unit respectively. 2A The gate of the third PMOS tube PM 2B The gate connection.

[0080] Furthermore, the differential mode current signal unit includes a fifth PMOS transistor PM 3B 、The sixth PMOS tube PM 3A , the first switch K5, the first NMOS tube NM 3B , the second NMOS tube NM 3A and the third NMOS transistor NM1. Among them, the fifth PMOS transistor PM 3B The source of the input current I IN , the current-voltage conversion module is connected, and the fifth PMOS tube PM 3B The drain of the sixth PMOS tube PM is connected to the negative input terminal of the dynamic comparator; 3A The source of the input current I IP , the current-voltage conversion module is connected, and the sixth PMOS tube PM 3A The gate of the fifth PMOS tube PM 3B The gate connection of the fifth PMOS tube PM 3B The drain of the first switch K5 is connected to the positive input terminal of the dynamic comparator; the two ends of the first switch K5 are respectively connected to the fifth PMOS tube PM 3B The drain and the sixth PMOS tube PM 3A The drain of the first NMOS tube NM 3B The drain of the first switch K5 and the fifth PMOS tube PM 3B The drain of the second NMOS tube NM 3A The drain of the first switch K5 and the drain of the sixth PMOS tube PM 3A The drain of the second NMOS tube NM 3A The gate of the first NMOS tube NM 3B The drain of the third NMOS tube NM1 is connected to the gate of the first NMOS tube NM 3B Source, second NMOS tube NM 3A The source of the third NMOS tube NM1 is connected to the output voltage VSS.

[0081] Specifically, the fifth PMOS tube PM 3B The source of the first PMOS tube PM 1B The drain of the third PMOS tube PM 2B The drain of the sixth PMOS tube PM 3A The source of the second PMOS tube PM 1A The drain of the fourth PMOS tube PM 2A Drain connection.

[0082] Furthermore, the gate of the third NMOS transistor NM1 is connected to the output port V BN1 connect.

[0083] Furthermore, the common mode current signal unit includes a fourth NMOS transistor NM 4B 、The fifth NMOS tube NM 4A And the sixth NMOS tube NM2. Among them, the fourth NMOS tube NM 4B The drain of the current-voltage conversion module and the input current I IN Connection: Fifth NMOS tube NM 4A The drain of the current-voltage conversion module and the input current I IP Connect the fifth NMOS tube NM 4A The gate of the fourth NMOS tube NM 4B The drain of the sixth NMOS tube NM2 is connected to the gate of the fourth NMOS tube NM 4B The source of the fifth NMOS tube NM 4A The source of the sixth NMOS tube NM2 is connected to the common-mode feedback circuit module, the gate of the sixth NMOS tube NM2 is connected to the common-mode feedback circuit module, and the source of the sixth NMOS tube NM2 is connected to the output voltage VSS.

[0084] Specifically, the fourth NMOS transistor NM 4B The drain of the first PMOS tube PM 1B The drain of the third PMOS tube PM 2B The drain of the fifth NMOS tube PM 4A The source of the second PMOS tube PM 1A The drain of the fourth PMOS tube PM 2A Drain connection.

[0085] Furthermore, the common-mode feedback circuit module is a switched capacitor common-mode feedback circuit, the common-mode voltage information of the common-mode feedback circuit module is extracted from the high-resistance node on the differential-mode current signal unit, and the feedback point of the common-mode feedback circuit module is at the tail current source of the common-mode current signal unit.

[0086] The tail current source is the third NMOS transistor NM1.

[0087] Furthermore, the operating phase of the common-mode feedback circuit module does not overlap with the phase in which the current comparator module for the high-precision digital-to-analog converter calibration circuit compares the input current, and during the operation of the current comparator module for the high-precision digital-to-analog converter calibration circuit, the switch in the common-mode feedback circuit module stops switching.

[0088] Furthermore, the common mode feedback circuit module includes a first capacitor C 1B , the second capacitor C 1A , the second switch K 3A , the third capacitor C 2B , the third switch K 3B , the fourth switch K 3C , the fourth capacitor C 2A , the fifth switch K 4A , the sixth switch K 4B And the seventh switch K 4C The first capacitor C 1B The first end of the first capacitor C is connected to the common mode current signal unit. 1B The second end of the second capacitor C is connected to the differential mode current signal unit; 1A The first end of the first capacitor C is connected to the common mode current signal unit. 1B The second end of the second switch K is connected to the differential mode current signal unit; 3A The first end of the third capacitor C is connected to the common mode current signal unit; 2B The first end of the second switch K 3A The second end of the third switch K 3B The first end of the first capacitor C 1B The second end of the third switch K 3B The second end of the third capacitor C 2B The second end of the fourth switch K 3C The first end and the second capacitor C 1A The second end of the fourth capacitor C 2A The first end of the fourth switch K 3C The second end of the fourth capacitor C 2A The second end of the second switch K 3A The second end of the fifth switch K 4A The first terminal and the fourth capacitor C 2A The second end of the fifth switch K 4A The second end of the sixth switch K is connected to the output port VBN2; 4B The first end of the third switch K 3B The second end of the sixth switch K 4B The second end of the seventh switch K is connected to the output port VCMO; 4C The first end of the fourth capacitor C 2A The first end of the seventh switch K 4C The second end of is connected to the output port VCMO.

[0089] Specifically, the first capacitor C 1B The second end of the first capacitor C is connected to the gate of the sixth NMOS transistor NM2; 1B The second end of the second switch K is connected to the gate of the sixth NMOS tube NM2; 3A The first end is connected to the gate of the sixth NMOS transistor NM2.

[0090] Compared with the prior art, the present invention removes the offset compensation amplifier and the input point cross-coupling switch, and introduces a switched capacitor common mode feedback circuit (SC-CMFB). The current comparator offset calibration function is transferred to the system level outside the current comparator for consideration. In the current-to-voltage conversion module, Figure 1 The current signal branches of the PM3 tube, NM3 tube, and NM2 tube in the present invention are decomposed into two: a differential mode current signal unit flowing through the PMOS tube PM3, the NMOS tube NM3, and the third NMOS tube NM1, and a common mode current signal branch flowing through the NMOS tube NM4 and the sixth NMOS tube NM2. The direct current (DC) current of the differential mode current signal unit is fixed by the tail current source NM1 tube, and the DC current of the common mode circuit signal unit is provided by the common mode feedback circuit module. Therefore, when the common mode of the input current changes, the changing common mode current will all flow through the common mode current signal unit, and the DC current of the differential mode current signal unit will not change. Therefore, the current voltage gain of the input differential mode current signal to the differential input terminal of the dynamic comparator is almost unchanged, and the minimum resolvable current of the comparator will not change with the change of the input common mode current. This makes the current comparator proposed by the present invention very suitable for the calibration of current steering DACs with more than three segments.

[0091] Figure 5 It is the working timing of the current comparator circuit proposed in the present invention in DAC calibration. P1 is the common mode establishment phase of the current comparator. In this phase, the switch K5 (first switch) is closed, and the capacitor C1 (second capacitor C 1A and the fourth capacitor C 2A )、Capacitor C2 (third capacitor C 2B and the fourth capacitor C 2A )、Switch K3 (second switch K 3A , the third switch K 3B and the fourth switch K 3C )、Switch K4 (fifth switch K 4A , the sixth switch K 4B and the seventh switch K 4C ) stabilizes the common-mode voltage at OP and ON to VCMO under the two-phase non-overlapping clocks F1 and F2. When the P1 phase ends, capacitor C2 is disconnected, while capacitor C1 is always connected between the NM2 gate and the OP / ON node. The I2V (current-to-voltage conversion module) always has an inherent common-mode feedback loop during the calibration process. Therefore, in the subsequent MSB calibration process, there is no need to refresh the common mode at each comparison step, which saves a lot of calibration time.

[0092] When the common-mode input current of the present invention changes, the changed common-mode current will all flow through the common-mode current signal unit, while the current voltage gain from the differential-mode current signal unit to the differential input terminal of the dynamic comparator remains almost unchanged, so that the minimum resolvable current of the current comparator module used in the high-precision digital-to-analog converter calibration circuit will not change with the input common-mode current change, so that the current comparator module for the high-precision digital-to-analog converter calibration circuit proposed by the present invention can be applied to the calibration of current steering DACs with more than three segments, solving the problem that the current comparator circuit in the prior art is difficult to be generalized and applied to three-segment DACs.

[0093] Example 2

[0094] An embodiment of the present invention further provides a digital-to-analog converter, comprising a current comparator module for a high-precision digital-to-analog converter calibration circuit as described in any one of the first embodiments.

[0095] Further, the input current I of the current comparator module used in the high-precision digital-to-analog converter calibration circuit IP Connected to the reference DAC, used as the input current I of the current comparator module of the high-precision DAC calibration circuit IN Connect to the reference current.

[0096] In the present invention, the offset calibration function of the comparator is transferred to the input end of the current comparator module for the high-precision digital-to-analog converter calibration circuit. A range can cover the sum of the comparator offset range and the DAC current source mismatch range. The L-bit reference DAC (Ref.DAC) with a minimum current step size smaller than the LSB of the cal-DAC in the MSB is connected to the positive input end of the current comparator. In the CALR phase, the reference current is connected to the negative input end of the current comparator, and the SAR logic adjusts the control word of the Ref.DAC so that the current of the Ref.DAC approaches the sum of the reference current and the current comparator input offset current. Then in the MSB <1> Calibration CAL <1> , the control word of Ref.DAC remains unchanged, the MSB <1> Instead of the reference current being connected to the negative input of the current comparator, the SAR logic adjusts the MSB <1> The control word of the cal-DAC makes the voltages at OP and ON equal to complete the MSB <1> When the MSB <1> After the current source current calibration is completed, the calibration of the remaining MSB current sources can be performed in sequence to complete the calibration of the entire DAC. Since switch K3 has a weak PN junction reverse bias leakage, the design can choose to open SC-CMFB again to refresh the common mode voltage at OP and ON after several MSB calibrations are completed according to the actual leakage situation ( Figure 5 The current source is refreshed once for each MSB after calibration.

[0097] When the current comparator module for the high-precision digital-to-analog converter calibration circuit proposed in the present invention is applied to the calibration of the three-segment DAC, after all USB current sources have completed the calibration, it is necessary to open the SC-CMFB again to refresh the common mode of I2V, and use the Ref.DAC to re-calibrate the offset, and then calibrate the MSB current source.

[0098] The excellent effects of the present invention are: 1. The separation of the differential mode input current signal and the common mode input current signal through the branch ensures the stability of the input differential current to voltage conversion gain; 2. The switch common mode feedback circuit ensures the stability of the internal operating point of the current comparator, so that the comparator can be calibrated continuously, thereby improving the calibration speed; 3. The current comparator offset calibration function is transferred to the system level, which can more accurately eliminate the influence of the comparator's own offset on the calibration.

[0099] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0100] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A current comparator module for a high-precision digital-to-analog converter calibration circuit, comprising a current-to-voltage conversion module and a dynamic comparator connected to the current-to-voltage conversion module, characterized in that: The current-voltage conversion module includes a first PMOS tube connected to the gate, a second PMOS tube, a third PMOS tube connected to the gate, a fourth PMOS tube, a differential mode current signal unit and a common mode current signal unit; The differential mode current signal unit is respectively connected to the drain of the first PMOS tube, the drain of the second PMOS tube, the drain of the third PMOS tube, the drain of the fourth PMOS tube and the dynamic comparator of the current-voltage conversion module; the common mode current signal unit is respectively connected to the drain of the first PMOS tube, the drain of the second PMOS tube, the drain of the third PMOS tube, and the drain of the fourth PMOS tube of the current-voltage conversion module; The drain of the first PMOS tube is also connected to the input current I IN The drain of the second PMOS tube is also connected to the input current I IP Unit connection; The current comparator module further includes: A common mode feedback circuit module, wherein an input end of the common mode feedback circuit module is connected to an input end of the dynamic comparator, and a feedback point of the common mode feedback circuit is connected to a tail current source of the common mode current signal unit.

2. The current comparator module for a high-precision digital-to-analog converter calibration circuit according to claim 1, characterized in that: The common-mode feedback circuit module is a switched capacitor common-mode feedback circuit, the common-mode voltage information of the common-mode feedback circuit module is extracted from the high-resistance node on the differential-mode current signal unit, and the feedback point of the common-mode feedback circuit module is at the tail current source of the common-mode current signal unit.

3. The current comparator module for a high-precision digital-to-analog converter calibration circuit according to claim 2, characterized in that: The operating phase of the common-mode feedback circuit module does not overlap with the phase of the current comparator module for the high-precision digital-to-analog converter calibration circuit comparing the input current, and during the operation of the current comparator module for the high-precision digital-to-analog converter calibration circuit, the switch in the common-mode feedback circuit module stops switching.

4. The current comparator module for a high-precision digital-to-analog converter calibration circuit according to claim 1, characterized in that: The current-voltage conversion module also includes: A first PMOS transistor, wherein a source of the first PMOS transistor is connected to an input voltage VDD; A second PMOS tube, wherein a source of the second PMOS tube is connected to the input voltage VDD; A third PMOS tube, wherein a source of the third PMOS tube is connected to the input voltage VDD; A fourth PMOS tube, wherein a source of the fourth PMOS tube is connected to the input voltage VDD.

5. The current comparator module for a high-precision digital-to-analog converter calibration circuit according to claim 1, characterized in that: The differential mode current signal unit comprises: The fifth PMOS tube, the source of the fifth PMOS tube is respectively connected to the input current I IN , the current-voltage conversion module is connected, and the drain of the fifth PMOS tube is connected to the negative input terminal of the dynamic comparator; The sixth PMOS tube, the source of the sixth PMOS tube is respectively connected to the input current I IP , the current-voltage conversion module is connected, and the gate of the sixth PMOS tube is connected to the gate of the fifth PMOS tube, and the drain of the fifth PMOS tube is connected to the positive input terminal of the dynamic comparator; a first switch, wherein two ends of the first switch are respectively connected to the drain of the fifth PMOS tube and the drain of the sixth PMOS tube; a first NMOS transistor, wherein a drain of the first NMOS transistor is respectively connected to the first end of the first switch and the drain of the fifth PMOS transistor; a second NMOS transistor, wherein a drain of the second NMOS transistor is respectively connected to the second end of the first switch and the drain of the sixth PMOS transistor, and a gate of the second NMOS transistor is connected to the gate of the first NMOS transistor; A third NMOS tube, wherein the drain of the third NMOS tube is respectively connected to the source of the first NMOS tube and the source of the second NMOS tube, and the source of the third NMOS tube is connected to the output voltage VSS.

6. The current comparator module for a high-precision digital-to-analog converter calibration circuit according to claim 5, characterized in that: The gate of the third NMOS tube is connected to the output port V BN1 connect.

7. The current comparator module for a high-precision digital-to-analog converter calibration circuit according to claim 1, characterized in that: The common mode current signal unit comprises: The fourth NMOS tube, the drain of the fourth NMOS tube is respectively connected to the current-voltage conversion module and the input current I IN connect; A fifth NMOS tube, the drain of which is connected to the current-voltage conversion module and the input current I IP The gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube; A sixth NMOS tube, wherein the drain of the sixth NMOS tube is respectively connected to the source of the fourth NMOS tube and the source of the fifth NMOS tube, the gate of the sixth NMOS tube is connected to the common-mode feedback circuit module, and the source of the sixth NMOS tube is connected to the output voltage VSS.

8. The current comparator module for a high-precision digital-to-analog converter calibration circuit according to claim 1, characterized in that: The common mode feedback circuit module comprises: a first capacitor, wherein a first end of the first capacitor is connected to the common-mode current signal unit, and a second end of the first capacitor is connected to the differential-mode current signal unit; A second capacitor, wherein a first end of the second capacitor is connected to the common-mode current signal unit, and a second end of the first capacitor is connected to the differential-mode current signal unit; a second switch, wherein a first end of the second switch is connected to the common mode current signal unit; a third capacitor, a first end of the third capacitor being connected to the second end of the second switch; a third switch, wherein a first end of the third switch is connected to the second end of the first capacitor, and a second end of the third switch is connected to the second end of the third capacitor; a fourth switch, wherein a first end of the fourth switch is connected to a second end of the second capacitor; a fourth capacitor, wherein a first end of the fourth capacitor is connected to the second end of the fourth switch, and a second end of the fourth capacitor is connected to the second end of the second switch; a fifth switch, wherein a first end of the fifth switch is connected to the second end of the fourth capacitor, and a second end of the fifth switch is connected to the output port VBN2; a sixth switch, wherein a first end of the sixth switch is connected to a second end of the third switch, and a second end of the sixth switch is connected to an output port VCMO; A seventh switch, wherein a first end of the seventh switch is connected to the first end of the fourth capacitor, and a second end of the seventh switch is connected to the output port VCMO.

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