Amplifiers and mixers in III-V materials for broadband sub-terahertz communications

Abstract

Embodiments herein relate to systems, devices or processes for a package for broadband sub-terahertz communications, where the package includes a mixer and an amplifier, such as a power amplifier or a low noise amplifier, implemented within a layer of Group III-V material. Other embodiments may be described and / or claimed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to the field of package assemblies, and more particularly, to package assemblies that include broadband communications circuitry. Background Art

[0002] The continued reduction in final product size of mobile electronic devices, such as smartphones and ultrabooks, is a driving force for the development of integrated circuit packaging that includes broadband wireless communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A cross-sectional side view of an older implementation of a silicon-based package including a broadband component is shown.

[0004] Figure 2A-2B A cross-sectional side view of an example of a sub-terahertz broadband communication package including baseband components in a silicon layer and amplifier and mixer components in a III-V layer according to various embodiments is shown.

[0005] Figure 3 A cross-sectional side view of an example of a sub-terahertz broadband communication package including a controller in a silicon layer coupled to one or more broadband communication components in a III-V group layer on the silicon layer according to various embodiments is shown.

[0006] Figure 4 A cross-sectional side view of an example of a sub-terahertz broadband communication package according to various embodiments is shown, the sub-terahertz broadband communication package including two chips including III-V layers on a silicon layer, wherein one chip is a transmitter and the other chip is a receiver.

[0007] Figure 5 A cross-sectional side view of an example of a sub-terahertz broadband communication package according to various embodiments is shown, the sub-terahertz broadband communication package including a chip, the chip including a III-V group layer located on a silicon layer, the III-V group layer including a transmitter, and the silicon layer including a receiver.

[0008] Figure 6 A top view of an example of a silicon layer with various chips thereon including III-V layers with sub-terahertz broadband communication components according to various embodiments is shown.

[0009] Figure 7A-7B Top and cross-sectional side views of wired and wireless communications between a chip and an antenna including III-V layers of a sub-terahertz broadband communications package are shown according to various embodiments.

[0010] Figure 8An example of a process for fabricating a sub-terahertz broadband communication package formed at least partially within III-V family layers according to various embodiments is shown.

[0011] Fig. 9 A computing device according to an embodiment is schematically shown. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure may generally relate to systems, devices, and / or processes for packages for broadband sub-terahertz or greater than 100 GHz communications, wherein the package includes mixers and amplifiers, such as power amplifiers or low noise amplifiers, implemented within a III-V material layer. In an embodiment, the III-V material layer may be within a chip or die. In an embodiment, the III-V material layer may be on a silicon layer or a CMOS layer that includes other components that support broadband sub-terahertz communications, such as baseband receive and / or baseband transmit circuitry.

[0013] In embodiments described herein, local oscillator (LO) distribution paths may be split between silicon layers and III-V material layers. In embodiments, such splitting may facilitate the generation of high performance phase locked loops (PLLs) and low to medium frequency multipliers, which may be referred to herein as multipliers, within the silicon domain while eliminating the need for broadband radio frequency (RF) routing between silicon layers and III-V material layers.

[0014] In an embodiment, the III-V material layer may also include an IQ phase generator, such as an orthogonal mixer, which may be coupled to the mixer and / or multiplier. In other embodiments, portions of the multiplier may exist in the III-V material layer and in the silicon layer. In other embodiments, other components, such as controllers, data converters, equalizers, power management circuitry, digital processing circuitry, and / or memory subsystems, may be fabricated within the silicon layer and may be electrically coupled to various components within the III-V material layer, such as amplifiers, mixers, IQ phase generators, and / or multipliers. In an embodiment, the PLL may be implemented at least partially within the silicon layer and coupled to one or more multipliers that may be located within the III-V material layer.

[0015] In embodiments, the locations of various components in the III-V material layer or silicon layer may be selected based on the processing capabilities of the III-V layer and the silicon layer, such as unit current gain frequency (ft), unit power gain frequency (fmax), transistor density, and digital performance, all of which affect system-level performance requirements. In embodiments, the locations of various components may be separated within a local oscillator (LO) distribution path. In other embodiments, the locations of various components may be separated at the output / input of a baseband signal path that may be located within the silicon layer and may be just before the input / output of a mixer that may be located in the III-V material layer.

[0016] In an embodiment, the LO multiplication may be distributed relative to the LO distribution path by using a multiplier implemented in the silicon layer coupled to a multiplier implemented in the III-V material layer. As a result, this may facilitate routing a single-phase LO frequency at a portion of the carrier that crosses the silicon / III-V boundary. In an embodiment, passive IQ generation may be performed locally at the mixers in the III-V layer. In an embodiment, all sub-terahertz range circuitry may be implemented in the III-V layer to improve gain, noise, output power capability, and power efficiency. In an embodiment, all or part of the baseband circuitry may be implemented in the silicon layer, where higher integration and scaling may be achieved.

[0017] In an embodiment, by implementing portions of a package for broadband sub-terahertz communications at least partially in a III-V material layer, bandwidth enhancement may be achieved compared to legacy implementations. Additionally, by implementing a sub-terahertz block including portions of LO generation in a III-V material, power efficiency may be improved. Additionally, there may be greater flexibility in positioning the III-V layer relative to the silicon layer, such that a lower frequency and / or lower bandwidth interface may be provided between the silicon layer and the III-V material layer, and therefore higher losses may be tolerated. Furthermore, an embodiment may provide a more scalable architecture compared to legacy implementations.

[0018] In these systems, scalability is often limited by LO distribution issues. A higher frequency LO cannot be easily distributed among many components. By generating a lower frequency and single-phase LO in the silicon layer, the same LO can more easily fan out and obtain the LO input of many front-end components implemented in the III-V layer.

[0019] In legacy implementations, only radio frequency (RF) signals can be passed between the silicon layer and the III-V material layer. However, in the embodiments described herein, multiple signals can be routed between the silicon layer and the III-V material layer, such as but not limited to single-phase local oscillators and baseband signals. In these legacy implementations, broadband through-silicon vias (TSVs) or broadband connections are typically required to deliver broadband modulated signals between chips. In legacy implementations, wire bonding components are used between the silicon layer and the III-V material layer, which, in addition to providing high selectivity of wire bonding length, may also provide limited bandwidth performance, which may challenge component tolerances. In addition, as the operating frequency increases, these legacy connections may result in higher losses and become more difficult to optimize.

[0020] In the detailed description hereinafter, reference will be made to the accompanying drawings which constitute part of the detailed description, wherein similar parts are represented by similar reference numerals throughout, and wherein embodiments in which the subject matter of the present disclosure may be practiced are shown by way of example. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed in a restrictive sense, and the scope of the embodiments is limited only by the appended claims and their equivalents.

[0021] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0022] The specification may use perspective-based descriptions, such as top / bottom, inside / outside, over / under, etc. Such descriptions are only used to facilitate discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0023] The description may use the phrase "in an embodiment," which may refer to one or more of the same or different embodiments. Furthermore, the terms "including," "having," and the like used in conjunction with the embodiments of the present disclosure are synonymous.

[0024] The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following meanings. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements said to be coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact.

[0025] Various operations may be described as multiple discrete operations in sequence in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent.

[0026] As used herein, the term "module" may refer to, include, or be part of: an ASIC, an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, and / or other appropriate components that provide the described functionality.

[0027] The figures herein may depict one or more layers of one or more packaged components. The layers depicted herein are depicted as examples of relative positions of layers of different packaged components. The layers are depicted for purposes of explanation and are not drawn to scale. Therefore, relative sizes of layers should not be assumed from the drawings, and for some embodiments, sizes, thicknesses, or dimensions may be assumed only where specifically indicated or discussed.

[0028] Various embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon, which, when executed, cause the actions of any of the embodiments described above. In addition, some embodiments may include a device or system having any appropriate module units for implementing the various operations of the embodiments described above.

[0029] Figure 1 A cross-sectional side view of an older embodiment of a silicon-based package including broadband components is shown. Package 100, which may also be referred to as a transceiver, includes a silicon layer 102 communicatively coupled to an antenna structure 106. In an embodiment, silicon layer 102 may be a chip or die. In an embodiment, silicon layer 102 includes a power amplifier 110 that may be communicatively coupled to antenna structure 106 and a first mixer 112 that may be coupled to power amplifier 110.

[0030] The first IQ phase generator 114 may be within the silicon layer 102 and may be communicatively coupled to the first mixer 112. The first multiplier 116 may be communicatively coupled to the first IQ phase generator 114. In an embodiment, a transmit baseband circuitry (TXBB) 118 may be communicatively coupled to the first mixer 112. The power amplifier 110, the first mixer 112, the first IQ phase generator 114, the first multiplier 116, and the TXBB 118 may be part of a transmitter circuitry within the silicon layer 102.

[0031] The silicon layer 102 may include a low noise amplifier 120, which may be communicatively coupled to the antenna structure 106. A second mixer 122 may be coupled to the low noise amplifier 120. A second IQ phase generator 124 may be coupled to the second mixer 122, and a second multiplier 126 may be coupled to the second IQ phase generator 124. In an embodiment, a receive baseband circuitry (RXBB) 128 may be communicatively coupled to the second mixer 122. A PLL 130 may be coupled to the first multiplier 116 and the second multiplier 126.

[0032] In these legacy implementations, silicon layer 102 may represent a monolithic system-on-chip solution. In these implementations, co-integration of two high frequency front end blocks (e.g., mixers 112, 122, power amplifier 110, and low noise amplifier 120) may not be sufficient to support high performance baseband and digital processing, such as for communications in the sub-terahertz range. Additionally, when the high frequency blocks are implemented in CMOS technology, the performance, area requirements, and power efficiency of the high frequency blocks may be limited.

[0033] In some legacy implementations, a III-V layer (not shown) may be present between the silicon layer 102 and the antenna structure 106 to amplify and drive a broadband modulated sub-terahertz carrier outside the silicon layer 102. As a result, these legacy implementations involve routing the broadband modulated signal off-chip and also require a broadband interface between the silicon layer 102 (which may be referred to as a CMOS layer) and the III-V component layer. However, these legacy implementations may be costly and power inefficient due to the loss and reduced bandwidth of the off-chip routing.

[0034] In older implementations that use a combination of silicon layer 102 and III-V material layers (not shown) to build a sub-terahertz transceiver chain, mixers 112, 122 and / or power amplifier 110 and low noise amplifier 120 are positioned within silicon layer 102. These older implementations result in routing broadband modulated signals off-chip, which requires a broadband, low-loss interface between silicon layer 102 and III-V layers (not shown).

[0035] Figure 2A-2B A cross-sectional side view of an example of a sub-terahertz broadband communication package including baseband components in a silicon layer and amplifier and mixer components in a III-V layer according to various embodiments is shown.

[0036] Figure 2A A package 200A is shown, which may also be referred to as a transceiver and may be similar to Figure 1The package 200A may include a power amplifier 210, a first mixer 212, a first IQ phase generator 214, and a first multiplier 216, which may be similar to Figure 1 The package 200A may further include a low noise amplifier 220, a second mixer 222, a second IQ phase generator 224, and a second multiplier 226, which may be similar to the power amplifier 110, the first mixer 112, the first IQ phase generator 114, and the first multiplier 116. Figure 1 The low noise amplifier 120, the second mixer 122, the second IQ phase generator 124 and the second multiplier 126 are provided.

[0037] However, Figure 1 Unlike the package 100 of FIG. 1 , the power amplifier 210 and the first mixer 212 and / or the low noise amplifier 220 and the second mixer 222 may be located within the III-V material layer 204. In an embodiment, the III-V material layer 204 may be part of a chip or die, and in an embodiment, may be a layer transferred to the top of the die or wafer. In an embodiment, the III-V material layer 204 may be located on the silicon layer 202, and the silicon layer 202 may be similar to Figure 1 The silicon layer 102. In an embodiment, the first IQ phase generator 214 and / or the multiplier 216 may also be located in the III-V material layer 204. In an embodiment, the second IQ phase generator 224 and the second multiplier 226 may be located in the III-V material layer 204.

[0038] In an embodiment, the silicon layer 202 may also be referred to as a CMOS layer, and may include Figure 1 TXBB 118 is similar to TXBB 218 and may be coupled to first mixer 212. In an embodiment, Figure 1 RXBB 228 similar to RXBB 128 may be located in silicon layer 202 and may be coupled to second mixer 222. In an embodiment, there may be a third multiplier 217 in silicon layer 202, which may be coupled to first multiplier 216 located in III-V material layer. In an embodiment, there may be a fourth multiplier 227 in silicon layer 202, which may be coupled to second multiplier 226 located in III-V material layer. In an embodiment, there may be a third multiplier 217 in silicon layer 202, which may be coupled to first multiplier 216 located in III-V material layer. Figure 1 PLL 230 of PLL 130 may couple third multiplier 217 with fourth multiplier 227 .

[0039] In an embodiment, various components and their locations in the silicon layer 202 or the III-V material layer 204 may be selected to achieve optimal efficiency for each layer. In an embodiment, the PLL 230 and the frequency synthesizer, along with the third multiplier 217 and the fourth multiplier 227 that may be used to multiply the local oscillator signal, may be efficiently implemented within the silicon layer. These embodiments within the silicon layer 202 may provide a high performance and low noise implementation of the PLL 230, which may have lower power consumption, a wider frequency tuning range, and lower phase noise.

[0040] In an embodiment, TXBB 218 and RXBB 228 may be placed within silicon layer 202, with respective outputs and / or inputs to and / or from mixers 212, 222 crossing boundary 203 between silicon layer 202 and III-V material layer 204. In an embodiment, this approach exploits the high energy efficiency of CMOS-based processes for analog baseband processing, and also allows the architecture of TXBB 218 and RXBB 228 to allow for higher performance as CMOS scales to deeper nodes. In addition, due to scaling, the architecture may allow for increased complexity of TXBB 218 and RXBB 228 at lower cost, and also yield higher data speeds.

[0041] In addition, in an embodiment, passing baseband signals from TXBB 218 and RXBB 228 across boundary 203 to mixers 212, 222 in III-V material layer 204 can more easily provide higher bandwidth and lower loss for interconnection at baseband frequency rather than radio frequency. In addition, since the cut boundary is used as a ground impedance node, the embodiment can improve bandwidth compared to the old implementation, so that the off-chip interface can more easily handle wider modulation bandwidth than the radio frequency interface. In addition, lower loss and higher output power can also be achieved compared to the old implementation.

[0042] Moreover, in an embodiment, placing the mixers 212, 222 within the III-V material layer 204 also allows the local oscillator multiplication and division by the multipliers 216, 226 to be completed within the III-V material layer 204. In an embodiment, within the III-V material layer 204, the single-phase local oscillator signal from the silicon layer 202 can be further multiplied to the final carrier frequency and then distributed to the mixers 212, 222. In an embodiment, depending on the transceiver architecture of the package 200A, there can be optional quadrature generation by the IQ phase generators 214, 224 to facilitate up / down conversion of the baseband signal to the carrier frequency. In an embodiment, the outputs of the mixers 212, 222 can then be passed to the amplifiers 210, 220.

[0043] In embodiments, implementing power amplifier 210 and low noise amplifier 220 within III-V material layer 204 may achieve greater efficiency, greater output power, and reduced noise when operating at sub-terahertz frequencies. In some embodiments, fabricating some components (e.g., PLL 230) within silicon layer 202 may achieve greater area efficiency (e.g., smaller size) and greater power efficiency due to the higher density and greater interconnect options available for devices within silicon layer 202.

[0044] In an embodiment, the power amplifier 210 and / or the low noise amplifier 220 may be coupled to the antenna 206. In an embodiment, the antenna 206 may be implemented on a substrate 205 that may be selected for sub-terahertz performance, and the materials used for the antenna 206 may be selected to achieve low losses at sub-terahertz frequencies. In an embodiment, this coupling may be a wide bandwidth coupling so as to preserve the integrity of the modulated signal. As described below in conjunction with Figure 7A-7B As further described, in embodiments, wireless and / or wired coupling structures may be used, such as near-field coupling, capacitive coupling, resonant electromagnetic structures, etc. In embodiments, conventional conductive connections using controlled impedance connections such as transmission lines may also be used for coupling, using micro-bumps, through-substrate vias, direct copper to copper bonding pads, etc.

[0045] In an embodiment, higher carrier frequencies may be accommodated by the higher modulation bandwidth provided by the III-V material layer 204 , which accommodates higher voltages and higher speeds compared to silicon.

[0046] Figure 2B shows a package 200B, which may be similar to Figure 2A Package 200A. Package 200B shows an embodiment in which the third multiplier 217 in the silicon layer 202 is coupled to the IQ phase generator 214a in the III-V material layer 204. Note that in the embodiment, no Figure 2A The first multiplier 216 and the second multiplier 226 are located in the III-V material layer 204. It should be noted that in other embodiments, the first IQ phase generator 214a can be located in the silicon layer 202 (not shown).

[0047] Figure 3 A cross-sectional side view of an example of a sub-terahertz broadband communication package according to various embodiments is shown, the sub-terahertz broadband communication package including a controller located in a silicon layer coupled to one or more broadband communication components located in a III-V family layer on the silicon layer. Figure 2AThe package 300 of the package 200A includes an antenna 306 within a substrate 305, wherein the antenna 306 is coupled to a power amplifier 310 and a low noise amplifier 320, which may be located in the III-V material layer 304. In an embodiment, the power amplifier 310 may be coupled to a first mixer 312, a first IQ phase generator 314, and a first multiplier 316. In an embodiment, the low noise amplifier 320 may be coupled to a second mixer 322, a second IQ phase generator 324, and a second multiplier 326.

[0048] The III-V material layer 304 may be on the silicon layer 302, which may be referred to as a CMOS layer. The silicon layer 302 may include a TXBB 318 that may be coupled to the first mixer 312 and an RXBB 328 that may be coupled to the second mixer 322. In an embodiment, a controller 332 may be formed within the silicon layer 302 and may be electrically coupled to the first multiplier 316, the first IQ phase generator 314, the first mixer 312, the power amplifier 310, the low noise amplifier 320, the second mixer 322, the second IQ phase generator 324, and / or the second multiplier 326.

[0049] In an embodiment, the controller 332 may be used to control the power amplifier 310, for example, by tuning the output power, tuning the impedance, or tuning the bandwidth of the power amplifier 310. In an embodiment, the controller 332 may control the calibration of the first IQ phase generator 314 or the second IQ phase generator 324 to achieve a good phase balance between the in-phase (I) and quadrature (Q) wiring paths or minimize the amplitude imbalance, and in an embodiment, the in-phase (I) and quadrature (Q) wiring paths may be preferably 90 degrees. In an embodiment, the controller 332 may be used to control the antenna 306 by changing the impedance or perform impedance tuning for the antenna 306 by changing the way the radiated signal is changed. In some embodiments, the controller 332 may act as a virtual IQ phase generator within the silicon layer 302.

[0050] Figure 4 A cross-sectional side view of an example of a sub-terahertz broadband communication package according to various embodiments is shown, the sub-terahertz broadband communication package including two chips including III-V family layers on a silicon layer, wherein one chip is a transmitter and the other chip is a receiver. Figure 3 The package 400 of the package 300 includes a silicon layer 402, which may be similar to Figure 3 The silicon layer 302 can be similar to Figure 3 The transmitter chip 404a and the receiver chip 404b of a portion of the III-V material layer 304 may be on the silicon layer 402. In an embodiment, the transmitter chip 404a and the receiver chip 404b may be individual independent chips.

[0051] In an embodiment, the first multiplier 416, the first IQ phase generator 414, the first mixer 412, and / or the power amplifier 410 may be in the transmitter chip 404a, and the second multiplier 426, the second IQ phase generator 424, the second mixer 422, and the low noise amplifier 420 may be in the receiver chip 404b. In an embodiment, the antenna 406, which may be within the substrate 405, may be on the transmitter chip 404a and / or the receiver chip 404b and communicatively coupled with the transmitter chip 404a and / or the receiver chip 404b. In an embodiment, the TXBB 418 and the RXBB 428 may be within the silicon layer 402 and may be coupled to the first mixer 412 and the second mixer 422, respectively. In an embodiment, the transmitter chip 404a and the receiver chip 404b may include a substrate including different III-V materials.

[0052] Figure 5 A cross-sectional side view of an example of a sub-terahertz broadband communication package according to various embodiments is shown, the sub-terahertz broadband communication package including a chip including a III-V group layer including a transmitter located on a silicon layer including a receiver. Figure 4 The package 500 of the package 400 includes a silicon layer 502, which may be similar to Figure 4 In an embodiment, the silicon layer 502, which may be referred to as a CMOS layer, may include receiver components, which may include a low noise amplifier 520, a second mixer 522, a second IQ phase generator 524, and a third multiplier 527. The RXBB 528 may also be within the silicon layer 502 and coupled to the second mixer 522.

[0053] In an embodiment, a III-V material layer 504, which may be in the form of a chip, may be on the silicon layer 502 and may include transmitter components, which may include a first multiplier 516, which is coupled to a first IQ phase generator 514, which is in turn coupled to a first mixer 512. The first mixer 512 may be coupled to a power amplifier 510. In an embodiment, a layer 507a may be on the silicon layer 502 and may include an antenna 506. In an embodiment, the layer 507a may be a chip. In an embodiment, the layer 507a including the antenna 506 may be a layer transferred on top of the silicon layer 502 or may be a layer transferred on top of the III-V material layer 504. In an embodiment, the thickness of the antenna 506 or the layer 507a does not have to be the same as the thickness of the III-V material layer 504 or the silicon layer 502.

[0054] In an embodiment, layer 507a may be coupled to the III-V material layer 504, wherein the power amplifier 510 is coupled to the antenna 506. In an embodiment, such coupling may be wireless coupling or conductive coupling, such as metal line coupling. In an embodiment, a low noise amplifier 520 may also be coupled to the antenna 506. It should be understood that although in this embodiment the receiver components are located within the silicon layer 502 and the transmitter components are located within the III-V material layer 504, in other embodiments, the transmitter components may be located within the silicon layer 502 and the receiver components may be located within the III-V material layer 504. In an embodiment, the antenna 506 may be implemented within the III-V material layer (not shown).

[0055] Figure 6 600 shows a top view of an example of a silicon layer with various chips thereon, the chips including III-V layers with sub-terahertz broadband communication components according to various embodiments. Package 600 shows a top view, which includes a silicon layer 602, which can be similar to Figure 4 In an embodiment, the computer / processor region 603 within the silicon layer 602 may include a processor and / or computing circuitry that may communicate with transmitter / receiver baseband components (e.g., Figure 4 TXBB 418 and / or RXBB 428) are electrically coupled.

[0056] In an embodiment, it can be similar to Figure 2A The III-V material layer 604a of the III-V material layer 204 may be on the silicon layer 602. In an embodiment, the III-V material layer 604a may include a combination of Figure 2A In an embodiment, the III-V material layer 604a may be in the form of a chip or a tube die. In an embodiment, it may be similar to Figure 4 Antenna 606a of antenna 406 may be on top of and communicatively coupled to group III-V material layer 604a.

[0057] In an embodiment, it can be similar to Figure 5 The III-V material layer 604b of the III-V material layer 504 may be on the silicon layer 602. In an embodiment, the III-V material layer 604b may include a transmitter component, and the receiver component is within the silicon layer 602, which is similar to the combination of Figure 5 In an embodiment, antenna 606 b , which may be similar to antenna 606 a , may be communicatively coupled to group III-V material layer 604 b and may be communicatively coupled to silicon layer 602 .

[0058] In an embodiment, the first chip 604c includes a III-V group material layer, which may include a layer similar to Figure 4 The transmitter components of the components within the transmitter chip 404a of FIG. 4 , the first chip 604c may be on the silicon layer 602. In an embodiment, the second chip 604d including the III-V material layer may be on the silicon layer 602 and may be close to the first chip 604c. In an embodiment, the III-V material layer in the second chip 604d may include a receiver component, which may be similar to Figure 4 In an embodiment, the antenna 606c may be on the first chip 604c and the second chip 604d. In an embodiment, the antenna 606c may be a layer transferred onto the silicon layer 602.

[0059] Figure 7A-7B Top and cross-sectional side views of wired and wireless communications between a chip and an antenna including III-V layers of a sub-terahertz broadband communications package are shown according to various embodiments. Fig. 7A , which includes a silicon layer 702 and a III-V material layer 704, the III-V material layer 704 including a transmitter portion 704a and a receiver portion 704b. In an embodiment, the silicon layer 702 may be similar to Figure 2A In an embodiment, the emitter portion 704a may include a silicon layer 202. Figure 2A The receiver portion 704b may include components of the first multiplier 216, the first IQ phase generator 214, the first mixer 212, and the power amplifier 210. In an embodiment, the receiver portion 704b may include components similar to Figure 2A The second multiplier 226, the second IQ phase generator 224, the second mixer 222 and the low noise amplifier 220 are components of the low noise amplifier 220.

[0060] The cross section shows antenna 707 within substrate 705, which may be similar to Figure 2A 706 and substrate 205. In an embodiment, electrical connector 709 can be between transmitter portion 704a and receiver portion 704b. In an embodiment, wire 711 can directly physically and electrically couple antenna 707 to electrical connector 709. In an embodiment, wire 711 can be some other metal or conductive material. In this way, antenna 707 can be directly physically and electrically coupled to components within III-V material layer 704.

[0061] Figure 7B Can be similar to Fig. 7A, except that wireless component 713 may be electrically coupled to electrical device 709, which may communicate wirelessly with antenna 707. Such devices include capacitively coupled structures such as patches or slots, near-field coupled structures, cavity resonators, or other resonant elements.

[0062] Figure 8 An example of a process for manufacturing a sub-terahertz broadband communication package formed at least partially within a III-V family layer according to various embodiments is shown. In embodiments, the present invention may be used, particularly in conjunction with Figure 2A-7B The described techniques, devices, systems and / or processes may be used to implement process 800.

[0063] At block 802, the process may include forming a mixer in a layer including a III-V material. In an embodiment, the mixer may be similar to Figure 2A-2B The first mixer 212 or the second mixer 222, Figure 3 The first mixer 312 or the second mixer 322, Figure 4 The first mixer 412 or the second mixer 422, or Figure 5 The first mixer 512 is configured to:

[0064] At block 804, the process may also include forming an amplifier in the layer. In an embodiment, the amplifier may be similar to Figure 2A-2B A power amplifier 210 or a low noise amplifier 220, Figure 3 A power amplifier 310 or a low noise amplifier 320, Figure 4 A power amplifier 410 or a low noise amplifier 420, or Figure 5 A power amplifier 510 is provided.

[0065] At block 806, the process may also include electrically coupling the mixer to the amplifier.

[0066] Fig. 9 is a schematic diagram of a computer system 900 according to an embodiment of the present invention. According to any of the several disclosed embodiments set forth in the present disclosure and their equivalents, the computer system 900 (also referred to as electronic system 900) as shown can embody amplifiers and mixers in III-V materials for broadband sub-terahertz communications. The computer system 900 can be a mobile device such as a netbook computer. The computer system 900 can be a mobile device such as a wireless smart phone. The computer system 900 can be a desktop computer. The computer system 900 can be a handheld reader. The computer system 900 can be a server system. The computer system 900 can be a supercomputer or a high performance computing system.

[0067] In an embodiment, the electronic system 900 is a computer system that includes a system bus 920 that electrically couples various components of the electronic system 900. The system bus 920 is a single bus or any combination of busses according to various embodiments. The electronic system 900 includes a voltage source 930 that provides power to the integrated circuit 910. In some embodiments, the voltage source 930 supplies current to the integrated circuit 910 through the system bus 920.

[0068] The integrated circuit 910 is electrically coupled to the system bus 920 and includes any circuit or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 910 includes a processor 912 that can be of any type. As used herein, the processor 912 can represent any type of circuit, such as but not limited to a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, as disclosed herein, the processor 912 includes or is coupled to an amplifier and a mixer for broadband sub-terahertz communication in III-V materials. In an embodiment, an SRAM embodiment is present in a memory cache of the processor. Other types of circuits that may be included in the integrated circuit 910 are custom circuits or application specific integrated circuits (ASICs), such as communication circuits 914 for use in wireless devices or communication circuits for servers, such as cellular phones, smart phones, pagers, portable computers, walkie-talkies, and similar electronic systems. In an embodiment, the integrated circuit 910 includes an on-die memory 916, such as a static random access memory (SRAM). In an embodiment, integrated circuit 910 includes embedded on-die memory 916, such as embedded dynamic random access memory (eDRAM).

[0069] In an embodiment, integrated circuit 910 is supplemented with a subsequent integrated circuit 911. Useful embodiments include dual processors 913, dual communication circuits 915, and dual on-die memory 917, such as SRAM. In an embodiment, dual integrated circuit 910 includes embedded on-die memory 917, such as eDRAM.

[0070] In an embodiment, the electronic system 900 also includes an external memory 940, which in turn may include one or more memory elements suitable for a particular application, such as a main memory 942 in the form of RAM, one or more hard disk drives 944, and / or one or more drives that manipulate removable media 946, such as floppy disks, compact disks (CDs), digital versatile disks (DVDs), flash memory drives, and other removable media known in the art. According to an embodiment, the external memory 940 may also be an embedded memory 948, such as the first die in the die stack.

[0071] In an embodiment, the electronic system 900 further includes a display device 950, an audio output 960. In an embodiment, the electronic system 900 includes an input device such as a controller 970, which may be a keyboard, a mouse, a trackball, a game controller, a microphone, a voice recognition device, or any other input device that inputs information into the electronic system 900. In an embodiment, the input device 970 is a camera. In an embodiment, the input device 970 is a digital audio recorder. In an embodiment, the input device 970 is a camera and a digital audio recorder.

[0072] As shown herein, an integrated circuit 910 including a packaging substrate having an amplifier and a mixer for broadband sub-terahertz communications located in III-V materials according to any of the several disclosed embodiments and their equivalents may be implemented in accordance with a wide variety of different embodiments, and an electronic system including a packaging substrate, a computer system, one or more methods of making an integrated circuit including a packaging substrate, and one or more methods of making an electronic assembly including a packaging substrate may also be implemented, wherein the packaging substrate has an amplifier and a mixer for broadband sub-terahertz communications located in III-V materials according to any of the several disclosed embodiments set forth herein in various embodiments and their art-recognized equivalents. According to any of the several disclosed packaging substrate embodiments having an amplifier and a mixer for broadband sub-terahertz communications located in III-V materials and their equivalents, the components, materials, geometries, dimensions, and order of operations may be varied to accommodate specific I / O coupling requirements including array contact count, array contact configuration, for a microelectronic die embedded in a processor mounting substrate. Such may include, for example, Fig. 9 The base substrate represented by the dotted line in FIG. Fig. 9 The passive components depicted in .

[0073] Although specific embodiments have been illustrated and described herein for purposes of description, a wide range of alternative and / or equivalent embodiments or implementations calculated to achieve the same purpose may be substituted for the illustrated and described embodiments without departing from the scope of the present disclosure. This application is intended to cover any adaptation or variation of the embodiments discussed herein. Therefore, it is expressly intended that the embodiments described herein be limited only by the claims.

[0074] When the disclosure refers to "a" or "first" element or its equivalent, such disclosure includes one or more such elements, and neither requires nor excludes two or more such elements. In addition, the use of ordinal indicators (e.g., first, second, or third) for identified elements to distinguish between elements does not indicate or imply a required or limited number of such elements, nor do they indicate a specific position or order of such elements unless specifically indicated otherwise.

[0075] Various embodiments may include any suitable combination of the embodiments described above, including alternative (or) embodiments of the embodiments described above in combination (and) (e.g., "and" may be "and / or"). In addition, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon, which, when executed, cause the actions of any of the embodiments described above. In addition, some embodiments may include a device or system having any suitable module units for implementing the various operations of the embodiments described above.

[0076] The above description of the illustrated embodiments, including the content described in the Abstract, is not intended to be exclusive or to limit the embodiments to the exact forms disclosed. Although specific embodiments are described herein for illustrative purposes, various equivalent modifications may exist within the scope of these embodiments, which will be recognized by those skilled in the relevant art.

[0077] These modifications may be made to the embodiments in light of the detailed description above. The terms used in the following claims should not be interpreted to limit the embodiments to the specific implementations disclosed in the specification and claims. Instead, the scope of the present invention will be determined entirely by the following claims, which should be interpreted in accordance with recognized principles of claim interpretation.

[0078] Example

[0079] The following paragraphs describe examples of various embodiments.

[0080] Example 1 is a device comprising: a layer comprising a III-V material; a mixer in the layer; and an amplifier in the layer, wherein the mixer and the amplifier are electrically coupled to each other

[0081] Example 2 includes the apparatus of Example 1, wherein the amplifier is a selected one of: a low noise amplifier or a power amplifier.

[0082] Example 3 includes the apparatus of Example 1 or 2, further comprising an IQ phase generator in the layer, wherein the IQ phase generator and the mixer are electrically coupled to each other.

[0083] Example 4 includes the apparatus of Example 3, further comprising a frequency multiplier in the layer, wherein the multiplier and the IQ phase generator are electrically coupled to each other.

[0084] Example 5 includes a device according to Example 1, 2, 3 or 4, wherein the mixer is a first mixer, wherein the amplifier is a first amplifier, and wherein the first amplifier is a power amplifier; and further includes: a second mixer in the layer; and a second amplifier in the layer, wherein the second amplifier is a low noise amplifier, and wherein the second mixer and the second amplifier are electrically coupled to each other.

[0085] Example 6 includes the apparatus of Example 1, 2, 3, 4, or 5, wherein the amplifier is electrically coupled to the antenna.

[0086] Example 7 includes the apparatus of Examples 1, 2, 3, 4, 5, or 6, wherein the layer is located within a selected one of: a chip or a die.

[0087] Example 8 is a system for broadband communications, the system comprising: a first layer comprising a III-V material; a mixer in the first layer; an amplifier in the first layer, wherein the amplifier and the mixer are electrically coupled to each other; a second layer comprising silicon; and a baseband circuit system in the second layer, wherein the baseband circuit system is electrically coupled to the mixer.

[0088] Example 9 includes a system according to Example 8, wherein the amplifier is a selected one of the following: a power amplifier or a low noise amplifier, and wherein the baseband circuit system is a selected one of the following: a transmitter baseband circuit system or a receiver baseband circuit system.

[0089] Example 10 includes the system of Example 8 or 9, wherein the first layer is on the second layer.

[0090] Example 11 includes the system of Example 8, 9, 10, or 11, further comprising a third layer, wherein the third layer includes one or more antennas, and wherein the one or more antennas are communicatively coupled to the amplifier.

[0091] Example 12 includes the system of Example 11, wherein the one or more antennas are directly electrically coupled to the amplifier.

[0092] Example 13 includes the system of Example 8, 9, 10, 11, or 12, further comprising an IQ phase generator in the first layer, wherein the IQ phase generator is electrically coupled to the mixer.

[0093] Example 14 includes the system of Example 13, further comprising a frequency multiplier in the first layer, wherein the multiplier is electrically coupled to the IQ phase generator.

[0094] Example 15 includes the system of Example 13 or 14, further comprising a controller in the second layer, wherein the controller is electrically coupled to the IQ phase generator in the first layer.

[0095] Example 16 includes the system of Examples 8, 9, 10, 11, 12, 13, 14, or 15, further comprising a controller in the second layer, wherein the controller is electrically coupled to the amplifier.

[0096] Example 17 includes the system of Examples 8, 9, 10, 11, 12, 13, 14, 15, or 16, further comprising at least a portion of the processor in the second layer.

[0097] Example 18 is a method comprising: forming a mixer in a layer comprising a III-V material; forming an amplifier in the layer; and electrically coupling the mixer to the amplifier.

[0098] Example 19 includes the method of Example 18, wherein the layer is a first layer; and the method further includes: forming a baseband circuit system in a second layer, wherein the second layer includes silicon; and electrically coupling the baseband circuit system with the mixer.

[0099] Example 20 includes the method of Example 18 or 19, further comprising: forming an IQ phase generator in the layer; and electrically coupling the IQ phase generator to the mixer.

Claims

1. A device comprising: a layer comprising a III-V material; a mixer in said layer; as well as An amplifier in the layer, wherein the mixer and the amplifier are electrically coupled to each other.

2. The device according to claim 1, wherein The amplifier is a selected one of: a low noise amplifier or a power amplifier.

3. The apparatus according to claim 1 or 2, further comprising an IQ phase generator in the layer, wherein: The IQ phase generator and the mixer are electrically coupled to each other.

4. The device of claim 3, further comprising a frequency multiplier in the layer, wherein: The multiplier and the IQ phase generator are electrically coupled to each other.

5. The device according to claim 1 or 2, wherein: The mixer is a first mixer, wherein the amplifier is a first amplifier, and wherein the first amplifier is a power amplifier; and the apparatus further comprises: a second mixer in the layer; and A second amplifier in the layer, wherein the second amplifier is a low noise amplifier, and wherein the second mixer and the second amplifier are electrically coupled to each other.

6. The device according to claim 1 or 2, wherein: The amplifier is electrically coupled to the antenna.

7. The device according to claim 1 or 2, wherein: The layer is located within a selected one of: a chip or a die.

8. A system for broadband communication, the system comprising: A first layer including a III-V material; a mixer in the first layer; an amplifier in the first layer, wherein the amplifier and the mixer are electrically coupled to each other; a second layer comprising silicon; and Baseband circuitry in the second layer, wherein the baseband circuitry is electrically coupled to the mixer.

9. The system according to claim 8, wherein: The amplifier is a selected one of: a power amplifier or a low noise amplifier, and wherein the baseband circuitry is a selected one of: a transmitter baseband circuitry or a receiver baseband circuitry.

10. The system according to claim 8 or 9, wherein: The first layer is on the second layer.

11. The system according to claim 8 or 9, further comprising a third layer, wherein: The third layer includes one or more antennas, and wherein the one or more antennas are communicatively coupled to the amplifier.

12. The system according to claim 11, wherein: The one or more antennas are electrically coupled directly to the amplifier.

13. The system according to claim 8 or 9, further comprising an IQ phase generator in the first layer, wherein: The IQ phase generator is electrically coupled to the mixer.

14. The system of claim 13, further comprising a frequency multiplier in the first layer, wherein: The multiplier is electrically coupled to the IQ phase generator.

15. The system of claim 13, further comprising a controller in the second layer, wherein: The controller is electrically coupled to the IQ phase generators in the first layer.

16. The system according to claim 8 or 9, further comprising a controller in the second layer, wherein: The controller is electrically coupled to the amplifier.

17. The system of claim 8 or 9, further comprising at least a portion of a processor in the second layer.

18. A method comprising: forming a mixer in a layer comprising a III-V material; forming an amplifier in the layer; as well as The mixer is electrically coupled to the amplifier.

19. The method according to claim 18, wherein: The layer is a first layer; and the method further comprises: forming baseband circuitry in a second layer, wherein the second layer comprises silicon; and The baseband circuitry is electrically coupled to the mixer.

20. The method according to claim 18 or 19, further comprising: forming an IQ phase generator in the layer; as well as The IQ phase generator is electrically coupled to the mixer.

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