An on-chip automatic calibration system for local oscillator leakage and I / Q imbalance

Abstract

The present invention discloses an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance, which includes a first part of the circuit used as a mixer, a second part of the circuit used as a local oscillator leakage and image frequency detection circuit, and a third part of the circuit used as a digital control circuit; the present invention detects the local oscillator leakage and image frequency signals at the output port of the transmitter through the method of self-mixing, realizes the detection of local oscillator leakage and I / Q imbalance, and uses an on-chip digital circuit to automatically adjust the output current of the current-mode DAC in the transconductance stage of the mixer according to the detected results, thereby realizing the on-chip integrated automatic calibration of local oscillator leakage and I / Q imbalance.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics design, and particularly to an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance. Background Art

[0002] In a frequency conversion transmitter, local oscillator leakage and I / Q imbalance are two of the most important indicators. Excessive local oscillator leakage and I / Q imbalance will affect the constellation diagram of the transmitted signal, causing the constellation diagram to shift horizontally or vertically. Therefore, when designing a transmitter, it is necessary to focus on reducing local oscillator leakage and I / Q imbalance. The local oscillator leakage and I / Q imbalance can be improved by optimizing the selection of mixer transistor sizes and the symmetry of the layout. The main factor of local oscillator leakage is the inconsistent current between the two differential paths inside the transconductance stage I path or Q path. The main reason for I / Q imbalance is the inconsistent current between the overall I path and Q path of the transconductance stage. By adjusting the bias voltage of the transconductance of each path of the actual chip mixer, the local oscillator leakage and I / Q imbalance can be improved.

[0003] The traditional method for calibrating local oscillator leakage and I / Q imbalance of a transmitter is to read the local oscillator leakage and image frequency signals output by the transmitter through a vector network analyzer and manually adjust the bias voltage of the transconductance stage of the mixer to minimize the output local oscillator leakage and image frequency signals. This method requires expensive instruments, takes a long time for calibration, and the internal environment of the chip may change after the chip has been running for a period of time, and the previously calibrated result is no longer the optimal value. Summary of the Invention

[0004] Technical Objective: Aiming at the three key issues of local oscillator leakage, I / Q imbalance, and inability to accurately perform on-chip automatic calibration in the prior art, the present invention discloses an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance. Based on a traditional frequency converter, a local oscillator leakage and I / Q imbalance calibration circuit is added, and a broadband local oscillator leakage and image frequency signal detection circuit and an on-chip digital control circuit are added to realize signal reading and automatic calibration without external instruments and manual adjustment.

[0005] Technical Solution: To achieve the above technical objective, the present invention adopts the following technical solutions.

[0006] An on-chip automatic calibration system for local oscillator leakage and I / Q imbalance includes a first part of the circuit 1000 serving as a mixer, a second part of the circuit 2000 serving as a local oscillator leakage and image frequency detection circuit, and a third part of the circuit 3000 serving as a digital control circuit;

[0007] The first part of the circuit 1000 includes an I / Q mixer composed of two Gilbert cells. The inputs are externally provided quadrature intermediate frequency signals, including IF_I+, IF_I-, IF_Q+, IF_Q-, and quadrature local oscillator signals, including LO_I+, LO_I-, LO_Q+, LO_Q-. The outputs are RF differential signals, including RF+ and RF-. After being amplified by a power amplifier, the RF differential signals are coupled into a single-ended RF signal RF at the RF output of the transmitter. The positive and negative four transconductance stages of the I / Q mixer are respectively controlled by a current-mode DAC, so as to achieve calibration of local oscillator leakage and I / Q imbalance.

[0008] The second part of the circuit 2000 is used to detect local oscillator leakage and image frequency of the single-ended RF signal RF, and finally convert the local oscillator leakage and image frequency signals into digital signals proportional to their powers. The digital signals are input to the third part of the circuit 3000.

[0009] The output end of the third part of the circuit 3000 is connected to the current-mode DAC in the first part of the circuit 1000, and is used to obtain the current magnitudes of local oscillator leakage and image frequency by reading the digital signals generated by the second part of the circuit 2000, so as to find the IDAC output that minimizes local oscillator leakage and image frequency by using a traversal method.

[0010] Beneficial effects: The present invention detects local oscillator leakage and image frequency signals at the output port of the transmitter by means of self-mixing, realizes detection of local oscillator leakage and I / Q imbalance, and uses an on-chip digital circuit to automatically adjust the output current of the current-mode DAC in the transconductance stage of the mixer according to the detection results, realizing on-chip integrated automatic calibration of local oscillator leakage and I / Q imbalance. Description of the Drawings

[0011] Figure 1 It is a schematic diagram of the framework of an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance provided by an embodiment of the present application;

[0012] Figure 2 It is a schematic diagram of the structure of the first part of the circuit of an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance provided by an embodiment of the present application;

[0013] Figure 3 It is a schematic diagram of the structure of the second part of an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance provided by an embodiment of the present application;

[0014] Figure 4 It is a schematic diagram of the control logic of the third part of an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance provided by an embodiment of the present application;

[0015] Figure 5It is a diagram showing the test results of local oscillator leakage suppression of a transmitter with an on-chip automatic calibration system having local oscillator leakage and I / Q imbalance;

[0016] Figure 6 It is a diagram showing the test results of image frequency suppression of a transmitter with an on-chip automatic calibration system having local oscillator leakage and I / Q imbalance. Detailed implementation manners

[0017] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Generally, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without making creative efforts fall within the scope of protection of the present application.

[0019] It should be noted that: like reference numerals and letters denote like items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0020] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or sequence between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the presence of additional identical elements in the process, method, article or device including the said element.

[0021] In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "arrangement" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0022] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings.

[0023] Embodiment

[0024] As shown in the Figure 1 accompanying drawings, an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance in this embodiment is applicable to a transmitter, and includes a first part of the circuit 1000 serving as a mixer, a second part of the circuit 2000 serving as a local oscillator leakage and image frequency detection circuit, and a third part of the circuit 3000 serving as a digital control circuit;

[0025] The first part of the circuit 1000 includes an I / Q mixer composed of two Gilbert cells, with the inputs being the quadrature intermediate frequency signals provided externally, including IF_I+, IF_I-, IF_Q+, IF_Q-, and the quadrature local oscillator signals, including LO_I+, LO_I-, LO_Q+, LO_Q-; the output is a radio frequency differential signal, including RF+ and RF-; after the radio frequency differential signal is amplified by a power amplifier, it is coupled to a single-ended radio frequency signal RF at the radio frequency output end of the transmitter; the positive and negative total four transconductance stages of the I / Q mixer are respectively controlled by a current-type DAC, so as to realize the calibration of local oscillator leakage and I / Q imbalance;

[0026] The second part of the circuit 2000 is used to detect local oscillator leakage and image frequency for the single-ended radio frequency signal RF, and finally convert the local oscillator leakage and image frequency signals into digital signals proportional to their powers; the digital signals are input to the third part of the circuit 3000;

[0027] The output end of the third part of the circuit 3000 is connected to the current-type DAC in the first part of the circuit 1000, and is used to obtain the current magnitudes of local oscillator leakage and image frequency by reading the digital signals generated by the second part of the circuit 2000, so as to find the IDAC output that minimizes local oscillator leakage and image frequency by using the traversal method.

[0028] As shown in Figure 2As shown, the first part of the circuit 1000 includes the I-channel mixer switch stage, the I-channel mixer transconductance stage, and the series inductor between the two stages that form the I mixer, the Q-channel mixer switch stage, the Q-channel mixer transconductance stage, and the series inductor between the two stages that form the Q mixer, the current-mode DAC that controls the four-channel mixer and is connected to the I-channel mixer transconductance stage and the Q-channel mixer transconductance stage, and the transconductance stage bias resistors that are connected to the I-channel mixer transconductance stage and the Q-channel mixer transconductance stage; the I mixer and the Q mixer have the same structure;

[0029] The I-channel mixer switch stage is connected to the I-channel mixer transconductance stage through a series inductor, and the Q-channel mixer switch stage is connected to the Q-channel mixer transconductance stage through a series inductor. The input signals of the I-channel mixer switch stage are LOI+ and LOI-; the input signals of the Q-channel mixer switch stage are LOQ+ and LOQ-; LOI+, LOI-, LOQ+ and LOQ- are quadrature local oscillator signals; the output signals of the mixer, that is, the output signals of the first part of the circuit 1000 are RF+ and RF-, that is, the radio frequency differential output signals; the input signals connected to the I-channel mixer transconductance stage are IF I+ and IF_I-, and the input signals connected to the Q-channel mixer transconductance stage are IF_Q+ and IF_Q-; IF_I+, IF_I-, IF_Q+ and IF_Q- are quadrature local oscillator signals after buffer amplification;

[0030] Among them, the I-channel mixer switch stage, as the switch stage of a Gilbert cell, includes the first transistor 1021, the second transistor 1022, the third transistor 1023, and the fourth transistor 1024; the sources of the first transistor 1021 and the second transistor 1022 are connected, and the sources of the third transistor 1023 and the fourth transistor 1024 are connected; the drains of the first transistor 1021 and the third transistor 1023 are connected, and the drains of the second transistor 1022 and the fourth transistor 1024 are connected as the output end of the I-channel mixer. The gates of the first transistor 1021 and the fourth transistor 1024 are connected as the positive input end of the I-channel local oscillator signal, and the input signal is LO I+. The gates of the second transistor 1022 and the third transistor 1023 are connected as the negative input end of the I-channel local oscillator signal, and the input signal is LO I-;

[0031] Similarly, the switching stage of the Q-channel mixer, as the switching stage of a Gilbert cell, includes a fifth transistor 1025, a sixth transistor 1026, a seventh transistor 1027, and an eighth transistor 1028; the sources of the fifth transistor 1025 and the sixth transistor 1026 are connected, and the sources of the seventh transistor 1027 and the eighth transistor 1028 are connected; the drains of the fifth transistor 1025 and the seventh transistor 1027 are connected, and the drains of the sixth transistor 1026 and the eighth transistor 1028 are connected, serving as the output terminals of the Q-channel mixer; the gates of the fifth transistor 1025 and the eighth transistor 1028 are connected, serving as the positive input terminal of the local oscillator signal Q-channel, inputting the signal LO_Q+, and the gates of the sixth transistor 1026 and the seventh transistor 1027 are connected, serving as the negative input terminal of the local oscillator signal Q-channel, inputting the signal LO_Q-.

[0032] After the output terminals of the two mixers, namely the I-channel mixer and the Q-channel mixer, are connected, the residual sidebands are canceled, and the sidebands are added to obtain a single-sideband output, the output signals RF+ and RF-, that is, the radio frequency differential output signal.

[0033] The transconductance stage of the I-channel mixer includes a ninth transistor 1002, a tenth transistor 1004, an eleventh transistor 1005, and a twelfth transistor 1007. The transconductance stage of the Q-channel mixer includes a thirteenth transistor 1010, a fourteenth transistor 1012, a fifteenth transistor 1013, and a sixteenth transistor 1015. The current-mode DACs that control the four mixers include a first IDAC 1001, a second IDAC 1008, a third IDAC 1009, and a fourth IDAC 1016. The transconductance stage bias resistors include a first resistor 1003, a second resistor 1006, a third resistor 1011, and a fourth resistor 1014;

[0034] The positive and negative transconductance stages of the I and Q mixers, a total of four paths, are respectively controlled by current-mode DACs, so as to achieve the calibration of local oscillator leakage and I / Q imbalance. The ninth transistor 1002, the twelfth transistor 1007, the thirteenth transistor 1010, and the sixteenth transistor 1015 form a current mirror of the transconductance stage. The gates and drains of all the transistors in the current mirror are connected, and the sources are grounded. The drain of the ninth transistor 1002 is connected to the first IDAC 1001, the drain of the twelfth transistor 1007 is connected to the second IDAC 1008, the drain of the thirteenth transistor 1010 is connected to the third IDAC 1009, and the drain of the sixteenth transistor 1015 is connected to the fourth IDAC 1016. Each IDAC can be controlled by a digital circuit, that is, the third part of the circuit 3000, to control the output current magnitude, and the control amplitude is 60 μA. In the present invention, current-mode DACs are used to control the current magnitudes of the four paths at the bias of the four transconductances of the mixer, so as to achieve the calibration of local oscillator leakage and I / Q imbalance.

[0035] The gates of the ninth transistor 1002 and the tenth transistor 1004 in the transconductance stage of the I-channel mixer are connected through a first resistor 1003. The gates of the eleventh transistor 1005 and the twelfth transistor 1007 are connected through a second resistor 1006. The sources of the tenth transistor 1004 and the eleventh transistor 1005 are grounded. The gates of the thirteenth transistor 1010 and the fourteenth transistor 1012 in the transconductance stage of the Q-channel mixer are connected through a third resistor 1011. The gates of the fifteenth transistor 1013 and the sixteenth transistor 1015 are connected through a fourth resistor 1014. The sources of the fourteenth transistor 1012 and the fifteenth transistor 1013 are grounded.

[0036] The series inductors between the mixer switching stage and the transconductance stage include a first inductor 1017, a second inductor 1018, a third inductor 1019, and a fourth inductor 1020. The drain of the tenth transistor 1004 in the transconductance stage of the I-channel mixer is connected to the sources of the first transistor 1021 and the second transistor 1022 in the I-channel mixer switching stage through the first inductor 1017. The drain of the eleventh transistor 1005 in the transconductance stage of the I-channel mixer is connected to the sources of the third transistor 1023 and the fourth transistor 1024 in the I-channel mixer switching stage through the second inductor 1018. The drain of the fourteenth transistor 1012 in the transconductance stage of the Q-channel mixer is connected to the sources of the fifth transistor 1025 and the sixth transistor 1026 in the Q-channel mixer switching stage through the third inductor 1019. The drain of the fifteenth transistor 1013 in the transconductance stage of the Q-channel mixer is connected to the sources of the seventh transistor 1027 and the eighth transistor 1028 in the Q-channel mixer switching stage through the fourth inductor 1020.

[0037] Among them, the first transistor 1021, the second transistor 1022, the third transistor 1023, the fourth transistor 1024, the fifth transistor 1025, the sixth transistor 1026, the seventh transistor 1027, and the eighth transistor 1028 have the same size. The ninth transistor 1002, the twelfth transistor 1007, the thirteenth transistor 1010, and the sixteenth transistor 1015 have the same size. The tenth transistor 1004, the eleventh transistor 1005, the fourteenth transistor 1012, and the fifteenth transistor 1013 have the same size. The first IDAC 1001, the second IDAC 1008, the third IDAC 1009, and the fourth IDAC 1016 have the same current output range. The first resistor 1003, the second resistor 1006, the third resistor 1011, and the fourth resistor 1014 have the same resistance value. The first inductor 1017, the second inductor 1018, the third inductor 1019, and the fourth inductor 1020 have the same inductance value.

[0038] As Figure 3As shown in the figure, the second part of the circuit 2000 includes an input coupling transformer 2100, a self-mixer 2200, a low-pass filter 2300, a voltage amplifier 2400, an envelope detector 2500, and an ADC 2600; the input coupling transformer 2100 is the first-stage input, and the self-mixer 2200, the low-pass filter 2300, the voltage amplifier 2400, and the envelope detector 2500 are cascaded in sequence. The two outputs of the envelope detector 2500 are respectively connected to the two inputs of the ADC 2600, and finally the local oscillator leakage and the image frequency signal are converted into digital signals proportional to their power; the digital signals are input to the third part of the circuit 3000;

[0039] Among them, the input coupling transformer 2100 is composed of a primary coil and a secondary coil coupled together, realizing the function of a T model composed of inductors in series and parallel, reducing the chip area, and realizing the function of coupling the transmitter output signal RF to the second part of the circuit 2000 with almost no impact on the transmission power;

[0040] The self-mixer 2200 is a first-stage self-mixer, including the seventeenth transistor 2203, the eighteenth transistor 2204, the nineteenth transistor 2207, the twentieth transistor 2208, the fifth resistor 2201, the sixth resistor 2202, the seventh resistor 2209, the eighth resistor 2210, the ninth resistor 2211, the first capacitor 2205, and the second capacitor 2206. The input terminals of the self-mixer 2200 are IN+ and IN-, and the output terminal is OUT;

[0041] The drain of the seventeenth transistor 2203 is connected to the source of the nineteenth transistor 2207, the drain of the eighteenth transistor 2204 is connected to the source of the twentieth transistor 2208, the gate of the seventeenth transistor 2203 is connected to the positive input terminal IN+, the gate of the eighteenth transistor 2204 is connected to the negative input terminal IN-, the sources of the seventeenth transistor 2203 and the eighteenth transistor 2204 are grounded, the gates of the nineteenth transistor 2207 and the twentieth transistor 2208 are connected to the bias voltage Vb2, the drains of the nineteenth transistor 2207 and the twentieth transistor 2208 are connected to the output terminal OUT, the output terminal OUT is connected to the power supply through the fifth resistor 2201, the output terminal OUT is connected to the gate of the seventeenth transistor 2203 through the seventh resistor 2209 and the first capacitor 2205 in series to form negative feedback, the output terminal OUT is connected to the gate of the eighteenth transistor 2204 through the eighth resistor 2210 and the second capacitor 2206 in series to form negative feedback, the gate of the seventeenth transistor 2203 is connected to the bias voltage Vb1 through the fifth resistor 2201, the gate of the eighteenth transistor 2204 is connected to the bias voltage Vb1 through the sixth resistor 2202, and the output terminal OUT is connected to the input terminal of the low-pass filter 2300;

[0042] The seventeenth transistor 2203 has the same size as the eighteenth transistor 2204, the nineteenth transistor 2207 has the same size as the twentieth transistor 2208, the fifth resistor 2201 has the same resistance value as the sixth resistor 2202, the seventh resistor 2209 has the same resistance value as the eighth resistor 2210, and the first capacitor 2205 has the same capacitance value as the second capacitor 2206;

[0043] The self - mixer 2200 mixes the radio frequency, local oscillator leakage, and image frequency signals coupled by the input coupling transformer 2100 with each other, and outputs components such as the first - order intermediate frequency, second - order intermediate frequency, radio frequency, and third - order radio - frequency harmonic. Among them, the first - order intermediate frequency is the product of the mixing of the radio frequency and the local oscillator leakage, and the second - order intermediate frequency is the product of the mixing of the radio frequency and the image frequency, which respectively represent the magnitudes of the local oscillator leakage and the image frequency in the original signal;

[0044] The low - pass filter 2300 is a first - order low - pass filter, including a fifth inductor 2301, a third capacitor 2302, and a fourth capacitor 2303. The input end of the low - pass filter is IN, and the output end is OUT. Among them, the fifth inductor 2301 is in parallel with the third capacitor 2302, one end is connected to IN, and the other end is connected to OUT. One end of the fourth capacitor 2303 is connected to OUT, and the other end is connected to the ground. The output end OUT is connected to the input end of the voltage amplifier 2400. The low - pass filter 2300 is used to filter the signals with frequencies above the second - order intermediate frequency output by the self - mixer 2200;

[0045] The voltage amplifier 2400 is a two - stage voltage amplifier, including a twenty - first transistor 2402, a twenty - second transistor 2403, a twenty - third transistor 2412, a twenty - fourth transistor 2411, a fifth capacitor 2401, a sixth capacitor 2407, a seventh capacitor 2408, an eighth capacitor 2410, a ninth capacitor 2414, a sixth inductor 2404, a seventh inductor 2406, a tenth resistor 2405, an eleventh resistor 2409, a twelfth resistor 2413, and a thirteenth resistor 2415. The input end of the voltage amplifier 2400 is IN, and the output end is OUT;

[0046] The gate of the twenty-first transistor 2402 is connected to the input terminal IN through the fifth capacitor 2401. The source of the twenty-first transistor 2402 is grounded. The gate of the twenty-first transistor 2402 is connected to the voltage bias Vb1. The drain of the twenty-first transistor 2402 is connected to the source of the twenty-second transistor 2403. The gate of the twenty-second transistor 2403 is connected to the bias voltage Vb2. The drain of the twenty-second transistor 2403 is connected to the power supply through the sixth inductor 2404 and the tenth resistor 2405 connected in series in sequence. The seventh inductor 2406 is connected in parallel with the sixth capacitor 2407, one end is connected to the drain of the twenty-second transistor 2403, and the other end is connected to the gate of the twenty-third transistor 2412 through the eighth capacitor 2410. The drain of the twenty-second transistor 2403 is connected to the gate of the twenty-first transistor 2402 through the seventh capacitor 2408 and the eleventh resistor 2409 connected in series in sequence. The sixth inductor 2404 and the seventh inductor 2406 are mutually coupled; the end of the sixth inductor 2404 far from the power supply and the end of the seventh inductor 2406 connected to the drain of the twenty-second transistor 2403 are the same-name terminals; the drain of the twenty-third transistor 2412 is connected to the source of the twenty-fourth transistor 2411. The gate of the twenty-third transistor 2412 is connected to the bias voltage Vb3. The source of the twenty-third transistor 2412 is grounded. The gate of the twenty-fourth transistor 2411 is connected to the bias voltage Vb4. The drain of the twenty-fourth transistor 2411 is connected to the power supply through the twelfth resistor 2413. The drain of the twenty-fourth transistor 2411 is connected to the output terminal OUT. The output terminal OUT is connected to the gate of the twenty-third transistor 2412 through the ninth capacitor 2414 and the thirteenth resistor 2415 connected in series in sequence. The output terminal OUT is connected to the input terminal of the envelope detector 2500;

[0047] The voltage amplifier 2400 is used to amplify the voltage of the first intermediate frequency and the second intermediate frequency signals output by the self-mixer 2200, and filter out the interference components above the second intermediate frequency; the low-pass filter 2300 and the voltage amplifier 2400 work together to filter out the interference components above the second intermediate frequency more thoroughly.

[0048] The envelope detector 2500 is a first-stage envelope detector, including the twenty-fifth transistor 2503, the twenty-sixth transistor 2504, the twenty-seventh transistor 2508, the twenty-eighth transistor 2509, the twenty-ninth transistor 2510, the thirtieth transistor 2513, the thirty-first transistor 2514, the tenth capacitor 2501, the eleventh capacitor 2506, the twelfth capacitor 2512, the thirteenth capacitor 2515, the fourteenth capacitor 2507, the fourteenth resistor 2502, the fifteenth resistor 2505, and the sixteenth resistor 2511. The input terminal of the envelope detector is IN, and the output terminals are OUT1 and OUT2;

[0049] The gate of the twenty-fifth transistor 2503 is connected to the input terminal IN through the tenth capacitor 2501. The gate of the twenty-fifth transistor 2503 is connected to the bias voltage Vb1 through the fourteenth resistor 2502. The source of the twenty-fifth transistor 2503 is grounded. The gate of the twenty-sixth transistor 2504 is connected to the ground through the eleventh capacitor 2506. The gate of the twenty-sixth transistor 2504 is connected to the bias voltage Vb1 through the fifteenth resistor 2505. The drain of the twenty-fifth transistor 2503 is connected to the drain of the twenty-sixth transistor 2504, the drain of the twenty-ninth transistor 2510, and the output terminal OUT2. The output terminal OUT2 is grounded through the fourteenth capacitor 2507. The drain of the twenty-ninth transistor 2510 is grounded through the twelfth capacitor 2512. The source of the twenty-ninth transistor 2510 is connected to the power supply. The gate of the twenty-ninth transistor 2510 is connected to the gate of the twenty-eighth transistor 2509. The gate of the twenty-eighth transistor 2509 is connected to its own drain. The source of the twenty-eighth transistor 2509 is connected to the power supply. The drain of the twenty-eighth transistor 2509 is connected to the drain of the twenty-seventh transistor 2508. The gate of the twenty-seventh transistor 2508 is connected to the bias voltage Vb2. The source of the twenty-seventh transistor 2508 is grounded. The drain of the twenty-ninth transistor 2510 is connected to the gate of the thirtieth transistor 2513 through the sixteenth resistor 2511. The source of the thirtieth transistor 2513 is connected to the power supply. The drain of the thirtieth transistor 2513 is connected to the drain of the thirty-first transistor 2514 and the output terminal OUT1. The gate of the thirty-first transistor 2514 is connected to the bias voltage Vb3. The source of the thirty-first transistor 2514 is grounded. The output terminal OUT1 is grounded through the thirteenth capacitor 2515. The output terminal OUT1 and the output terminal OUT2 are connected to the first-stage ADC 2600;

[0050] The twenty-fifth transistor 2503 and the twenty-sixth transistor 2504 have the same size. The fourteenth resistor 2502 and the fifteenth resistor 2505 have the same resistance value. The tenth capacitor 2501 and the eleventh capacitor 2506 have the same capacitance value.

[0051] The envelope detector 2500 is used to convert the first intermediate frequency and the second intermediate frequency signals into DC components. The level output from the output terminal OUT1 is positively correlated with the voltage of the input signal, and it changes more sensitively when the voltage of the input signal is small; the level output from the output terminal OUT2 is negatively correlated with the voltage of the input signal, and it changes more sensitively when the voltage of the input signal is large; the difference between the results of the output terminal OUT1 and the output terminal OUT2 is positively correlated with the voltage of the input signal, and it changes more sensitively at each voltage than the individual output terminal OUT1 or output terminal OUT2, and can represent the power levels of the transmitter local oscillator leakage and the image frequency components;

[0052] The ADC2600 includes two DC level input ports, a digital control port for switching the read port, and a digital bus output port. The two DC level input ports are respectively connected to the output terminals OUT1 and OUT2 of the envelope detector 2500, and the digital bus output port is connected to the third part of the circuit 3000. The level range sampled by the ADC is 0 - 1V, and the sampling accuracy is 10 bits.

[0053] The ADC2600 converts the input DC level into a digital signal and outputs it to the third part of the circuit 3000 through the bus, enabling the digital control circuit to obtain the power levels of the transmitter local oscillator leakage and the image frequency component and perform automatic calibration accordingly.

[0054] The local oscillator leakage and the image frequency generated by the I / Q mixer are coupled as RF signals at the transmitter output and input to the detection circuit. The local oscillator and the image frequency are respectively converted into the first intermediate frequency and the second intermediate frequency through the self - mixer, and then converted into DC levels after filtering and amplification, and transmitted to the third part of the circuit after ADC sampling.

[0055] The third part of the circuit 3000 is a digital control circuit automatically generated by Verilog code, including a digital bus input port, a calibration signal input port, a calibration end signal output port, and four digital bus output ports. The digital bus output ports are respectively connected to the first IDAC1001, the second IDAC1008, the third IDAC1009, and the fourth IDAC1016 to control the current magnitude output by the DAC.

[0056] The signal flow process of this embodiment is as follows:

[0057] The input of the first part of the circuit 1000 is the quadrature intermediate frequency signals provided externally, including IF I+, IF I -, IF_Q+, IF_Q -, and the quadrature local oscillator signals, including LO_I+, LO_I -, LO_Q+, LO_Q -. The output is the RF differential signals, including RF+ and RF -. After being amplified by the power amplifier, the RF differential signals become the single - ended RF signal RF at the RF output port. The input of the second part of the circuit 2000 is the RF signal RF, and the output is the digital bus signal. The input of the third part of the circuit 3000 includes the digital bus signal from the second part of the circuit 2000 and a calibration start signal, and the output is a calibration end signal and four digital bus outputs. The digital bus outputs are respectively connected to the first IDAC1001, the second IDAC1008, the third IDAC1009, and the fourth IDAC1016 in the first part of the circuit 1000, thus forming a closed - loop control loop.

[0058] The local oscillator leakage and I / Q imbalance calibration process of this embodiment is as follows: Due to the differences in chip process manufacturing, the sizes of the transconductance-stage transistors, namely the tenth transistor 1004, the eleventh transistor 1005, the fourteenth transistor 1012, and the fifteenth transistor 1013, may vary, which leads to the imbalance of the DC currents of the transconductance-stage transistors. The imbalance of the currents of the transconductance-stage transistors will cause the local oscillator signal or the image frequency at the output port to not be completely cancelled out. The local oscillator signal or the image frequency with a larger current has a larger output amplitude, thus generating a larger local oscillator leakage or image frequency. In the present invention, by controlling the output current of the current-mode DAC, the magnitudes of the four currents are further changed, so that the DC currents of the transconductance-stage transistors are restored to balance, thereby realizing the calibration of the local oscillator leakage and I / Q imbalance. To achieve the on-chip automation of this calibration process, the present invention adds a local oscillator leakage and image frequency detection circuit at the output port of the transmitter, converts the component to be detected into a digital signal and then outputs it to the on-chip digital control circuit. After receiving the calibration start signal, the digital control circuit obtains the IDAC control code when the local oscillator leakage and image frequency are minimized in a traversal manner, thereby realizing the calibration of the local oscillator leakage and I / Q imbalance.

[0059] As Figure 4 shown, the control logic of the third part of the circuit 3000 of the system according to the present invention includes a main process and three sub-processes, namely sub-process 3100a, sub-process 3100b, and sub-process 3100c; the main process is: when starting automatic calibration, the system first executes step 3001, and the third part of the circuit 3000 receives the calibration signal from the calibration signal input port and enters sub-process 3100a; in sub-process 3100a, the system calibrates the local oscillator leakage of the I channel, that is, calibrates the first IDAC 1001. The steps of 3100a are the same as those of 3100, and the IDAC register to be modified is the control register corresponding to the first IDAC 1001. After completion, it enters sub-process 3100b;

[0060] Sub-process 3100a, sub-process 3100b, and sub-process 3100c all execute the same process, namely, sub-process 3100; in sub-process 3100, the circuit first enters step 3101, sets the control register value of the corresponding IDAC to 0, then enters step 3102, adds 1 to the value of the register, and then enters step 3103, the third part of the circuit reads the values ​​of the output terminal OUT1 and the output terminal OUT2 read by ADC2600 through the digital bus input port, and calculates the value of OUT1-OUT2, and then enters step 3104, if the value of OUT1-OUT2 is less than the previous reading at this time, the value of OUT1-OUT2 is stored, and step 3105 is triggered to store the current register value. After step 3104 ends, step 3106 is entered to determine whether the register value reaches the upper limit. If it does not reach the upper limit, it returns to step 3102. If it has reached the upper limit, it enters step 3107, sets the register to the optimal bias value obtained in the loop, and ends sub-process 3100;

[0061] In sub-process 3100b, the system calibrates the local oscillator leakage of the Q path, that is, calibrates the fourth IDAC1016, wherein the steps of 3100b are consistent with 3100, and the modified IDAC register is the control register corresponding to the fourth IDAC1016, and after completion, it enters sub-process 310c;

[0062] In sub-process 3100c, the circuit calibrates the imbalance of the I and Q paths, that is, the first IDAC1001 and the second IDAC1008 are calibrated at the same time. At this time, step 3102 in the sub-process becomes to increase the register values ​​of the first IDAC1001 and the second IDAC1008 by 1 at the same time, that is, to keep the difference between the two registers constant. Step 3106 in the sub-process becomes to determine whether the value of the first IDAC1001 or the second IDAC1008 register reaches the upper limit. If one of them reaches it, step 3107 is entered. The remaining steps are the same, and after completion, step 3002 is entered. In step 3002, since the calibration of local oscillator leakage and the calibration of I / Q imbalance will affect each other, it is necessary to determine whether the value of the current register is the same as the value of the previous register. If they are not the same, it means that the calibration has not converged, and the process goes to step 3003. If they are the same, it means that the calibration has converged, and the process goes to step 3004. In step 3003, it is determined whether the upper limit of the number of iterations is reached. If not, the process returns to subprocess 3100a. If it has been reached, the process goes to step 3004. In step 3004, the circuit sends a calibration end signal through the calibration signal input port to complete the automatic calibration.

[0063] The digital control circuit realizes automatic local oscillator leakage and I / Q imbalance calibration by automatically traversing the register values that control the output current of the IDAC and combining the digital signals input by the detection circuit.

[0064] The present invention adopts an I / Q mixing architecture, which has two mixers, namely an I-channel mixer and a Q-channel mixer. Orthogonal intermediate-frequency signals and orthogonal local oscillator signals are respectively input to the I-channel mixer and the Q-channel mixer. For the two sidebands obtained by the I-channel mixer and the Q-channel mixer, one has the same phase and the other has the opposite phase. Finally, the required sideband is retained and the remaining sidebands are cancelled, realizing single-sideband upconversion. The output matching network of the mixer realizes the selection of sidebands. Specifically, the sidebands can be switched by changing the connection method of the outputs of the I-channel mixer and the Q-channel mixer: connecting the positive end of the I-channel output to the positive end of the Q-channel output and the negative end to the negative end selects the upper sideband; connecting the positive end of the I-channel output to the negative end of the Q-channel output and the negative end to the positive end selects the lower sideband.

[0065] Based on the traditional frequency converter, the present invention adds a local oscillator leakage and I / Q imbalance calibration circuit, that is, the first part of the circuit including a current-mode DAC, and adds a broadband local oscillator leakage and image frequency signal detection circuit and an on-chip digital control circuit. Without the need for external instruments such as an external vector network analyzer and manual adjustment, signal reading and automatic calibration are realized; the on-chip circuit is used to detect the local oscillator leakage and image frequency signals output by the transmitter, and the on-chip digital control circuit automatically adjusts the bias voltage of the mixer transconductance stage to the optimal value, which can save a large amount of costs in large-scale chip production, and can also be calibrated at any time when put into the whole machine for use to maintain the optimal state.

[0066] As Figure 5 shown, this is a schematic diagram of the comparison of the situation before and after local oscillator leakage suppression calibration during the test of this example. The abscissa in the figure is the intermediate-frequency frequency, and the ordinate is the local oscillator leakage suppression ratio. It can be seen from Figure 5 that in the range of 2.4 - 7.5 GHz of the intermediate-frequency signal, the local oscillator leakage suppression of the transmitter has increased by at least 20 dBc after automatic calibration, and in the required radio frequency range, the local oscillator leakage suppression ratio of the transmitter is greater than 40 dBc.

[0067] As Figure 6 shown, this is a schematic diagram of the comparison of the situation before and after image frequency suppression calibration during the test of this example. Figure 6 The abscissa in Figure 6 is the intermediate-frequency frequency, and the ordinate is the image frequency suppression ratio. It can be seen from

[0068] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0069] For those skilled in the art, it is obvious that the present application is not limited to the details of the above-described exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed within the present application. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. An on-chip automatic calibration system for local oscillator leakage and I / Q imbalance, characterized in that: It comprises a first circuit section (1000) used as a mixer, a second circuit section (2000) used as a local oscillator leakage and image frequency detection circuit, and a third circuit section (3000) used as a digital control circuit; The first circuit (1000) comprises an I, Q mixer composed of two Gilbert units, the input of which is an externally provided orthogonal intermediate frequency signal, including IF_I+, IF_I-, IF_Q+, IF_Q-, and an orthogonal local oscillator signal, including LO_I+, LO_I-, LO_Q+, LO_Q-; The output is a radio frequency differential signal, including RF+ and RF-; after being amplified by the power amplifier, the radio frequency differential signal is coupled to a single-ended radio frequency signal RF at the radio frequency output end of the transmitter; The positive and negative transconductance stages of the I and Q mixers are controlled by current-mode DACs, respectively, so that local oscillator leakage and I / Q imbalance can be calibrated. The second circuit (2000) is used to perform local oscillator leakage and image frequency detection on the single-ended radio frequency signal RF, and finally convert the local oscillator leakage and image frequency signals into digital signals proportional to their powers; the digital signals are input into the third circuit (3000); The output end of the third circuit (3000) is connected to the current-mode DAC in the first circuit (1000), and is used to obtain the magnitude of the current local oscillator leakage and the image frequency by reading the digital signal generated by the second circuit (2000), so as to find the IDAC output that minimizes the local oscillator leakage and the image frequency by using the traversal method; the third circuit (3000) is a digital control circuit, comprising a digital bus input port, a calibration signal input port, a calibration end signal output port, and four digital bus output ports, the digital bus output ports being respectively connected to the current-mode DACs in the first circuit (1000), namely the first IDAC (1001), the second IDAC (1008), the third IDAC (1009), and the fourth IDAC (1016), and being used to control the magnitude of the current output by the DAC; The control logic of the third part of the circuit (3000) includes a main process and three sub-processes, namely, sub-process 3100 (a), sub-process 3100 (b), and sub-process 3100 (c); the main process is: when starting automatic calibration, the system first executes step 3001, receives a calibration signal from the calibration signal input port, and enters sub-process 3100 (a); in sub-process 3100 (a), the circuit calibrates the first IDAC (1001), and the modified IDAC register is the control register corresponding to the first IDAC (1001), and after the end, it enters sub-process 3100 (b); in sub-process 3100 (b), the circuit calibrates the fourth IDAC (1016), and the modified IDAC register is the control register corresponding to the fourth IDAC (1016), and after the end, it enters sub-process 3100 (c); in sub-process 3100 (c), the circuit calibrates the first IDAC (1001) and the second IDAC (1008) at the same time , at this time, step 3102 in the sub-process becomes to add 1 to the register values ​​controlling the first IDAC (1001) and the second IDAC (1008), that is, to keep the difference between the two registers constant, and step 3106 in the sub-process becomes to determine whether the value of the first IDAC (1001) or the second IDAC (1008) register has reached the upper limit. If one of them has reached it, it enters step 3107, and the other steps are the same. After the end, it enters step 3002; in step 3002, it is determined whether the value of the current register is the same as the value of the register in the previous round. If not, it enters step 3003. If the same, it enters step 3004; in step 3003, it is determined whether the upper limit of the number of iterations has been reached. If not, it returns to sub-process 3100 (a). If it has reached the upper limit of the number of iterations, it enters step 3004; in step 3004, the circuit sends a calibration end signal through the calibration signal input port to complete the automatic calibration.

2. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 1, characterized in that: The first circuit (1000) comprises an I-channel mixer switch stage, an I-channel mixer transconductance stage and a series inductor between the two stages constituting an I mixer, a Q-channel mixer switch stage, a Q-channel mixer transconductance stage and a series inductor between the two stages constituting a Q mixer, a current-type DAC for controlling four mixers connected to the I-channel mixer transconductance stage and the Q-channel mixer transconductance stage, and a transconductance stage bias resistor connected to the I-channel mixer transconductance stage and the Q-channel mixer transconductance stage; The I-channel mixer switch stage is connected to the I-channel mixer transconductance stage through a series inductor, and the Q-channel mixer switch stage is connected to the Q-channel mixer transconductance stage through a series inductor. The input signal of the I-channel mixer switch stage is LOI+ and LOI-; the input signal of the Q-channel mixer switch stage is LOQ+ and LOQ-; LOI+, LOI-, LOQ+ and LOQ- are orthogonal local oscillator signals; the mixer output signal is RF+ and RF-, that is, the RF differential output signal; the input signal connected to the I-channel mixer transconductance stage is IF_I+ and IF_I-, and the input signal connected to the Q-channel mixer transconductance stage is IF_Q+ and IF_Q-; IF_I+, IF_I-, IF_Q+ and IF_Q- are orthogonal local oscillator signals after buffering and amplification.

3. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 2, characterized in that: The I-channel mixer switch stage, as a switch stage of a Gilbert unit, comprises a first transistor (1021), a second transistor (1022), a third transistor (1023), and a fourth transistor (1024); the source electrodes of the first transistor (1021) and the second transistor (1022) are connected, the source electrodes of the third transistor (1023) and the fourth transistor (1024) are connected, the drain electrodes of the first transistor (1021) and the third transistor (1023) are connected, the drain electrodes of the second transistor (1022) and the fourth transistor (1024) are connected, serving as the output end of the I-channel mixer, the gate electrodes of the first transistor (1021) and the fourth transistor (1024) are connected, serving as the positive input end of the local oscillation signal I-channel, the input signal LO_I+, the gate electrodes of the second transistor (1022) and the third transistor (1023) are connected, serving as the negative input end of the local oscillation signal I-channel, the input signal LO_I-; A Q-channel mixer switch stage, as a switch stage of a Gilbert unit, comprises a fifth transistor (1025), a sixth transistor (1026), a seventh transistor (1027), and an eighth transistor (1028); the source electrodes of the fifth transistor (1025) and the sixth transistor (1026) are connected, the source electrodes of the seventh transistor (1027) and the eighth transistor (1028) are connected, the drain electrodes of the fifth transistor (1025) and the seventh transistor (1027) are connected, the drain electrodes of the sixth transistor (1026) and the eighth transistor (1028) are connected, serving as the output end of the Q-channel mixer, the gate electrodes of the fifth transistor (1025) and the eighth transistor (1028) are connected, serving as the positive input end of the local oscillator signal Q-channel, the input signal LO_Q+, the gate electrodes of the sixth transistor (1026) and the seventh transistor (1027) are connected, serving as the negative input end of the local oscillator signal Q-channel, the input signal LO_Q-; The first transistor (1021), the second transistor (1022), the third transistor (1023), the fourth transistor (1024), the fifth transistor (1025), the sixth transistor (1026), the seventh transistor (1027), and the eighth transistor (1028) have the same size.

4. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 2, characterized in that: The I-channel mixer transconductance stage comprises a ninth transistor (1002), a tenth transistor (1004), an eleventh transistor (1005), and a twelfth transistor (1007); the Q-channel mixer transconductance stage comprises a thirteenth transistor (1010), a fourteenth transistor (1012), a fifteenth transistor (1013), and a sixteenth transistor (1015); the current-mode DAC for controlling the four-channel mixer comprises a first IDAC (1001), a second IDAC (1008), a third IDAC (1009), and a fourth IDAC (1016); and the transconductance stage bias resistor comprises a first resistor (1003), a second resistor (1006), a third resistor (1011), and a fourth resistor (1014); The ninth transistor (1002), the twelfth transistor (1007), the thirteenth transistor (1010), and the sixteenth transistor (1015) have the same size; the tenth transistor (1004), the eleventh transistor (1005), the fourteenth transistor (1012), and the fifteenth transistor (1013) have the same size; the first IDAC (1001), the second IDAC (1008), the third IDAC (1009), and the fourth IDAC (1016) have the same current output range; the first resistor (1003), the second resistor (1006), the third resistor (1011), and the fourth resistor (1014) have the same resistance value; A total of four positive and negative transconductance stages of the I and Q mixers are controlled by current-type DACs, respectively, so that local oscillator leakage and I / Q imbalance can be calibrated. The ninth transistor (1002), the twelfth transistor (1007), the thirteenth transistor (1010), and the sixteenth transistor (1015) form a current mirror of the transconductance stage, and the gate is connected to the drain. The drain of the ninth transistor (1002) is connected to the first IDAC (1001), the drain of the twelfth transistor (1007) is connected to the second IDAC (1008), the drain of the thirteenth transistor (1010) is connected to the third IDAC (1009), and the drain of the sixteenth transistor (1015) is connected to the fourth IDAC (1016). The output size of the current of each IDAC can be controlled by a digital circuit, and the control amplitude is 60μA; The gate of the ninth transistor (1002) in the I-channel mixer transconductance stage is connected to the gate of the tenth transistor (1004) through a first resistor (1003), the gate of the eleventh transistor (1005) is connected to the gate of the twelfth transistor (1007) through a second resistor (1006), the sources of the tenth transistor (1004) and the eleventh transistor (1005) are grounded, the gate of the thirteenth transistor (1010) in the Q-channel mixer transconductance stage is connected to the gate of the fourteenth transistor (1012) through a third resistor (1011), the gate of the fifteenth transistor (1013) is connected to the gate of the sixteenth transistor (1015) through a fourth resistor (1014), and the sources of the fourteenth transistor (1012) and the fifteenth transistor (1013) are grounded.

5. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 4, characterized in that: The series inductance between the mixer switch stage and the transconductance stage comprises a first inductance (1017), a second inductance (1018), a third inductance (1019), and a fourth inductance (1020), and the inductance values ​​of the first inductance (1017), the second inductance (1018), the third inductance (1019), and the fourth inductance (1020) are the same; the drain of the tenth transistor (1004) in the I-channel mixer transconductance stage is connected to the source of the first transistor (1021) and the second transistor (1022) in the switch stage through the first inductance (1017); the eleventh transistor (1004) in the transconductance stage is connected to the source of the first transistor (1021) and the second transistor (1022) in the switch stage through the first inductance (1017); The drain of the transistor (1005) is connected to the source of the third transistor (1023) and the fourth transistor (1024) in the switch stage through a second inductor (1018), the drain of the fourteenth transistor (1012) in the Q-channel mixer transconductance stage is connected to the source of the fifth transistor (1025) and the sixth transistor (1026) in the switch stage through a third inductor (1019), and the drain of the fifteenth transistor (1013) in the transconductance stage is connected to the source of the seventh transistor (1027) and the eighth transistor (1028) in the switch stage through a fourth inductor (1020).

6. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 1, characterized in that: The second circuit (2000) comprises an input coupling transformer (2100), a self-mixer (2200), a low-pass filter (2300), a voltage amplifier (2400), an envelope detector (2500) and an ADC (2600); the input coupling transformer (2100) is the first-stage input, the self-mixer (2200), the low-pass filter (2300), the voltage amplifier (2400) and the envelope detector (2500) are cascaded in sequence, and the two outputs of the envelope detector (2500) are respectively connected to the two inputs of the ADC (2600), and finally the local oscillator leakage and the image frequency signal are converted into a digital signal proportional to the power thereof.

7. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The self-mixer (2200) comprises a seventeenth transistor (2203), an eighteenth transistor (2204), a nineteenth transistor (2207), a twentieth transistor (2208), a fifth resistor (2201), a sixth resistor (2202), a seventh resistor (2209), an eighth resistor (2210), a ninth resistor (2211), a first capacitor (2205), and a second capacitor (2206); the input terminals of the self-mixer are IN+ and IN-, and the output terminal is OUT; The drain of the seventeenth transistor (2203) is connected to the source of the nineteenth transistor (2207), the drain of the eighteenth transistor (2204) is connected to the source of the twentieth transistor (2208), the gate of the seventeenth transistor (2203) is connected to the positive input terminal IN+, the gate of the eighteenth transistor (2204) is connected to the negative input terminal IN-, the sources of the seventeenth transistor (2203) and the eighteenth transistor (2204) are grounded, the gates of the nineteenth transistor (2207) and the twentieth transistor (2208) are connected to the bias voltage Vb2, the drains of the nineteenth transistor (2207) and the twentieth transistor (2208) are connected to the output terminal OUT, the output terminal is connected to the power supply through the fifth resistor (2201), and the output terminal is connected to the gate of the seventeenth transistor (2203) by sequentially connecting the seventh resistor (2209) and the first capacitor (2205) in series to form a negative The output terminal is connected to the gate of the eighteenth transistor (2204) by sequentially connecting an eighth resistor (2210) and a second capacitor (2206) in series to form a negative feedback; the gate of the seventeenth transistor (2203) is connected to the bias voltage Vb1 through a fifth resistor (2201); the gate of the eighteenth transistor (2204) is connected to the bias voltage Vb1 through a sixth resistor (2202); the output terminal OUT is connected to the input terminal of the low-pass filter (2300); the seventeenth transistor (2203) and the eighteenth transistor (2204) have the same size; the nineteenth transistor (2207) and the twentieth transistor (2208) have the same size; the fifth resistor (2201) and the sixth resistor (2202) have the same resistance value; the seventh resistor (2209) and the eighth resistor (2210) have the same resistance value; and the first capacitor (2205) and the second capacitor (2206) have the same capacitance value.

8. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The low-pass filter (2300) comprises a fifth inductor (2301), a third capacitor (2302), and a fourth capacitor (2303); the input end of the low-pass filter is IN, and the output end is OUT; wherein the fifth inductor (2301) is connected in parallel with the third capacitor (2302), one end of which is connected to IN, and the other end of which is connected to OUT; the fourth capacitor (2303) has one end connected to OUT, and the other end connected to ground; and the output end OUT is connected to the input end of the voltage amplifier (2400).

9. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The voltage amplifier (2400) comprises a twenty-first transistor (2402), a twenty-second transistor (2403), a twenty-third transistor (2412), a twenty-fourth transistor (2411), a fifth capacitor (2401), a sixth capacitor (2407), a seventh capacitor (2408), an eighth capacitor (2410), a ninth capacitor (2414), a sixth inductor (2404), a seventh inductor (2406), a tenth resistor (2405), an eleventh resistor (2409), a twelfth resistor (2413), and a thirteenth resistor (2415), wherein the input terminal of the voltage amplifier is IN, and the output terminal is OUT; The gate of the twenty-first transistor (2402) is connected to the input terminal IN through the fifth capacitor (2401), the source of the twenty-first transistor (2402) is grounded, the gate of the twenty-first transistor (2402) is connected to the voltage bias Vb1, the drain of the twenty-first transistor (2402) is connected to the source of the twenty-second transistor (2403), the gate of the twenty-second transistor (2403) is connected to the bias voltage Vb2, the drain of the twenty-second transistor (2403) is connected to the power supply through the sixth inductor (2404) and the tenth resistor (2405) connected in series, the seventh inductor (2406) is connected in parallel with the sixth capacitor (2407), one end of the seventh inductor (2406) is connected to the drain of the twenty-second transistor (2403), and the other end is connected to the gate of the twenty-third transistor (2412) through the eighth capacitor (2410), the drain of the twenty-second transistor (2403) is connected to the seventh capacitor (2404) and the tenth resistor (2405) connected in series, 8), an eleventh resistor (2409) is connected to the gate of the twenty-first transistor (2402), the sixth inductor (2404) and the seventh inductor (2406) are coupled to each other, the drain of the twenty-third transistor (2412) is connected to the source of the twenty-fourth transistor (2411), the gate of the twenty-third transistor (2412) is connected to the bias voltage Vb3, the source of the twenty-third transistor (2412) is grounded, the gate of the twenty-fourth transistor (2411) is connected to the bias voltage Vb4, the drain of the twenty-fourth transistor (2411) is connected to the power supply through the twelfth resistor (2413), the drain of the twenty-fourth transistor (2411) is connected to the output terminal OUT, the output terminal OUT is connected to the gate of the twenty-third transistor (2412) through the ninth capacitor (2414) and the thirteenth resistor (2415) connected in series in sequence, and the output terminal OUT is connected to the input terminal of the envelope detector (2500).

10. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The envelope detector (2500) comprises a twenty-fifth transistor (2503), a twenty-sixth transistor (2504), a twenty-seventh transistor (2508), a twenty-eighth transistor (2509), a twenty-ninth transistor (2510), a thirtieth transistor (2513), a thirty-first transistor (2514), a tenth capacitor (2501), an eleventh capacitor (2506), a twelfth capacitor (2512), a thirteenth capacitor (2515), a fourteenth capacitor (2507), a fourteenth resistor (2502), a fifteenth resistor (2505), and a sixteenth resistor (2511), wherein the input terminal of the envelope detector is IN, and the output terminals are OUT1 and OUT2; The gate of the twenty-fifth transistor (2503) is connected to the input terminal IN through the tenth capacitor (2501), the gate of the twenty-fifth transistor (2503) is connected to the bias voltage Vb1 through the fourteenth resistor (2502), the source of the twenty-fifth transistor (2503) is grounded, the gate of the twenty-sixth transistor (2504) is connected to the ground through the eleventh capacitor (2506), the gate of the twenty-sixth transistor (2504) is connected to the bias voltage Vb1 through the fifteenth resistor (2505), the drain of the twenty-fifth transistor (2503) is connected to the twenty-sixth transistor (2504). The drain of the transistor (2504), the drain of the twenty-ninth transistor (2510) and the output terminal OUT2 are connected, the output terminal OUT2 is connected to the ground via the fourteenth capacitor (2507), the drain of the twenty-ninth transistor (2510) is connected to the ground via the twelfth capacitor (2512), the source of the twenty-ninth transistor (2510) is connected to the power supply, the gate of the twenty-ninth transistor (2510) is connected to the gate of the twenty-eighth transistor (2509), the gate of the twenty-eighth transistor (2509) is connected to its own drain, and the gate of the twenty-eighth transistor (2509) is connected to the power supply. The source of the 28th transistor (2509) is connected to the drain of the 27th transistor (2508), the gate of the 27th transistor (2508) is connected to the bias voltage Vb2, the source of the 27th transistor (2508) is grounded, the drain of the 29th transistor (2510) is connected to the gate of the 30th transistor (2513) through the 16th resistor (2511), the source of the 30th transistor (2513) is connected to the power supply, the drain of the 30th transistor (2513) is connected to the drain of the 31st transistor (2514) and the output terminal The output terminal OUT1 is connected, the gate of the thirty-first transistor (2514) is connected to the bias voltage Vb3, the source of the thirty-first transistor (2514) is grounded, the output terminal OUT1 is connected to the ground through the thirteenth capacitor (2515), and the output terminals OUT1 and OUT2 are connected to the ADC (2600); the size of the twenty-fifth transistor (2503) and the twenty-sixth transistor (2504) are the same, the resistance value of the fourteenth resistor (2502) and the fifteenth resistor (2505) are the same, and the capacitance value of the tenth capacitor (2501) and the eleventh capacitor (2506) are the same.

11. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The ADC (2600) comprises two DC level input ports, a digital control port for switching a reading port, and a digital bus output port. The two DC level input ports are respectively connected to an output terminal OUT1 and an output terminal OUT2 of an envelope detector (2500), and the digital bus output port is connected to a third circuit (3000).

12. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 11, characterized in that: Sub-process 3100(a), sub-process 3100(b), and sub-process 3100(c) all execute the same process, namely, sub-process (3100); in sub-process (3100), the circuit first enters step 3101, sets the control register value of the corresponding IDAC to 0, then enters step 3102, adds 1 to the register value, and then enters step 3103, reads the values ​​of OUT1 and OUT2 read by the ADC through the digital bus input port, and calculates the value of OUT1-OUT2, and then enters step 3104. If the value of OUT1-OUT2 is less than the previous reading at this time, the value of OUT1-OUT2 is stored, and step 3105 is triggered to store the current register value. After step 3104 ends, step 3106 is entered to determine whether the register value has reached the upper limit. If it has not reached the upper limit, return to step 3102. If it has reached the upper limit, step 3107 is entered to set the register to the optimal bias value obtained in the loop, and end sub-process (3100).

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