Delay measurement system and method

Abstract

A delay measurement system includes a controller having a first input port and a second input port. The controller is programmed to receive a start trigger signal using the first input port. The controller is further programmed to perform a first action in response to receiving the start trigger signal. The controller is further programmed to receive a stop trigger signal using the second input port. The controller is further programmed to perform a second action in response to receiving the stop trigger signal. The controller is further programmed to determine a delay measurement based at least in part on the first action and the second action.

Description

Technical Field

[0001] The present disclosure relates to systems and methods for communication delay measurement between electrical devices, and more particularly, to systems and methods for communication delay measurement between electrical devices in a vehicle electrical system. Background Art

[0002] Vehicles can be equipped with various electrical devices, such as controllers (e.g., powertrain control module, brake control module, body control module, etc.), sensors, and actuators. Sensors and actuators can communicate with controllers so that the sensors can collect information and / or detect stimulus factors, and the controllers can analyze the sensor data and provide signals to the actuators. Vehicles can be equipped with multiple controllers that are configured to handle specific aspects of vehicle operation. In some cases, the controllers can be placed near the corresponding sensors and / or actuators. In other cases, the controllers can be placed in a central location in the vehicle. In both cases, it may be necessary to accurately measure the communication delays between the vehicle's electrical devices for development, troubleshooting, and testing purposes.

[0003] Therefore, while current delay measurement systems and methods achieve their intended purposes, a new and improved system and method for communication delay measurement between electrical devices in a vehicle is needed. Summary of the invention

[0004] According to several aspects, a delay measurement system is provided. The delay measurement system includes a controller having a first input port and a second input port. The controller is programmed to receive a start trigger signal using the first input port. The controller is also programmed to perform a first action in response to receiving the start trigger signal. The controller is also programmed to receive a stop trigger signal using the second input port. The controller is also programmed to perform a second action in response to receiving the stop trigger signal. The controller is also programmed to determine a delay measurement result based at least in part on the first action and the second action.

[0005] In another aspect of the present disclosure, the first input port is in electrical communication with a first device under test (DUT).The start trigger signal is at least one of a rising edge and a falling edge of a digital logic signal.

[0006] In another aspect of the present disclosure, the second input port is in electrical communication with a second device under test (DUT).The stop trigger signal is at least one of a rising edge and a falling edge of a digital logic signal.

[0007] In another aspect of the disclosure, to perform the first action, the controller is further programmed to record a first timestamp in response to receiving a start trigger signal. To perform the first action, the controller is further programmed to perform a first error checking action in response to receiving a start trigger signal.

[0008] In another aspect of the present disclosure, to perform the first error checking action, the controller is further programmed to identify a type of trigger signal previously received. The trigger signal type includes at least one of a start trigger signal and a stop trigger signal. To perform the first error checking action, the controller is further programmed to store an error log in a non-transitory memory of the controller in response to determining that the type of trigger signal previously received is a start trigger signal.

[0009] In another aspect of the present disclosure, to perform the second action, the controller is further programmed to record a second timestamp in response to receiving a stop trigger signal. To perform the second action, the controller is further programmed to perform a second error checking action in response to receiving the stop trigger signal. To perform the second action, the controller is further programmed to calculate a delay measurement based at least in part on the first timestamp and the second timestamp. The delay measurement is stored in a non-transitory memory of the controller. To perform the second action, the controller is further programmed to calculate at least one delay measurement statistic based at least in part on a plurality of delay measurements stored in the non-transitory memory of the controller.

[0010] In another aspect of the present disclosure, to perform the second error checking action, the controller is further programmed to identify the type of trigger signal previously received. The trigger signal type includes one of a start trigger signal and a stop trigger signal. To perform the second error checking action, the controller is further programmed to store an error log in a non-transitory memory of the controller in response to determining that the type of trigger signal previously received is a stop trigger signal.

[0011] In another aspect of the present disclosure, the controller further comprises a network interface in electrical communication with the data acquisition system. The controller is further programmed to transmit at least one delay measurement statistic to the data acquisition system using the network interface.

[0012] In another aspect of the present disclosure, the controller further comprises a first output port in electrical communication with at least one of the first input port and the second input port. The controller is further programmed to perform a calibration action using at least the first output port and at least one of the first input port and the second input port.

[0013] In another aspect of the present disclosure, to perform the calibration action, the controller is further programmed to provide a test pulse having a predetermined expected test duration to at least one of the first input port and the second input port using the first output port. To perform the calibration action, the controller is further programmed to measure an actual test duration of the test pulse using at least one of the first input port and the second input port. To perform the calibration action, the controller is further programmed to determine a difference between the actual test duration and the predetermined expected test duration. To perform the calibration action, the controller is further programmed to calibrate a system timer module of the controller based at least in part on the difference between the actual test duration and the predetermined expected test duration.

[0014] According to several aspects, a method for measuring network delay is provided. The method includes electrically connecting a plurality of devices under test (DUTs) to a controller. Each of the plurality of DUTs is connected to one of a plurality of input ports of the controller. Each of the plurality of DUTs is configured to send a start trigger signal to one of the plurality of input ports when transmitting a data message. Each of the plurality of DUTs is configured to send a stop trigger signal to one of the plurality of input ports when receiving a data message. The method also includes receiving a start trigger signal, performing a first action in response to receiving the start trigger signal, receiving a stop trigger signal, performing a second action in response to receiving the stop trigger signal, and determining a delay measurement result based at least in part on the first action and the second action.

[0015] In another aspect of the present disclosure, performing the first action may further include recording a first timestamp in a non-transitory memory of the controller in response to receiving a start trigger signal. Performing the first action may further include performing a first error checking action in response to receiving a start trigger signal.

[0016] In another aspect of the present disclosure, performing the first error checking action may further include identifying a type of trigger signal previously received. The trigger signal type includes at least one of a start trigger signal and a stop trigger signal. Performing the first error checking action may further include, in response to determining that the type of trigger signal previously received is a start trigger signal, storing an error log in a non-transitory memory of the controller.

[0017] In another aspect of the present disclosure, performing the second action may further include recording a second timestamp in response to receiving a stop trigger signal. Performing the second action may further include performing a second error checking action in response to receiving a stop trigger signal. Performing the second action may further include calculating a delay measurement result based at least in part on the first timestamp and the second timestamp. Performing the second action may further include storing the delay measurement result in a non-transitory memory of the controller. Performing the second action may further include calculating at least one delay measurement result statistic based at least in part on a plurality of delay measurements stored in the non-transitory memory of the controller.

[0018] In another aspect of the present disclosure, performing the second error checking action may further include identifying a type of trigger signal previously received. The trigger signal type includes at least one of a start trigger signal and a stop trigger signal. Performing the second error checking action may further include, in response to determining that the type of trigger signal previously received is a stop trigger signal, storing an error log in a non-transitory memory of the controller.

[0019] In another aspect of the present disclosure, the method further includes transmitting the at least one delay measurement statistic to a data acquisition system using a network interface of the controller.

[0020] In another aspect of the present disclosure, the method further includes receiving at least one delay measurement statistic using a data collection system. The method further includes generating a graphical visualization of at least one delay measurement statistic using the data collection system.

[0021] According to several aspects, a delay measurement system for a vehicle is provided. The delay measurement system includes a controller having a first input port, a second input port, and a network interface, wherein the first input port is in electrical communication with a first device under test (DUT), the second input port is in electrical communication with a second device under test (DUT), and the network interface is in electrical communication with a data acquisition system. The controller is configured to receive a start trigger signal using the first input port. The controller is also programmed to perform a first action in response to receiving the start trigger signal. The controller is also programmed to receive a stop trigger signal using the second input port. The controller is also programmed to perform a second action in response to receiving the stop trigger signal. The controller is also programmed to determine a delay measurement result based at least in part on the first action and the second action. The controller is also programmed to calculate at least one delay measurement result statistic based at least in part on a plurality of delay measurement results stored in a non-transitory memory of the controller. The controller is also programmed to transmit at least one delay measurement result statistic to the data acquisition system using the network interface.

[0022] In another aspect of the present disclosure, to perform the first action, the controller is further programmed to record a first timestamp in response to receiving a start trigger signal. To perform the first action, the controller is further programmed to identify a type of trigger signal previously received. The trigger signal type includes at least one of a start trigger signal and a stop trigger signal. To perform the first action, the controller is further programmed to store an error log in a non-transitory memory of the controller in response to determining that the type of trigger signal previously received is a start trigger signal.

[0023] In another aspect of the present disclosure, to perform the second action, the controller is further programmed to record a second timestamp in response to receiving a stop trigger signal. To perform the second action, the controller is further programmed to identify the type of trigger signal previously received. The trigger signal type includes at least one of a start trigger signal and a stop trigger signal. To perform the second action, the controller is further programmed to store an error log in a non-transitory memory of the controller in response to determining that the type of trigger signal previously received is a stop trigger signal. To perform the second action, the controller is further programmed to calculate a delay measurement result based at least in part on the first timestamp and the second timestamp. To perform the second action, the controller is further programmed to store the delay measurement result in the non-transitory memory of the controller.

[0024] Further areas of applicability will become apparent from the description provided herein.It should be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way.

[0026] Figure 1 is a schematic diagram of a delay measurement system according to an exemplary embodiment;

[0027] Figure 2 is a flow chart of a method for measuring network delay according to an exemplary embodiment;

[0028] Figure 3 is a flow chart of a setup routine according to an exemplary embodiment;

[0029] Figure 4 is a flow chart of a calibration routine according to an exemplary embodiment; and

[0030] Figure 5 is a schematic diagram of a delay measurement system in a vehicle according to an exemplary embodiment. DETAILED DESCRIPTION

[0031] The following description is merely exemplary in nature and is not intended to limit the present disclosure, application, or uses.

[0032] In some vehicle electrical architectures, controller units may be centralized in a central location, possibly remote from other vehicle components that must communicate with the controller units. Communication delays between devices in a vehicle system may result in unexpected behavior and / or difficult to diagnose errors. Accordingly, the present disclosure provides a system and method for quantifying transmission delays between vehicle devices, thereby allowing for faster development of new vehicle electrical systems and diagnosis of faults in current vehicle electrical systems.

[0033] refer to Figure 1 , a delay measurement system is shown and generally indicated by reference numeral 10 . The system 10 generally includes a controller 12 .

[0034] The controller 12 is used to implement the method 100 for measuring network delay, as described below. The controller 12 includes at least one processor 14, a non-transitory computer-readable storage device or medium 16, a system timer module 18, a network interface 20, and a plurality of input ports 22.

[0035] Processor 14 may be a custom or commercially available processor, a central processing unit (CPU), a graphics processing unit (GPU), an auxiliary processor of several processors associated with controller 12, a semiconductor-based microprocessor (in the form of a microchip or chipset), a macroprocessor, a combination of the above, or a device generally used to execute instructions. Controller 12 may also be composed of multiple controllers that communicate electrically with each other.

[0036] The computer readable storage device or medium 16 may include volatile and non-volatile storage devices such as read-only memory (ROM), random access memory (RAM), and keep alive memory (KAM). KAM is a persistent or non-volatile memory that can be used to store various operating variables when the processor 14 is powered off. The computer readable storage device or medium 16 can be implemented using a plurality of storage devices, such as PROM (programmable read-only memory), EPROM (electrical PROM), EEPROM (electrically erasable PROM), flash memory, or other electrical, magnetic, optical, or a combination thereof storage device capable of storing data (some of which represent executable instructions) that is used by the controller 12 to perform the method 100.

[0037] The system timer module 18 is used to track and manage the timing and synchronization of various system operations and events of the controller 12. In a non-limiting example, the system timer module 18 operates by utilizing a precise clock source (e.g., a crystal oscillator) to generate a consistent and accurate time base for the controller 12. Through a series of internal registers and counters, the system timer module 18 tracks time intervals, thereby allowing precise timing control and synchronization of events to be achieved. The system timer module 18 facilitates the execution of time-dependent functions, such as scheduling tasks, generating time delays, measuring time differences between events, and coordinating system operations with external devices. The system timer module 18 operates in conjunction with the processor 14. The processor 14 can periodically query the system timer module 18 to retrieve time-related information, such as timestamps. By evaluating the difference between two retrieved timestamps, the controller 12 can determine the time elapsed between the two retrieved timestamps. The system timer module 18 is in electrical communication with the controller 12. In an exemplary embodiment, the system timer module 18 is integrated into the controller 12 as a peripheral device.

[0038] The network interface 20 is used by the controller 12 to communicate with an external device (e.g., a data acquisition system 26). The network interface 20 is configured to facilitate data exchange between two or more devices. In an exemplary embodiment, the network interface 20 operates using a network protocol such as Ethernet or Wi-Fi. It should be understood that other communication protocols such as near field communication, Bluetooth, CAN bus, universal serial bus (USB), etc. are also within the scope of the present disclosure. In a non-limiting example, the network interface 20 uses a combination of hardware components and software components to establish and maintain a connection. In a non-limiting example, the network interface 20 utilizes a communication protocol such as TCP / IP or UDP to implement the transmission and reception of data packets. The network interface 20 can handle tasks such as data encapsulation, error detection and correction, data packet routing, and network addressing. The network interface 20 is in electrical communication with the controller 12. In an exemplary embodiment, the network interface 20 is integrated into the controller 12 as a peripheral device.

[0039] The data acquisition system 26 is used to aggregate and process data generated by the controller 12 and transmitted by the network interface 20. In an exemplary embodiment, the data acquisition system 26 is a personal computing device, such as a laptop computer, a desktop computer, a tablet computer, a smart phone, etc. In another exemplary embodiment, the data acquisition system 26 is a cloud-based server system, such as a server cluster. The data acquisition system 26 generally includes at least a central processing unit (CPU), a non-transitory memory, and a display. In a non-limiting example, the data acquisition system 26 uses the CPU and the non-transitory memory to analyze the data generated by the controller 12 and generate visual content (e.g., graphs, tables, etc.) to be displayed using a display. The data acquisition system 26 is in electrical communication with the network interface 20. It should be understood that the electrical communication between the data acquisition system 26 and the network interface 20 can be implemented using wired and / or wireless communication protocols without departing from the scope of the present disclosure.

[0040] Multiple input ports 22 are used to allow the controller 12 to receive signals from other devices and / or systems outside the controller 12. In an exemplary embodiment, the multiple input ports 22 are general purpose input and output (GPIO) ports, which can be software and / or hardware configured to be used as input ports. In an exemplary embodiment, multiple input ports provide additional functions, such as pull-up and / or pull-down resistors, filters, amplifiers, analog-to-digital converters, etc. In a non-limiting example, when a signal is received using one of the multiple input ports 22, an interrupt routine is started, which interrupts the normal control flow of the program running on the processor 14. The interrupt routine can be configured to take action based on the received signal. Therefore, using multiple input ports 22 and interrupt routines, the controller 12 can respond to external signals when an interrupt is received without the need to continuously poll multiple input ports 22.

[0041] It should be appreciated that the controller 12 may include additional components and / or peripherals without departing from the scope of the present disclosure.

[0042] In an exemplary embodiment, a plurality of input ports 22 are in electrical communication with a plurality of devices under test (DUTs) 24. Within the scope of the present disclosure, a plurality of DUTs are devices that are in electrical communication with each other. The system 10 is used to measure communication delays between a plurality of DUTs 24. In a non-limiting example, a plurality of DUTs 24 include devices such as vehicle controllers (e.g., vehicle electronic control units), vehicle sensors (e.g., vehicle suspension damper sensors), vehicle actuators (e.g., vehicle active suspension actuators), vehicle display systems (e.g., vehicle infotainment head units), and the like. In an exemplary embodiment, electrical communication between a plurality of DUTs is established using, for example, a CAN network, a FLEXRAY network, a local area network (e.g., WiFi, Ethernet, etc.), a serial peripheral interface (SPI) network, and the like. It should be understood that various additional wired and / or wireless technologies and communication protocols for communication between a plurality of DUTs are within the scope of the present disclosure.

[0043] Each of the plurality of DUTs 24 is configured to send a signal to one of the plurality of input ports 22 when sending / receiving communication to / from another of the plurality of DUTs 24. In an exemplary embodiment, a first DUT 24a of the plurality of DUTs 24 is in electrical communication with a first input port 22a of the plurality of input ports 22. A second DUT 24b of the plurality of DUTs 24 is in electrical communication with a second input port 22b of the plurality of input ports 22. A third DUT 24c of the plurality of DUTs 24 is in electrical communication with a third input port 22c of the plurality of input ports 22. Thus, the controller 12 receives signals from the plurality of DUTs 24 and determines network delays, as will be discussed in more detail below. For clarity, the present disclosure discusses an exemplary embodiment in which the plurality of DUTs 24 includes three devices. However, it should be understood that the plurality of DUTs 24 may include any number of devices without departing from the scope of the present disclosure.

[0044] refer to Figure 2 , a flow chart of a method 100 for measuring network delay is shown. For the sake of clarity, the following explanation will mainly relate to measuring the network delay of transmission between the first DUT 24a and the second DUT 24b. However, it should be understood that the same and / or similar methods can be used to measure the network delay between any combination of multiple DUTs 24.

[0045] The method 100 begins at frame 102 and proceeds to frame 104. At frame 104, the controller 12 performs a setup routine to configure the controller 12 to perform the method 100, as will be discussed in more detail below. After frame 104, the method 100 proceeds to frame 106. At frame 106, the controller 12 performs a calibration routine, as will be discussed in more detail below. After frame 106, the method 100 proceeds to frames 108 and 110.

[0046] At block 108, the controller 12 receives a start trigger signal from the first DUT 24a using the first input port 22a. In an exemplary embodiment, the start trigger signal is a rising edge of a digital logic signal. In another exemplary embodiment, the start trigger signal is a falling edge of a digital logic signal. In a non-limiting example, the start trigger signal initiates a hardware interrupt. The hardware interrupt stops the execution of non-essential program instructions so that the next method steps are executed immediately. After block 108, the method 100 proceeds to block 112.

[0047] At block 112, the controller 12 records a first timestamp in response to receiving the start trigger signal. In an exemplary embodiment, the controller 12 retrieves the first timestamp from a system timer module of the controller 12. In a non-limiting example, the first timestamp is stored in the medium 16 of the controller 12 along with the trigger signal type (i.e., the start trigger signal) and one of the plurality of input ports 22 (e.g., the first input port 22a) from which the start trigger signal was received. After block 112, the method 100 proceeds to block 114.

[0048] At box 114, the controller 12 performs a first error checking action. In an exemplary embodiment, to perform the first error checking action, the controller 12 identifies a type of trigger signal previously received. The type of trigger signal previously received includes one of: a start trigger signal and a stop trigger signal. In an exemplary embodiment, to identify the previously received trigger signal, the controller 12 accesses the medium 16 and identifies the previously received trigger signal based on a timestamp of the trigger signal stored in the medium 16. If the type of trigger signal previously received is a start trigger signal, the method 100 proceeds to box 116. If the type of trigger signal previously received is not a start trigger signal, the method 100 proceeds to box 118, as will be discussed in more detail below.

[0049] At block 116, the controller 12 stores an error log to the medium 16 of the controller 12. In an exemplary embodiment, the error log includes the first timestamp and trigger signal type (as determined at block 112), the previously received trigger signal type (as determined at block 114), and the one of the plurality of input ports 22 (e.g., the first input port 22a) from which the start trigger signal was received. The error log is stored because if the controller 12 is not configured to measure multiple delays simultaneously, consecutive receipt of two start trigger signals without a stop trigger signal would constitute an error condition.

[0050] However, in some embodiments, the controller 12 may be configured to measure multiple delays simultaneously. For example, if it is known that a first transmission will be sent from the first DUT 24a to the second DUT 24b, and a second transmission will be sent from the first DUT 24a to the third DUT 24c, the controller 12 may measure both transmissions simultaneously because it is known that the stop trigger signal received at the second input port 22b corresponds to the first start trigger signal, and the stop trigger signal received at the third input port 22c corresponds to the second start trigger signal. Therefore, it should be understood that in some embodiments, the first error checking actions performed at blocks 112 and 114 may be omitted or modified based on the configuration of the controller 12. After block 116, the method 100 proceeds to block 118, as will be discussed in more detail below.

[0051] At block 110, the controller 12 receives a stop trigger signal from the second DUT 24b using the second input port 22b. In an exemplary embodiment, the stop trigger signal is a rising edge of a digital logic signal. In another exemplary embodiment, the stop trigger signal is a falling edge of a digital logic signal. In a non-limiting example, the stop trigger signal initiates a hardware interrupt. The hardware interrupt stops the execution of non-essential program instructions so that the next method steps are executed immediately. After block 110, the method 100 proceeds to block 120.

[0052] At block 120, the controller 12 records a second timestamp in response to receiving the stop trigger signal. In an exemplary embodiment, the controller 12 retrieves the second timestamp from a system timer module of the controller 12. In a non-limiting example, the second timestamp is stored in the medium 16 of the controller 12 along with the trigger signal type (i.e., stop trigger signal) and one of the plurality of input ports 22 (e.g., second input port 22 b) from which the start trigger signal was received. After block 120, the method 100 proceeds to block 122.

[0053] At block 122, the controller 12 performs a second error checking action. In an exemplary embodiment, to perform the second error checking action, the controller 12 identifies a type of a previously received trigger signal. The type of the previously received trigger signal includes one of: a start trigger signal and a stop trigger signal. In an exemplary embodiment, to identify the previously received trigger signal, the controller 12 accesses the medium 16 and identifies the previously received trigger signal based on a timestamp of the trigger signal stored in the medium 16. If the type of the previously received trigger signal is a stop trigger signal, the method 100 proceeds to block 124. If the type of the previously received trigger signal is not a start trigger signal, the method 100 proceeds to block 126.

[0054] At block 124, the controller 12 stores an error log in the medium 16 of the controller 12. In an exemplary embodiment, the error log includes the second timestamp and the trigger signal type (as determined at block 120), the previously received trigger signal type (as determined at block 122), and one of the plurality of input ports 22 (e.g., the second input port 22b) from which the stop trigger signal was received. The error log is stored because if the controller 12 is not configured to measure multiple delays simultaneously, receiving two stop trigger signals in succession without a start trigger signal would constitute an error condition. As discussed above with reference to the first error checking action, it should be understood that in some embodiments, the second error checking actions performed at blocks 122 and 124 may be omitted or modified based on the configuration of the controller 12. After block 124, the method 100 proceeds to block 118, as will be discussed in more detail below.

[0055] At block 126, the controller 12 calculates a delay measurement. In an exemplary embodiment, the delay measurement is the difference between the first timestamp recorded at block 112 and the second timestamp recorded at block 120. Thus, the delay measurement represents the time that elapsed between receiving the start trigger signal at block 108 and receiving the stop trigger signal at block 110. In a non-limiting example, the delay measurement is stored in the medium 16 of the controller 12. After block 126, the method 100 proceeds to block 128.

[0056] At block 128, the controller 12 calculates at least one delay measurement statistic. In an exemplary embodiment, after multiple executions of the method 100, the multiple delay measurements are stored in the medium 16 of the controller 12. Thus, at least one measurement statistic is calculated based on the multiple delay measurements stored in the medium 16 of the controller 12. In an exemplary embodiment, the at least one delay measurement statistic includes one or more of the following: a minimum delay measurement, a maximum delay measurement, an average delay measurement, a moving average delay measurement, a windowed average delay measurement, a standard deviation of the multiple delay measurements, etc. In a non-limiting example, the at least one delay measurement statistic is stored in the medium 16 of the controller 12. After block 128, the method 100 proceeds to block 130.

[0057] At block 130, the controller 12 sets a flag indicating that new delay measurement statistics are available. In the scope of the present disclosure, a flag refers to a one-bit variable or state bit associated with a specific condition or event (i.e., at least one delay measurement statistic is available). The flag can have a set state or an unset state. The set state indicates that new delay measurement statistics are available for transmission. The unset state indicates that no new delay measurement statistics are available for transmission. After block 130, the method 100 proceeds to block 118.

[0058] At block 118, the controller 12 evaluates whether the flag is set. If the flag is not set, the method 100 continues to enter a standby state at block 132. If the flag is set, the method 100 proceeds to block 134 to transmit the data to the data acquisition system 26. Therefore, in the exemplary embodiment, the controller 12 does not continuously transmit each delay measurement result to the data acquisition system 26, but rather periodically transmits at least one delay measurement result statistic, thereby reducing network bandwidth consumption and processing power usage.

[0059] At block 134, the controller 12 uses the network interface 20 to transmit the at least one delay measurement statistic calculated at block 128 to the data acquisition system 26 and resets the flag to an unset state. In an exemplary embodiment, after receiving the at least one delay measurement statistic, the data acquisition system 26 saves the at least one delay measurement statistic in a non-transitory memory of the data acquisition system 26. In a non-limiting example, the data acquisition system 26 generates a graphical visualization of the at least one delay measurement statistic and displays the graphical visualization using a display of the data acquisition system 26. In a non-limiting example, the graphical visualization includes, for example, a scatter plot, a line graph, a table, an animation, etc., including any other type of graphical representation of the at least one delay measurement statistic received from the controller 12. After block 134, the method 100 continues at block 132 to enter a standby state.

[0060] In an exemplary embodiment, the controller 12 repeatedly exits the standby state 132 and restarts the method 100 at box 102. In a non-limiting example, the controller 12 exits the standby state 132 and restarts the method 100 according to a timer, for example, every three hundred milliseconds. In an exemplary embodiment, the setup routine at box 104 and the calibration routine at box 106 are only performed when the system 10 is initially started and are not repeated during subsequent executions of the method 100.

[0061] refer to Figure 3, a flow chart of an exemplary embodiment of block 104 (i.e., a setup routine for configuring the controller 12 to perform the method 100) is shown. The setup routine begins at block 302. At block 302, the controller 12 initializes variables for storing program data, such as a first timestamp, a second timestamp, a type of trigger signal previously received, etc. In an exemplary embodiment, the variables are initialized in the medium 16 of the controller 12. In another exemplary embodiment, the variables are initialized in a temporary memory of the controller 12 and can be erased when the controller 12 is restarted. After block 302, the exemplary embodiment of block 104 proceeds to block 304.

[0062] At block 304, the controller 12 initializes the system timer module 18. In an exemplary embodiment, the controller 12 activates the system timer module 18 by setting a binary bit in a corresponding register of the processor 14 to enable the system timer module 18. In a non-limiting example, the controller 12 may also configure various aspects of the system timer module 18, such as the speed and reset parameters of the system timer module 18. In an exemplary embodiment, the controller 12 also initializes a calibration offset value, which may be used to compensate for performance variations of the system timer module 18. In a non-limiting example, the system timer module 18 operates under the assumption that a predetermined amount of time (e.g., one second) corresponds to a predetermined amount of clock cycles (e.g., one thousand clock cycles) of the processor 14. However, the clock speed of the processor 14 may vary due to factors such as temperature, humidity, power supply voltage level, etc. Therefore, the calibration offset value may be added to the predetermined amount of clock cycles to adjust for clock speed variations. After block 304, the exemplary embodiment of block 104 proceeds to block 306.

[0063] At block 306, the controller 12 initializes the plurality of input ports 22. In an exemplary embodiment, the controller 12 sets binary bits in corresponding registers of the processor 14 to enable the plurality of input ports 22. In a non-limiting example, the controller 12 sets bits to configure the plurality of input ports 22 to function as input ports 22, rather than output ports. The controller 12 may additionally configure other parameters of the plurality of input ports 22, such as pull-up / pull-down resistors, enable or disable peripheral devices (e.g., analog-to-digital converters), etc. After block 306, the exemplary embodiment of block 104 ends, and the method 100 continues as described above.

[0064] refer to Figure 4, a flow chart of an exemplary embodiment of block 106 (i.e., a calibration routine, also referred to as a calibration action) is shown. The exemplary embodiment of block 106 begins at block 402. At block 402, the controller 12 configures one of the plurality of input ports 22 as an output port and connects the output port to another of the plurality of input ports 22. The controller 12 then provides a test pulse from the output port to one of the plurality of input ports 22. In an exemplary embodiment, the test pulse is a digital pulse having a predetermined desired test duration (e.g., a predetermined desired period of time during which the pulse is high). After block 402, the exemplary embodiment of block 106 proceeds to block 404.

[0065] At block 404, the controller 12 measures the actual test duration of the test pulse using one of the plurality of input ports 22. In an exemplary embodiment, the controller 12 records a third timestamp when the test pulse begins and a fourth timestamp when the test pulse ends. The difference between the fourth timestamp and the third timestamp is the actual test duration. In an exemplary embodiment, the output port is additionally in electrical communication with an external device, such as a data acquisition system 26. The external device also measures the actual test duration of the test pulse and transmits the measured actual test duration to the controller 12 using the network interface 20. Thus, by utilizing an external device for measurement, clock speed variations of the processor 14 are isolated from the measurement results. After block 404, the exemplary embodiment of block 106 proceeds to block 406.

[0066] At block 406 , the controller 12 determines a difference between the actual test duration determined at block 404 and the predetermined desired test duration of the pulse generated at block 402 . After block 406 , the exemplary embodiment of block 106 proceeds to block 408 .

[0067] At block 408, the controller 12 calibrates the system timer module 18 based at least in part on the difference determined at block 406. In an exemplary embodiment, the controller 12 adjusts the calibration offset value of the system timer module 18 to account for the difference between the actual test duration determined at block 404 and the predetermined expected test duration of the pulse generated at block 402. Thus, the calibration action may effectuate calibration of the system timer module 18. After block 408, the exemplary embodiment of block 106 ends, and the method 100 continues as described above.

[0068] refer to Figure 5, a schematic diagram of a system 10 used in a vehicle 30 is shown. Although a passenger vehicle is shown, it should be understood that the vehicle 30 can be any type of vehicle without departing from the scope of the present disclosure. In an exemplary embodiment, the system 10 and method 100 are used within a vehicle to analyze network communications between vehicle devices. In a non-limiting example, a first DUT 24a is a vehicle control unit (VCU), a second DUT 24b is a vehicle rain sensor, and a third DUT 24c is a vehicle windshield wiper actuator. Multiple DUTs 24 communicate electrically via a CAN bus. The system 10 is used to measure network communication delays between multiple DUTs 24 on the CAN bus. In a first exemplary embodiment, the system 10 is integrated into the vehicle 30 as a discrete component and can be used by a vehicle system (e.g., a VCU) for diagnostic purposes to determine the health and function of the vehicle system. In a second exemplary embodiment, the system 10 is integrated into one of the multiple DUTs 24, such as into the VCU. In a third exemplary embodiment, system 10 is a diagnostic system external to vehicle 30 that may be connected to vehicle 30 by a service technician or engineer to diagnose problems and / or aid in the development and / or improvement of vehicle systems and features.

[0069] The system 10 and method 100 of the present disclosure provide several advantages. In some vehicle systems, controller units may be collected in a central location, possibly remote from other vehicle components. The system 10 and method 100 may be used to quantify transmission delays between vehicle devices, thereby allowing for faster development of new vehicle electrical systems and diagnosis of faults in current vehicle electrical systems. By using start and stop trigger pulses generated by multiple DUTs 24, the system 10 and method 100 are agnostic to the specific communication protocol for which the delay measurements are being made, making the system 10 and method 100 general and flexible for a variety of applications.

[0070] The description of the present disclosure is merely exemplary in nature, and variations that do not depart from the gist of the present disclosure are intended to fall within the scope of the present disclosure. These variations should not be regarded as departing from the spirit and scope of the present disclosure.

Claims

1. A delay measurement system, the delay measurement system comprising: A controller having a first input port and a second input port, wherein the controller is programmed to: Using the first input port to receive a start trigger signal; executing a first action in response to receiving the start trigger signal; Using the second input port to receive a stop trigger signal; performing a second action in response to receiving the stop trigger signal; as well as A delay measurement is determined based at least in part on the first action and the second action.

2. The delay measurement system of claim 1, wherein the first input port is in electrical communication with a first device under test (DUT), and wherein the start trigger signal is at least one of a rising edge and a falling edge of a digital logic signal.

3. The delay measurement system according to claim 1, wherein: The second input port is in electrical communication with a second device under test (DUT), and wherein the stop trigger signal is at least one of a rising edge and a falling edge of a digital logic signal.

4. The delay measurement system according to claim 1, wherein: To perform the first action, the controller is further programmed to: recording a first timestamp in response to receiving the start trigger signal; and A first error checking action is performed in response to receiving the start trigger signal.

5. The delay measurement system according to claim 4, wherein: To perform the first error checking action, the controller is further programmed to: identifying a type of a previously received trigger signal, wherein the type of the trigger signal comprises at least one of the start trigger signal and the stop trigger signal; as well as In response to determining that the previously received trigger signal type is the start trigger signal, an error log is stored in a non-transitory memory of the controller.

6. The delay measurement system according to claim 4, wherein: To perform the second action, the controller is further programmed to: recording a second timestamp in response to receiving the stop trigger signal; performing a second error checking action in response to receiving the stop trigger signal; calculating the delay measurement based at least in part on the first timestamp and the second timestamp, wherein the delay measurement is stored in a non-transitory memory of the controller; as well as At least one delay measurement statistic is calculated based at least in part on a plurality of delay measurements stored in a non-transitory memory of the controller.

7. The delay measurement system according to claim 6, wherein: To perform the second error checking action, the controller is further programmed to: identifying a trigger signal type previously received, wherein the trigger signal type comprises one of the start trigger signal and the stop trigger signal; and In response to determining that the previously received trigger signal type is the stop trigger signal, an error log is stored in a non-transitory memory of the controller.

8. The delay measurement system according to claim 6, wherein: The controller also includes a network interface in electrical communication with the data acquisition system, and wherein the controller is further programmed to: The at least one delay measurement statistic is transmitted to the data collection system using the network interface.

9. The delay measurement system according to claim 1, wherein: The controller further comprises a first output port in electrical communication with at least one of the first input port and the second input port, and wherein the controller is further programmed to: A calibration action is performed using at least the first output port and at least one of the first input port and the second input port.

10. The delay measurement system according to claim 9, wherein: To perform the calibration action, the controller is also programmed to: providing a test pulse having a predetermined desired test duration to at least one of the first input port and the second input port using the first output port; measuring an actual test duration of the test pulse using at least one of the first input port and the second input port; determining a difference between the actual test duration and the predetermined expected test duration; as well as A system timer module of the controller is calibrated based at least in part on a difference between the actual test duration and the predetermined desired test duration.

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