Time delay estimation method, device and equipment and readable storage medium

Abstract

The invention relates to a time delay estimation method, device and equipment and a readable storage medium. An electric chip sends a time delay calibration sequence to an optical chip; then, in the received data sent by the optical chip, identifying a feature sequence matched with the time delay calibration sequence; and finally, according to the sending time of the time delay calibration sequence and the receiving time of the feature sequence, determining a time delay estimation value of the optical chip. Wherein the feature sequence is obtained after the optical chip calls a data processing model and processes the time delay calibration sequence. By adopting the method, the electric chip can more accurately sample the data transmitted by the optical chip on the basis of obtaining the accurate time delay estimation value, so that the data joint processing between the optical chip and the electric chip is realized, and the data processing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a delay estimation method, apparatus, device and readable storage medium. Background Art

[0002] The continuous evolution of artificial intelligence technology has brought about the need to process and transmit massive amounts of data, and traditional electronic chips have gradually shown bottlenecks in the face of these needs. The advantages of optical chips, such as high speed, high bandwidth, and low energy consumption, make them play an important role in artificial intelligence applications and become a key factor in promoting the advancement of artificial intelligence. Optical chips use optical signal transmission instead of traditional electrical signal transmission, which greatly improves the data transmission rate, thereby better meeting the application needs of artificial intelligence.

[0003] Taking the Field Programmable Gate Array (FPGA) as an example, the function of the electrical chip can change every time the device is powered on. When the function needs to be changed, just download the new configuration file to the device. Therefore, FPGA has diverse functionality and good flexibility, which is suitable for joint computing with optical chips. FPGA can send data such as pictures to the optical chip for convolution layer calculation in the neural network model. After the optical chip completes the convolution layer calculation, it will send the data back to the FPGA to continue the pooling layer calculation through the FPGA.

[0004] However, in the above data processing process, since the electrical chip cannot obtain the accurate data processing delay of the optical chip, after the electrical chip receives the data transmitted by the optical chip, it is unable to use the accurate delay estimation value for data sampling, resulting in poor data processing efficiency for the joint calculation of the optical chip and the electrical chip. Summary of the invention

[0005] The embodiments of the present application provide a delay estimation method, apparatus, device and readable storage medium, which can enable an electrical chip to obtain an accurate delay estimation value, thereby improving the data processing efficiency of the joint calculation of the optical chip and the electrical chip.

[0006] In a first aspect, a delay estimation method is provided, which is applied to an electrical chip connected to an optical chip, and the method comprises:

[0007] Sending a delay calibration sequence to the optical chip;

[0008] In the received data sent by the optical chip, a characteristic sequence matching the delay calibration sequence is identified; wherein the characteristic sequence is obtained after the optical chip calls the data processing model and processes the delay calibration sequence;

[0009] The delay estimation value of the optical chip is determined according to the sending time of the delay calibration sequence and the receiving time of the characteristic sequence.

[0010] In one embodiment, the electrical chip is connected to the optical chip via a digital-to-analog converter DAC module, and the delay calibration sequence is sent to the optical chip, including:

[0011] Converting the delay calibration sequence into first channel data and second channel data; wherein the first channel data and the second channel data are sent through different time slots of the same cycle;

[0012] With reference to the clock cycle of the DAC module, the first channel data is sent to the optical chip when the rising edge is reached, and the second channel data is sent to the optical chip when the falling edge is reached.

[0013] In one embodiment, the electrical chip is connected to the optical chip through a plurality of DAC modules, and the step of converting the delay calibration sequence into the first channel data and the second channel data includes:

[0014] The delay calibration sequence is converted into a plurality of first channel data and a plurality of second channel data; the plurality of first channel data corresponds one-to-one to the plurality of DAC modules; the plurality of second channel data corresponds one-to-one to the plurality of DAC modules.

[0015] In one embodiment, the step of identifying a characteristic sequence matching the delay calibration sequence in the received data sent by the optical chip includes:

[0016] Sampling the data sent by the optical chip to obtain an initial sampling sequence;

[0017] A plurality of preset characteristic values ​​are used to match the data in the initial sampling sequence respectively; wherein the preset characteristic values ​​are values ​​in the reference characteristic sequence corresponding to the delay calibration sequence; the plurality of preset characteristic values ​​are arranged in chronological order and are used to characterize the change characteristics of the reference characteristic sequence;

[0018] In the reference feature sequence, if the plurality of preset feature values ​​correspond to the plurality of sampling values ​​in the initial sampling sequence in sequence, the sequence in which the plurality of sampling values ​​are located is determined as the feature sequence.

[0019] In one embodiment, the delay calibration sequence is a triangle wave sequence, the reference characteristic sequence is waveform data including peaks, and the time series range of the plurality of characteristic values ​​covers the peaks of the waveform data.

[0020] In one embodiment, the above-mentioned electronic chip is provided with a DAC data path module connected to the delay calibration sequence sending module and the service data sending module, and an analog-to-digital conversion ADC data path module connected to the delay verification module and the service data receiving module;

[0021] The step of determining the estimated delay value of the optical chip according to the sending time of the delay calibration sequence and the receiving time of the characteristic sequence includes:

[0022] Determine the time when the delay calibration sequence arrives at the DAC data path module as the sending time;

[0023] Determine the time when the characteristic sequence reaches the ADC data path module as the receiving time;

[0024] The delay estimation value is determined based on the time difference between the sending time and the receiving time.

[0025] In one embodiment, determining the time when the characteristic sequence reaches the ADC data path module as the receiving time includes:

[0026] In the case where a plurality of continuous sequences are identified as the characteristic sequences, determining a target sequence located in the middle of the plurality of continuous sequences;

[0027] The time when the target sequence arrives at the ADC pathway module is determined as the receiving time.

[0028] In a second aspect, a delay estimation device is provided, which is applied to an electrical chip connected to an optical chip, and the device includes:

[0029] A sending module, used for sending a delay calibration sequence to the optical chip;

[0030] An identification module is used to identify a characteristic sequence matching the delay calibration sequence in the received data sent by the optical chip; wherein the characteristic sequence is obtained after the optical chip calls the data processing model and processes the delay calibration sequence;

[0031] The determination module is used to determine the delay estimation value of the above optical chip according to the sending time of the above delay calibration sequence and the receiving time of the above characteristic sequence.

[0032] In a third aspect, a data processing device is provided, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the method described in the first aspect.

[0033] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0034] In the above-mentioned delay estimation method, device, equipment and readable storage medium, the electrical chip sends a delay calibration sequence to the optical chip; then, in the data received from the optical chip, a feature sequence matching the above-mentioned delay calibration sequence is identified; finally, based on the sending time of the above-mentioned delay calibration sequence and the receiving time of the above-mentioned feature sequence, the delay estimation value of the above-mentioned optical chip is determined; wherein the above-mentioned feature sequence is obtained after the above-mentioned optical chip calls the data processing model and processes the above-mentioned delay calibration sequence. Since the electrical chip sends a delay calibration sequence to the optical chip, when the delay calibration sequence is sent from the electrical chip, it reaches the optical chip through the DAC module, and is further processed by the optical chip calling the data processing model, and then the feature sequence is returned to the electrical chip. The electrical chip can determine the delay required for the electrical chip to send the delay calibration sequence, send the delay calibration sequence to the optical chip through the DAC module, process the delay calibration sequence, and return the processed feature sequence to the electrical chip based on the reception time of the feature sequence returned by the optical chip and the sending time of the delay calibration sequence, and obtain a more accurate delay estimate. Furthermore, on the basis of obtaining an accurate delay estimate, the electrical chip can more accurately sample the data transmitted by the optical chip, realize joint data processing between the optical chip and the electrical chip, and improve data processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 This is an application environment diagram of a delay estimation method in one embodiment of the present application;

[0037] Figure 2 This is a flowchart of a delay estimation method in one embodiment of the present application;

[0038] Figure 3 A schematic diagram of a delay calibration sequence in a delay estimation method in one embodiment of the present application;

[0039] Figure 4 This is a flowchart of a delay estimation method in another embodiment of the present application;

[0040] Figure 5A schematic diagram of a delay estimation method in another embodiment of the present application;

[0041] Figure 6 A schematic diagram of a delay estimation method in another embodiment of the present application;

[0042] Figure 7 This is a flowchart of a delay estimation method in another embodiment of the present application;

[0043] Figure 8 A schematic diagram of a delay estimation method in another embodiment of the present application;

[0044] Fig. 9 This is a flowchart of a delay estimation method in another embodiment of the present application;

[0045] Fig.10 A schematic diagram of a delay estimation method in another embodiment of the present application;

[0046] Fig.11 A schematic diagram of a delay estimation method in another embodiment of the present application;

[0047] Fig.12 This is a structural block diagram of a delay estimation device in one embodiment of the present application;

[0048] Fig.13 This is a structural block diagram of a delay estimation device in another embodiment of the present application;

[0049] Fig.14 This is a structural block diagram of a delay estimation device in another embodiment of the present application;

[0050] Fig.15 FIG. 1 is a schematic diagram of the structure of a data processing device in an embodiment. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0052] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, the first data may be referred to as the second data, and similarly, the second data may be referred to as the first data. Both the first data and the second data are data, but they are not the same data.

[0053] Figure 1A schematic diagram of an application scenario of the delay estimation method provided in the embodiment of the present application. Figure 1 As shown, the application environment includes an electric chip 100 and an optical chip 200. The electric chip 100 can use electric signals as information carriers, such as field programmable gate array (FPGA), and the optical chip 200 can use higher frequency light waves as information carriers. The electric chip 100 and the optical chip 200 can perform data conversion through a digital to analog converter (DAC) 300 and an analog to digital converter (ADC) 400. The electric chip 100 and the optical chip 200 can perform data processing in technical fields such as data centers, cloud computing, artificial intelligence, image processing, and intelligent control. The embodiments of the present application do not limit the application scenarios.

[0054] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0055] In one embodiment, Figure 2 As shown, a delay estimation method is provided, which is applied to Figure 1 The electronic chip in the example is used to illustrate, including:

[0056] S102: Send a delay calibration sequence to the optical chip.

[0057] The electrical chip can be a chip such as FPGA that uses electrical signals as information carriers, and the optical chip can be a chip that uses light waves as information carriers. The optical chip and the electrical chip can perform data joint computing, and the advantages of the optical chip such as high speed, high bandwidth, and low energy consumption can greatly improve the data processing efficiency of the joint computing.

[0058] The above-mentioned electrical chip and optical chip can jointly perform data processing of the neural network model. The above-mentioned neural network model may include multiple data processing layers, and the above-mentioned optical chip can process one or more of the data processing layers. In one implementable manner, the electrical chip can complete the processing of the data input layer in the neural network model, and send the processed data to the optical chip after DAC conversion. The optical chip continues to complete the data processing of the convolution layer. The optical chip converts the processed data through ADC and then sends it to the electrical chip. The electrical chip can complete the processing of modules such as the pooling layer in the neural network model. The joint processing method of the optical chip and the electrical chip is not limited here.

[0059] The delay calibration sequence is used to estimate the processing delay of the optical chip. The delay calibration sequence can be one or more sets of preset logic data, and the logic data can be a square wave sequence or other waveform data, which is not limited here. Optionally, the delay calibration sequence can be a triangle wave sequence, and the triangle wave can include a rising sequence and a falling sequence. The triangle wave sequence can include a set of rising sequences and a set of falling sequences, or can include multiple sets of rising sequences and multiple sets of falling sequences, which is not limited here. Figure 3 As shown, the above verification sequence is a set of triangular wave sequences including 2 rising sequences and 2 falling sequences.

[0060] When sending a delay calibration sequence, the electrical chip can select a corresponding delay calibration sequence from the preset multiple groups of delay calibration sequences according to the data scenario for sending; it can also randomly select one group from the preset multiple groups of delay calibration sequences for sending. The sending method of the delay calibration sequence is not limited here.

[0061] The above-mentioned delay calibration sequence can be sent together with the business data between the electrical chip and the optical chip. For example, when the electrical chip sends the jointly calculated business data to the optical chip, it can send the above-mentioned delay calibration sequence to the optical chip according to a preset sending cycle to perform real-time correction of the current optical chip processing delay. Alternatively, the electrical chip can also send the delay calibration sequence to the optical chip within a fixed delay calibration cycle, which is not limited here. Among them, the above-mentioned business data can be data to be jointly processed by the neural network model in the electrical chip and the optical chip, which can be image data, audio data, or data of other business types, which is not limited here.

[0062] S104. Identify a characteristic sequence matching the delay calibration sequence in the received data sent by the optical chip; wherein the characteristic sequence is obtained after the optical chip calls a data processing model and processes the delay calibration sequence.

[0063] The above-mentioned characteristic sequence can be obtained by the optical chip performing data processing after the electrical chip sends the delay calibration sequence to the optical chip. The electrical chip can send the delay calibration sequence to the optical chip through the DAC. After the optical chip calls the data processing model to process the optical signal corresponding to the delay calibration sequence, it obtains a set of processed optical signals, and converts the processed optical signals into characteristic sequences through the ADC, and returns them to the electrical chip.

[0064] The optical chip processes the delay calibration sequence by running a data processing model, taking the optical signal corresponding to the delay calibration sequence as the input of the data processing model, and outputting the processed optical signal. The data processing model can be one or more layers in the neural network model.

[0065] The above-mentioned characteristic sequence can maintain the same waveform characteristics as the delay calibration sequence. For example, when the delay calibration sequence is a triangular wave sequence, its corresponding characteristic sequence is also a triangular wave sequence. Alternatively, the waveform characteristics of the above-mentioned characteristic sequence may also be different from those of the delay calibration sequence. For example, when the delay calibration sequence is a square wave sequence, its corresponding characteristic sequence is a triangular wave sequence. This is not limited here.

[0066] The electrical chip can receive data sent by the optical chip to the electrical chip in real time after sending the delay calibration sequence. The above data may include business data returned by the optical chip to the electrical chip, feature sequences returned by the optical chip to the electrical chip, and other invalid data such as empty bubble data. The electrical chip can identify which feature sequences correspond to the delay calibration sequence in the received data.

[0067] Specifically, before the electrical chip identifies the feature sequence in the received data, it can first obtain the reference feature sequence corresponding to the delay calibration sequence. Among them, the above-mentioned reference feature sequence can be the standard calculation result corresponding to the delay calibration sequence obtained after the optical chip pre-processes the delay calibration sequence. The above-mentioned reference feature sequence can be pre-stored in a register in the electrical chip, and the electrical chip can directly call the reference feature sequence stored in the register for matching after the current delay feature sequence is sent; or, the electrical chip can select one from multiple preset delay feature sequences for sending, and then select the corresponding reference feature sequence from multiple preset reference feature sequences for matching; the method for obtaining the reference feature sequence is not limited here.

[0068] After the electronic chip obtains the reference feature sequence, it can match each value in the reference feature sequence in order, determine which sequence in the received data is the same as the reference feature sequence, and determine the sequence that is the same as the reference feature sequence as the feature sequence. Alternatively, the electronic chip can randomly extract multiple feature values ​​from the reference feature sequence, and then identify the sequence that matches the multiple feature values ​​in the received data, and determine it as the feature sequence that matches the reference feature sequence. The method for identifying the feature sequence is not limited here.

[0069] S106: Determine the delay estimation value of the optical chip according to the sending time of the delay calibration sequence and the receiving time of the characteristic sequence.

[0070] In the above process, the time required for the electrical chip to send the delay calibration sequence to the optical chip, the DAC to perform data conversion, the optical chip to perform data processing, and the ADC to perform data conversion is the delay estimate of the optical chip in the link.

[0071] The electrical chip can determine the time difference between sending the delay calibration sequence and receiving the characteristic sequence according to the sending time of the delay calibration sequence and the receiving time of the characteristic sequence. The above time difference can be used to characterize the delay required by the optical chip for processing data.

[0072] In one implementation, the electronic chip can mark a timestamp on the transmitted delay calibration sequence so that after identifying the characteristic sequence, the electronic chip can directly extract the transmission time of the delay calibration sequence; further, the electronic chip can determine the reception time of the characteristic sequence based on the clock cycle of the received characteristic sequence.

[0073] In another implementation, the electrical chip can generate a calibration request signal while sending the delay calibration sequence, and then determine the rising edge of the calibration request signal as the sending time of the delay calibration sequence; further, the electrical chip can output a calibration pass signal after identifying the characteristic sequence, so as to determine the time corresponding to the rising edge of the calibration pass signal as the receiving time of the characteristic sequence. The method for determining the above-mentioned sending time and receiving time is not limited here.

[0074] On the basis of obtaining the time difference between the sending moment and the receiving moment, the electrical chip can directly use the time difference as the delay estimation value of the optical chip; or, the electrical chip can perform coefficient weighting processing on the time difference to obtain the delay estimation value. For example, the electrical chip can multiply the time difference by a weighting coefficient, or add a weighting coefficient to the time difference. The weighting coefficient can be related to the model of the optical chip, or to the model of DAC and ADC, or to the model of the operation of the optical chip. In one implementation, the electrical chip can obtain the time difference between multiple sending delay calibration sequences and receiving characteristic sequences by sending delay calibration sequences multiple times, and determine the delay estimation value of the optical chip by the average value of the multiple time differences. The method for obtaining the delay estimation value is not limited here.

[0075] The electrical chip can write the obtained delay estimation value into the register. When the electrical chip and the optical chip transmit service data, the electrical chip can call the delay estimation value stored in the register to sample the data sent by the optical chip.

[0076] It should be noted that the delay estimation value stored in the above register can be a value associated with the optical chip, or multiple values ​​associated with the optical chip, ADC, DAC, etc.; the specific form of the above delay estimation value is not limited here. Optionally, when the optical chip is connected to multiple DACs, the delay estimation value includes the delay estimation sub-values ​​corresponding to each DAC path. By performing delay estimation on each DAC path separately, the accuracy of the delay estimation value can be improved.

[0077] In the above-mentioned delay estimation method, device, equipment and readable storage medium, the electrical chip sends a delay calibration sequence to the optical chip; then, in the data received from the optical chip, a feature sequence matching the above-mentioned delay calibration sequence is identified; finally, based on the sending time of the above-mentioned delay calibration sequence and the receiving time of the above-mentioned feature sequence, the delay estimation value of the above-mentioned optical chip is determined; wherein the above-mentioned feature sequence is obtained after the above-mentioned optical chip calls the data processing model and processes the above-mentioned delay calibration sequence. Since the electrical chip sends a delay calibration sequence to the optical chip, when the delay calibration sequence is sent from the electrical chip, it reaches the optical chip through the DAC module, and is further processed by calling the data processing model through the optical chip and then returns the feature sequence to the electrical chip. The electrical chip can determine the delay required for the electrical chip to send the delay calibration sequence, send the delay calibration sequence to the optical chip through the DAC module, process the delay calibration sequence, and return the processed feature sequence to the electrical chip based on the reception time of the feature sequence returned by the optical chip and the sending time of the delay calibration sequence, so as to obtain a more accurate delay estimate. Furthermore, on the basis of obtaining an accurate delay estimate, the electrical chip can more accurately sample the data transmitted by the optical chip, realize joint data processing between the optical chip and the electrical chip, and improve data processing efficiency.

[0078] Figure 4 FIG. 1 is a flow chart of a delay estimation method in an embodiment. This embodiment relates to a specific implementation method of sending a delay calibration sequence from an electrical chip to an optical chip. Based on the above embodiment, Figure 4 As shown, the above S102 includes:

[0079] S202: Convert the delay calibration sequence into first channel data and second channel data.

[0080] When the electrical chip sends data to the optical chip, the data may be divided into two channels for transmission. When sending a delay calibration sequence, the delay calibration sequence may be converted into a first data channel and a second data channel. The difference between the first channel data and the second channel data is that the electrical chip may send the first channel data and the second channel data through different time slots within a clock cycle. For example, within a clock cycle, the first time slot sends the first channel data, and the second time slot sends the second channel data.

[0081] like Figure 5 As shown, an ADC controller and a DAC controller can be set in the electrical chip, wherein the ADC controller is connected to the optical chip via the ADC, and the DAC controller is connected to the optical chip via the DAC. The same optical chip can be connected to one DAC module or multiple DAC modules. The electrical chip can divide the data of the delay calibration sequence through the DAC module.

[0082] When the electrical chip converts the delay calibration sequence into the first channel data and the second channel data, it can be converted into a group of first channel data and a group of second channel data, and then the first channel data and the second channel data are sent to the optical chip through a DAC module connected to the optical chip; or the electrical chip can send the first channel data and the second channel data to the optical chip at the same time through multiple DAC modules connected to the optical chip to achieve backup sending of the delay calibration data; or the electrical chip can send the first channel data and the second channel data to the optical chip through multiple DAC modules connected to the optical chip in a preset order, respectively, to obtain the delay estimation sub-values ​​corresponding to the multiple DAC modules respectively; the sending method of the delay calibration sequence is not limited here.

[0083] Optionally, the electronic chip can convert the delay calibration sequence into a plurality of first channel data and a plurality of second channel data. The plurality of first channel data corresponds to a plurality of DAC modules one by one; the plurality of second channel data corresponds to a plurality of DAC modules one by one. The electronic chip can send the first channel data and the second channel data corresponding to each other through the plurality of DAC modules.

[0084] S204 , referring to the clock cycle of the DAC module, sending the first channel data to the optical chip when the rising edge is reached, and sending the second channel data to the optical chip when the falling edge is reached.

[0085] by Figure 6 For example, the optical chip can be connected to 25 DAC modules, namely DAC0 to DAC25, and each DAC module sends the corresponding first channel data and second channel data. The electrical chip can refer to the clock cycle of the reference DAC module and send the first channel data to the optical chip when the rising edge arrives, such as Figure 6 When the falling edge arrives, the second channel data is sent to the optical chip, such as Figure 6 Medium data b.

[0086] After the optical chip receives the above data a and data b through multiple DAC modules, it can multiply the data a and data b corresponding to each DAC module, and then add the data multiplication results corresponding to each DAC module to obtain the above delay calibration sequence.

[0087] In the above-mentioned delay estimation method, the electrical chip converts the delay calibration sequence into first channel data and second channel data, which can adapt to the data transmission requirements between the electrical chip and the optical chip, more accurately reflect the data processing delay of the optical chip, and thus improve the accuracy of the delay estimation value.

[0088] Figure 7FIG. 1 is a flow chart of a delay estimation method in an embodiment. This embodiment relates to a specific implementation of an electrical chip identification feature sequence. Based on the above embodiment, Figure 7 As shown, the above S104 includes:

[0089] S302: Sample the data sent by the optical chip to obtain an initial sampling sequence.

[0090] The electronic chip may sample the received data in real time to obtain an initial sampling sequence; or, it may sample using a preset initial delay estimate value to obtain an initial sampling sequence, which is not limited here.

[0091] S304, using multiple preset characteristic values ​​to match the data in the initial sampling sequence respectively; wherein the preset characteristic values ​​are values ​​in the reference characteristic sequence corresponding to the delay calibration sequence; the multiple preset characteristic values ​​are arranged in chronological order to characterize the change characteristics of the reference characteristic sequence.

[0092] The delay calibration sequence is input into the data processing model stored in the optical chip to obtain a reference feature sequence. The electrical chip can extract multiple preset feature values ​​from the reference feature sequence in chronological order. Among them, the multiple preset feature values ​​can be used to characterize the change characteristics of the reference feature sequence. The change characteristics are used for the electrical chip to quickly and accurately identify the feature sequence from the initial sampling sequence. When selecting the multiple preset feature values, the electrical chip can extract at the position where the change characteristics are more obvious in the reference feature sequence.

[0093] Optionally, when the delay calibration sequence is a triangular wave sequence, the reference characteristic sequence is waveform data including a peak; then the time series range of the multiple characteristic values ​​covers the peak of the waveform data.

[0094] like Figure 8 As shown, the reference characteristic sequence corresponding to the triangle wave sequence can be the waveform data containing the peak shown in the figure. When the electric chip selects multiple preset characteristic values, it can select the position covering the peak, such as the preset characteristic values ​​A1 to A5 in the figure, where A1 and A2 are located at the rising edge stage of the peak, A3 is located at the peak position, and A4 and A5 are located at the falling edge stage of the peak. The electric chip selects the above five preset characteristic values, which can make the data matching determine which data in the initial sampling sequence corresponds to the peak segment of the characteristic sequence, thereby improving the recognition accuracy of the characteristic sequence.

[0095] Furthermore, the electronic chip can perform data matching in the initial sampling sequence based on the above-mentioned multiple preset feature values. Specifically, the electronic chip can use a step-by-step approach to perform data matching, or a simple pattern matching algorithm. For example, the electronic chip first determines whether the first character in the initial sampling sequence is the same as the first preset feature value. If they are the same, a subsequent comparison is performed. If they are different, the second character is re-compared with the first preset feature value, and so on. The recognition method of the feature sequence is not limited here.

[0096] It should be noted that the feature sequence sent by the optical chip to the electrical chip may be the same as the reference feature sequence; or, due to the influence of data transmission accuracy, ADC sampling accuracy, data interference, etc., the feature sequence sent by the optical chip to the electrical chip may also be different from the reference feature sequence. Therefore, the electrical chip can use fuzzy matching to identify the feature sequence in the initial sampling sequence.

[0097] S306: In the reference feature sequence, if a plurality of preset feature values ​​correspond to a plurality of sampling values ​​in the initial sampling sequence in sequence, the sequence in which the plurality of sampling values ​​are located is determined as the feature sequence.

[0098] The above-mentioned sequential correspondence may mean that the difference between each preset characteristic value and the corresponding sampling value is less than a preset threshold, and the distance between two adjacent preset characteristic values ​​is the same as the distance between the corresponding sampling values.

[0099] When the multiple characteristic values ​​correspond to the multiple sampling values ​​in the initial sampling sequence in sequence, the electronic chip can determine the sequence where the multiple sampling values ​​are located as the characteristic sequence. Figure 8 As shown in the example, when A1 to A5 correspond to B1 to B5 in the initial sampling sequence in sequence, the difference between A1 and B1 is less than the preset threshold, the difference between A2 and B2 is less than the preset threshold, and so on. In addition, the interval between A1 and A2 is the same as the interval between B1 and B2, the interval between A2 and A3 is the same as the interval between B2 and B3, and so on. When there are B1 to B5 that meet the above requirements, the electronic chip can consider that the sequence of B1 to B5 is a feature sequence that matches the reference feature sequence.

[0100] In the initial sampling sequence obtained by the electrical chip, there may be one or more characteristic sequences matching the reference sequence. The above-mentioned multiple matching characteristic sequences may be multiple continuous sequences or non-continuous sequences, which is not limited here.

[0101] In the above-mentioned delay estimation method, the electronic chip adopts multiple preset characteristic values ​​that can represent the changing characteristics of the reference sequence, and performs data matching in the initial sampling sequence. The data matching can determine which data in the initial sampling sequence corresponds to the sequence with changing characteristics of the feature sequence, thereby improving the recognition accuracy of the feature sequence; further, by performing data matching through multiple preset characteristic values, the recognition efficiency of the feature sequence can be improved.

[0102] Fig. 9 FIG. 1 is a flow chart of a delay estimation method in an embodiment. This embodiment relates to a specific implementation method of determining a delay estimation value in an electrical chip. Based on the above embodiment, Fig. 9 As shown, the above S106 includes:

[0103] S402: Determine the time when the delay calibration sequence arrives at the DAC data path module as the sending time.

[0104] like Fig.10 As shown, in the DAC controller in the electrical chip, the electrical chip can be provided with a DAC data path module connected to the delay calibration sequence sending module and the service data sending module. Among them, the delay calibration sequence sending module can be used to generate a timing calibration sequence, and send the timing calibration sequence to the DAC module through the DAC data path module. The above-mentioned delay calibration sequence sending module can also be used to divide the delay calibration sequence into first path data and second path data, etc. The above-mentioned service data sending module is used to send service data to the optical chip.

[0105] In the DAC controller in the electronic chip, the electronic chip can be provided with an analog-to-digital conversion ADC data path module connected to the delay check module and the service data receiving module. The delay check module can be used to identify the characteristic sequence in the received data and determine the delay estimation value. The service data receiving module is used to sample and receive the service data.

[0106] Since the delay calibration sequence sending module and the business data sending module require different delays for data processing, in order to make the delay estimation value obtained by the delay calibration more suitable for business data sampling, the time when the delay calibration sequence arrives at the DAC data path module can be determined as the sending time, thereby eliminating the delay deviation between the business data and the delay calibration sequence and improving the accuracy of the delay estimation value.

[0107] S404: Determine the time when the characteristic sequence reaches the ADC data path module as the receiving time.

[0108] Furthermore, after identifying the characteristic sequence, the electronic chip can further obtain the time when the characteristic sequence arrives at the ADC data path module, and determine this moment as the reception moment of the characteristic sequence.

[0109] In one implementation, when multiple consecutive sequences are identified as feature sequences, a target sequence located in the middle of the multiple consecutive sequences is determined; then, the time when the target sequence reaches the ADC pathway module is determined as the receiving time.

[0110] By determining the time when the feature sequence arrives at the ADC data path module as the receiving time, the delay deviation after the feature sequence and business data enter the electronic chip can be eliminated, further improving the accuracy of the delay estimation value.

[0111] S406: Determine a delay estimation value based on the time difference between the sending time and the receiving time.

[0112] After determining the sending time of the delay calibration sequence and the receiving time of the characteristic sequence, the electrical chip can determine the delay estimation value based on the time difference between the sending time and the receiving time. Specifically, the electrical chip can directly determine the time difference as the delay estimation value, or perform weighted calculation on the time difference to obtain the delay estimation value, which is not limited here.

[0113] In the above delay estimation method, the electronic chip determines the time when the delay calibration sequence arrives at the DAC data path module as the sending time, and determines the time when the characteristic sequence arrives at the ADC data path module as the receiving time, thereby eliminating the delay deviation between the business data and the delay calibration sequence and improving the accuracy of the delay estimation value.

[0114] In one embodiment, based on the above embodiment, Fig.11 As shown, the delay calibration sending module in the electrical chip uses the DAC clock as a reference to generate multiple first data channels a and multiple second data channels b, and sends the delay calibration sequence to the optical chip through 25 DAC modules. When the delay calibration sequence reaches the DAC data path module, the delay calibration sending module can use the system clock of the electrical chip as a reference to generate a calibration request signal calib_chk, and the rising edge of the calibration request signal can be the sending time T1 of the delay calibration sequence. After receiving the delay calibration sequence, the optical chip processes the delay calibration sequence through a neural network model to obtain a feature sequence corresponding to the delay calibration sequence, and sends the feature sequence to the electrical chip through the ADC module.

[0115] The electrical chip can sample the data sent by the optical chip with the companion clock as a reference to obtain an initial sampling sequence. The electrical chip can split the initial sampling sequence to obtain two single-edge signals c and d, where c is the data sent on the rising edge and the other d is the data sent on the falling edge. Furthermore, the delay verification module can adopt a five-level verification mode to perform fuzzy matching in the initial sampling sequence to obtain sampling values ​​that match five preset characteristic values. The electrical chip determines the characteristic sequence in which the sampling value is located, and determines the time when the characteristic sequence arrives at the ADC data path module as the reception time T2 of the characteristic sequence. The delay verification module can determine the time difference between T1 and T2 as the delay estimate of the optical chip.

[0116] After determining the characteristic sequence, the electrical chip can generate a verification pass signal PASS with reference to the electrical chip system clock. The electrical chip can determine whether confirmation of the delay estimation value is completed according to the PASS signal.

[0117] In one embodiment, based on the above embodiment, the delay check module can store the delay estimation value in a data register. The stored delay estimation value can be sampled and stored in the data register to reduce the influence of the delay estimation value caused by data interference, equipment accuracy, etc., thereby improving the accuracy of the delay estimation value.

[0118] In one embodiment, based on the above embodiment, after the electrical chip receives a trigger instruction for updating the delay estimate value, the delay estimate value can be reacquired. The above trigger instruction may be related to the data application scenario of the optical chip. Among them, the above update trigger instruction may be an instruction input by the user, or an instruction triggered by the electrical chip through data monitoring, which is not limited here. The electrical chip stores the acquired delay estimate value in a register, and calls the value for data sampling when performing data joint calculation with the optical chip. Due to changes in the data application scenario, the delay estimate value stored in the register may not meet the data sampling requirements. The electrical chip can re-call the delay estimation method in the above embodiment to re-acquire the delay estimate value. Among them, the above data application scenario can be that the optical chip and the electrical chip perform data joint calculation under different temperature conditions, or that they perform data joint calculation under different neural network models or different versions of the same neural network model. The specific type of the above data application scenario is not limited here.

[0119] In the above delay estimation method, the electrical chip updates the delay estimation value according to the changes in the data application scenario, so that the delay estimation value can adapt to the data sampling requirements in different scenarios, further improving the joint computing efficiency between the electrical chip and the optical chip.

[0120] It should be understood that although Figure 2-9The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2-9 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0121] Fig.12 FIG. 4 is a structural block diagram of a delay estimation device according to an embodiment. Fig.12 As shown, the device is applied to an electrical chip connected to an optical chip, and includes:

[0122] A sending module 10, used for sending a delay calibration sequence to the optical chip;

[0123] The identification module 20 is used to identify a characteristic sequence matching the delay calibration sequence in the received data sent by the optical chip; wherein the characteristic sequence is obtained after the optical chip calls the data processing model and processes the delay calibration sequence;

[0124] The determination module 30 is used to determine the delay estimation value of the optical chip according to the sending time of the delay calibration sequence and the receiving time of the characteristic sequence.

[0125] In one embodiment, based on the above embodiment, Fig.13 As shown, the sending module 10 includes:

[0126] A conversion unit 101 is used to convert the delay calibration sequence into first channel data and second channel data; wherein the first channel data and the second channel data are sent through different time slots of the same cycle;

[0127] The sending unit 102 is used to refer to the clock cycle of the DAC module, send the first channel data to the optical chip when the rising edge is reached, and send the second channel data to the optical chip when the falling edge is reached.

[0128] In one embodiment, based on the above embodiment, the sending unit 102 is specifically used to: convert the delay calibration sequence into multiple first channel data and multiple second channel data; the multiple first channel data correspond one-to-one to the multiple DAC modules; the multiple second channel data correspond one-to-one to the multiple DAC modules.

[0129] In one embodiment, based on the above embodiment, Fig.14 As shown, the above identification module 20 includes:

[0130] The sampling unit 201 is used to sample the data sent by the optical chip to obtain an initial sampling sequence;

[0131] A matching unit 202 is used to use a plurality of preset characteristic values ​​to match the data in the initial sampling sequence respectively; wherein the preset characteristic values ​​are values ​​in a reference characteristic sequence corresponding to the delay calibration sequence; the plurality of preset characteristic values ​​are arranged in chronological order and are used to characterize the change characteristics of the reference characteristic sequence;

[0132] The determination unit 203 is configured to determine, in the reference feature sequence, if the plurality of preset feature values ​​correspond in sequence to the plurality of sampling values ​​in the initial sampling sequence, the sequence in which the plurality of sampling values ​​are located as the feature sequence.

[0133] In one embodiment, based on the above embodiment, the delay calibration sequence is a triangle wave sequence, the reference characteristic sequence is waveform data containing peaks; and the time series range of the multiple characteristic values ​​covers the peaks of the waveform data.

[0134] In one embodiment, based on the above embodiment, the electronic chip is provided with a DAC data path module connected to the delay calibration sequence sending module and the business data sending module, and an analog-to-digital conversion ADC data path module connected to the delay verification module and the business data receiving module; the determination module 30 is specifically used to: determine the time when the delay calibration sequence reaches the DAC data path module as the sending time; determine the time when the characteristic sequence reaches the ADC data path module as the receiving time; and determine the delay estimation value based on the time difference between the sending time and the receiving time.

[0135] In one embodiment, based on the above embodiment, the determination module 30 is specifically used to: when multiple consecutive sequences are identified as the characteristic sequences, determine a target sequence located in the middle of the multiple consecutive sequences; and determine the time when the target sequence arrives at the ADC pathway module as the receiving time.

[0136] The implementation principle and technical effects of the above-mentioned delay estimation device refer to the above-mentioned method embodiment, which will not be described in detail here.

[0137] The division of the various modules in the above-mentioned time delay estimation device is only for illustration. In other embodiments, the time delay estimation device may be divided into different modules as needed to complete all or part of the functions of the above-mentioned time delay estimation device.

[0138] For the specific definition of the delay estimation device, please refer to the definition of the delay estimation method above, which will not be repeated here. Each module in the above-mentioned delay estimation device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0139] Fig.15 Schematic diagram of the internal structure of a data processing device in an embodiment. The device includes a processor and a memory connected by a system bus. Among them, the processor may be a CPU (Central Processing Unit) or a DSP (Digital Signal Processing, digital signal processor) and the like. The memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The computer program can be executed by the processor to implement a delay estimation method provided in each of the following embodiments. The internal memory provides a cache operating environment for the operating system computer program in the non-volatile storage medium. It can be understood by those skilled in the art that the structure shown in the figure is only a block diagram of a partial structure related to the present application scheme, and does not constitute a limitation on the server to which the present application scheme is applied. The specific server may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0140] The implementation of each module in the delay estimation device provided in the embodiment of the present application may be in the form of a computer program. The computer program may be run on a terminal or a server. The program module constituted by the computer program may be stored in a memory of an electronic device. When the computer program is executed by a processor, the steps of the method described in the embodiment of the present application are implemented.

[0141] The embodiment of the present application further provides a computer-readable storage medium, one or more non-volatile computer-readable storage media containing computer-executable instructions, when the computer-executable instructions are executed by one or more processors, the processors execute the steps of the delay estimation method.

[0142] An embodiment of the present application also provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute a delay estimation method.

[0143] Any reference to memory, storage, database or other medium used in this application may include non-volatile and / or volatile memory. Non-volatile memory may include ROM (Read-Only Memory), PROM (Programmable Read-only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-only Memory) or flash memory. Volatile memory may include RAM (Random Access Memory), which is used as an external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), Double Data Rate DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access memory), ESDRAM (Enhanced Synchronous Dynamic Random Access memory), SLDRAM (Sync Link Dynamic Random Access Memory), RDRAM (Rambus Dynamic Random Access Memory), and DRDRAM (Direct Rambus Dynamic Random Access Memory).

[0144] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A delay estimation method, applied to an electrical chip connected to an optical chip, characterized in that: The method comprises: Sending a delay calibration sequence to the optical chip; In the received data sent by the optical chip, a feature sequence matching the delay calibration sequence is identified; wherein the feature sequence is obtained after the optical chip calls a data processing model and processes the delay calibration sequence; The delay estimation value of the optical chip is determined according to the sending time of the delay calibration sequence and the receiving time of the characteristic sequence.

2. The method according to claim 1, characterized in that The electrical chip is connected to the optical chip via a digital-to-analog converter DAC module, and the delay calibration sequence is sent to the optical chip, including: Converting the delay calibration sequence into first channel data and second channel data; wherein the first channel data and the second channel data are sent through different time slots of the same cycle; With reference to the clock cycle of the DAC module, the first channel data is sent to the optical chip when the rising edge is reached, and the second channel data is sent to the optical chip when the falling edge is reached.

3. The method according to claim 2, characterized in that The electrical chip is connected to the optical chip through a plurality of DAC modules, and the step of converting the delay calibration sequence into first channel data and second channel data includes: The delay calibration sequence is converted into a plurality of first channel data and a plurality of second channel data; the plurality of first channel data corresponds one-to-one to the plurality of DAC modules; and the plurality of second channel data corresponds one-to-one to the plurality of DAC modules.

4. The method according to any one of claims 1 to 3, characterized in that: The step of identifying, in the received data sent by the optical chip, a characteristic sequence matching the delay calibration sequence comprises: Sampling the data sent by the optical chip to obtain an initial sampling sequence; Using multiple preset characteristic values ​​to match the data in the initial sampling sequence respectively; wherein the preset characteristic values ​​are values ​​in the reference characteristic sequence corresponding to the delay calibration sequence; the multiple preset characteristic values ​​are arranged in chronological order and are used to characterize the change characteristics of the reference characteristic sequence; In the reference feature sequence, if the plurality of preset feature values ​​correspond to the plurality of sampling values ​​in the initial sampling sequence in sequence, the sequence in which the plurality of sampling values ​​are located is determined as the feature sequence.

5. The method according to claim 4, characterized in that The delay calibration sequence is a triangle wave sequence, the reference characteristic sequence is waveform data containing peaks, and the time series range of the multiple characteristic values ​​covers the peaks of the waveform data.

6. The method according to any one of claims 1 to 3, characterized in that: The electronic chip is provided with a DAC data path module connected to the delay calibration sequence sending module and the service data sending module, and an analog-to-digital conversion ADC data path module connected to the delay verification module and the service data receiving module; The step of determining the estimated delay value of the optical chip according to the sending time of the delay calibration sequence and the receiving time of the characteristic sequence includes: Determine the time when the delay calibration sequence arrives at the DAC data path module as the sending time; Determine the time when the characteristic sequence reaches the ADC data path module as the receiving time; The delay estimation value is determined based on the time difference between the sending time and the receiving time.

7. The method according to claim 6, characterized in that The step of determining the time when the characteristic sequence reaches the ADC data path module as the receiving time comprises: When a plurality of continuous sequences are identified as the characteristic sequences, determining a target sequence located in the middle of the plurality of continuous sequences; The time when the target sequence arrives at the ADC pathway module is determined as the receiving time.

8. A delay estimation device, applied to an electrical chip connected to an optical chip, characterized in that: The device comprises: A sending module, used for sending a delay calibration sequence to the optical chip; An identification module is used to identify a characteristic sequence matching the delay calibration sequence in the received data sent by the optical chip; wherein the characteristic sequence is obtained after the optical chip calls the data processing model and processes the delay calibration sequence; A determination module is used to determine the delay estimation value of the optical chip according to the sending time of the delay calibration sequence and the receiving time of the characteristic sequence.

9. A data processing device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the computer program is executed by the processor, the processor is caused to perform the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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