Ultra-low delay universal simplex transmission method and system based on 8b / 10b coding

Abstract

The invention discloses an ultra-low time delay universal simplex transmission method and system based on 8b / 10b coding, and adopts a Buffer-free all-slave synchronous TX sending architecture to synchronously send and eliminate sending data skew between Lanes so as to realize multi-Lane minimum time data sending. A communication protocol realizes receiving byte boundary alignment through common, a sending end sends the same sequence with a certain length after each piece of common data of Lane, the same sequence is used as a bond sequence byte sequence for a receiving end, and Lane alignment and protocol analysis 4-byte boundary positioning are realized. Through the intelligent design of the channel-bonding configuration and the alignment sequence of the receiving end, the data transmission efficiency can be improved, a bond sequence or a control code is modified to flexibly regulate and control the protocol analysis byte output sequence, and the adaptive capacity of the system to different transmission requirements is improved while the transmitting and receiving delay is shortened to the maximum extent.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to an ultra-low-latency universal simplex transmission method and system based on 8b / 10b encoding. Background Art

[0002] FPGA low-latency high-speed transmission is generally based on aurora protocol IP improvements and custom high-speed transmission. Aurora protocol improvements optimize fifo size and cross-clock domain response, compressing data transmission time. Custom high-speed transmission is used to streamline transmission protocols and shorten transmission time, using transceiver buffers across clocks.

[0003] The application of fifo\buffer increases the transmission delay and the uncertainty of delay. In addition to the necessary functional overhead such as the necessary alignment between lanes and the byte order arrangement within the lane, the transmission delay of transmission and reception can generally only be shortened to the range of 200-300ns at 10Gbps (gigabits per second). The transmission delay of different power-on times and multiple link establishments fluctuates randomly in this range. If the addition and subtraction function is enabled to reduce the bit error rate, the transmission delay will be further increased. Figure 1 This is a flow chart of the test method for high-speed transmission delay in the prior art: the FPGA on the left is a high-speed transmitter, and the FPGA on the right is a high-speed receiver. When the transmitter FPGA sends the frame header of the transmission message, it synchronously sends the frame header pulse or message level signal to the receiving FPGA through the LVDS interface. The receiving FPGA can obtain the transmission delay of high-speed transmission and reception by comparing the timing relationship between the received high-speed message and the frame header pulse / message level. In applications where delay optimization is not performed, the transmission delay is usually 500ns to 700ns.

[0004] In the prior art, FPGA widely uses high-speed transmission interfaces. This type of interface has the advantage of large transmission bandwidth, but generally has a large transmission delay. How to overcome the disadvantage of large delay and make FPGA high-speed transmission have a wide range of application scenarios in situations with strong real-time control and requirements of fast timing response speed has become one of the research directions of technical personnel in this field. Summary of the invention

[0005] The purpose of this application is to provide an ultra-low latency universal simplex transmission method and system based on 8b / 10b encoding in order to overcome the existing technical defects. The sending end has no buffer and is driven synchronously. The channel-bonding configuration of the receiving end and the intelligent design of the alignment sequence can improve the data transmission efficiency. The bond sequence or control code can be modified to flexibly adjust the internal byte order of the Lane, shorten the sending and receiving delay, and improve the system's adaptability to different transmission requirements.

[0006] The purpose of this application is achieved through the following technical solutions:

[0007] In a first aspect, the present application proposes an ultra-low latency universal simplex transmission method based on 8b / 10b coding, the method being applied to an ultra-low latency universal simplex transmission system, the system comprising a controlled slave aligned receiving end and a transmitting end adopting a bufferless TX slave synchronous transmission architecture, the method comprising:

[0008] The transmitter uses the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels;

[0009] The transmitter configures all lanes to the slave synchronization mode without buffer. After power-on reset, the state machine is used to manually control the delay, phase initialization, and transmission phase alignment mechanism inside the channel lane to eliminate the skew between the transmitted data lanes. The transmitted data contains a continuous comma sequence, which is used by the receiver to determine the receiving byte boundary. After sending the data comma sequence, each lane sends the same byte or byte sequence for lane alignment.

[0010] The receiving end is reset based on receiving continuous comma sequences on the Lane channel, and returns to the initial state when a non-comma sequence is received after the reset;

[0011] The receiving end sets all lane channels as slave lanes in chanel-bond mode and selects the same 4-byte string after the continuous comma sequence as the bond sequence alignment identification sequence;

[0012] When the receiving end detects that the commadet control signal changes from high level to low level, it sends a control sequence to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the sending end;

[0013] The receiving end reselects the bond sequence or modifies the bondi control sequence code to control the order of the parallel output bytes within the Lane.

[0014] In a possible embodiment, the receiving end receives a continuous comma sequence based on a Lane channel to reset, and the step of returning to an initial state when a non-comma sequence is received after the reset includes:

[0015] The receiving end receives the continuous comma sequence and starts the reset state machine to count and obtain the comma sequence count value;

[0016] When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state;

[0017] When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

[0018] In a possible embodiment, the steps after the receiving state machine is reset and enters the reset state include:

[0019] The self-state machine using flexible buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all Lanes in the receiving channel become high.

[0020] In a possible embodiment, the clock management component adopts MMCM, PLL or BUFG.

[0021] In the first aspect, the present application also proposes an ultra-low latency universal simplex transmission system based on 8b / 10b coding, the system comprising a controlled slave aligned receiving end and a transmitting end adopting a bufferless TX slave synchronous transmission architecture, the method comprising:

[0022] The transmitting end is used to use the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels;

[0023] All Lanes are configured as slave synchronization mode without buffer. After power-on reset, the state machine is used to manually control the delay, phase initialization, and transmission phase alignment mechanism inside the channel Lane to eliminate the skew between the transmitted data Lanes. The transmitted data contains a continuous comma sequence, which is used by the receiving end to determine the received byte boundary. After each Lane sends the data comma sequence, it sends the same byte or byte sequence for Lane alignment.

[0024] The receiving end is used to reset based on the continuous comma sequence received by the Lane channel, and return to the initial state when a non-comma sequence is received after the reset;

[0025] Set all Lane channels as slave Lanes in chanel-bond mode, and select the same 4-byte string after the continuous comma sequence as the bond sequence alignment recognition sequence;

[0026] When the commadet control signal is detected to be converted from high level to low level, a control sequence is sent to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the transmitting end;

[0027] Reselect the bond sequence or modify the bondi control sequence code to control the order of the parallel output bytes within the Lane.

[0028] In a possible embodiment, the receiving end is further used to: receive a continuous comma sequence through the receiving end, start a reset state machine to count and obtain a comma sequence count value;

[0029] When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state;

[0030] When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

[0031] In a possible embodiment, the receiving end is further configured to:

[0032] The self-state machine of the flexible buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all Lanes in the receiving channel become high.

[0033] In a possible embodiment, the clock management component adopts MMCM, PLL or BUFG.

[0034] The above-mentioned main scheme of the present application and its further options can be freely combined to form multiple schemes, all of which are schemes that can be adopted and claimed for protection in the present application; and in the present application, (non-conflicting options) options and other options can also be freely combined. After understanding the scheme of the present application, those skilled in the art can understand that there are multiple combinations based on the prior art and common knowledge, all of which are technical schemes to be protected by the present application, and they are not exhaustively listed here.

[0035] The present application discloses an ultra-low latency universal simplex transmission method and system based on 8b / 10b encoding. The transmitting end adopts a bufferless TX slave synchronous transmission architecture and uses a clock management component to convert an external input reference clock into a user clock TXUSERCLK2 to drive all transmission Lane channels. The receiving end receives a continuous comma sequence for reset, and returns to the initial state when a non-comma sequence is received. The receiving end sets all Lane channels as chanel-bond slave Lanes, and sets comma and subsequent bytes of the comma sequence, or subsequent strings of the comma sequence to bond sequence sequences. When a comma control signal is detected to be converted from high to low, a control sequence is sent to the bondi control sequence code so that the transmission data of all Lanes are arranged and aligned for output according to the byte order of the transmitting end, and the bond sequence sequence is reselected or the bondi control sequence code is modified to control the arrangement of the byte order inside the Lane. The intelligent design of the bufferless output of the transmitting end and the alignment sequence can shorten the delay of data transmission, reception, and transmission, and the bond sequence sequence or control code can be modified to flexibly adjust the internal byte order of the Lane, thereby improving the flexibility of the system in protocol parsing. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 It is a flow chart of a method for testing high-speed transmission delay in the prior art.

[0038] Figure 2 A schematic diagram of an ultra-low latency universal simplex transmission system proposed in an embodiment of the present application is shown.

[0039] Figure 3 A flow chart of an ultra-low-latency universal simplex transmission method based on 8b / 10b encoding proposed in an embodiment of the present application is shown.

[0040] Figure 4 A schematic diagram of a fully slave synchronous transmission Lane clock architecture and a traditional transmission synchronous Lane architecture is shown.

[0041] Figure 5 The control timing diagram of sending all slave Lanes proposed in the embodiment of the present application is shown.

[0042] Figure 6The figure shows the adaptive RX end reset flow chart proposed in the embodiment of the present application.

[0043] Figure 7 A schematic diagram of the bond sequence change arrangement proposed in an embodiment of the present application is shown.

[0044] Figure 8 A schematic diagram of the byte order fine-tuning delay proposed in an embodiment of the present application is shown.

[0045] Fig. 9 A schematic diagram of 8Lane JESD204B data channel initialization alignment sequence ILAS data received by the ultra-low latency universal simplex transmission method of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0047] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0048] In the prior art, FPGA widely uses high-speed transmission interfaces. This type of interface has the advantage of large transmission bandwidth, but generally has a large transmission delay. How to overcome the disadvantage of large delay and make FPGA high-speed transmission have a wide range of application scenarios in situations with strong real-time control and requirements of fast timing response speed has become one of the research directions of technical personnel in this field.

[0049] Therefore, in order to solve the above-mentioned technical problems, the embodiment of the present application proposes an ultra-low latency general simplex transmission method and system based on 8b / 10b encoding, which can shorten the total latency of high-speed transmission and reception to about 100ns under 10Gbps conditions, and the latency jitter does not exceed 1 internal logic clock cycle. At the same time, it enables FPGA high-speed transmission to be applied to long-distance and strong real-time response scenarios, which will be described in detail below.

[0050] Please refer to Figure 2 , Figure 2A schematic diagram of an ultra-low latency universal simplex transmission system proposed in an embodiment of the present application is shown, which is divided into a TX transmitting end and an RX receiving end, both of which process and send data through an FPGA (field programmable gate array), and then the data is received through real-time control instructions via digital optical transmission, and is applied in a high-speed instruction execution mechanism with fast response requirements, and is used in a control environment with high precision and high speed requirements.

[0051] Figure 3 A flow chart of an ultra-low-latency universal simplex transmission method based on 8b / 10b encoding proposed in an embodiment of the present application is shown. The method is applied to the above-mentioned ultra-low-latency universal simplex transmission system. The method includes the following steps:

[0052] Step S100: The transmitting end uses the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels.

[0053] The principle of TXUSERCLK2 generation is to use the reference clock as a reference to accurately generate a clock signal with a frequency of 1 / 40 of the high-speed transmission baud rate, which is driven by BUFG to become the TXUSERCLK2 of all transmission lanes.

[0054] If the frequency is appropriate, that is, the input clock has met the clock frequency requirement of 1 / 40 of the high-speed transmission baud rate required by the internal Lane of the system, then BUFG (Buffered Global Clock) can be used directly to drive the clock network.

[0055] Step S200, the transmitting end configures all Lanes to a slave synchronization mode without a buffer. After power-on reset, the state machine is used to manually control the delay, phase initialization, and transmission phase alignment mechanism inside the channel Lane to eliminate the skew between the transmitted data Lanes. The transmitted data contains a continuous comma sequence, which is used by the receiving end to determine the received byte boundary. After each Lane sends the data comma sequence, it sends the same byte or byte sequence for Lane alignment.

[0056] Configure Lane to non-buffered slave synchronization mode. On the sending end of the system, the data channel (Lane) is set to a mode in which there is no additional data buffering and follows a master clock source to synchronize data transmission, which helps reduce latency and ensures instant data transmission.

[0057] Manual control with state machine after power-on reset: After the system is powered on and goes through the reset phase, a state machine logic is used to finely control the internal operations of each lane. A state machine is a digital logic circuit that can switch between different states based on input signals, and is used to implement complex and orderly initialization processes.

[0058] The delay and phase initialization within the channel Lane adjusts the signal path delay and phase of each Lane to ensure that the signals of all Lanes are accurately aligned in time. Avoid data skew (differences in data arrival time). The sending phase alignment mechanism is used to further fine-tune the phase of the sending signal to ensure that all Lane data packets can be correctly converged at the receiving end, eliminate the skew between the sending data Lanes, eliminate the differences in data packet arrival time caused by differences in physical path lengths between different Lanes, and ensure synchronous data transmission.

[0059] Comma sequence is a special character or bit sequence that is inserted into the data stream as a reference point for the receiver to identify the packet boundary and perform synchronization, helping the receiver to accurately determine the starting position of each packet. Lane sends the same byte or byte sequence after sending the data comma sequence, allowing the receiver to compare the reception of each lane based on these known identical data and further refine the alignment between lanes.

[0060] The transmitter configures all transmission lanes as a non-buffered slave synchronous TX transmission architecture, which saves buffer cache write and read latency, and avoids the transmission delay jitter problem caused by the randomness of the read and write address difference. The TX transmission architecture can perform synchronous transmission to eliminate the transmission skew between lanes, and also prevent the slow transmission lane from affecting the overall transmission delay.

[0061] After power-on, the state machine manually controls Lane synchronization, drives the internal delay, initialization, and alignment timing of Lane to achieve precise synchronization between TXUSERCLK2 and the high-speed clock PHYCLK, eliminates the transmission skew between Lanes, and cancels the clock compensation code to achieve full-bandwidth data transmission.

[0062] The high-speed clock PHYCLK of each Lane is precisely synchronized with TXUSERCLK2 to ensure that data is sent simultaneously on each Lane.

[0063] The timing drive of sending all slave synchronization generates a common and reliable clock signal TXUSERCLK2 for all sending lanes, thereby achieving precise synchronous transmission between lanes and even between interfaces. It is one of the key technologies to ensure data accuracy and efficiency in high-speed data transmission systems.

[0064] An externally provided clock source is used as the reference for all internal clock signals. The external reference clock is fed into the MMCM or PLL. Using a fully synchronous transmission lane synchronization scheme, in a high-speed serial communication system, all data transmission channels (Lane) are synchronized and controlled using a unified clock signal, ensuring that data packets on all Lanes are sent simultaneously, reducing timing deviation (skew), and improving signal integrity and overall system performance.

[0065] Please refer to the comparison of the all-slave transmission Lane synchronization clock architecture of this application with the traditional transmission Lane synchronization architecture. Figure 4 , Figure 4 A schematic diagram of the all-slave transmission Lane synchronous clock architecture and the traditional transmission Lane synchronous architecture is shown. The left side is the traditional transmission Lane synchronous architecture, which cannot achieve cross-interface synchronous transmission. The right side is the all-slave transmission Lane synchronous clock architecture, which can achieve full-chip cross-interface transmission synchronization.

[0066] XINLINX recommends a master-slave synchronization solution for multi-Lane transmission synchronization. Take 4Lane as an example. The 4Lane on the left is divided into one master and three slaves. The TXOUTCLK2 of the master Lane is driven by MMCM / PLL, and then drives the user clock TXUSERCLK of all its own Lanes. The 4Lane on the right is divided into all slaves. The TXOUTCLK of all Lanes is driven by MMCM / PLL, and then drives the user clock TXUSERCLK of all Lanes.

[0067] Please refer to Figure 5 , Figure 5 The control timing diagram of sending all slave lanes proposed in the embodiment of the present application is shown. After each lane is powered on, the TXDLYSRESET, TXPHINIT and TXPHAIGN processes need to be executed in sequence. The advantage of using all slave lanes for synchronous transmission is that the control timing gets rid of the constraint on the number of slave lanes caused by the dynamic adjustment of the master lane output clock delay, and is more suitable for large-scale, cross-interface synchronous transmission. In a high-speed digital signal transmission system, in order to ensure that the signals of all data channels (Lane) can arrive at the receiving end accurately and synchronously, all slave lane control timing is performed. TXDLYSRESET, TXPHINIT and TXPHAIGN are used to calibrate the signal delay and phase of each Lane to achieve low-latency synchronous transmission of data.

[0068] TXDLYSRESET (Delay Reset) is used to reset the delay calibration logic on the Lane. Executed after power-on or system reset, it clears any delay settings that may have existed before and prepares for the next precise delay adjustment.

[0069] The TXPHINIT (Phase Initialization) command starts a process to determine and set the initial phase of each Lane. Phase alignment is critical for high-speed serial data transmission because even a small phase deviation can cause data errors.

[0070] TXPHAIGN (phase fine tuning or eye diagram optimization) fine-tunes the serial bit phase after completing the preliminary phase alignment in order to send precise synchronization.

[0071] Step S300: The receiving end performs a reset based on receiving a continuous comma sequence on the Lane channel, and returns to an initial state when a non-comma sequence is received after the reset.

[0072] After the receiving end performs the reset operation, in order to ensure that the system is ready to receive data and eliminate the abnormal state of the buffer, when the first non-comma (K28.5) signal is received, it means that data transmission has officially started. The receiving end needs to perform steps to return to the initial working state so that it can automatically reset again when the next comma continuous sequence is received.

[0073] Step S300 includes:

[0074] The receiving end receives the continuous comma sequence and starts the reset state machine to count and obtain the comma sequence count value;

[0075] When the comma sequence count value reaches a preset threshold, the receiving state machine triggers a reset and enters a reset state;

[0076] When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

[0077] The reset mechanism uses a specific control character (comma character K28.5) to trigger the receiver's state reset process, thereby optimizing the receiving performance.

[0078] Since the simplex receiver may not be able to reach the optimal working state immediately when powered on or reset at high speed, the initial received data has a high bit error rate. First, receive the comma count: the receiver monitors the input data stream, and when a continuous comma sequence (K28.5) is detected, a state machine is activated to count. When the number of comma occurrences reaches the preset threshold, it indicates that the receiver may have stably identified the data stream, and a reset operation is triggered at this time. Reset can recalibrate the timing and phase of the receiver to prepare for data reception. After reset, the system will remain in the reset state for a period of time to ensure that all internal states are fully refreshed, and then gradually resume normal operation mode. Once non-comma data is received, it indicates that normal data transmission has begun, and the reset state machine returns to the initial state to prepare for actual data transmission.

[0079] The transmitter (TX) can proactively guide the receiver (RX) to reset by sending a string of comma characters in advance. This approach is particularly effective for system initialization or fault recovery.

[0080] The comma count is not reset continuously to ensure that the occasional comma characters in the normal communication process will not trigger a reset. This ensures the compatibility of the protocol and the continuity of the data and avoids unnecessary interference.

[0081] The advantage of this method is that it can be dynamically adjusted based on the characteristics of the actual data stream, ensuring that the receiver can quickly self-adjust to the optimal working state when encountering unfavorable initial conditions or link changes, thereby effectively reducing the bit error rate and improving the reliability and efficiency of communications.

[0082] Figure 6 The adaptive RX reset flow chart proposed in the embodiment of the present application is shown. First, power on and initialize RX to enter the initial state). The system asks whether the specific character comma is detected. If not detected, the comma count is cleared. If detected, the number of occurrences of the comma character is checked. If it is the first time, the counter is set to 0. When the count value is not enough to reset, the count continues. When the threshold is met, the RX will be reset or initialized, and wait for the completion of resetdone. After that, it is determined whether non-comma data is received. If not, continue to wait. If received, the state machine is reset and returns to the initial state.

[0083] In a possible implementation, the steps after the receiving state machine is reset and enters the reset state include:

[0084] The self-state machine using flexible buffer coarse alignment sends a reset pulse to RXBUFRESE when it detects that the resetdone signals of all Lanes in the receiving channel become high.

[0085] In the reset process described above, a self-state machine for coarse alignment of flexible buffers is run while waiting for resetdone. After detecting that resetdone of all Lanes in the receiving channel is pulled high for a period of time, a reset pulse is uniformly given to the RXBUFRESET signal to ensure that the delay characteristics of each buffer are basically consistent.

[0086] Since the original function of chanel-bond is to use a specific string (up to 4 bytes) to synchronize the output character order of the slave Lane and the main Lane, but it cannot realize the function of arranging the byte order within the Lane in the order of origin, the subsequent steps are performed to realize the alignment between Lanes and the byte order arrangement within the Lane based on chanel-bond.

[0087] First, when there is no actual data transmission, the sender sends a continuous comma sequence, which enables the receiver to identify and prepare to receive the upcoming data frame. When data transmission starts, each Lane first sends a frame header containing at least 4 bytes (8 bytes or more are recommended), which serves as a synchronization mark. The frame header is followed by the actual data payload to be transmitted.

[0088] Step S400: The receiving end sets all Lane channels as slave Lanes in the chanel-bond mode, and selects the same 4-byte string after the continuous comma sequence as the bond sequence alignment identification sequence.

[0089] Configure the receiving end: All receiving lanes in the interface are configured as chanel-bond slave lanes and set the same alignment sequence (bond sequence), which is taken from a part of the frame header of the transmitting end. When a valid transition from comma to data is detected (the comma signal changes from high to low), the receiving end starts a counting process.

[0090] Step S500: When the receiving end detects that the commandeer control signal is converted from a high level to a low level, the receiving end sends a control sequence to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the transmitting end.

[0091] After that, byte alignment is performed. By sending a specific control sequence to bondi (the interface for controlling Lane) after a specific clock cycle, the data of all Lanes can be aligned and output according to the byte order of the sender. The control sequence (5-bit data "10000", "00000", "00000", "00000", "01110") is used to adjust the synchronization state. This process is completed after about 6 cycles, and then the data will be output in the extended order of the alignment sequence.

[0092] Step S600: The receiving end reselects the bond sequence or modifies the bondi control sequence code to control the arrangement of the parallel output byte order within the Lane.

[0093] By modifying the bond sequence or control sequence, the byte output order of the receiving end can be adjusted to achieve byte alignment under different requirements. The precise timing control triggered by the command signal and the selection of the bond sequence can be used to fine-tune the output delay to ensure accurate data synchronization. Figure 7 A schematic diagram of the bond sequence change order proposed in an embodiment of the present application is shown. In the figure, the alignment sequence d2-d5 is offset by 2 bytes relative to the TX end. After the alignment process is performed on the RX end, the final byte output order is offset by 2 bytes.

[0094] In a possible implementation, the method further includes:

[0095] The transmitter uses the command control signal to trigger the bond control code sequence and selects the bond sequence to adjust the output delay of the receiver.

[0096] Use command to trigger the bond control timing, and select the bond sequence to fine-tune the RX output delay. Figure 8 A schematic diagram of the byte order fine-tuning delay proposed in an embodiment of the present application is shown, where the bond sequence of RX is one user clock later than that of RX1, and the sequence of the final aligned output is one clock earlier than that of RX1. If the bond sequence is offset relative to the position of the data at the transmitting end (such as 2 bytes), then after the alignment process, the output sequence of the receiving end will also reflect this offset, that is, the final output will be offset by 2 bytes compared to the original transmission. The bond sequence control at the RX end starts one user clock later than RX1 (assuming it is the reference Lane), but after alignment, its output can be aligned one clock cycle earlier, reflecting the fine-tuning ability of this mechanism.

[0097] In addition, a single Lane is used for bond to achieve low-latency byte-sequenced output.

[0098] Fig. 9 A schematic diagram of the JESD204B data channel initialization alignment sequence ILAS data of 8 Lanes received by the ultra-low latency universal simplex transmission method of an embodiment of the present application is shown, the bond sequence is "KKKR" (K is comma, output X"bc", R multi-frame alignment K code, output X"1c"), and the transmission of "10000", "00000", "00000", "00000", and "01110" after the bond control sequence is earlier than the moment when any channel outputs "R". After 6 cycles, the padding code X"14131211" in ILAS is synchronously output, and the outputs of different AD channels are also aligned.

[0099] If the JESD204B interface is to achieve the stable low-latency performance of this patent, it is necessary to remove the addition and subtraction and frame and multi-frame alignment online inspection functions. Under this condition, some additional means are needed to maintain the long-term stability of the link. Because 64b / 66b, 64b / 67b, and 128b / 130b encoding must use addition and subtraction during transmission and lanes cannot be hard aligned, only the adaptive reset and buffer coarse alignment methods in this patent are effective, and cannot significantly shorten the propagation delay.

[0100] In a possible implementation, the ultra-low-latency universal simplex transmission method proposed in this application is applied to hundreds of optical fibers in a certain subject for high-speed data transmission (X4 mode), and the sending and receiving delay is controlled within 24 to 25 processing clocks, while the traditional aurora protocol generally has a random delay within 70 to 100 processing clocks. In comparison, the ultra-low-latency universal simplex transmission method proposed in this application has greatly improved the real-time and stability of the timing.

[0101] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0102] Custom control protocol and standard protocol application: It is compatible with custom control protocols, which means it has high flexibility and can customize data transmission methods according to specific needs. At the same time, it is also suitable for widely used standard protocols such as JESD204B and Gigabit Ethernet. JESD204B is a high-performance serial interface standard commonly used for communication between high-speed data converters and logic devices, while Gigabit Ethernet is a high-speed transmission protocol commonly used in network communications. Both require efficient and accurate data transmission mechanisms.

[0103] Multi-Lane Data Transmission and Test Methodology: In a multi-Lane configuration, data is split and transmitted in parallel through multiple channels to increase the total bandwidth. High-speed optical interfaces and LVDS (low voltage differential signaling) electrical interfaces are used, which helps to evaluate the performance on different physical layers. The shortest measured transmit and receive delay is 24 USERCLK2 cycles, which means the time base required for data to be sent and received. USERCLK usually refers to the user clock frequency, which is the basis for data transmission synchronization.

[0104] Byte order and delay jitter issues: When the transmit and receive delay is set to 24 clock cycles, there is about a 10% probability of byte order errors and delay jitter. This indicates that under this configuration, the system may occasionally fail to accurately reconstruct the original data sequence, or the delay fluctuates between different data packets. The problem disappears when the delay is relaxed to 25 clock cycles, indicating that the system needs additional time to stabilize data processing and ensure data integrity and timing accuracy.

[0105] Relationship between clock frequency and transmission rate: When the high-speed transmission rate is 10Gbps and the user clock frequency is 250MHz, the transmission and reception delay is stable at 100ns. Reducing the delay requires increasing the user clock frequency, which is directly related to increasing the transmission rate. This is because a higher clock frequency can process data faster, thereby reducing the waiting time of data in the system and thus reducing the delay.

[0106] This application takes into account the common challenges in high-speed data transmission, and achieves support for multiple protocols and performance improvement by adjusting latency and optimizing clock frequency.

[0107] A possible implementation of an ultra-low-latency universal simplex transmission system is provided below, which is used to execute the various execution steps and corresponding technical effects of the ultra-low-latency universal simplex transmission method shown in the above embodiments and possible implementations. The system includes a controlled slave aligned receiving end and a transmitting end using a bufferless TX slave synchronous transmission architecture. The method includes:

[0108] The transmitting end is used to use the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels;

[0109] All Lanes are configured as slave synchronization mode without buffer. After power-on reset, the state machine is used to manually control the delay, phase initialization, and transmission phase alignment mechanism inside the channel Lane to eliminate the skew between the transmitted data Lanes. The transmitted data contains a continuous comma sequence, which is used by the receiving end to determine the received byte boundary. After each Lane sends the data comma sequence, it sends the same byte or byte sequence for Lane alignment.

[0110] The receiving end is used to reset based on the continuous comma sequence received by the Lane channel, and return to the initial state when a non-comma sequence is received after the reset;

[0111] Set all Lane channels as slave Lanes in chanel-bond mode, and select the same 4-byte string after the continuous comma sequence as the bond sequence alignment recognition sequence;

[0112] When the commadet control signal is detected to be converted from high level to low level, a control sequence is sent to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the transmitting end;

[0113] Reselect the bond sequence or modify the bondi control sequence code to control the order of the parallel output bytes within the Lane.

[0114] In a possible embodiment, the receiving end is further used to: receive a continuous comma sequence through the receiving end, start a reset state machine to count and obtain a comma sequence count value;

[0115] When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state;

[0116] When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

[0117] In a possible embodiment, the receiving end is further configured to:

[0118] The self-state machine of the flexible buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all Lanes in the receiving channel become high.

[0119] In a possible embodiment, the clock management component adopts MMCM, PLL or BUFG.

[0120] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An ultra-low-latency universal simplex transmission method based on 8b / 10b coding, characterized in that: The method is applied to an ultra-low-latency universal simplex transmission system, the system comprising a controlled slave-aligned receiving end and a transmitting end adopting a bufferless TX slave synchronous transmission architecture, and the method comprises: The transmitter uses the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels; The transmitter configures all lanes to the slave synchronization mode without buffer. After power-on reset, the state machine is used to manually control the delay, phase initialization, and transmission phase alignment mechanism inside the channel lane to eliminate the skew between the transmitted data lanes. The transmitted data contains a continuous comma sequence, which is used by the receiver to determine the receiving byte boundary. After sending the data comma sequence, each lane sends the same byte or byte sequence for lane alignment. The receiving end is reset based on receiving continuous comma sequences on the Lane channel, and returns to the initial state when a non-comma sequence is received after the reset; The receiving end sets all lane channels as slave lanes in chanel-bond mode and selects the same 4-byte string after the continuous comma sequence as the bond sequence alignment identification sequence; When the receiving end detects that the commadet control signal changes from high level to low level, it sends a control sequence to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the sending end; The receiving end reselects the bond sequence or modifies the bondi control sequence code to control the order of the parallel output bytes within the Lane.

2. The ultra-low-latency universal simplex transmission method according to claim 1, characterized in that: The steps of the receiving end resetting based on receiving a continuous comma sequence on a Lane channel and returning to an initial state when receiving a non-comma sequence after the reset include: The receiving end receives the continuous comma sequence and starts the reset state machine to count and obtain the comma sequence count value; When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state; When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

3. The ultra-low delay universal simplex transmission method according to claim 2, characterized in that: The steps after the state machine is reset and enters the reset state include: The self-state machine using flexible buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all Lanes in the receiving channel become high.

4. The ultra-low delay universal simplex transmission method according to claim 1, characterized in that: The clock management components use MMCM, PLL or BUFG.

5. An ultra-low latency universal simplex transmission system based on 8b / 10b coding, characterized in that: The system comprises a receiving end of controlled slave alignment and a transmitting end of adopting a bufferless TX slave synchronous transmission architecture, and the method comprises: The transmitting end is used to use the clock management component to convert the external input reference clock into the TXUSERCLK2 clock to drive all Lane channels; All Lanes are configured as slave synchronization mode without buffer. After power-on reset, the state machine is used to manually control the delay, phase initialization, and transmission phase alignment mechanism inside the channel Lane to eliminate the skew between the transmitted data Lanes. The transmitted data contains a continuous comma sequence, which is used by the receiving end to determine the received byte boundary. After each Lane sends the data comma sequence, it sends the same byte or byte sequence for Lane alignment. The receiving end is used to reset based on the continuous comma sequence received by the Lane channel, and return to the initial state when a non-comma sequence is received after the reset; Set all Lane channels as slave Lanes in chanel-bond mode, and select the same 4-byte string after the continuous comma sequence as the bond sequence alignment recognition sequence; When the commadet control signal is detected to be converted from high level to low level, a control sequence is sent to the bondi control sequence code so that the transmission data of all lanes are aligned and output according to the byte order of the transmitting end; Reselect the bond sequence or modify the bondi control sequence code to control the order of the parallel output bytes within the Lane.

6. The ultra-low delay universal simplex transmission system according to claim 5, characterized in that: The receiving end is further used for: receiving a continuous comma sequence through the receiving end, starting a reset state machine to count and obtain a comma sequence count value; When the comma sequence count value reaches the preset threshold, the receiving state machine is started to reset and enter the reset state; When the receiving end receives a non-comma sequence, the reset state machine is set to the initial state.

7. The ultra-low delay universal simplex transmission system according to claim 6, characterized in that: The receiving end is also used to: The self-state machine of the flexible buffer coarse alignment sends an asynchronous reset pulse to RXBUFRESE when it detects that the resetdone signals of all Lanes in the receiving channel become high.

8. The ultra-low-latency universal simplex transmission system according to claim 5, characterized in that: The clock management components use MMCM, PLL or BUFG.

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