Low-delay control method, system and equipment of gallium nitride gate driver and medium

Abstract

The invention relates to the technical field of drivers, and discloses a low-delay control method, system, equipment and medium for a gallium nitride gate driver, and the method comprises the steps: carrying out the feature extraction and nonlinear mapping processing of the driving voltage, gate charge and switching time sequence parameters of the gate driver, and obtaining time domain characteristic data and a parameter distribution model; duty ratio modulation function calculation is carried out to obtain a rising edge duty ratio parameter and a falling edge duty ratio parameter; performing dynamic planning solution on the state transition equation to obtain an optimal control sequence; performing driving control on a gate driver according to the optimal control sequence, and acquiring running state data through a plurality of monitoring points to obtain an actual driving delay value and an actual switching loss value; the Gaussian process model is constructed based on the actual driving delay value and the actual switching loss value, the updated control parameters are obtained through iterative sampling calculation, the optimal control sequence considering multivariable constraints is obtained, and the accuracy of driving control is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of driver technology, and in particular to a low-latency control method, system, device and medium for a gallium nitride gate driver. Background Art

[0002] With the widespread application of gallium nitride (GaN) power devices in the field of high-frequency power electronics, their excellent switching characteristics and low conduction loss make them an ideal choice for high-efficiency power systems. However, the high-speed switching characteristics of GaN power devices also bring new challenges to the design of gate drivers, especially the control issues in terms of drive delay and switching loss become more prominent.

[0003] Traditional gate drive control methods mainly rely on fixed drive timing and preset control parameters, which cannot effectively deal with parameter uncertainty and dynamic load changes in actual applications. This control strategy is prone to increase drive delay, increase switching loss, and even cause parasitic oscillation under high-frequency switching conditions, seriously affecting the reliability and efficiency of the system. Summary of the invention

[0004] The present invention provides a low-latency control method, system, device and medium for a gallium nitride gate driver. The present invention obtains an optimal control sequence considering multivariable constraints, thereby significantly improving the accuracy of drive control.

[0005] In a first aspect, the present invention provides a low-latency control method for a gallium nitride gate driver, the low-latency control method for a gallium nitride gate driver comprising: Perform feature extraction and nonlinear mapping processing on the gate driver's driving voltage, gate charge, and switching timing parameters to obtain time domain characteristic data and parameter distribution model; Performing duty cycle modulation function calculation on the time domain characteristic data and the parameter distribution model to obtain a rising edge duty cycle parameter and a falling edge duty cycle parameter; Performing dynamic programming to solve a state transfer equation based on the rising edge duty cycle parameter and the falling edge duty cycle parameter to obtain an optimal control sequence, wherein the state transfer equation includes three variables: gate voltage, gate charge, and drive delay; The gate driver is driven and controlled according to the optimal control sequence, and operation status data is collected through multiple monitoring points to obtain an actual driving delay value and an actual switching loss value; A Gaussian process model is constructed based on the actual driving delay value and the actual switching loss value, and the posterior probability distribution is calculated through iterative sampling to obtain updated control parameters.

[0006] In a second aspect, the present invention provides a low-latency control system of a gallium nitride gate driver, the low-latency control system of the gallium nitride gate driver comprising: A feature extraction module is used to perform feature extraction and nonlinear mapping processing on the driving voltage, gate charge, and switching timing parameters of the gate driver to obtain time domain characteristic data and parameter distribution model; A calculation module, used for performing duty cycle modulation function calculation on the time domain characteristic data and the parameter distribution model to obtain a rising edge duty cycle parameter and a falling edge duty cycle parameter; A solution module, used for performing dynamic programming solution on a state transfer equation based on the rising edge duty cycle parameter and the falling edge duty cycle parameter to obtain an optimal control sequence, wherein the state transfer equation includes three variables: gate voltage, gate charge and drive delay; An acquisition module, used to drive and control the gate driver according to the optimal control sequence, and to acquire operation status data through multiple monitoring points to obtain an actual drive delay value and an actual switching loss value; A construction module is used to construct a Gaussian process model based on the actual driving delay value and the actual switching loss value, and calculate the posterior probability distribution through iterative sampling to obtain updated control parameters.

[0007] A third aspect of the present invention provides a computer device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory so that the computer device executes the low-latency control method of the gallium nitride gate driver.

[0008] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the low-latency control method of the gallium nitride gate driver.

[0009] In the technical solution provided by the present invention, feature extraction and nonlinear mapping are performed through a feedforward neural network, so as to realize accurate modeling of driving parameters, accurately capture the dynamic characteristics of the gate driver, adopt a duty cycle modulation function calculation method, combine time domain characteristic data and parameter distribution model, accurately control the waveform characteristics of the rising and falling edges, and effectively reduce switching losses; solve the state transfer equation through a dynamic programming algorithm, and obtain the optimal control sequence considering multivariable constraints, which significantly improves the accuracy of drive control; based on a Gaussian process model and a Bayesian update mechanism, online optimization of control parameters is realized, so that the system can quickly adapt to load changes; a hierarchical collaborative control strategy is adopted, and the operation of multiple drivers is effectively coordinated through a time-space coupling model, so as to ensure the synchronization and stability of the system; an intelligent predictive controller IPC module is introduced, and combined with a phase mapping technology, accurate timing control between multiple drivers is realized, thereby improving the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0011] Figure 1 Schematic diagram of the steps of a low-delay control method of a gallium nitride gate driver in an embodiment of the present invention; Figure 2 Schematic diagram of the structure of a low-latency control system of a gallium nitride gate driver in an embodiment of the present invention; Figure 3 It is a schematic block diagram of the structure of a computer device in an embodiment of the present invention. DETAILED DESCRIPTION

[0012] Embodiments of the present invention provide a low-latency control method, system, device and medium for a gallium nitride gate driver. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0013] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 , an embodiment of a low-delay control method of a gallium nitride gate driver in an embodiment of the present invention includes: Step S1, performing feature extraction and nonlinear mapping processing on the driving voltage, gate charge, and switch timing parameters of the gate driver to obtain time domain characteristic data and a parameter distribution model; It is understandable that the execution subject of the present invention may be a low-latency control system of a gallium nitride gate driver, or a terminal or a server, which is not specifically limited here. The embodiment of the present invention is described by taking a server as an execution subject as an example.

[0014] Specifically, the driving voltage, gate charge and switching timing parameters of the gate driver are constructed as a feature vector matrix, and the correlation between these variables is captured by the organization of the matrix. The feature vector matrix is ​​normalized to zero mean. By adjusting the mean of each feature to zero and normalizing the standard deviation to unit value, standardized input data is generated. The standardized input data is input into the input layer of the feedforward neural network, which is designed to contain 8 neurons, each of which corresponds to a feature in the input data. Through the weight matrix operation of the input layer, each input data is linearly combined with a specific weight, and nonlinearly transformed through the ReLU (rectified linear unit) activation function to generate the input data of the first hidden layer. The input data of the first hidden layer is processed. The first hidden layer contains 16 neurons, each of which is linearly combined with the input data with its weight, and combined with the bias term and the ReLU activation function to extract the potential features in the data. This feature extraction mechanism can enhance the expression ability of the network and generate the feature mapping results of the first layer. The feature mapping results of the first layer will be passed to the second hidden layer, which contains 32 neurons and extracts high-order features by introducing a deep residual learning structure. The residual structure directly introduces the input of the previous layer into the output of the current layer through skip connections, thereby alleviating the gradient vanishing problem in deep network training and improving the efficiency of feature learning. This design enables the second hidden layer to effectively capture the complex nonlinear relationship in the input data and generate the feature mapping results of the second layer. The feature mapping results of the second layer are input to the fully connected layer for processing. The fully connected layer contains 64 neurons, which perform nonlinear transformation on the input data through matrix multiplication and Sigmoid activation function to generate multidimensional feature representations to reflect the deep-level characteristics of the input data. Based on the multidimensional feature representation, the probability distribution parameters are calculated. The kernel density estimation method is used to construct a three-dimensional joint probability density function, which includes three dimensions: drive delay, gate voltage, and switching loss. The parameter distribution model generated in this way can reflect the joint distribution characteristics of the driver characteristics in these dimensions. The multidimensional feature representation is input to the time domain feature extraction layer, which contains 32 neurons. Through the time series convolution operation and combined with batch normalization processing, the time domain feature extraction layer can capture the time-related dynamic change characteristics in the input data and generate a time domain feature vector. These feature vectors are mapped through the output layer, which uses a linear activation function to map the features to the target domain to generate the final time domain feature data.

[0015] Step S2, performing duty cycle modulation function calculation on the time domain characteristic data and the parameter distribution model to obtain rising edge duty cycle parameters and falling edge duty cycle parameters; Specifically, the time domain characteristic data is input into the duty cycle calculation module, and the initial duty cycle modulation function is generated by segmenting the driving waveform. The parameter distribution model is subjected to probability density analysis, and the joint distribution characteristics of driving delay, gate voltage and switching loss are analyzed by using a three-dimensional probability distribution function. The probability correlation between the dimensions is calculated by the kernel density estimation method to generate the constraints of the waveform modulation. Through these constraints, the feasible solution space of the duty cycle modulation function is effectively limited to ensure that the subsequent optimized modulation results can not only meet the requirements of the time domain dynamic characteristics, but also reduce the switching loss and optimize the driving delay. Based on the generated waveform modulation constraints, the initial duty cycle modulation function is corrected and calculated. The optimization algorithm is used to convert the waveform modulation problem into a parameter optimization problem by solving the modulation coefficient matrix. In this process, optimization methods such as gradient descent method, Lagrange multiplier method or genetic algorithm are used to find the global optimal solution. The optimization calculation can correct the inaccurate part of the initial duty cycle modulation function so that it meets the constraints of the multidimensional parameter distribution model, while taking into account the trade-off between delay and energy consumption of the gate driver. Substitute the modified modulation function into the rising edge waveform equation, and use the numerical integration method to calculate the characteristic parameters of the rising edge waveform. The numerical integration method obtains an accurate description of the rising edge waveform by integrating the waveform equation over time, including time constant, slope and dynamic characteristics. Through these characteristic parameters, the changing law of the rising edge waveform at different time points is analyzed. Similarly, substitute the modified duty cycle modulation function into the falling edge waveform equation, and obtain the characteristic parameters of the falling edge waveform by numerical integration again. These parameters describe the dynamic characteristics of the falling edge waveform, including the falling slope of the waveform, time response and driving power change characteristics. By comparing with the rising edge waveform characteristics, the applicability and effectiveness of the modified modulation function in the entire driving cycle are evaluated. After obtaining the waveform characteristic parameters of the rising and falling edges, in order to improve the accuracy of the duty cycle parameters, the waveform characteristic parameters are dynamically compensated. This process is achieved through a feedback control algorithm, in which the control algorithm adjusts the time constants of the rising and falling edges in real time to ensure the dynamic adaptability of the duty cycle modulation. For example, by comparing the deviation between the actual drive delay and the target delay, the rising edge time constant is dynamically adjusted to generate the rising edge duty cycle parameters. Likewise, the dynamic compensation operation of the falling edge waveform parameters also relies on the feedback control algorithm, and the falling edge duty cycle parameters are generated by adjusting the falling edge time constant.

[0016] Step S3, performing dynamic programming to solve the state transfer equation based on the rising edge duty cycle parameter and the falling edge duty cycle parameter to obtain an optimal control sequence, wherein the state transfer equation includes three variables: gate voltage, gate charge, and drive delay; Specifically, the rising edge duty cycle parameter and the falling edge duty cycle parameter are substituted into the state transfer equation, where the state transfer equation contains three core variables, namely, gate voltage, gate charge and driving delay. These variables jointly describe the dynamic behavior of the gate driver and express its evolution characteristics over time in a recursive form through the state transfer equation. The state transfer equation is subjected to matrix decomposition. The state transfer matrix is ​​decomposed into the product form of the upper triangular matrix and the lower triangular matrix to generate a recursive expression of the state transfer. The purpose of matrix decomposition is to decompose the complexity of the state transfer process into sub-problems that are easier to solve, so that the recursive expression can efficiently calculate the state change at each time step. The recursive expression of the state transfer is substituted into the cost function to construct a cumulative cost calculation formula. The cost function is defined as the weighted sum of driving delay, gate voltage deviation and energy loss, so as to balance the driving energy consumption and performance under the premise of ensuring low delay. In order to solve the problem of minimizing the cumulative cost, the three-dimensional state space (gate voltage, gate charge and driving delay) is discretized. The state space is divided into multiple discrete points using a grid search operation to generate a state space search grid. These discrete points are used as inputs to the dynamic programming algorithm, which transforms complex continuous optimization problems into discrete optimization problems, making them easier to solve. By inputting the state space search grid into the dynamic programming recursive equation, the problem is recursively solved in combination with terminal constraints and boundary conditions. The terminal constraints include the target value of the final gate voltage and the allowable driving delay range, while the boundary conditions limit the physical range of the initial state and the control variable. In the dynamic programming framework, these conditions are used to calculate the state transition cost matrix of each grid point, and each element of the cost matrix corresponds to the minimum cumulative cost under a specific state. After the state transition cost matrix is ​​calculated, the reverse recursive algorithm is used to gradually solve the optimal control quantity. The reverse recursive process calculates the optimal control quantity of each time step in reverse from the terminal time point according to the preset time step sequence to generate the optimal control decision sequence. The design of the reverse recursive ensures that the control decision of each step is locally optimal under a given state, and the global optimality of the entire sequence is guaranteed by the dynamic programming method. The optimal control decision sequence is substituted into the state transfer equation for verification and further calculation. The fourth-order Runge-Kutta integral method is used to accurately calculate the state values ​​of all discrete time points to generate a complete state trajectory. The fourth-order Runge-Kutta method effectively improves the accuracy of integral calculation through multi-point sampling and weighted averaging, ensuring that the state trajectory can accurately reflect the dynamic behavior of the gate driver. The segmented control function is constructed based on the complete state trajectory, and the control strategy is optimized in combination with the gate voltage threshold condition and the drive delay constraint. The segmented control function is based on the optimal control decision in different time intervals, and maps the optimal control sequence to the actual drive signal, thereby achieving precise control of the gate driver.

[0017] Step S4, driving and controlling the gate driver according to the optimal control sequence, and collecting operation status data through multiple monitoring points to obtain an actual driving delay value and an actual switching loss value; Specifically, the optimal control sequence obtained by dynamic programming is input into a high-speed digital-to-analog converter, which converts the discrete digital control quantity into a continuous signal, completes the reconstruction operation of discrete points, and generates a discrete sampling sequence with high precision. These discrete sampling sequences are processed by a drive waveform synthesis module to generate a standard drive voltage waveform. The waveform has the time and amplitude information contained in the optimal control sequence and meets the requirements of the gallium nitride power device for the drive signal response speed and stability. The standard drive voltage waveform is applied to the gate end of the gallium nitride power device, and 8 sampling channels are set between the gate and the source to monitor the dynamic response of the driver in real time. Each sampling channel captures the gate voltage value at different time points to generate a complete gate voltage response curve. In order to analyze the dynamic behavior of the gate voltage, a threshold detection operation is performed on the gate voltage response curve. By setting the switching threshold (such as the moment when the gate voltage rises or falls to a specified value), the corresponding switching time data points in the gate voltage response curve are extracted. These data points directly reflect the switching behavior of the gallium nitride power device. In order to calculate the actual driving delay value, the adjacent switching moment data points are differenced, and the accurate driving delay value is obtained by comparing the time interval between the control signal application time and the switching action completion time. This delay value reflects the time difference between the driver input of the control signal and the response of the power device. In the calculation process of the actual switching loss, the gate voltage response curve and the gate charging current are multiplied point by point to calculate the instantaneous power value at each time point during the gate charging or discharging process. By accumulating these instantaneous power values ​​within the switching cycle, the single-cycle switching energy is obtained. The single-cycle switching energy represents the energy consumption of the GaN power device in a complete switching cycle and is an important indicator for evaluating switching losses. The single-cycle switching energy is multiplied by the switching frequency value to obtain the power loss per unit time, and the actual switching loss value is obtained.

[0018] Step S5: construct a Gaussian process model based on the actual driving delay value and the actual switching loss value, calculate the posterior probability distribution through iterative sampling, and obtain updated control parameters.

[0019] Specifically, the actual driving delay value and the actual switching loss value are normalized to eliminate the influence of the original data due to different dimensions. In the normalization process, each set of data is scaled to the same scale interval so that the delay value and the loss value participate in the calculation together in the Gaussian process modeling. After the normalization process is completed, the data are mapped to a two-dimensional Gaussian random field, which is based on the Gaussian distribution and describes the joint probability relationship between driving delay and switching loss. Based on the generated two-dimensional Gaussian random field, the prior distribution model of the Gaussian process is established to generate the corresponding prior probability function. The prior distribution of the Gaussian process model reflects the initial assumption of the system behavior in the absence of observed data. It is based on the point value in the Gaussian random field and describes the correlation between the data through the covariance function. At this stage, the prior probability function is only constructed based on the model assumptions and the input space structure, and has not yet been combined with the actual observations. The actual observed driving delay value and switching loss value are used as sample data, and the Bayesian update operation is performed with the prior probability function of the Gaussian process. The core of Bayesian updating is to correct the prior distribution through sample data to obtain a posterior distribution function that is closer to the actual system behavior. In this process, the conditional probability is calculated to integrate the information of the observed value and generate the posterior distribution function. The posterior distribution function is sampled probabilistically to generate a probability sampling sequence used to describe the system performance. Based on this sampling sequence, the joint distribution probability density of the driving delay and switching loss is calculated to construct a two-dimensional probability density matrix. By performing a maximum a posteriori probability search on the constructed two-dimensional probability density matrix, the optimal point of delay and loss is effectively located. During the search process, the maximum a posteriori probability point is identified as the optimal control parameter point that satisfies the balance between delay and loss. In order to ensure the safety and reliability of the control parameters in practical applications, a safe constraint region of the parameters is constructed with the optimal control parameter point as the center. The safe constraint region defines the feasible range of parameter adjustment to avoid system instability or performance degradation caused by over-optimization. Within the feasible domain of parameters, the control parameter vector is optimized and adjusted by introducing the gradient descent algorithm. During the gradient descent process, the parameters are iteratively updated according to the preset learning rate to gradually approach the optimal solution. The updated control parameters, through a combination of gradient descent and Gaussian process, can dynamically adapt to changes in the system's operating state while ensuring low drive delay and low switching loss.

[0020] The updated control parameters are divided into master control parameters and slave control parameters according to the drive function. The master control parameters are preferentially allocated to the drive with the highest power level, making it the master control unit, while the slave control parameters are allocated to other drives to form slave control units. Through classification, a hierarchical control unit group with the master control unit as the core is established to ensure that the control functions of drives of different levels are optimally allocated. A distributed network topology is constructed on the basis of the hierarchical control unit group, with the master control unit placed at the central node of the network and the slave control units arranged at the peripheral nodes. The network topology can not only improve the efficiency of signal transmission, but also centrally coordinate the entire system through the central node to realize the distributed management of the multi-drive system. The design of the drive control network utilizes the high performance characteristics of the master control unit, enabling it to quickly process global information and command the slave control units. In order to enhance the intelligence level of each node unit, an intelligent predictive controller (IPC) module is configured in each unit. The core of the IPC module is that it can perform fast dynamic prediction and real-time adjustment. Therefore, it is necessary to set appropriate control parameters and response thresholds for each module to construct a corresponding node unit prediction model. The node unit prediction model combines the dynamic response characteristics of the drive and provides prediction capabilities and calculation basis for timing optimization and phase allocation. The node unit prediction model is decomposed in the time domain, and the control cycle is divided into multiple time intervals. The length of each time interval is set to Δt=100ns, so as to obtain a high-precision control timing table. The function of the control timing table is to provide a control framework in the time series for the entire drive system, so that each unit can perform its corresponding control task at the appropriate time. The generated control timing table is input into the phase mapper, and a phase offset φi is assigned to each slave control unit. These offsets are evenly distributed in the interval [0,2π] to form a phase allocation sequence. The function of the phase allocation sequence is to avoid interference or conflict caused by the simultaneous action of multiple drive units by staggering the phase in time, so as to ensure the stability and efficiency of the system operation. The trigger timing matrix is ​​generated according to the phase allocation sequence. The trigger timing matrix defines the trigger time of each drive unit, and constructs the weight coefficient matrix by weighted calculation of spatial distance, considering the physical distance between the drives. The introduction of the weight coefficient matrix is ​​to reflect the coupling relationship of the drives in the physical space, integrate the information of spatial distance into the timing design, and form the space-time coupling constraint condition. These constraints can optimize the collaborative efficiency of the multi-drive system and reduce control delays and signal conflicts caused by distance differences. The spatiotemporal coupling constraints are combined with the phase allocation sequence to generate a multi-drive collaborative control strategy. This strategy comprehensively considers the constraints in time and space, allowing each drive unit to operate independently while ensuring global consistency.The implementation of the collaborative control strategy relies on the coordination of the entire network and the intelligence of the IPC module, which can dynamically adapt to the operating status of the system and changes in the external environment, and ultimately achieve low-latency, high-efficiency collaborative control of multiple drivers.

[0021] In the embodiment of the present invention, feature extraction and nonlinear mapping are performed through a feedforward neural network to achieve accurate modeling of drive parameters, accurately capture the dynamic characteristics of the gate driver, and adopt a duty cycle modulation function calculation method, combined with time domain characteristic data and parameter distribution model, to accurately control the waveform characteristics of the rising and falling edges, effectively reducing switching losses; the state transfer equation is solved by a dynamic programming algorithm, and the optimal control sequence considering multivariable constraints is obtained, which significantly improves the accuracy of drive control; based on the Gaussian process model and Bayesian update mechanism, online optimization of control parameters is achieved, so that the system can quickly adapt to load changes; a hierarchical collaborative control strategy is adopted, and the operation of multiple drivers is effectively coordinated through a time-space coupling model, ensuring the synchronization and stability of the system; an intelligent predictive controller IPC module is introduced, combined with phase mapping technology, to achieve precise timing control between multiple drivers, thereby improving the reliability of the system.

[0022] In a specific embodiment, the process of executing step S1 may specifically include the following steps: The driving voltage, gate charge, and switch timing parameters of the gate driver are constructed as an eigenvector matrix, and the eigenvector matrix is ​​subjected to zero-mean normalization to obtain standardized input data; The standardized input data is input into the input layer of the feedforward neural network, which contains 8 input neurons. The first hidden layer input data is obtained through weight matrix operation and ReLU activation function calculation. The input data of the first hidden layer is processed. The first hidden layer contains 16 neurons. Each neuron is subjected to feature extraction through a linear combination operation with a bias term and a ReLU activation function to obtain the first layer feature mapping result. The first layer feature mapping results are input into the second hidden layer, which contains 32 neurons. The high-order features are extracted through the deep residual learning structure with jump connections to obtain the second layer feature mapping results. The second-layer feature mapping result is processed by a fully connected layer, which contains 64 neurons. Nonlinear transformation is performed through matrix multiplication and Sigmoid activation function to obtain multi-dimensional feature representation. The probability distribution parameters are calculated based on the multi-dimensional feature representation, and a three-dimensional joint probability density function is constructed by the kernel density estimation method. The three-dimensional joint probability density function includes the drive delay dimension, the gate voltage dimension, and the switching loss dimension, and a parameter distribution model is obtained. The multidimensional feature representation is input into the time domain feature extraction layer, which contains 32 neurons. The time domain feature vector is obtained through temporal convolution operation and batch normalization processing. The time domain feature vector is input into the output layer, and the feature is mapped to the target domain through a linear activation function to obtain the time domain feature data.

[0023] Specifically, the gate driver voltage , Gate charge and switch timing parameters As input features, construct the feature vector matrix. Assume that Group data, each group of data consists of the above three variables, then the eigenvector matrix is ​​expressed as: ; in It is The driving voltage of each sample, is the corresponding gate charge, is the switch timing parameter. In order to avoid the influence of different feature scales, the feature vector matrix is ​​normalized to zero mean. For each column of the feature matrix, its mean is calculated. and standard deviation , then follow the formula: ; Standardize the features to get the standardized input data matrix The purpose of standardization is to adjust all features to zero mean and unit variance, thereby improving the training stability of the neural network. Enter the input layer of the feedforward neural network. The input layer contains 8 input neurons, corresponding to the expanded input feature space. Assume that the input feature is , through the weight matrix and the bias term Perform a linear transformation: ; And through the ReLU activation function, nonlinear transformation is performed to obtain the input data of the first hidden layer: ; Where ReLU The output of this layer is is passed to the first hidden layer, which contains 16 neurons, each of which performs a similar operation, namely: ; ; Through the feature extraction of this layer, the first layer feature mapping result is generated , which contains a deeper representation of the input features after nonlinear combination. The first layer feature mapping result is input into the second hidden layer, which consists of 32 neurons and introduces a deep residual learning structure (ResNet). The residual structure uses jump connections to make the input of the previous layer Directly add it to the output of the current layer to alleviate the gradient vanishing problem. The calculation expression of the second hidden layer is: ; ; Thereby extracting high-order features and generating the second-layer feature mapping results The output of the second layer is passed to a fully connected layer, which contains 64 neurons, and the feature representation is further processed through matrix multiplication and Sigmoid activation function: ; ; Generating multi-dimensional feature representations The Sigmoid activation function is defined as: ; The output is compressed to the interval (0,1) for subsequent probability distribution modeling. Based on multidimensional feature representation , the kernel density estimation method is used to calculate the probability distribution parameters and construct a three-dimensional joint probability density function. Three-dimensional joint probability density function Through the kernel function It is expressed as: ; in is the kernel width, Usually a Gaussian kernel function, defined as: ; Through this function, a parameter distribution model is generated to characterize the probability relationship between drive delay, gate voltage and switching loss. The multi-dimensional feature representation is input to the time domain feature extraction layer, which extracts time domain features through time series convolution operation and batch normalization. Assume that the convolution kernel is , the input is , the convolution result is: ; And perform batch normalization to obtain the time domain feature vector The feature vector is mapped to the target domain through the linear activation function of the output layer: ; Finally, time domain characteristic data is generated.

[0024] In a specific embodiment, the process of executing step S2 may specifically include the following steps: Input the time domain characteristic data into the duty cycle calculation module, perform segmented processing on the driving waveform, and obtain the initial duty cycle modulation function; The probability density analysis of the parameter distribution model is performed, and the joint distribution characteristics of driving delay, gate voltage and switching loss are calculated using a three-dimensional probability distribution function to obtain the waveform modulation constraint conditions. Based on the waveform modulation constraint condition, the initial duty cycle modulation function is modified and calculated, and the modulation coefficient matrix is ​​solved by the optimization algorithm to obtain the modified duty cycle modulation function; Substitute the modified duty cycle modulation function into the rising edge waveform equation, and use numerical integration to calculate the rising edge waveform characteristics to obtain the rising edge waveform parameters; Substitute the modified duty cycle modulation function into the falling edge waveform equation, and use numerical integration to calculate the falling edge waveform characteristics to obtain the falling edge waveform parameters; Dynamic compensation operation is performed on the rising edge waveform parameters, and the rising edge time constant is adjusted through the feedback control algorithm to obtain the rising edge duty cycle parameters. Dynamic compensation operation is performed on the falling edge waveform parameters, and the falling edge time constant is adjusted through the feedback control algorithm to obtain the falling edge duty cycle parameters.

[0025] Specifically, the time domain characteristic data Input to the duty cycle calculation module, this data describes the dynamic behavior of the gate driver at different time points. By segmenting the drive waveform, it is divided into time intervals, each of which is The segmentation process is expressed as: ; in It is The time domain characteristic value in the time interval. Construct the initial duty cycle modulation function based on the segmented data , whose expression is: ; in It is The modulation coefficient of the segment, For the The time window function of the segment is defined as when , otherwise 0. Perform probability density analysis on the parameter distribution model. The parameter distribution model is a three-dimensional probability distribution function Indicates, describes the drive delay , gate voltage and switching losses The joint features of . Using the kernel density estimation method, the joint distribution is calculated: ; Where N is the number of samples; is the nuclear width (in units corresponding to the dimension of the variable, e.g., volts, coulombs, seconds); is a three-dimensional Gaussian kernel function used to smooth the data distribution: ; in They are By calculating , extract the joint distribution characteristics of driving delay, gate voltage and switching loss, and then generate waveform modulation constraints. These constraints are expressed as inequalities: ; in , , and is the delay, voltage range and power consumption limit allowed by the system. Based on these constraints, the initial duty cycle modulation function Perform correction calculation. The correction process adopts the optimization algorithm, and the objective function is set as: ; in, is the target cost function, which is used to evaluate the modulation error and is dimensionless; is the total time length; is the desired duty cycle modulation function. The modulation coefficient is optimized using the gradient descent method. , the update formula is: ; in, It is The modulation coefficient of the iteration; is the learning rate, unit is dimensionless. Substitute the rising edge waveform equation and the falling edge waveform equation for analysis. Assume that the rising edge waveform equation is: ; in is the maximum gate voltage, is the rising edge time constant. The waveform characteristics are calculated by numerical integration method: ; in is the duration of the rising edge. Similarly, the equation for the falling edge waveform is: ; The falling edge waveform characteristics are calculated as: ; For rising edge waveform parameters And falling edge waveform parameters Perform dynamic compensation calculations and use feedback control algorithms to adjust the rising edge time constant and the falling edge time constant The feedback control algorithm calculates the adjustment amount based on the deviation between the target and the actual, for example: the rising edge waveform characteristics And falling edge waveform characteristics Perform dynamic compensation calculations and adjust the time constant through feedback control and The adjustment formula is: ; in is the proportional gain, is the target rising edge waveform characteristic value. Similarly, the falling edge parameters are compensated and calculated, and finally the optimized rising edge and falling edge duty cycle parameters are obtained.

[0026] In a specific embodiment, the process of executing step S3 may specifically include the following steps: Substituting the rising edge duty cycle parameter and the falling edge duty cycle parameter into the state space equation, a state transfer equation is obtained. The state transfer equation contains three variables: gate voltage, gate charge and drive delay. Perform matrix decomposition operation on the state transfer equation, decompose the state transfer matrix into the product form of the upper triangular matrix and the lower triangular matrix, and obtain the recursive expression of the state transfer; Substitute the recursive expression of state transfer into the cost function to obtain the cumulative cost calculation formula, and perform grid search operation on the cumulative cost calculation formula to divide multiple discrete points in the three-dimensional state space to obtain a state space search grid; Input the state space search grid into the dynamic programming recursive equation, combine the terminal constraints and boundary conditions, and obtain the state transition cost matrix; Perform reverse recursive calculation on the state transfer cost matrix, solve the optimal control quantity of each time step in sequence according to the preset order, and obtain the optimal control decision sequence; The optimal control decision sequence is substituted into the state transfer equation, and the state values ​​of all discrete time points are calculated using the fourth-order Runge-Kutta integral to obtain the complete state trajectory. A piecewise control function is constructed based on the complete state trajectory, and the optimal control sequence is obtained by combining the gate voltage threshold condition and the drive delay constraint.

[0027] Specifically, the rising edge duty cycle parameter And the falling edge duty cycle parameters The state space equation is introduced to describe the dynamic behavior of the gate driver. The state variables include the gate voltage , Gate charge And drive delay The state-space equations are expressed as a set of first-order differential equations: ; in, is the state transition matrix, describing the intrinsic dynamic characteristics of the system; is the control input matrix, which describes the influence of duty cycle parameters on the system state. In order to simplify the calculation, the state transfer matrix Decompose into upper triangular matrix and the lower triangular matrix The product form is: ; in, is a lower triangular matrix, is an upper triangular matrix. This decomposition can improve computational efficiency and facilitate solving state recursive expressions. By decomposing, the state transfer equation is expressed in recursive form: ; in, It is The state vector of the time step; It is The control input vector of time steps. Substitute the state recursive expression into the cost function and define the cumulative cost as: ; in, is the state weight matrix, which is used to measure the cost of state deviation; is the control weight matrix, which is used to measure the cost of the control input. In order to find the minimum value of the cumulative cost, the gate voltage, gate charge and drive delay are discretized in the three-dimensional state space to generate a state space search grid. Assume that each dimension is divided into discrete points, the number of grid points is The cost value of each point is calculated through grid search, and the state transition cost matrix is ​​constructed. The state space search grid is input into the dynamic programming recursive equation, and the terminal constraints (such as the target gate voltage) are combined. and target delay ) and boundary conditions (such as initial state and maximum allowable deviation) to solve the optimal control quantity for each time step. The recursive formula of dynamic programming is: ; in It is The value function of the step describes the minimum cost of the current state. By reverse recursion, from the terminal time step Start solving the optimal control quantity for each step in turn and generate the optimal control decision sequence Substitute the optimal control decision sequence into the state transfer equation, use the fourth-order Runge-Kutta method to calculate the state values ​​of all discrete time points, and generate a complete state trajectory. The calculation formula of the Runge-Kutta method is: ; in: ; ; in is the state transition function, is the time step. Through the complete state trajectory, a segmented control function is constructed to describe the control strategy of the driver in each time period. At the same time, the threshold condition of the gate voltage is combined and the constraints of driving delay , generating the final optimal control sequence.

[0028] In a specific embodiment, the process of executing step S4 may specifically include the following steps: The optimal control sequence is input into a high-speed digital-to-analog converter, the control quantity is reconstructed at discrete points to obtain a discrete sampling sequence, and the discrete sampling sequence is synthesized into a driving waveform to obtain a standard driving voltage waveform; Apply a standard driving voltage waveform to the gate end of the GaN power device, set 8 sampling channels between the gate and source, obtain the gate voltage response curve, and perform threshold detection on the gate voltage response curve to obtain the switching time data point; Perform difference calculation on adjacent switch time data points, take the time interval between the control signal time and the switch completion time as the delay time, and obtain the actual drive delay value; The gate voltage response curve is multiplied by the gate charging current, and the energy value is accumulated within the switching cycle to obtain the single-cycle switching energy. The single-cycle switching energy is multiplied by the switching frequency value, and the power loss per unit time is calculated to obtain the actual switching loss value.

[0029] Specifically, the optimal control sequence Enter the high speed digital to analog converter. Indicates The high-speed digital-to-analog converter converts these discrete digital control quantities into continuous analog signals. In this process, in order to ensure the smoothness and accuracy of signal conversion, discrete point reconstruction is performed, and linear interpolation or high-order interpolation methods are used to reconstruct discrete points into continuous waveforms. The interpolated discrete sampling sequence is expressed as: ; in is the interpolation basis function, using the linear interpolation basis function, such as when , otherwise it is 0. Through interpolation and conversion, a smooth driving waveform is obtained . For the reconstructed discrete sampling sequence Drive waveform synthesis is to synthesize the drive waveform. With preset duty cycle modulation function Multiply to generate a standard driving voltage waveform , whose expression is: ; in is the maximum drive voltage. The standard drive voltage waveform generated It is applied to the gate end of the GaN power device, and 8 sampling channels are set between the gate and the source. Each sampling channel corresponds to a different time period, and the dynamic changes of the gate voltage are recorded through high-frequency sampling to form a gate voltage response curve. The sampling frequency should be much higher than the frequency of the driving signal to ensure the accuracy of the response curve. Perform threshold detection on the gate voltage response curve. Set a threshold ,when Rise to or fall to When, record the corresponding time point and , respectively represent the opening and closing time. Through detection, the switching time data points are obtained. The adjacent switching time data points are and Perform difference calculation to calculate the time interval between the moment the drive signal is applied and the moment the switch action is completed as the delay time The specific calculation formula is: ; in Is the moment when the control signal is input. Delay time It is one of the key indicators to measure the performance of the driver. In order to calculate the actual switching loss value, the gate voltage response curve With the gate charging current Perform point-by-point multiplication to calculate instantaneous power : ; Then in a switching cycle The instantaneous power is accumulated and integrated to obtain the single-cycle switching energy : ; To calculate the switching loss per unit time, multiply the single cycle switching energy by the switching frequency. : ; in is the switching frequency). The final Indicates the power consumption of the driver per unit time.

[0030] In a specific embodiment, the process of executing step S5 may specifically include the following steps: The actual driving delay value and the actual switching loss value are normalized, and the normalized data are mapped to the Gaussian space to obtain a two-dimensional Gaussian random field; Based on the two-dimensional Gaussian random field, a Gaussian process prior distribution model is established to obtain a priori probability function; Perform Bayesian update operation on the prior probability function and sample observation value, calculate the conditional probability, obtain the posterior distribution function, and generate the probability sampling sequence according to the posterior distribution function; Calculate the joint distribution probability density of delay and loss according to the probability sampling sequence and construct a two-dimensional probability density matrix; Perform maximum a posteriori probability search on the two-dimensional probability density matrix to locate the optimal point of delay loss and obtain the optimal control parameter point; The safety constraint region is constructed based on the optimal control parameter point to obtain the parameter feasible domain, and gradient descent optimization is performed within the parameter feasible domain. The control parameter vector is updated according to the preset learning rate to obtain the updated control parameters.

[0031] Specifically, for the actual drive delay value and actual switching loss values Normalization is performed to eliminate the differences between different physical dimensions, which is convenient for subsequent probability modeling and optimization. Group data, each group of data includes and The normalization formula is: ; in, and yes and The mean of and is the corresponding standard deviation; and is the normalized delay value and loss value. The normalized data is mapped to the Gaussian space to form a two-dimensional Gaussian random field , whose probability density is described by a two-dimensional Gaussian distribution: ; in, is the input vector; is the mean vector of the Gaussian distribution (usually a zero vector after normalization); is the covariance matrix, describing and Based on the two-dimensional Gaussian random field, a Gaussian process prior distribution model is established. The Gaussian process model is a nonparametric model used to model functions in the input space, assuming that all possible function values ​​satisfy the Gaussian distribution. The mean function of the prior probability function and covariance function is defined as: ; ; in Represents the expected value. Based on Gaussian process modeling, the prior probability function and the sample observation value are updated by Bayesian operation. Assuming that Observation points and the corresponding observations , the posterior distribution function is expressed as: ; in, is the observation vector; is the observation point matrix. The probability sampling sequence is generated by the posterior distribution function , each sampling point Represents a possible delay and loss combination. Based on the probability sampling sequence, the delay is calculated and loss The joint distribution probability density of constructing a two-dimensional probability density matrix , whose elements Indicates sampling point The probability density value of . Through the maximum a posteriori probability search, the optimal point is located in the probability density matrix. The maximum a posteriori probability point satisfy: ; Map the optimal point back to the original parameter space to obtain the optimal control parameter point Based on the optimal control parameter point, a safety constraint region is constructed, which is defined as the parameter feasible domain that meets the system operating conditions. The control parameters are further optimized using the gradient descent algorithm in the feasible region, and the update formula is: ; in, It is The control parameters of the iteration; is the learning rate; is the target cost function, such as .

[0032] In a specific embodiment, the low-latency control method for executing a GaN gate driver further includes the following steps: The updated control parameters are divided into master control parameters and slave control parameters according to the drive function, the master control parameters are allocated to the drive with the highest power level as the master control unit, and the slave control parameters are allocated to other drives as slave control units to obtain a hierarchical control unit group; A distributed network topology is established for the hierarchical control unit group, the master control unit is placed in the network center node, and the slave control unit is placed in the peripheral nodes to obtain a drive control network; Each node unit in the drive control network is configured with an intelligent prediction controller IPC module, and control parameters and response thresholds are set for the intelligent prediction controller IPC module to obtain a node unit prediction model; Perform time domain decomposition operation on the node unit prediction model, divide the control period into n time intervals, and set the length of each time interval to Δt = 100ns to obtain the control timing table; Input the control timing table into the phase mapper, assign a phase offset φi to each slave control unit, where φi∈[0,2π], and obtain a phase allocation sequence; Generate a trigger timing matrix according to the phase allocation sequence to obtain the drive operation timing, perform spatial distance weighted calculation on the drive operation timing, build a weight coefficient matrix according to the physical distance between the drives, and obtain the space-time coupling constraint conditions; The spatiotemporal coupling constraints are combined with the phase allocation sequence to generate a multi-actuator cooperative control strategy.

[0033] Specifically, the updated control parameters Divided into main control parameter sets according to drive functions and slave control parameter set . Main control parameters Contains parameters used to implement the main drive functions, such as key timing, duty cycle and waveform modulation coefficients associated with high-power drivers; slave control parameters The control unit is used for auxiliary functions, such as the regulation of low-power drives. The allocation rule is based on the power level. The drive with the highest power level is designated as the master control unit and receives , while other drives receive The hierarchical control units form a control structure, in which the master control unit is in the central position and is responsible for global coordination. A distributed network topology is established based on the hierarchical control unit group. In this network topology, the master control unit is placed at the central node of the network, while the slave control units are distributed in the peripheral nodes. Assuming that there are control units, including a main control unit and slave control units, the network topology is represented by the adjacency matrix Indicates that Indicates and There is a direct connection between the units. Indicates no connection. By optimizing the adjacency matrix , ensuring low latency and high reliability of the network. An intelligent predictive controller (IPC) module is configured in each node unit of the drive control network. Each IPC module is configured based on the functional requirements of the node and sets control parameters and response threshold . Prediction model of IPC module It is expressed as: ; in, is the predicted state vector for the next moment; is the current state vector; is the current control input vector activity, is the prediction function, defined by the internal model of the IPC module; is the time step in seconds. The prediction model of each node unit is decomposed in the time domain and the control cycle is divided into time intervals, and the length of each interval is set to ns. Control Timing Table The start time and duration of each time interval are defined to guide the implementation of the control strategy. The control timing table is input into the phase mapper to assign phase offsets to each slave control unit. ,in The phase offset distribution formula is: ; in is the index of the slave unit (from 1 to ). The introduction of phase offset makes the control signals of each slave control unit staggered in time, avoiding signal conflict. Generate trigger timing matrix . Trigger Timing Matrix Elements Defined as In the time period Whether a unit is triggered, the expression is: ; Through the trigger timing matrix , determine the control state of each driver in each time period. Perform spatial distance weighted calculation on the driver operation sequence. Assume that the driver and The physical distance between , construct the weight coefficient matrix ,in: ; in is the scale parameter of the distance weight, which controls the decay rate of the weight. It reflects the spatial coupling relationship between the drives and is used to generate spatiotemporal coupling constraints. Combining the spatiotemporal coupling constraints and the phase allocation sequence, a multi-drive collaborative control strategy is finally generated. The goal of the collaborative control strategy is to minimize delay and loss while ensuring the stability of the system. The optimization problem is expressed as: ; in It is The control input vector of each unit is is the objective function, which is used to measure the control consistency.

[0034] The above describes the low-latency control method of the gallium nitride gate driver in the embodiment of the present invention. The following describes the low-latency control system of the gallium nitride gate driver in the embodiment of the present invention. Figure 2 , an embodiment of a low-latency control system of a gallium nitride gate driver in an embodiment of the present invention includes: A feature extraction module is used to perform feature extraction and nonlinear mapping processing on the driving voltage, gate charge, and switching timing parameters of the gate driver to obtain time domain characteristic data and parameter distribution model; A calculation module is used to calculate the duty cycle modulation function on the time domain characteristic data and the parameter distribution model to obtain the rising edge duty cycle parameters and the falling edge duty cycle parameters; A solution module is used to perform dynamic programming solution on the state transfer equation based on the rising edge duty cycle parameter and the falling edge duty cycle parameter to obtain an optimal control sequence, wherein the state transfer equation includes three variables: gate voltage, gate charge and drive delay; An acquisition module is used to drive and control the gate driver according to the optimal control sequence, and collect operating status data through multiple monitoring points to obtain actual drive delay value and actual switching loss value; The building module is used to build a Gaussian process model based on the actual driving delay value and the actual switching loss value, calculate the posterior probability distribution through iterative sampling, and obtain the updated control parameters.

[0035] Through the coordinated cooperation of the above-mentioned components, feature extraction and nonlinear mapping are performed through feedforward neural networks, and the precise modeling of drive parameters is realized, the dynamic characteristics of the gate driver are accurately captured, and the duty cycle modulation function calculation method is adopted, combined with the time domain characteristic data and parameter distribution model, the waveform characteristics of the rising and falling edges are precisely controlled, and the switching loss is effectively reduced; the state transfer equation is solved by the dynamic programming algorithm, and the optimal control sequence considering multivariable constraints is obtained, which significantly improves the accuracy of drive control; based on the Gaussian process model and Bayesian update mechanism, the online optimization of control parameters is realized, so that the system can quickly adapt to load changes; a hierarchical collaborative control strategy is adopted, and the operation of multiple drivers is effectively coordinated through the time-space coupling model, ensuring the synchronization and stability of the system; the introduction of the intelligent predictive controller IPC module, combined with the phase mapping technology, realizes the precise timing control between multiple drivers and improves the reliability of the system.

[0036] Reference Figure 3 In an embodiment of the present invention, a computer device is also provided. The computer device may be a server, and its internal structure may be as follows: Figure 3 As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0037] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0038] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0039] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0040] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0041] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0042] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-delay control method for a gallium nitride gate driver, characterized in that: The method comprises: Perform feature extraction and nonlinear mapping processing on the gate driver's driving voltage, gate charge, and switching timing parameters to obtain time domain characteristic data and parameter distribution model; Performing duty cycle modulation function calculation on the time domain characteristic data and the parameter distribution model to obtain a rising edge duty cycle parameter and a falling edge duty cycle parameter; Performing dynamic programming to solve a state transfer equation based on the rising edge duty cycle parameter and the falling edge duty cycle parameter to obtain an optimal control sequence, wherein the state transfer equation includes three variables: gate voltage, gate charge, and drive delay; The gate driver is driven and controlled according to the optimal control sequence, and operation status data is collected through multiple monitoring points to obtain an actual driving delay value and an actual switching loss value; A Gaussian process model is constructed based on the actual driving delay value and the actual switching loss value, and the posterior probability distribution is calculated through iterative sampling to obtain updated control parameters.

2. The low-delay control method of the gallium nitride gate driver according to claim 1, characterized in that: The feature extraction and nonlinear mapping processing of the driving voltage, gate charge, and switch timing parameters of the gate driver are performed to obtain time domain characteristic data and parameter distribution model, including: The driving voltage, gate charge, and switch timing parameters of the gate driver are constructed as an eigenvector matrix, and the eigenvector matrix is ​​subjected to zero-mean normalization processing to obtain normalized input data; Input the standardized input data into the input layer of the feedforward neural network, the input layer comprising 8 input neurons, and obtain the first hidden layer input data through weight matrix operation and ReLU activation function calculation; Processing the first hidden layer input data, the first hidden layer includes 16 neurons, each neuron performs feature extraction through a linear combination operation with a bias term and a ReLU activation function to obtain a first layer feature mapping result; The first layer feature mapping result is input into the second hidden layer, the second hidden layer includes 32 neurons, and high-order features are extracted through a deep residual learning structure with jump connections to obtain the second layer feature mapping result; The second layer feature mapping result is processed by a fully connected layer, wherein the fully connected layer includes 64 neurons, and a nonlinear transformation is performed through matrix multiplication operation and Sigmoid activation function to obtain a multidimensional feature representation; Calculating probability distribution parameters based on the multidimensional feature representation, constructing a three-dimensional joint probability density function by a kernel density estimation method, wherein the three-dimensional joint probability density function includes a driving delay dimension, a gate voltage dimension, and a switching loss dimension, and obtaining a parameter distribution model; The multidimensional feature representation is input into the time domain feature extraction layer, which includes 32 neurons. A time domain feature vector is obtained through temporal convolution operation and batch normalization processing. The time domain feature vector is input into the output layer, and the feature is mapped to the target domain through a linear activation function to obtain time domain feature data.

3. The low-delay control method of the gallium nitride gate driver according to claim 2, characterized in that: The step of performing duty cycle modulation function calculation on the time domain characteristic data and the parameter distribution model to obtain a rising edge duty cycle parameter and a falling edge duty cycle parameter includes: Input the time domain characteristic data into a duty cycle calculation module, perform segmented processing on the driving waveform, and obtain an initial duty cycle modulation function; Performing probability density analysis on the parameter distribution model, and using a three-dimensional probability distribution function to calculate the joint distribution characteristics of drive delay, gate voltage and switching loss, to obtain waveform modulation constraint conditions; Based on the waveform modulation constraint condition, the initial duty cycle modulation function is modified and calculated, and a modulation coefficient matrix is ​​solved by an optimization algorithm to obtain a modified duty cycle modulation function; Substituting the modified duty cycle modulation function into the rising edge waveform equation, and using numerical integration to calculate the rising edge waveform characteristics to obtain the rising edge waveform parameters; Substituting the modified duty cycle modulation function into the falling edge waveform equation, and using numerical integration to calculate the falling edge waveform characteristics to obtain the falling edge waveform parameters; Dynamic compensation operation is performed on the rising edge waveform parameters, and the rising edge time constant is adjusted through the feedback control algorithm to obtain the rising edge duty cycle parameters. Dynamic compensation operation is performed on the falling edge waveform parameters, and the falling edge time constant is adjusted through the feedback control algorithm to obtain the falling edge duty cycle parameters.

4. The low-delay control method of the gallium nitride gate driver according to claim 3, characterized in that: The state transfer equation is dynamically programmed and solved based on the rising edge duty cycle parameter and the falling edge duty cycle parameter to obtain an optimal control sequence, wherein the state transfer equation contains three variables: gate voltage, gate charge, and drive delay, including: Substituting the rising edge duty cycle parameter and the falling edge duty cycle parameter into a state space equation to obtain a state transfer equation, wherein the state transfer equation includes three variables: gate voltage, gate charge, and drive delay; Performing a matrix decomposition operation on the state transfer equation, decomposing the state transfer matrix into a product form of an upper triangular matrix and a lower triangular matrix, and obtaining a recursive expression of the state transfer; Substituting the recursive expression of the state transfer into the cost function to obtain a cumulative cost calculation formula, and performing a grid search operation on the cumulative cost calculation formula to divide a plurality of discrete points in the three-dimensional state space to obtain a state space search grid; Inputting the state space search grid into the dynamic programming recursive equation, combining the terminal constraint conditions and the boundary conditions, to obtain the state transition cost matrix; Performing reverse recursive calculation on the state transfer cost matrix, solving the optimal control quantity of each time step in sequence according to a preset order, and obtaining an optimal control decision sequence; The optimal control decision sequence is substituted into the state transfer equation, and the state values ​​of all discrete time points are calculated using the fourth-order Runge-Kutta integral to obtain a complete state trajectory. A piecewise control function is constructed based on the complete state trajectory, and the optimal control sequence is obtained by combining the gate voltage threshold condition and the drive delay constraint.

5. The low-delay control method of the gallium nitride gate driver according to claim 4, characterized in that: The gate driver is driven and controlled according to the optimal control sequence, and operation status data is collected through multiple monitoring points to obtain an actual driving delay value and an actual switching loss value, including: The optimal control sequence is input into a high-speed digital-to-analog converter, the control amount is reconstructed at discrete points to obtain a discrete sampling sequence, and the discrete sampling sequence is synthesized into a driving waveform to obtain a standard driving voltage waveform; Applying the standard driving voltage waveform to the gate end of the gallium nitride power device, setting 8 sampling channels between the gate and source, obtaining a gate voltage response curve, and performing threshold detection on the gate voltage response curve to obtain a switching time data point; Perform difference calculation on adjacent switch time data points, take the time interval between the control signal time and the switch completion time as the delay time, and obtain the actual drive delay value; The gate voltage response curve is multiplied by the gate charging current, and the energy value is accumulated within the switching cycle to obtain the single-cycle switching energy. The single-cycle switching energy is multiplied by the switching frequency value, and the power loss per unit time is calculated to obtain the actual switching loss value.

6. The low-delay control method of the gallium nitride gate driver according to claim 5, characterized in that: The Gaussian process model is constructed based on the actual driving delay value and the actual switching loss value, and the posterior probability distribution is calculated by iterative sampling to obtain the updated control parameters, including: Normalizing the actual driving delay value and the actual switching loss value, and mapping the normalized data to a Gaussian space to obtain a two-dimensional Gaussian random field; Establishing a Gaussian process prior distribution model based on the two-dimensional Gaussian random field to obtain a prior probability function; Performing a Bayesian update operation on the prior probability function and the sample observation value, calculating the conditional probability, obtaining the posterior distribution function, and generating a probability sampling sequence according to the posterior distribution function; Calculate the joint distribution probability density of delay and loss according to the probability sampling sequence, and construct a two-dimensional probability density matrix; Performing a maximum a posteriori probability search on the two-dimensional probability density matrix, locating the optimal point of delay loss, and obtaining the optimal control parameter point; A safety constraint region is constructed based on the optimal control parameter point to obtain a parameter feasible domain, and gradient descent optimization is performed within the parameter feasible domain. The control parameter vector is updated according to a preset learning rate to obtain updated control parameters.

7. The low-delay control method of the gallium nitride gate driver according to claim 6, characterized in that: The low-latency control method of the gallium nitride gate driver further includes: The updated control parameters are divided into master control parameters and slave control parameters according to the driving function, the master control parameters are allocated to the driver with the highest power level as the master control unit, and the slave control parameters are allocated to other drivers as slave control units to obtain a hierarchical control unit group; Establishing a distributed network topology structure for the hierarchical control unit group, placing the master control unit at the network center node and the slave control units at the peripheral nodes, to obtain a driver control network; Configure an intelligent prediction controller IPC module for each node unit in the driver control network, set control parameters and response thresholds for the intelligent prediction controller IPC module, and obtain a node unit prediction model; Performing time domain decomposition operation on the node unit prediction model, dividing the control period into n time intervals, setting the length of each time interval to Δt=100ns, and obtaining a control timing table; Input the control timing table into the phase mapper, assign a phase offset φi to each slave control unit, where φi∈[0,2π], and obtain a phase allocation sequence; Generate a trigger timing matrix according to the phase allocation sequence to obtain the driver operation timing, perform spatial distance weighted calculation on the driver operation timing, construct a weight coefficient matrix according to the physical distance between the drivers, and obtain the space-time coupling constraint condition; The time-space coupling constraint condition is combined with the phase allocation sequence to generate a multi-drive cooperative control strategy.

8. A low-latency control system for a gallium nitride gate driver, characterized in that: A method for executing a low-latency control method of a gallium nitride gate driver according to any one of claims 1 to 7, wherein the low-latency control system of the gallium nitride gate driver comprises: A feature extraction module is used to perform feature extraction and nonlinear mapping processing on the driving voltage, gate charge, and switching timing parameters of the gate driver to obtain time domain characteristic data and parameter distribution model; A calculation module, used for performing duty cycle modulation function calculation on the time domain characteristic data and the parameter distribution model to obtain a rising edge duty cycle parameter and a falling edge duty cycle parameter; A solution module, used for performing dynamic programming solution on a state transfer equation based on the rising edge duty cycle parameter and the falling edge duty cycle parameter to obtain an optimal control sequence, wherein the state transfer equation includes three variables: gate voltage, gate charge and drive delay; An acquisition module, used to drive and control the gate driver according to the optimal control sequence, and to acquire operation status data through multiple monitoring points to obtain an actual drive delay value and an actual switching loss value; A construction module is used to construct a Gaussian process model based on the actual driving delay value and the actual switching loss value, and calculate the posterior probability distribution through iterative sampling to obtain updated control parameters.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and is characterized in that when the processor executes the computer program, the low-latency control method of the gallium nitride gate driver according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the processor is enabled to execute the low-delay control method for the gallium nitride gate driver according to any one of claims 1 to 7.

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