Image sensor, reading method thereof and electronic equipment

Abstract

The invention provides an image sensor. The image sensor comprises a plurality of pixel units arranged in an array and at least one gain control circuit, the pixel unit comprises at least one photosensitive unit, a floating diffusion node, a gain control transistor, a source following transistor and a reset transistor, and the photosensitive unit is connected to the floating diffusion node through a corresponding transmission transistor. The reset transistor and the gain control transistor are sequentially connected to the floating diffusion node and are jointly connected with the gate end of the source following transistor; for each row of pixel units in the same column, every X rows of pixel units share the same column line, and the adjacent (X * Y) rows of pixel units are read out through Y column lines respectively; and the gain control circuit is connected with the drain ends of the gain control transistors in the K rows of pixel units in the same column. The problems that an existing image sensor cannot output finer and smoother images based on different highlight scenes, a finally synthesized image has a trailing phenomenon, and circuit reading noise is large are solved.

Description

Technical Field

[0001] The present application relates to the technical field of image sensors, and in particular to an image sensor and a reading method thereof, and an electronic device. Background Art

[0002] Image sensors are used in a variety of electronic products (such as smart phones, digital cameras, video surveillance equipment, intelligent AI, face recognition, drones, etc.) to capture and recognize images.

[0003] With the continuous improvement of process technology and pixel performance, the pixel full well capacity of traditional image sensors is getting higher and higher; in the signal readout stage, high conversion gain is usually used to obtain dark light scenes of the image, and low conversion gain is used to obtain bright light scenes of the image. However, with the improvement of pixel full well capacity, the demand for low conversion gain to obtain bright light scenes is getting higher and higher.

[0004] like Figure 1 As shown, in the existing image sensor 10 with dual gain conversion, multiple pixel units 100 are arranged in a matrix, and each pixel unit 100 in each column is read out through the same column line. Among them, the circuit structure of each pixel unit is the same, such as Figure 2 As shown, it includes: a photodiode PD, a transfer transistor M1, a floating diffusion node FD, a reset transistor M2, a gain control transistor M3, a source follower transistor M4 and a selection transistor M5. In addition, a capacitor Ca is also arranged between the reset transistor M2 and the gain control transistor M3. The capacitor Ca can be a parasitic capacitor or a device capacitor.

[0005] The above pixel unit 100 has two conversion gain modes when working, namely, a high conversion gain (HCG) mode and a low conversion gain (LCG) mode; taking any row of pixel units as an example, wherein:

[0006] In HCG mode: the gain control transistor M3 is turned off, and the gain capacitance value of the pixel unit in this row is the capacitance value of the floating diffusion node in this row, that is, Cfd. At this time, the circuit works in HCG mode and can collect images in dark light scenes;

[0007] In LCG mode: the gain control transistor M3 is turned on, and the charge storage capacity is improved by connecting the capacitor Ca, so that the gain capacitance value of the pixel unit in this row is the sum of the capacitance value of the floating diffusion node in this row and the capacitor Ca, that is, Cfd+Ca. At this time, the circuit works in LCG mode and can capture images in high-light scenes.

[0008] Existing image sensors can achieve a large dynamic range by setting HCG mode and LCG mode, but the pixel full well capacity in LCG mode is fixed and cannot be adjusted for different high-light scenes, which makes the output image fineness insufficient as the demand for high-light scenes gradually increases.

[0009] In addition, each pixel unit 100 in the same column is read out through the same column line. When multiple frames are read, there is a time difference between the reading processes, which will cause a tailing phenomenon in the final synthesized image, and the circuit has a large reading noise. Summary of the invention

[0010] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide an image sensor and a reading method thereof, and an electronic device, so as to solve the problems that the existing image sensors are unable to output more delicate images based on different high-light scenes, the final synthesized image has a tailing phenomenon, and the circuit reading noise is large.

[0011] To achieve the above-mentioned and other related purposes, the present application provides an image sensor, comprising a plurality of pixel units arranged in an array and at least one gain control circuit, wherein:

[0012] The pixel unit comprises: at least one photosensitive unit, a floating diffusion node, a gain control transistor, a source follower transistor and a reset transistor, wherein the photosensitive unit is connected to the floating diffusion node through a corresponding transmission transistor, and the reset transistor and the gain control transistor are sequentially connected to the floating diffusion node and are commonly connected to the gate terminal of the source follower transistor;

[0013] The pixel units in each row in the same column share the same column line in every X rows, and the pixel units in adjacent (X×Y) rows are read out through Y column lines respectively, where X is an integer greater than or equal to 1, and Y is an integer greater than or equal to 2;

[0014] The gain control circuit is connected to the drain ends of the gain control transistors in the K rows of pixel units in the same column, where K is an integer greater than or equal to 2.

[0015] Optionally, the gain control circuit includes (K-1) segments of connecting lines, and the (K-1) segments of the connecting lines are sequentially connected to the drain ends of the gain control transistors in the K rows of pixel units.

[0016] Optionally, among the (K-1) sections of connecting wires, at least one section of the connecting wires is provided with a switching transistor.

[0017] Optionally, when K is an even number, in the (K-1)th section of the connecting lines, a switching transistor is provided only on the connecting line between the pixel units in the K / 2th row and the pixel units in the (K / 2+1)th row.

[0018] Optionally, in the (K-1) sections of connecting wires, each section of the connecting wires is provided with a switching transistor.

[0019] Optionally, in a direction perpendicular to the pixel unit, the orthographic projection of the connecting line overlaps with the orthographic projection of the photosensitive unit, and a ratio of the overlapping area is no greater than 50%.

[0020] Optionally, every K rows of pixel units in the same column constitute a first pixel group, and each of the first pixel groups corresponds to one of the gain control circuits.

[0021] Optionally, each (X×Y) row of pixel units in the same column constitutes a second pixel group, and corresponding rows in each of the second pixel groups are connected to the same column line.

[0022] Optionally, when the number of the photosensitive units in the pixel unit is greater than one, the plurality of photosensitive units are configured to receive light of the same color; wherein the plurality of photosensitive units constitute a shared pixel unit.

[0023] Optionally, the number of the photosensitive units in the pixel unit is four, and the four photosensitive units are arranged in a 2×2 array; wherein the photosensitive unit includes a photosensitive element and a transfer transistor, and the photosensitive element is connected to the floating diffusion node through the transfer transistor.

[0024] Optionally, the pixel unit further includes a selection transistor connected to a source terminal of the source follower transistor.

[0025] The present invention further provides a method for reading an image sensor as described in any one of the above items, which reads image signals of K rows of pixel units row by row, wherein the image signals include a reset signal and a pixel signal.

[0026] Optionally, the image sensor reading method includes:

[0027] Turning on the reset transistor and the gain control transistor in the pixel unit of the selected row to reset the floating diffusion node in the pixel unit of the selected row; turning off the gain control transistor in the pixel unit of the selected row to read the reset signal of the pixel unit of the selected row;

[0028] The transfer transistors in the pixel units in the selected row are turned on, and charge transfer is performed in a high conversion gain mode and pixel signals of the pixel units in the selected row are read.

[0029] Optionally, the reset transistors in the pixel units in the K rows are always turned on; when the gain control transistors in the pixel units in the selected row are turned off, the gain control transistors in the pixel units in other rows except the selected row are turned on; the pixel units also include selection transistors, and when reading the reset signal and the pixel signal, the selection transistors in the pixel units in the selected row are turned on, and the selection transistors in the pixel units in other rows except the selected row are turned off.

[0030] Optionally, the image sensor reading method includes:

[0031] Turning on the reset transistor and the gain control transistor in the pixel unit of the selected row, turning off the gain control transistor in the pixel units of other rows except the selected row, and performing a reset operation on the floating diffusion node in the pixel unit of the selected row; turning off the reset transistor in the pixel unit of the selected row, and reading a reset signal of the pixel unit of the selected row;

[0032] The transfer transistors in the pixel units of the selected row are turned on, and charge transfer is performed in a first low conversion gain mode and pixel signals of the pixel units of the selected row are read.

[0033] Optionally, when the gain control circuit further includes a switching transistor, before performing a reset operation on the floating diffusion node in the pixel unit of the selected row, a step of turning off all the switching transistors is also included.

[0034] Optionally, the pixel unit further includes a selection transistor, and when reading the reset signal and the pixel signal, the selection transistor in the pixel unit of the selected row is turned on, and the selection transistors in the pixel units of other rows except the selected row are turned off.

[0035] Optionally, the image sensor reading method includes:

[0036] Turning on the gain control transistors in the pixel units of the K rows, turning on the reset transistors in the pixel units of the selected row, and performing a reset operation on the floating diffusion nodes in the pixel units of the selected row; turning off the reset transistors in the pixel units of the selected row, and reading the reset signals of the pixel units of the selected row;

[0037] The transfer transistors in the pixel units in the selected row are turned on, charge transfer is performed in a Zth lowest conversion gain mode, and pixel signals of the pixel units in the selected row are read, wherein Z is an integer greater than or equal to K.

[0038] Optionally, when the gain control circuit further includes a switching transistor, before performing a reset operation on the floating diffusion node in the pixel unit of the selected row, a step of turning on all the switching transistors is further included.

[0039] Optionally, the pixel unit also includes a selection transistor. When reading the reset signal and the pixel signal, the selection transistor in the pixel unit of the selected row is turned on, and the selection transistors in the pixel units of other rows except the selected row are turned off, or the selection transistors in the pixel units of row K are always turned on.

[0040] The present invention also provides an electronic device, comprising the image sensor as described in any one of the above items.

[0041] As described above, the image sensor and its reading method and electronic device of the present application provide more and richer low conversion gains by using a gain control circuit in the image sensor to connect the drain ends of the gain control transistors in the K rows of pixel units located in the same column. In other words, by controlling the number of capacitors connected to one end of the gain control transistor in the LCG mode of the image sensor to adjust the conversion gain and thus improve the dynamic range, more delicate images can be output for different high-light scenes; the image signal readout efficiency of the present invention is higher, and the noise level of the circuit is lower, which can further improve the performance of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 The figure is a schematic diagram of the structure of the image sensor described in the background technology.

[0043] Figure 2 The circuit diagram of a pixel unit in an image sensor described in the background art is shown in FIG.

[0044] Figure 3 A schematic diagram of the structure of an image sensor provided in this application.

[0045] Figure 4 A schematic diagram of the structure of another image sensor provided in this application.

[0046] Figure 5-Figure 9 For this application Figure 3 The circuit diagram of the pixel unit in the image sensor is shown, wherein: Figure 5-Figure 9 Only one of the four photosensitive cells is shown.

[0047] Figure 10-12 This is a schematic diagram of the structure of the photosensitive unit in the pixel unit provided in this application.

[0048] Figure 13-Figure 16 A schematic diagram of the circuit layout of the image sensor provided in this application.

[0049] Figure 17-Figure 19 Schematic diagrams of the structures of three more image sensors provided in this application.

[0050] Fig. 20 A timing diagram of an image sensor provided in the present application for reading an image signal in a high conversion gain mode.

[0051] Fig.21 A timing diagram of an image sensor provided by the present application reading an image signal in a first low conversion gain mode.

[0052] Fig. 22 and Fig.23 A timing diagram of an image sensor provided by the present application for reading an image signal in a Zth lowest conversion gain mode.

[0053] Component number description

[0054] 10 Image Sensor

[0055] 100 pixel unit

[0056] 101 Photosensitive unit

[0057] 102 Orthographic projection of connecting lines

[0058] 200 Gain Control Circuit DETAILED DESCRIPTION

[0059] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0060] See also Figures 3 to 23 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0061] Embodiment 1

[0062] like Figure 3-Figure 9As shown, this embodiment provides an image sensor 10, which includes a plurality of pixel units 100 arranged in an array and at least one gain control circuit 200. The circuit structure of each pixel unit 100 is the same, including: at least one photosensitive unit 101, a floating diffusion node (such as FD1), a reset transistor M2, a gain control transistor M3 and a source follower transistor M4; further, it also includes a selection transistor M5.

[0063] The photosensitive unit 101 is connected between the floating diffusion node (such as FD1) and the reference ground, and is used to generate charges according to the photoelectric effect and transfer the output. Specifically, the photosensitive unit 101 includes a photosensitive element PD and a transfer transistor M1, and the photosensitive element PD is connected to the floating diffusion node through the transfer transistor M1 (for example, one end of the photosensitive element PD is connected to the reference ground, and the other end is connected to the source end of the transfer transistor M1, the gate end of the transfer transistor M1 is connected to the transmission control signal TX1, and the drain end is connected to the floating diffusion node FD1); wherein the photosensitive element PD converts the light signal carrying the image information into charges according to the photoelectric effect, and the transfer transistor M1 is controlled by the transmission control signal TX1 to open and transfer the charges to the floating diffusion node FD1.

[0064] It can be understood that the photosensitive element PD mentioned in the present application can be any one of a photodiode, a grating or a photoconductor. As a preferred solution, the photosensitive element PD in this embodiment is a photodiode. At this time, the anode end of the photodiode is connected to the reference ground, and the cathode end is connected to the source end of the transfer transistor.

[0065] In practical applications, the number of photosensitive units 101 in the pixel unit 100 can be designed according to actual needs, such as 1, 2, 3, 4, 8, etc.; when the pixel unit 100 includes one photosensitive unit 101, the power consumption of the pixel unit 100 is lower, but correspondingly, the photoelectric conversion efficiency is also lower; when the pixel unit 100 includes more than one photosensitive unit 101, the multiple photosensitive units 101 are configured to receive light of the same color, and the multiple photosensitive units 101 constitute a shared pixel unit, so that the fill factor of the pixel unit can be improved, thereby improving the photoelectric conversion efficiency of the image sensor, such as Figure 10-12 shown.

[0066] As a preferred solution, in the image sensor 10 disclosed in this embodiment, the pixel unit 100 includes four photosensitive units 101, and the four photosensitive units 101 are arranged in a 2×2 array, such as Fig.11As shown. Of course, the four photosensitive units 101 can also be arranged in sequence horizontally instead of in a 2×2 array. The embodiment of the present application does not limit the arrangement form or shape of the multiple photosensitive units 101 in the pixel unit 100. In other schemes, the number of photosensitive units included in the pixel unit 100 can also be an odd number. By setting multiple photosensitive units in the pixel unit, the photoelectric conversion efficiency of the image sensor 10 can be effectively improved.

[0067] In the image sensor 10 provided in this embodiment, the four photosensitive units 101 in the same pixel unit 100 are configured to receive light of the same color, which may be red (R), green (G), or blue (B). In other implementations, the four photosensitive units 101 may also be configured to receive white (W) light. Specifically, the color of the photosensitive unit 101 is realized by adding a color filter of a corresponding color to the optical path corresponding to the pixel unit, and by accurately selecting a small range of wavelength bands of light waves to pass through during the process of collecting light signals by the photosensitive unit, and reflecting other wavelength bands that are not desired to pass through.

[0068] In some embodiments, Figure 3 and Figure 4 As shown, four pixel units 100 are grouped together and arranged in an array, the difference being that: Figure 3 In the image sensor 10 shown, each group of four pixel units 100 is configured to receive three primary color lights of red (R), green (G), and blue (B). Figure 4 In the image sensor 10 shown, the receivable white (W) light is increased compared with the former. Receiving white (W) light can ensure the clarity of photos in a low-light environment when the image sensor 10 is in working state, and at the same time help to improve the dynamic range of the image sensor 10.

[0069] in, Figure 3 The image sensor shown adopts a conventional Bayer array pixel unit arrangement, that is, four pixel units 100 in each 2×2 pixel array receive red (R), green (G), blue (B) and green (G) light respectively; Figure 4 In the image sensor shown, four pixel units 100 in each 2×2 pixel array receive red (R), green (G), blue (B) and white (W) light respectively. The pixel arrangement provided in this embodiment is only an example. In fact, other forms of pixel array arrangement can also be used.

[0070] The floating diffusion node (eg, FD1 ) includes a capacitor (eg, Cfd1 ) for storing the charge transferred from the transfer transistor M1 and completing the conversion from charge to voltage.

[0071] The reset transistor M2 and the gain control transistor M3 are sequentially connected to the floating diffusion node and are connected to the gate terminal of the source follower transistor M4. For example, the gate terminal of the reset transistor M2 is connected to the reset control signal RST1, the drain terminal is connected to the power supply VDD, and the source terminal is connected to the drain terminal of the gain control transistor M3; the gate terminal of the gain control transistor M3 is connected to the gain control signal DCG1, and the source terminal is connected to the floating diffusion node FD1; the gate terminal of the source follower transistor M4 is connected to the floating diffusion node FD1, the drain terminal is connected to the power supply VDD, and the source terminal outputs a voltage signal (such as a reset signal and a pixel signal). Among them,

[0072] The reset transistor M2 is used to reset the voltage of the floating diffusion node (such as FD1) according to the reset control signal (such as RST1), and provides the voltage of the power supply VDD as the reset voltage to achieve the potential reset of the floating diffusion node when the gain control transistor M3 is turned on.

[0073] The gain control transistor M3 is used to switch each pixel unit 100 between a high conversion gain mode and a low conversion gain mode. When turned off, the pixel unit is switched to a high conversion gain (HCG) mode, and when turned on, the pixel unit is switched to a low conversion gain (LCG) mode. It should be noted that in the image sensor provided in this embodiment, there is not only one LCG mode, but multiple LCG modes, such as a first low conversion gain (LCG1) mode, a second low conversion gain (LCG2), etc., and the relevant description can be found below.

[0074] The source follower transistor M4 is used to transfer the voltage stored at the floating diffusion node (converted from the charge transferred by the transfer transistor M1) to the source terminal of the source follower transistor M4 and amplify the output. It should be noted that when the pixel unit 100 does not include the selection transistor M5, the source terminal of the source follower transistor M4 is connected to the corresponding column line; when the pixel unit 100 includes the selection transistor M5, the source terminal of the source follower transistor M4 is connected to the drain terminal of the selection transistor M5.

[0075] As a preferred solution, the pixel unit 100 provided in the embodiment of the present application includes a selection transistor M5, wherein the selection transistor M5 is connected to the source terminal of the source follower transistor M4; for example, the gate terminal of the selection transistor M5 is connected to the row selection signal RS1, the drain terminal is connected to the source terminal of the source follower transistor M4, and the source terminal is connected to the corresponding column line; the selection transistor M5 is controlled to be turned on by the row selection signal RS1 to select and output the voltage signal output by the source follower transistor M4. When it is necessary to output several rows of pixel units 100 in the same column of the image sensor 10 in sequence according to a predetermined order, the output can be performed in sequence by turning on or off the selection transistors M5 of different rows.

[0076] The gain control circuit 200 is connected to the drain end of the gain control transistor M3 in the K rows of pixel units 100 located in the same column, and is used to adjust the pixel full well capacity of the floating diffusion node of the corresponding row, so as to provide more conversion gains and enrich the low conversion gain mode; wherein K is an integer greater than or equal to 2.

[0077] In one embodiment, each column includes K rows, in which case the number of gain control circuits 200 is one; in another embodiment, each column includes more than K rows, in which case every K rows of pixel units 100 in the same column constitute a first pixel group, and each first pixel group corresponds to a gain control circuit 200, that is, there are multiple gain control circuits 200 in each column.

[0078] With respect to one column, no matter whether the number of gain control circuits 200 is one or more, the principle of regulating the full well capacity of the floating diffusion node pixel of the corresponding row remains unchanged. It is just that when the gain control circuit 200 is connected to more rows, more conversion gains can be provided, but the corresponding control will be more complicated. In fact, an image sensor generally includes many rows and columns of pixel units. Considering the conversion gain and control complexity, a plurality of first pixel groups are usually arranged in one column, and the first pixel group may include pixel units of different numbers of rows, such as 2 rows, 3 rows, or 4 rows.

[0079] In the K rows of pixel units in this embodiment, any row of pixel units includes (Z+1) different conversion gain modes, namely, one high conversion gain mode and Z low conversion gain modes, where Z is an integer greater than or equal to K; it should be noted that the value of Z is determined by the value of K and the circuit structure of the gain control circuit 200, for example, when the gain control circuit 200 includes (K-1) segments of connecting lines, Z=K, and when the gain control circuit 200 also includes a switching transistor, Z>K.

[0080] As an example, Figure 5 and Figure 7 As shown, the gain control circuit 200 includes (K-1) segments of connecting lines, and the (K-1) segments of connecting lines are sequentially connected to the drain terminals of the gain control transistors M3 in K rows of pixel units 100 .

[0081] In the present embodiment, in K rows of pixel units 100, a connecting line is set between the drain ends of the gain control transistors M3 of the adjacent rows of pixel units 100 to form a capacitor. Since the connecting line is located at a high-resistance node, the characteristic impedance can be reduced by adjusting the line width of the connecting line to form a capacitor that meets the gain conversion switching requirements, or a capacitor that meets the gain conversion switching requirements can be formed by setting a device capacitor. It can be understood that the connecting line may not be limited to one routing line, and it is only required to achieve connectivity with the gain control transistors M3 of the adjacent rows when the gain control transistors M3 of the adjacent rows of pixel units 100 are turned on.

[0082] Assume that the capacitance value of the floating diffusion node of each row of pixel units 100 in K rows of pixel units is Cfd1-Cfdk, and the capacitance value of the (K-1) segment of connecting line is Ca; then:

[0083] When all the gain control transistors M3 in the K-row pixel units 100 are turned off, the gain capacitance value of the first-row pixel units 100 is the capacitance value of the floating diffusion node of the row, that is, Cfd1, and the conversion gain is q / Cfd1, where q is the charge amount generated in the first-row pixel units when the photoelectric effect occurs. At this time, the conversion gain is the largest, so it can be used as a high conversion gain (HCG) mode;

[0084] When the gain control transistor M3 in the first row of pixel units 100 is turned on, and the gain control transistors M3 in the remaining (K-1) rows of pixel units 100 are turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row and the capacitance value of the (K-1) segment of the connecting line, that is, Cfd1+Ca. Since the capacitance value Ca of the (K-1) segment of the connecting line is added, its conversion gain is q / (Cfd1+Ca), which is smaller than the conversion gain in the HCG mode, so it can be used as the first low conversion gain (LCG1) mode to adapt to providing a lower conversion gain in a relatively bright environment, but the LCG1 mode is the mode with the highest conversion gain among all low conversion gain modes;

[0085] When the gain control transistors M3 in the first two rows of pixel units 100 are turned on and the gain control transistors M3 in the remaining rows of pixel units 100 are turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the first two rows of pixel units 100 and the capacitance value of the (K-1) segment connecting line, that is, Cfd1+Ca+Cfd2, and its conversion gain is q / (Cfd1+Ca+Cfd2). Since the drain ends of the gain control transistors M3 of only two adjacent pixel units 100 are connected to each other through corresponding connecting lines, the conversion gain at this time is lower than that of the LCG1 mode, which is the second low conversion gain (LCG2) mode.

[0086] For the case of K=2, the LCG2 mode is the mode with the lowest conversion gain in the low conversion gain mode. For the case where K is greater than 2, in fact, in the previous mode, the gain control transistor M3 in the next row of pixel units 100 can be turned on to set a lower conversion gain; for example, the third low conversion gain (LCG3) mode is that the gain control transistors M3 in the first three rows of pixel units 100 are turned on, and the gain control transistors M3 in the remaining rows of pixel units 100 are turned off. At this time, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node itself of the first three rows of pixel units 100 and the capacitance value of the (K-1) segment connecting line, that is, Cfd1+Ca+Cfd2+Cfd3, and its conversion gain is q / (Cfd1+Ca+Cfd2+Cfd3), which is lower than the LCG2 mode.

[0087] And so on, until all the gain control transistors M3 in the K-row pixel units 100 are turned on, the K-row pixel units 100 will share the capacitance of each other's floating diffusion nodes. At this time, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the K-row pixel units 100 itself and the capacitance value of the (K-1)-segment connecting line, that is, Cfd1+Ca+Cfd2+…+Cfdk, and its conversion gain is q / (Cfd1+Ca+Cfd2+…+Cfdk), as the Zth low conversion gain (LCGz) mode, the LCGz mode is the mode with the lowest conversion gain among all low conversion gain modes.

[0088] It can be understood that as the number of connected gain control transistors M3 increases, the gain capacitance value of the corresponding row pixel unit 100 also increases, thereby providing a greater expansion for the gain capacitance value, thereby making the conversion gain lower; by providing more and richer low conversion gain modes, more delicate images can be output for different high-light scenes.

[0089] Based on the same principle, the pixel units 100 in other rows in row K can also provide more low conversion gain modes. By controlling the opening and closing of the gain control transistor M3 in each row of pixel units 100, the gain capacitance value of each row of pixel units 100 is controlled, so that the pixel full well capacity of the image sensor 10 is more controllable; therefore, the image sensor 10 provided in this embodiment can provide more gain modes, so as to adapt to more diverse scene usage requirements.

[0090] As another example, Figure 6 , Figure 8 and Fig. 9As shown, among the (K-1) segments of connecting wires, at least one segment of the connecting wire is provided with a switch transistor; when the switch control signal is turned off, the switch transistor is controlled to separate the segment of the connecting wire into at least two segments of connecting sub-wires. Since the connecting wire itself has a capacitance value, in some embodiments, the connecting wire is also provided with a device capacitor, so each segment of the connecting sub-wire separated can provide a new conversion gain, thereby expanding the pixel full well capacity and the selectable range of the gain mode of the pixel unit 100. It can be understood that, for each additional switch transistor, at least a new conversion gain and a corresponding gain selection mode can be added to the image sensor 10.

[0091] In one embodiment, Figure 6 and Figure 8 As shown, in the (K-1) segment connecting line, each segment connecting line is provided with a switch transistor; wherein, the number of switch transistors on each segment connecting line can be 1, or a plurality greater than 1, and at the same time, the number of switch transistors on each segment connecting line can be the same or different, so that the pixel unit 100 in the image sensor 10 has more adjustable gain capacitance values, thereby making the image sensor 10 more delicate when dealing with high-light images. As a preferred solution, in this embodiment, each segment connecting line has only one switch transistor.

[0092] exist Figure 8 In the figure, K=4, that is, the gain control circuit 200 includes 3 connecting lines and 3 switching transistors arranged on the 3 connecting lines, the 3 connecting lines sequentially connect the drain ends of the gain control transistors M3 in the first to fourth rows of pixel units 100; the capacitance values ​​of the floating diffusion nodes of the first to fourth rows of pixel units 100 are respectively: Cfd1, Cfd2, Cfd3, Cfd4, the 3 connecting lines are divided into 6 connecting sub-lines by the switching transistors M01, M02, M03, the capacitance values ​​of the 6 connecting sub-lines are respectively Cb, Cc, Cd, Ce, Cf, Cg, and Ca=Cb+Cc+Cd+Ce+Cf+Cg;

[0093] When the gain control transistors M3 in the four rows of pixel units 100 are all turned off, the gain capacitance value of the first row of pixel units 100 is the capacitance value of the floating diffusion node of the row, that is, Cfd1, and its conversion gain is q / Cfd1. At this time, the image sensor 10 works in the HCG mode;

[0094] When the gain control transistor M3 in the first row of pixel units 100 is turned on, and the switch transistor M01 provided on the first section of the connecting line is turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row itself and the capacitance value of the first connecting sub-line separated by the switch transistor M01 from the first section of the connecting line, that is, Cfd1+Cb, and its conversion gain is q / (Cfd1+Cb), which is lower than the conversion gain in the HCG mode, serving as the first low conversion gain (LCG1) mode, and the LCG1 mode is the mode with the highest conversion gain among all low conversion gain modes;

[0095] When the gain control transistor M3 in the first row of pixel units 100 is turned on, the switch transistor M01 set on the first section of the connecting line is turned on, and the gain control transistor M3 in the second row of pixel units 100 and the switch transistor M02 set on the second section of the connecting line are turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row itself, the capacitance value of the first section of the connecting line and the capacitance value of the first connecting sub-line separated by the switch transistor M02 from the second section of the connecting line, that is, Cfd1+Cb+Cc+Cd, and its conversion gain is q / (Cfd1+Cb+Cc+Cd), which is lower than the aforementioned conversion gain, as the second low conversion gain (LCG2) mode;

[0096] When the gain control transistor M3 in the first row of pixel units 100 is turned on, the switch transistor M01 set on the first section of the connecting line is turned on, the switch transistor M02 set on the second section of the connecting line is turned on, the gain control transistors M3 in the second and third rows of pixel units 100 are turned off, and the switch transistor M03 set on the third section of the connecting line is turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row itself, the capacitance value of the first section of the connecting line, the capacitance value of the second section of the connecting line and the capacitance value of the first connecting sub-line separated by the switch transistor M03 from the third section of the connecting line, that is, Cfd1+Cb+Cc+Cd+Ce+Cf, and its conversion gain is q / (Cfd1+Cb+Cc+Cd+Ce+Cf), which is lower than the aforementioned conversion gain, as the third low conversion gain (LCG3) mode;

[0097] By analogy, by turning on the gain control transistor M3 in the corresponding row of pixel units 100 and / or the switch transistor on the corresponding segment connection line, the gain capacitance value of the first row of pixel units 100 can be adjusted, thereby generating more low conversion gain modes;

[0098] Until the gain control transistors M3 in the four rows of pixel units 100 are all turned on and the three switching transistors on the three connecting lines are all turned on, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node itself of the four rows of pixel units 100 and the capacitance value of the three connecting lines, that is, Cfd1+Cfd2+Cfd3+Cfd4+Ca, and its conversion gain is q / (Cfd1+Cfd2+Cfd3+Cfd4+Ca), which is the Zth low conversion gain (LCGz) mode, and the LCGz mode is the mode with the lowest conversion gain among all low conversion gain modes.

[0099] In another embodiment, in the (K-1) segment of connecting lines, not every segment of connecting lines is provided with a switching transistor, but only one or several segments of connecting lines are provided with a switching transistor; of course, the number of switching transistors may be 1 or a plurality greater than 1. As a preferred solution, when K is an even number, in the (K-1) segment of connecting lines, only the connecting line between the K / 2th row of pixel units 100 and the (K / 2+1)th row of pixel units 100 is provided with a switching transistor; by providing only the connecting line between the K / 2th row of pixel units and the (K / 2+1)th row of pixel units in the (K-1) segment of connecting lines with a switching transistor, the area of ​​the pixel array composed of a plurality of pixel units 100 in the image sensor 10 can be maximized while increasing the conversion gain of the image sensor 10, reducing the actual scale loss of the pixel array due to the increase in the number of switching transistors in the gain control circuit, thereby improving the photosensitivity efficiency of the image sensor 10.

[0100] exist Fig. 9 In the embodiment, K=4, the gain control circuit 200 includes three connecting lines and a switch transistor, the switch transistor is arranged on the second connecting line between the second row of pixel units 100 and the third row of pixel units 100, assuming that the capacitance values ​​of the floating diffusion nodes of the four rows of pixel units 100 are Cfd1, Cfd2, Cfd3, and Cfd4, respectively, the capacitance value of the first connecting line is (Cb+Cc), the second connecting line is divided into two connecting sub-lines by the switch transistor, the two connecting sub-lines correspond to a capacitance value Cd and Ce, respectively, the capacitance value of the third connecting line is (Cf+Cg), and Ca=Cb+Cc+Cd+Ce+Cf+Cg; wherein,

[0101] When the gain control transistors M3 in the four rows of pixel units 100 are all turned off, the gain capacitance value of the first row of pixel units 100 is the capacitance value of the floating diffusion node of the row, that is, Cfd1, and its conversion gain is q / Cfd1. At this time, the image sensor 10 works in the HCG mode;

[0102] When the gain control transistor M3 in the first row of pixel units 100 is turned on, the switch transistor M0 is turned off, and the gain control transistor M3 in the second row of pixel units 100 is turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row, the capacitance value of the first section of the connection line, and the capacitance value of the first connection sub-line separated by the switch transistor M0 from the second section of the connection line, that is, Cfd1+Cb+Cc+Cd, and its conversion gain is q / (Cfd1+Cb+Cc+Cd), which is lower than the conversion gain in the HCG mode, as the first low conversion gain (LCG1) mode, and the LCG1 mode is the mode with the highest conversion gain among all low conversion gain modes;

[0103] When the gain control transistor M3 in the first row of pixel units 100 is turned on, the switch transistor M0 is turned on, and the gain control transistors M3 in the other rows of pixel units are turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the row, the capacitance value of the first section of the connecting line, the capacitance value of the second section of the connecting line, and the capacitance value of the third section of the connecting line, that is, Cfd1+Ca, and its conversion gain is q / (Cfd1+Ca), which is lower than the aforementioned conversion gain, as the second low conversion gain (LCG2) mode;

[0104] When the gain control transistors M3 in the first and second rows of pixel units 100 are turned on and the switch transistors M0 are turned off, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion nodes of the first two rows, the capacitance value of the first section of the connection line, and the capacitance value of the first connection sub-line separated by the switch transistor M0 from the second section of the connection line, that is, Cfd1+Cb+Cc+Cfd2+Cd, and its conversion gain is q / (Cfd1+Cb+Cc+Cfd2+Cd), which is lower than the aforementioned conversion gain, as the third low conversion gain (LCG3) mode;

[0105] When the gain control transistors M3 in the first two rows of pixel units 100 are turned on, the gain control transistors M3 in the other rows of pixel units 100 are turned off, and the switch transistor M0 is turned on, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the first two rows of pixel units 100, the capacitance value of the first section of the connecting line, the capacitance value of the second section of the connecting line, and the capacitance value of the third section of the connecting line, that is, Cfd1+Cfd2+Ca, and its conversion gain is q / (Cfd1+Cfd2+Ca), which is lower than the aforementioned conversion gain, as the fourth low conversion gain (LCG4) mode;

[0106] When the gain control transistors M3 in the first three rows of pixel units 100 are turned on, the gain control transistors M3 in the fourth row of pixel units 100 are turned off, and the switch transistors M0 are turned on, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance value of the floating diffusion node of the first three rows of pixel units 100, the capacitance value of the first section of the connecting line, the capacitance value of the second section of the connecting line, and the capacitance value of the third section of the connecting line, that is, Cfd1+Cfd2+Cfd3+Ca, and its conversion gain is q / (Cfd1+Cfd2+Cfd3+Ca), which is lower than the aforementioned conversion gain, as the fifth low conversion gain (LCG5) mode;

[0107] When the gain control transistors M3 in the four rows of pixel units 100 are all turned on and the switch transistor M0 is turned on, the gain capacitance value of the first row of pixel units 100 is the sum of the capacitance values ​​of the floating diffusion nodes of the first four rows, the capacitance values ​​of the first section of the connecting line, the capacitance values ​​of the second section of the connecting line and the capacitance values ​​of the third section of the connecting line, that is, Cfd1+Cfd2+Cfd3+Cfd4+Ca, and its conversion gain is q / (Cfd1+Cfd2+Cfd3+Cfd4+Ca), which is lower than the aforementioned conversion gain, serving as the sixth low conversion gain (LCG6) mode, and the LCG6 mode is the mode with the lowest conversion gain among all low conversion gain modes (that is, Z=6).

[0108] Specifically, in a direction perpendicular to the pixel unit, the orthographic projection 102 of the connecting line overlaps with the orthographic projection of the photosensitive unit 101, and the overlapping area ratio is not greater than 50%. Fig.13 As shown in the figure, taking four photosensitive units 101 arranged in 2×2 to form a pixel unit 100 as an example, the shaded area in the figure is the projection of the connecting line on each pixel unit 100. Considering the effective photosensitive area of ​​the photosensitive unit 101, it is necessary to control the connecting line in the direction perpendicular to the pixel unit 100, and the overlapping area ratio of the orthographic projection 102 of the connecting line and the orthographic projection of the photosensitive unit 101 is not greater than 50%, that is, the routing area of ​​the connecting line and the area ratio of the photosensitive unit 101 are less than 1:2; wherein, the routing of the connecting line can adopt a variety of distribution methods, such as Figure 14-16 shown.

[0109] It should be noted that the above examples all take the case where the capacitance value Ca of the (K-1) segment connecting line is less than the capacitance value of any floating diffusion node itself as an example, and the low conversion gain modes are sorted from high to low. However, those skilled in the art should understand that this scheme is only used as an exemplary description and is not a limitation to the embodiments of the present application. In actual applications, the capacitance value Ca of the (K-1) segment connecting line can be made greater than any floating diffusion node, or even greater than all floating diffusion nodes by adjusting the line width, line type, etc. These are all feasible and have no substantial impact on the embodiments of the present application. It is only necessary to adjust the sorting of the low conversion gain modes accordingly.

[0110] The embodiment of the present application provides more and richer low conversion gains by using the gain control circuit 200 in the image sensor 10 to connect the drain ends of the gain control transistors M3 of the K rows of pixel units 100 located in the same column. In other words, by controlling the number of capacitors connected to one end of the gain control transistors in each row of pixel units in the LCG mode of the image sensor to adjust the conversion gain and thus improve the dynamic range, more delicate images can be output in a high-light environment.

[0111] For the image sensor 10 provided in the embodiment of the present application, when outputting signals through column lines, as shown in FIG. Figure 3 , Figure 17-Figure 19 As shown, each row of pixel units 100 located in the same column shares the same column line for every X rows of pixel units 100, and adjacent (X×Y) rows of pixel units 100 are read out through Y column lines, respectively, where X is an integer greater than or equal to 1, and Y is an integer greater than or equal to 2. Such arrangement of column lines can make the readout speed faster and more efficient. Since there is no need to sample and hold the output of the pixel circuit, the KT / C noise of the circuit can be reduced, and the noise level of the circuit will be lower, which can further improve the performance of the image sensor.

[0112] In one embodiment, each column contains (X×Y) rows, and each X rows from top to bottom share a column line, and are read out through Y column lines in total. In another embodiment, each column contains more than (X×Y) rows, and in this case, each (X×Y) row of pixel units in the same column constitutes a second pixel group, and the corresponding rows in each second pixel group are connected to the same column line; wherein, Figure 3 A column line connection mode of each row pixel unit in each second pixel group when X=1 and Y=2 is shown. Fig.17 A column line connection mode of each row pixel unit in each second pixel group when X=2 and Y=2 is shown. Fig.18 A column line connection mode of each row pixel unit in each second pixel group when X=4 and Y=2 is shown. Fig.19 A column line connection mode of each row of pixel units in each second pixel group when X=1 and Y=4 is shown.

[0113] In practical applications, the values ​​of X and Y should be set according to specific requirements, for example, X is 1, 2, 4, etc., and Y is 2, 4, 8, etc., which is not limited in this embodiment.

[0114] In addition, during the readout process of the image signal, it is necessary to perform binning on the pixel units that receive the same color light, so that the sampling resolution can be reduced and the frame rate can be improved under the premise of a fixed channel bandwidth; binning readout is divided into horizontal binning readout and vertical binning readout. Horizontal binning readout is to add the charges of adjacent rows together for reading; vertical binning readout is to add the charges of adjacent columns together for reading.

[0115] This embodiment takes horizontal direction combined readout as an example. In this embodiment, the connection mode of the column line is positively correlated with the data bit width (unit: bit) of the image signal read out by the image sensor. When the data bit width of the readout image signal is Y bit, Y column lines are connected, and the color of the pixel units connected to each column line is the same. There is an equal number of row intervals between the multiple pixel units connected to each column line. For example, Figure 3 In , the data width is 2 bits, connected to 2 column lines, the pixel units connected to each column line have the same color, and the connected pixel units are separated by 1 row; Fig.19 In the embodiment, the data bit width is 4 bits, connected to 4 column lines, the pixel units connected to each column line have the same color, and the pixel units connected to each column line are spaced 3 rows apart from each other; by connecting the pixel units of the same color to the same column line, the technical effect of faster pixel merging can be achieved; it should be noted that since the column lines will increase the actual area of ​​the quantization circuit and occupy the layout area of ​​the image sensor, therefore, as a preferred solution, Y≤4, that is, the data bit width of the read image signal is 4 bits and connected to 4 column lines.

[0116] Embodiment 2

[0117] This embodiment provides a method for reading the image sensor 10 according to the first embodiment, including: reading image signals of K rows of pixel units 100 row by row. Specifically, when reading the image sensor 10 provided in the first embodiment, the image signals of the pixel units 100 in the image sensor 10 are read row by row starting from the first row; wherein the image signals include a reset signal and a pixel signal.

[0118] like Figure 5-Figure 9As shown, among the K rows of pixel units, any row of pixel units includes (Z+1) different conversion gain modes, namely, one high conversion gain mode and Z low conversion gain modes, Z≥K; it should be noted that the value of Z is determined by the K value and the gain control circuit structure, such as, for the case where the gain control circuit includes (K-1) segments of connecting lines, Z=K, and for the case where the gain control circuit also includes a switching transistor, Z>K. Below, this scheme takes any row in the K rows (such as the first row) as the selected row, and exemplifies the reading control of different conversion gain modes:

[0119] like Fig. 20 As shown, the specific steps of reading the image signal of the first row of pixel units 100 in the high conversion gain (HCG) mode are as follows: turn on the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100, and perform a reset operation on the floating diffusion node FD1 in the first row of pixel units 100; turn off the gain control transistor M3 in the first row of pixel units 100, and read the reset signal of the first row of pixel units 100 (such as at the N_1 moment); turn on the transfer transistor M1 in the first row of pixel units 100, perform charge transfer in the HCG mode and read the pixel signal of the first row of pixel units 100 (such as at the S_1 moment).

[0120] Specifically, for different circuit structures of the gain control circuit 200 (including the case of (K-1) segments of connecting lines, such as Figure 5 and Figure 7 As shown, and also includes the case of switching transistors, such as Figure 6 , Figure 8 and Fig. 9 As shown), reading the reset signal, charge transfer and reading the pixel signal are all performed during the period when the gain control transistor M3 in the first row of pixel units 100 is turned off. At this time, the gain capacitance value of the first row of pixel units 100 is the capacitance value of the floating diffusion node itself, that is, Cfd1, and its conversion gain is q / Cfd1.

[0121] When executing this step, the reset transistor M2 in the K-row pixel unit 100 is always turned on. In fact, the reset transistor M2 in each row of pixel units 100 can also be turned off after the reset operation is performed; however, since the gain control transistor M3 in each row of pixel units 100 is in a closed state when reading the reset signal and the pixel signal, even if the reset transistor M2 in each row of pixel units 100 is turned on for a long time, it will not affect the signal reading of the selected row.

[0122] When the gain control transistor M3 in the pixel unit 100 of the selected row is turned off, the gain control transistors M3 in the pixel units 100 of other rows except the selected row are turned on; in fact, the gain control transistors M3 in the pixel units 100 of each row are turned off only when reading the reset signal, transferring the charge and reading the pixel signal, and are always turned on at other times. Of course, when the gain control transistor M3 in the pixel unit 100 of the selected row is turned off, the gain control transistors M3 in the pixel units 100 of other rows can also be turned off, which has no effect on the signal reading of the selected row.

[0123] The pixel unit 100 also includes a selection transistor M5, through which the reset signal and the pixel signal are read out by row selection; when reading the reset signal and the pixel signal, the selection transistor M5 in the pixel unit 100 of the selected row is turned on, and the selection transistors M5 in the pixel units 100 of other rows except the selected row are turned off, thereby completing the readout of the reset signal and the pixel signal of the selected row.

[0124] Take the first low conversion gain (LCG1) mode as an example, where the LCG1 mode is the mode with the highest conversion gain among all low conversion gain modes; Fig.21 As shown, the specific steps of reading the image signal of the first row of pixel units 100 in the LCG1 mode are as follows: turn on the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100, turn off the gain control transistor M3 in the pixel units 100 in other rows except the first row, and reset the floating diffusion node in the first row of pixel units 100; turn off the reset transistor M2 in the first row of pixel units 100, and read the reset signal of the first row of pixel units 100 (such as the N_1 moment); turn on the transfer transistor M1 in the first row of pixel units 100, perform charge transfer in the LCG1 mode and read the image signal of the first row of pixel units 100 (such as the S_1 moment).

[0125] Specifically, for the case where the gain control circuit 200 includes (K-1) segments of connecting lines, such as Figure 5 and Figure 7 As shown, the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100 are turned on, and the gain control transistors M3 in the pixel units 100 in other rows except the first row are turned off. At this time, the gain capacitance value of the first row of pixel units 100 is Cfd1+Ca, and its conversion gain is q / (Cfd1+Ca), which is smaller than the conversion gain in the HCG mode and is the maximum conversion gain in all low conversion gain modes.

[0126] For the case where the gain control circuit 200 further includes a switching transistor, such as Figure 6 , Figure 8 and Fig. 9As shown, before resetting the floating diffusion node in the selected row of pixel units 100, when the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100 are turned on and the gain control transistors M3 in the pixel units 100 in other rows except the first row are turned off, all the switch transistors on the connecting line need to be turned off. At this time, the gain capacitance value of the first row of pixel units 100 is Cfd1+Cb, and its conversion gain is q / (Cfd1+Cb), which is less than the conversion gain in the HCG mode and is the maximum conversion gain in all low conversion gain modes.

[0127] The pixel unit 100 further includes a selection transistor M5, through which the reset signal and the pixel signal of the selected row are read out by row selection. When reading the reset signal and the image signal, the selection transistor M5 in the pixel unit 100 of the selected row is turned on, and the selection transistors M5 in the pixel units 100 of other rows except the selected row are turned off, completing the readout of the reset signal and the pixel signal of the selected row.

[0128] Taking the second low conversion gain (LCG2) mode as an example, for the case where the gain control circuit 200 includes (K-1) segments of connecting lines (eg Figure 5 and Figure 7 As shown in FIG. 1 , the specific steps of reading the image signal of the first row of pixel units 100 in the LCG2 mode are as follows: turn on the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100, turn on the gain control transistor M3 in the second row of pixel units 100, turn off the gain control transistors M3 in the pixel units 100 in other rows except the first row and the second row, and perform a reset operation on the floating diffusion node in the first row of pixel units 100; turn off the reset transistor M2 in the first row of pixel units 100, and read the reset signal of the first row of pixel units 100; turn on the transfer transistor M1 in the first row of pixel units 100, perform charge transfer in the LCG2 mode, and read the image signal of the first row of pixel units 100. Among them, the gain capacitance value of the first row of pixel units 100 is Cfd1+Ca+Cfd2, and its conversion gain is q / (Cfd1+Ca+Cfd2), which is less than the conversion gain in the corresponding LCG1 mode.

[0129] By analogy, the third to (Z-1)th low conversion gain modes are achieved by increasing the number of open gain control transistors M3 in the non-selected row pixel units 100, such as turning on the gain control transistors M3 in the 1st to 3rd rows of pixel units 100 and turning off the gain control transistors M3 in other rows of pixel units 100 in the third low conversion gain (LCG3) mode, turning on the gain control transistors M3 in the 1st to 4th rows of pixel units 100 and turning off the gain control transistors M3 in other rows of pixel units 100 in the fourth low conversion gain (LCG4) mode, and accordingly, the conversion gains in different low conversion gain modes gradually decrease.

[0130] For the case where the gain control circuit 200 also includes a switching transistor (eg Figure 6 , Figure 8 and Fig. 9 As shown in FIG. 1 , the specific steps for reading the image signal of the first row of pixel units 100 in the LCG2 mode are as follows: turn on the reset transistor M2 and the gain control transistor M3 in the first row of pixel units 100, turn off the gain control transistor M3 in the pixel units 100 in other rows except the first row, turn on the first switch transistor, turn off the other switch transistors except the first switch transistor, and perform a reset operation on the floating diffusion node in the first row of pixel units 100; turn off the reset transistor M2 in the first row of pixel units 100, and read the reset signal of the first row of pixel units 100; turn on the transfer transistor M1 in the first row of pixel units 100, perform charge transfer in the LCG2 mode and read the image signal of the first row of pixel units 100. Among them, for Figure 6 and Fig. 9 In the structure shown in FIG. 1 , the gain capacitance value of the pixel unit 100 in the first row is Cfd1+Ca, and its conversion gain is q / (Cfd1+Ca), which is smaller than the conversion gain in the LCG1 mode; Figure 8 In the structure shown, the gain capacitance value of the pixel unit 100 in the first row is Cfd1+Cb+Cc+Cd, and its conversion gain is q / (Cfd1+Cb+Cc+Cd), which is smaller than the conversion gain in the LCG1 mode.

[0131] The third to (Z-1)th low conversion gain modes are achieved by increasing the number of open gain control transistors M3 in the non-selected row pixel units 100 and / or the number of open switch transistors in the gain control circuit 200. Accordingly, the conversion gains in different low conversion gain modes gradually decrease.

[0132] For the second to (Z-1)th low conversion gain modes, when the reset signal and pixel signal of the selected row are read out by the selection transistor M5, when the reset signal and image signal are read out, the selection transistor M5 in the pixel unit 100 of the selected row is turned on, and the selection transistors M5 in the pixel units 100 of other rows except the selected row are turned off, and the reset signal and pixel signal of the selected row are read out. Of course, the selection transistors M5 of the row where the turned-on gain control transistor M3 is located can also be turned on, and a multi-row common readout method can be used to read the reset signal and pixel signal of the first row of pixel units 100, which can effectively improve the signal readout speed.

[0133] Take the Zth low conversion gain (LCGz) mode as an example, where the LCGz mode is the mode with the lowest conversion gain among all low conversion gain modes; Fig. 22 and Fig.23 As shown, the specific steps for reading the image signal of the first row of pixel units 100 in the Zth low conversion gain mode LCGz are as follows: turn on the gain control transistor M3 in the K row of pixel units 100, turn on the reset transistor M2 in the first row of pixel units 100, and perform a reset operation on the floating diffusion node in the first row of pixel units 100; turn off the reset transistor M2 in the first row of pixel units 100, and read the reset signal of the first row of pixel units 100 (such as at the N_1 moment); turn on the transfer transistor M1 in the first row of pixel units 100, perform charge transfer in the LCGz mode and read the pixel signal of the first row of pixel units 100 (such as at the S_1 moment).

[0134] Specifically, for the case where the gain control circuit 200 includes (K-1) segments of connecting lines, such as Figure 5 and Figure 7 As shown in FIG. 1 , when the gain control transistor M3 in the K-row pixel unit 100 is turned on, the K-row pixel units 100 will share each other's floating diffusion nodes. Figure 6 , Figure 8 and Fig. 9 As shown, before resetting the floating diffusion node in the selected row of pixel units, when the gain control transistor M3 in the K row of pixel units 100 is turned on, all switch transistors need to be turned on. At this time, the K row of pixel units 100 will share each other's floating diffusion nodes. Among them, the gain capacitance value of the first row of pixel units 100 is Cfd1+Ca+Cfd2+…+Cfdk, and its conversion gain is q / (Cfd1+Ca+Cfd2+…+Cfdk), which is the minimum value of the conversion gain in all low conversion gain modes.

[0135] The pixel unit 100 further includes a selection transistor M5, through which the reset signal and the pixel signal of the selected row are read out. In one embodiment, when reading the reset signal and the image signal, Fig. 22 As shown, the selection transistor M5 in the pixel unit 100 of the selected row is turned on, and the selection transistors M5 in the pixel units 100 of other rows except the selected row are turned off, completing the reading of the reset signal and the pixel signal of the selected row. In another embodiment, when reading the reset signal and the image signal, as shown in FIG. Fig.23 As shown, the selection transistors M5 in the K-row pixel units 100 are always turned on, and the reset signals and pixel signals of the 1-row pixel units 100 are read by reading the selected row and the non-selected row together, which can effectively improve the signal readout speed.

[0136] It can be understood that when facing changes in dynamic pictures, such as entering a high-light scene from a dark light scene, the conversion gain mode needs to be switched from a high conversion gain mode to a low conversion gain mode. For example, when entering a dark light scene from a high-light scene, the conversion gain mode needs to be switched from a low conversion gain mode to a high conversion gain mode. No reset operation is performed during the switching between high and low conversion gains.

[0137] Embodiment 3

[0138] This embodiment provides an electronic device, which includes the image sensor 10 as described in the first embodiment. In fact, the electronic device may include security cameras, automotive electronic cameras, mobile phone cameras, drones, machine vision, and existing cameras, but is not limited to the above devices.

[0139] In summary, the image sensor and its reading method and electronic device of the present application provide more and richer low conversion gains by using a gain control circuit in the image sensor to connect the drain ends of the gain control transistors in K rows of pixel units in the same column. In other words, by controlling the number of capacitors connected to one end of the gain control transistor in the LCG mode of the image sensor to adjust the conversion gain and thus improve the dynamic range, more delicate images can be output for different high-light scenes. The image signal readout efficiency of the present invention is higher and the noise level of the circuit is lower, which can further improve the performance of the image sensor.

[0140] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An image sensor, characterized in that: The invention comprises a plurality of pixel units arranged in an array and at least one gain control circuit, wherein: The pixel unit comprises: at least one photosensitive unit, a floating diffusion node, a gain control transistor, a source follower transistor and a reset transistor, wherein the photosensitive unit is connected to the floating diffusion node through a corresponding transmission transistor, and the reset transistor and the gain control transistor are sequentially connected to the floating diffusion node and are commonly connected to the gate terminal of the source follower transistor; The pixel units in each row in the same column share the same column line in every X rows, and the pixel units in adjacent (X×Y) rows are read out through Y column lines respectively, where X is an integer greater than or equal to 1, and Y is an integer greater than or equal to 2; The gain control circuit is connected to the drain ends of the gain control transistors in the K rows of pixel units in the same column, where K is an integer greater than or equal to 2.

2. The image sensor according to claim 1, characterized in that The gain control circuit includes (K-1) segments of connecting wires, and the (K-1) segments of the connecting wires are sequentially connected to the drain ends of the gain control transistors in the K rows of pixel units.

3. The image sensor according to claim 2, characterized in that Among the (K-1) sections of connecting wires, at least one section of the connecting wire is provided with a switching transistor.

4. The image sensor according to claim 3, characterized in that: When K is an even number, in the (K-1)th segment of the connecting lines, a switch transistor is provided only on the connecting line between the pixel units in the K / 2th row and the pixel units in the (K / 2+1)th row.

5. The image sensor according to claim 3, characterized in that: In the (K-1) segment of connecting wires, each segment of the connecting wires is provided with a switching transistor.

6. The image sensor according to any one of claims 2 to 5, characterized in that: In a direction perpendicular to the pixel unit, the orthographic projection of the connecting line overlaps with the orthographic projection of the photosensitive unit, and the overlapping area ratio is no more than 50%.

7. The image sensor according to claim 1, characterized in that: The pixel units in every K rows in the same column constitute a first pixel group, and each of the first pixel groups corresponds to one of the gain control circuits.

8. The image sensor according to claim 1, characterized in that The pixel units in each (X×Y) row in the same column form a second pixel group, and corresponding rows in each of the second pixel groups are connected to the same column line.

9. The image sensor according to claim 1, characterized in that: When the number of the photosensitive units in the pixel unit is greater than one, the plurality of photosensitive units are configured to receive light of the same color; wherein the plurality of photosensitive units constitute a shared pixel unit.

10. The image sensor according to claim 9, characterized in that: The number of the photosensitive units in the pixel unit is four, and the four photosensitive units are arranged in a 2×2 array; wherein the photosensitive unit includes a photosensitive element and a transfer transistor, and the photosensitive element is connected to the floating diffusion node through the transfer transistor.

11. The image sensor according to claim 1, characterized in that: The pixel unit further includes a selection transistor connected to a source terminal of the source follower transistor.

12. A method for reading an image sensor according to any one of claims 1 to 11, characterized in that: The image signals of the K rows of pixel units are read row by row, wherein the image signals include a reset signal and a pixel signal.

13. The method for reading an image sensor according to claim 12, characterized in that: The image sensor reading method comprises: Turning on the reset transistor and the gain control transistor in the pixel unit of the selected row to reset the floating diffusion node in the pixel unit of the selected row; turning off the gain control transistor in the pixel unit of the selected row to read the reset signal of the pixel unit of the selected row; The transfer transistors in the pixel units in the selected row are turned on, and charge transfer is performed in a high conversion gain mode and pixel signals of the pixel units in the selected row are read.

14. The method for reading an image sensor according to claim 13, characterized in that: The reset transistors in the pixel units of the K rows are always turned on; when the gain control transistors in the pixel units of the selected row are turned off, the gain control transistors in the pixel units of the other rows except the selected row are turned on; the pixel units also include selection transistors, and when reading the reset signal and the pixel signal, the selection transistors in the pixel units of the selected row are turned on, and the selection transistors in the pixel units of the other rows except the selected row are turned off.

15. The method for reading an image sensor according to claim 12, characterized in that: The image sensor reading method comprises: Turning on the reset transistor and the gain control transistor in the pixel unit of the selected row, turning off the gain control transistor in the pixel units of other rows except the selected row, and performing a reset operation on the floating diffusion node in the pixel unit of the selected row; turning off the reset transistor in the pixel unit of the selected row, and reading a reset signal of the pixel unit of the selected row; The transfer transistors in the pixel units of the selected row are turned on, and charge transfer is performed in a first low conversion gain mode and pixel signals of the pixel units of the selected row are read.

16. The method for reading an image sensor according to claim 15, characterized in that: When the gain control circuit further includes a switch transistor, before performing a reset operation on the floating diffusion node in the pixel unit of the selected row, a step of turning off all the switch transistors is also included.

17. The method for reading an image sensor according to claim 15, characterized in that: The pixel unit further includes a selection transistor. When the reset signal and the pixel signal are read, the selection transistor in the pixel unit of the selected row is turned on, and the selection transistors in the pixel units of other rows except the selected row are turned off.

18. The method for reading an image sensor according to claim 12, characterized in that: The image sensor reading method comprises: Turning on the gain control transistors in the pixel units of the K rows, turning on the reset transistors in the pixel units of the selected row, and performing a reset operation on the floating diffusion nodes in the pixel units of the selected row; turning off the reset transistors in the pixel units of the selected row, and reading the reset signals of the pixel units of the selected row; The transfer transistors in the pixel units in the selected row are turned on, charge transfer is performed in a Zth lowest conversion gain mode, and pixel signals of the pixel units in the selected row are read, wherein Z is an integer greater than or equal to K.

19. The method for reading an image sensor according to claim 18, characterized in that: When the gain control circuit further includes a switch transistor, before performing a reset operation on the floating diffusion node in the pixel unit of the selected row, a step of turning on all the switch transistors is also included.

20. The method for reading an image sensor according to claim 18, characterized in that: The pixel unit also includes a selection transistor. When reading the reset signal and the pixel signal, the selection transistor in the pixel unit of the selected row is turned on, and the selection transistors in the pixel units of other rows except the selected row are turned off, or the selection transistors in the pixel units of row K are always turned on.

21. An electronic device, characterized in that: Comprising the image sensor as claimed in any one of claims 1 to 11.

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