Display device

Abstract

The present disclosure relates to a display device capable of increasing capacitance of a capacitor and improving image quality. The display device may include a first data line, a first pixel connected to the first data line and including a driving transistor, and a first capacitor between a gate electrode of the driving transistor and the first data line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0082442 filed in the Korean Intellectual Property Office on June 27, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device for increasing capacitance of a capacitor and for improving image quality. Background Art

[0004] An organic light emitting display device includes a display element, for example, an organic light emitting diode, whose brightness changes according to current. Summary of the invention

[0005] Aspects of the present disclosure provide a display device for increasing capacitance of a capacitor and for improving image quality.

[0006] Aspects of the present disclosure are not limited to the above-mentioned aspects, and additional aspects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0007] According to one or more embodiments of the present disclosure, a display device includes: a first data line; a first pixel connected to the first data line and including a driving transistor; and a first capacitor between a gate electrode of the driving transistor and the first data line.

[0008] The first capacitor may overlap the first data line and the gate electrode.

[0009] The display device may further include: a second data line adjacent to the first data line; and a second pixel connected to the second data line.

[0010] The first capacitor may be between the first data line and the gate electrode and between the second data line and the gate electrode.

[0011] The second data line may be farther from the gate electrode than the first data line.

[0012] The first pixel and the second pixel may be between the first data line and the second data line.

[0013] The first pixel and the second pixel may be configured to provide light of the same color.

[0014] The first capacitor may include: a first capacitor electrode including a plurality of electrodes spaced apart from each other to have a gap; an insulating layer over the first capacitor electrode; and a second capacitor electrode over the insulating layer, the second capacitor electrode overlapping the gap and the plurality of electrodes of the first capacitor electrode.

[0015] At least a portion of the second capacitor electrode may be between adjacent electrodes of the plurality of electrodes of the first capacitor electrodes.

[0016] The second capacitor electrode may overlap the entirety of the first capacitor electrode.

[0017] An end portion of the second capacitor electrode may extend further in one direction than an end portion of the first capacitor electrode.

[0018] The first capacitor may include: a first insulating layer including a plurality of layers having a plurality of step portions having different corresponding sizes; a first capacitor electrode over the first insulating layer, and the first capacitor electrode having a plurality of step portions corresponding to the plurality of step portions of the first insulating layer; a second insulating layer over the first capacitor electrode, and the second insulating layer having a plurality of step portions corresponding to the plurality of step portions of the first capacitor electrode; and a second capacitor electrode over the second insulating layer, and the second capacitor electrode having a plurality of step portions corresponding to the plurality of step portions of the second insulating layer.

[0019] The first capacitor electrode may have a larger number of layers than the first insulating layer.

[0020] The first capacitor electrode may include: a first electrode extending along a first direction; and a plurality of second electrodes extending from the first electrode along a second direction crossing the first direction, adjacent second electrodes of the plurality of second electrodes being spaced apart so that the gap exists between the adjacent second electrodes.

[0021] The first capacitor electrode may include: a first electrode having a closed curved shape; and a plurality of second electrodes inside the first electrode in a plan view and extending from the first electrode in one direction, adjacent second electrodes of the plurality of second electrodes being spaced apart such that the gap exists between the adjacent second electrodes.

[0022] The first capacitor electrode may include: a first electrode having a closed curved shape; and a plurality of second electrodes, which are inside the first electrode in a plan view and extend from the first electrode in a first direction and a second direction, respectively, wherein a second electrode in the first direction of the plurality of second electrodes and a second electrode in the second direction of the plurality of second electrodes cross each other substantially perpendicularly, and wherein adjacent second electrodes in the plurality of second electrodes are spaced apart so that the gap exists between the adjacent second electrodes.

[0023] The first capacitor electrode may include: a first electrode having a closed curved shape; and a plurality of second electrodes, which are inside the first electrode in a plan view and extend from the first electrode along a first inclined direction and a second inclined direction, respectively, wherein a second electrode in the first inclined direction among the plurality of second electrodes and a second electrode in the second inclined direction among the plurality of second electrodes cross each other substantially perpendicularly, and wherein adjacent second electrodes in the plurality of second electrodes are spaced apart so that the gap exists between the adjacent second electrodes.

[0024] The first capacitor electrode may include a plurality of first electrodes and a plurality of second electrodes having a spiral structure extending outward while rotating in a counterclockwise direction from a central portion, wherein adjacent first electrodes among the plurality of first electrodes are spaced apart such that the gap exists between the adjacent first electrodes, and wherein adjacent second electrodes among the plurality of second electrodes are spaced apart such that the gap exists between the adjacent second electrodes.

[0025] The display device may further include a second capacitor above the first capacitor.

[0026] The second capacitor may be at the same layer as the first data line.

[0027] The second capacitor may include: a first capacitor electrode; and a second capacitor electrode adjacent to the first capacitor electrode, and the second capacitor electrode is at the same layer as the first capacitor electrode.

[0028] The first capacitor may include a first capacitor electrode and a second capacitor electrode facing each other on different layers, wherein an inclination angle of the first capacitor electrode in the first capacitor is smaller than an inclination angle of the first capacitor electrode in the second capacitor.

[0029] The display device may further include: a first connection electrode connected to the first capacitor electrode; a second connection electrode above the first connection electrode; and a third connection electrode connecting the first connection electrode to the second connection electrode, and the third connection electrode is between the first connection electrode and the second connection electrode.

[0030] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a transistor over the substrate; a first data line over the transistor; and a capacitor between a gate electrode of the transistor and the first data line.

[0031] The capacitor may overlap the first data line and the gate electrode.

[0032] The display device may further include a second data line adjacent to the first data line.

[0033] The capacitor may be between the first data line and the gate electrode and between the second data line and the gate electrode.

[0034] The second data line may be farther from the gate electrode than the first data line.

[0035] The capacitor may include: a first capacitor electrode including a plurality of electrodes spaced apart from each other to have a gap; an insulating layer over the first capacitor electrode; and a second capacitor electrode over the insulating layer to overlap the gap and the plurality of electrodes of the first capacitor electrode.

[0036] At least a portion of the second capacitor electrode may be between adjacent electrodes of the plurality of electrodes of the first capacitor electrodes.

[0037] According to the display device according to one or more embodiments of the present disclosure, at least a portion of the second capacitor electrode is located in the gap of the first capacitor electrode, so that the surface area of ​​the facing surface between the first capacitor electrode and the second capacitor electrode can be increased. Therefore, the capacitance of the capacitor can be increased.

[0038] In addition, according to the display device according to one or more embodiments of the present disclosure, the capacitor is located between the gate electrode of the transistor and the data line, so that the capacitance of the coupling capacitor between the gate electrode and the data line can be reduced or minimized. Therefore, crosstalk can be reduced and image quality can be improved.

[0039] It should be noted that aspects of the present disclosure are not limited to the aspects described above, and other aspects not mentioned will be clearly understood from the following description by those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0041] Figure 1 is a cross-sectional view of a display device according to one or more embodiments;

[0042] Figure 2 It is shown that the Figure 1 A 3D view of some of the metal and insulating layers in the transistor layer;

[0043] Figure 3 Only shows Figure 2 A view of the metal layer in

[0044] Figure 4 It is along Figure 2 A cross-sectional view of a display device according to one or more embodiments taken along line II';

[0045] Figure 5 is a cross-sectional view of a display device according to one or more embodiments;

[0046] Figure 6 is a plan view of a first capacitor electrode of a display device according to one or more embodiments;

[0047] Figure 7 is a plan view of a first capacitor electrode of a display device according to one or more embodiments;

[0048] Figure 8 is a plan view of a first capacitor electrode of a display device according to one or more embodiments;

[0049] Fig. 9 is a plan view of a first capacitor electrode of a display device according to one or more embodiments;

[0050] Fig.10 is a diagram showing an arrangement of pixels of a display device according to one or more embodiments;

[0051] Fig.11 yes Fig.10 A circuit configuration diagram of a first pixel shown in ;

[0052] Fig.12 is a cross-sectional view of a display device according to one or more embodiments;

[0053] Fig.13 yes Fig.12 A plan view of one or more embodiments of a first-second capacitor;

[0054] Fig.14is a cross-sectional view of a display device according to one or more embodiments;

[0055] Fig.15 is a cross-sectional view of a display device according to one or more embodiments;

[0056] Fig.16 is a cross-sectional view of a display device according to one or more embodiments;

[0057] Fig.17 yes Fig.14 an enlarged view of a portion A of;

[0058] Fig.18 yes Fig.14 an enlarged view of portion B of ; and

[0059] Fig.19 is a diagram illustrating effects of a display device according to one or more embodiments. DETAILED DESCRIPTION

[0060] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for implementing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, throughout the drawings and the specification, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0061] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "may", "can" or "may not" in the description of the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and replacements within the spirit and scope of the present disclosure. In addition, each feature of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0062] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally used to make the boundaries between adjacent elements clear. Therefore, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0063] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but will include deviations in shapes caused by, for example, manufacturing.

[0064] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0065] For ease of explanation, spatial relative terms such as "under...", "below...", "lower", "under...", "under...", "above...", "upper", and "upper side" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device is turned over in the drawings, the element described as "under", "under", or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "under..." and "under..." can cover both upper and lower orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when a first part is described as being arranged "on" a second part, this means that the first part is arranged at the upper or lower side of the second part, without being limited to the upper side of the second part based on the direction of gravity.

[0066] In addition, the phrase "in a plan view" refers to when the object portion is observed from above, and "in a schematic cross-sectional view" refers to when the schematic cross-section obtained by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapping with..." refers to that the first object can be above or below the second object or on the side of the second object, and vice versa. In addition, the term "overlap" can include stacking, facing or facing, extending thereon, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The expression "non-overlapping" can include the meaning of any other suitable equivalent such as "away from", "separated" or "deviation" and will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object can be understood as still facing each other but indirectly opposite to each other.

[0067] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to," another element, layer, region, or component, the element, layer, region, or component may be formed directly on, directly on, directly connected to, or directly coupled to, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to, such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may be collectively referred to as direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, and / or capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, the statement of connection indicates an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component or is on another component without intervening components.

[0068] In addition, in this specification, when a part of a layer, film, zone or plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, zone or plate, etc. is formed "below" another part, this includes not only the case where the part is "directly below" the other part, but also the case where there are other parts between the part and the other part. At the same time, other expressions describing the relationship between components, such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intermediate elements or intermediate layers may also be present.

[0069] For the purposes of this disclosure, when expressions such as "at least one of ...," "any one of ...," or "one or more of ...," are after a list of elements, the entire list of elements is modified without modifying the individual elements in the list. For example, "at least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ as examples) or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. Similarly, when expressions such as "at least one of ...," "a plurality of," "one of ...," and other prepositional phrases are before / after a list of elements, the entire list of elements is modified without modifying the individual elements in the list.

[0070] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers and / or parts, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, area, area, layer, section or part from another element, member, component, area, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, area, layer or part described below can be referred to as the second element, component, area, layer or part. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish between elements of different categories or groups. For the sake of brevity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0071] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2 and / or the third direction DR3.

[0072] The terms used in this article are only for the purpose of describing embodiments, and are not intended to limit the present disclosure. As used in this article, unless the context clearly states otherwise, the singular forms "one (person)" and "a kind of" are also intended to include plural forms, and the plural forms are also intended to include singular forms. It will also be understood that when used in this specification, the terms "include", "comprise", "contain", "have", "have", "contain" and "have" illustrate the existence of stated features, integers, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0073] As used herein, the terms "substantially", "approximately", "approximately" and similar terms are used as approximate terms rather than terms of degree, and are intended to explain the inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the measurement discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" as used herein include the stated values ​​and are meant to be within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10% or ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0074] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their context in the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense.

[0075] Figure 1 is a cross-sectional view of a display device according to one or more embodiments.

[0076] like Figure 1 As shown in , the display device may include a base substrate SUB1, a transistor layer TRL, a light emitting element layer EMTL, an encapsulation layer ENC, a color filter layer CFL, a lens array layer LAL, and an encapsulation substrate SUB2.

[0077] The base substrate SUB1 may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The base substrate SUB1 may be a substrate doped with first type impurities.

[0078] The well region W may be located on the base substrate SUB1 (or in the base substrate SUB1). The well region W may be a region doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. At the same time, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0079] The source region S, drain region D, and channel region CH of the transistor TR may be located in the well region W. For example, the source region S (or source electrode S) and drain region D (or drain electrode D) of the transistor TR may be located in the well region W. Each of the source region S and the drain region D may be a region doped with the aforementioned first type impurities. The gate electrode G of the transistor TR may intersect and overlap with the well region W. In a plan view, the well region W intersecting with the gate electrode G is defined as two parts, and the source region S may be located in any one of the two parts, and the drain region D may be located in the other of the two parts. In other words, in the well region W, the source region S and the drain region D may be located on each side (e.g., both sides) of the channel region CH and the channel region CH is between the source region S and the drain region D. The channel region CH of the transistor TR may be located in the region of the well region W overlapping with the gate electrode G.

[0080] Meanwhile, the source region S may include a first low-concentration impurity region having an impurity concentration relatively lower than that of other portions of the source region S. In other words, a portion of the source region S may include a low concentration of impurities compared to other portions of the source region S. The drain region D may include a second low-concentration impurity region having an impurity concentration relatively lower than that of other portions of the drain region D. In other words, a portion of the drain region D may include a low concentration of impurities compared to other portions of the drain region D.

[0081] The first low-concentration impurity region and the second low-concentration impurity region may be located near the channel region CH of the transistor TR. For example, the first low-concentration impurity region may be located relatively close to the channel region CH to overlap with the first spacer located on one side of the gate electrode G, and the second low-concentration impurity region may be located relatively close to the channel region CH to overlap with the second spacer located on the other side of the gate electrode G. In this way, the distance between the high-concentration impurity region in the source region S and the high-concentration impurity region in the drain region D may be increased due to the first low-concentration impurity region and the second low-concentration impurity region, and the length of the channel region CH may be increased due to the increase in the distance. Therefore, the possibility of punch-through and hot carrier phenomena caused by a short channel may be reduced or prevented.

[0082] An interlayer insulating layer VA may be located on the base substrate SUB1.

[0083] A passivation layer PAS may be located on the interlayer insulating layer VA.

[0084] The light emitting element layer EMTL may be located on the passivation layer PAS. The light emitting element layer EMTL may include, for example, a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 located in different emission regions. For example, the first light emitting element ED1 of the light emitting element layer EMTL may be located in the first emission region EA1, the second light emitting element ED2 of the light emitting element layer EMTL may be located in the second emission region EA2, and the third light emitting element ED3 of the light emitting element layer EMTL may be located in the third emission region EA3.

[0085] Each of the first light emitting element ED1 , the second light emitting element ED2 , and the third light emitting element ED3 may provide white light.

[0086] The first light emitting element ED1 may include a first pixel electrode PE1 (or a first anode electrode), a light-providing layer LPL, and a common electrode CE, which are stacked in the third direction DR3 .

[0087] The second light emitting element ED2 may include a second pixel electrode PE2 (or a second anode electrode), a light-providing layer LPL, and a common electrode CE, which are stacked in the third direction DR3.

[0088] The third light emitting element ED3 may include a third pixel electrode PE3 (or a third anode electrode), a light-providing layer LPL, and a common electrode CE stacked in the third direction DR3.

[0089] Here, the light-supplying layer LPL and the common electrode CE may be common layers commonly used by the light emitting elements ED1 to ED3. In other words, the plurality of light emitting elements ED1 to ED3 of the light emitting element layer EMTL may share the light-supplying layer LPL and the common electrode CE.

[0090] The light providing layer LPL may include a plurality of light emitting layers for respectively providing light of different colors, and the plurality of light emitting layers may be stacked along the third direction DR3. Different lights from the plurality of light emitting layers may be mixed to generate white light. Meanwhile, the light providing layer LPL may further include a charge generating layer.

[0091] The first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 may be respectively connected to the source region S of the corresponding transistor TR through the pixel connection electrode PCE and the metal connection layer ME.

[0092] The first pixel electrode PE1 may correspond to the first emission area EA1, the second pixel electrode PE2 may correspond to the second emission area EA2, and the third pixel electrode PE3 may correspond to the third emission area EA3.

[0093] The embankment PDL (or pixel defining layer) may be located on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The embankment PDL may define the emission area of ​​the pixel (e.g., the first emission area EA1 of the first pixel, the second emission area EA2 of the second pixel, and the third emission area EA3 of the third pixel). To this end, the embankment PDL may expose a partial area of ​​each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 on the passivation layer PAS. The embankment PDL may cover the edge of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The embankment PDL may be formed by an organic layer (e.g., a layer including, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin).

[0094] The light providing layer LPL may be located on the pixel electrodes PE1, PE2 and PE3 and the dike PDL. For example, the light providing layer LPL may be located on the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the dike PDL. The light providing layer LPL may include a plurality of light emitting units. For example, the light providing layer LPL may include a first light emitting unit, a second light emitting unit and a third light emitting unit stacked in a third direction DR3. The light emitting units may provide light of different corresponding wavelengths. For example, the first light emitting unit, the second light emitting unit and the third light emitting unit may emit light of different corresponding colors. For example, the light providing layer LPL may have a series structure in which a plurality of light emitting units providing light of different colors are stacked in a vertical direction (e.g., the third direction DR3).

[0095] The first light emitting unit may be located on the pixel electrodes PE1, PE2, and PE3. The first light emitting unit may include a first light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0096] The second light emitting unit may be located on the first light emitting unit. The second light emitting unit may include a second light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0097] The third light emitting unit may be located on the second light emitting unit. The third light emitting unit may include a third light emitting layer, a hole transport layer, an organic material layer and an electron transport layer.

[0098] The light emitting elements ED1, ED2, and ED3 can provide white light by mixing light of a first color (e.g., blue) from a first light emitting unit, light of a second color (e.g., red) from a second light emitting unit, and light of a third color (e.g., green) from a third light emitting unit. For example, each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can provide white light.

[0099] In addition, in addition to the aforementioned light-emitting units, the light-providing layer LPL may further include at least one charge generating layer. For example, the charge generating layer may be located between light-emitting units adjacent to each other in the third direction DR3. For example, the charge generating layer may include a first charge generating layer and a second charge generating layer stacked in the third direction DR3. In this case, the first charge generating layer may be located between the first light-emitting unit and the second light-emitting unit, and the second charge generating layer may be located between the second light-emitting unit and the third light-emitting unit.

[0100] On the other hand, each charge generation layer may include a negative charge generation layer and a positive charge generation layer. For example, the first charge generation layer may include a first negative charge generation layer and a first positive charge generation layer stacked in the third direction DR3, and the second charge generation layer may include a second negative charge generation layer and a second positive charge generation layer stacked in the third direction DR3.

[0101] The common electrode CE may be located on the light providing layer LPL. For example, the common electrode CE may be located on the light providing layer LPL to overlap with the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the first emission area EA1, the second emission area EA2, the third emission area EA3, and the dike PDL. In the top emission structure, the common electrode CE may be formed of a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or may be formed of a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and / or silver (Ag). When the common electrode CE is formed of a semi-transmissive conductive material, the luminous efficiency may be improved due to the microcavity effect.

[0102] The cover layer CPL may be located on the common electrode CE. The cover layer CPL may include an inorganic insulating material. In one or more embodiments, the cover layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride.

[0103] The encapsulation layer ENC may be located on the cover layer CPL. The encapsulation layer ENC may cover the top surface and the side surface of the light emitting element layer EMTL, and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer (e.g., a first inorganic encapsulation layer TFE1 and / or a second inorganic encapsulation layer TFE3) to reduce or prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer ENC may include at least one organic layer (e.g., an organic encapsulation layer TFE2) to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0104] The first inorganic encapsulation layer TFE1 may be located on the cover layer CPL, the organic encapsulation layer TFE2 may be located on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be located on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed of a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer are alternately stacked. The organic encapsulation layer TFE2 may be an organic layer including, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0105] The light blocking layer BM may be located on the encapsulation layer ENC. The light blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 overlapping the emission areas EA1, EA2, and EA3, respectively. For example, the first hole OPT1 may overlap the first emission area EA1, the second hole OPT2 may overlap the second emission area EA2, and the third hole OPT3 may overlap the third emission area EA3. The area or size of each of the holes OPT1, OPT2, and OPT3 may be larger than the area or size of each of the emission areas EA1, EA2, and EA3 defined by the embankment PDL. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM are formed to be larger than the emission areas EA1, EA2, and EA3, so that the light emitted from the emission areas EA1, EA2, and EA3 can be visually recognized by the user not only from the front surface of the display device but also from the side surface of the display device.

[0106] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the inorganic black pigment and the organic black pigment are not limited thereto. The light blocking layer BM may reduce or prevent visible light penetration and color mixing between the first emission area EA1, the second emission area EA2, and the third emission area EA3, which leads to an improvement in the color reproducibility of the display device.

[0107] In addition, the display device may include a plurality of color filters CF1, CF2, and CF3 located on the emission areas EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3 may correspond to the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be located on the light blocking layer BM including a plurality of holes OPT1, OPT2, and OPT3 corresponding to the emission areas EA1, EA2, and EA3, respectively.

[0108] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 corresponding to different emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or a pigment that absorbs light in a band other than the light in the corresponding band, and may correspond to the color of the light emitted from the emission areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that overlaps with the first emission area EA1 and transmits only red first light. The second color filter CF2 may be a green color filter that overlaps with the second emission area EA2 and transmits only green second light, and the third color filter CF3 may be a blue color filter that overlaps with the third emission area EA3 and transmits only blue third light.

[0109] Each of the plurality of color filters CF1, CF2, and CF3 may be spaced apart from an adjacent color filter on the light blocking layer BM. The color filters CF1, CF2, and CF3 may have an area larger than the area of ​​the holes OPT1, OPT2, and OPT3 of the light blocking layer BM, respectively, while covering the holes OPT1, OPT2, and OPT3. Each of the color filters CF1, CF2, and CF3 may have an area sufficient to be spaced apart from an adjacent color filter on the light blocking layer BM. However, the present disclosure is not limited thereto. Each of the plurality of color filters CF1, CF2, and CF3 may partially overlap with an adjacent color filter. Different color filters CF1, CF2, and CF3 do not overlap with the emission areas EA1, EA2, and EA3, and may overlap with each other on the light blocking layer BM. In the display device, the color filters CF1, CF2, and CF3 overlap with each other, so that the intensity of the reflected light of the external light can be reduced. In addition, the color of the reflected light of the external light may be controlled by adjusting the arrangement, shape, and area of ​​the color filters CF1, CF2, CF3 in a plan view.

[0110] The overcoat layer OC may be located on the color filters CF1, CF2, and CF3 to flatten the tops of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0111] The lens array layer LAL may be located on the outer coating layer OC. The lens array layer LAL may include a plurality of microlenses ML1, ML2, and ML3. For example, the lens array layer LAL may include a first microlens ML1 corresponding to the first emission area EA1 or the first hole OPT1, a second microlens ML2 corresponding to the second emission area EA2 or the second hole OPT2, and a third microlens ML3 corresponding to the third emission area EA3 or the third hole OPT3.

[0112] The microlenses ML1, ML2, and ML3 may have sizes larger than the sizes of the corresponding holes OPT1, OPT2, and OPT3, respectively. For example, the microlenses ML1, ML2, and ML3 may completely cover the corresponding holes OPT1, OPT2, and OPT3, respectively, and may overlap with a portion of the light blocking layer BM. Because the microlenses ML1, ML2, and ML3 are formed to be larger than the holes OPT1, OPT2, and OPT3 of the light blocking layer BM, light emitted from the emission areas EA1, EA2, and EA3 may be recognized by a user from the side surfaces and the front surface of the display device.

[0113] The filler FL may be located on the lens array layer LAL. The filler FL may be located between adjacent microlenses.

[0114] The package substrate SUB2 may be located on the filler FL.

[0115] Figure 2 It is shown that the Figure 1 A 3D view of some of the metal and insulating layers in the transistor layer TRL. Figure 3 Only shows Figure 2 A view of the metal layer in Figure 4 It is along Figure 2 FIG. 5 is a cross-sectional view of a display device according to one or more embodiments, taken along line II′.

[0116] like Figures 2 to 4 As shown in FIG. 1 , the transistor layer TRL (see FIG. 1 ) of the display device Figure 1 ) may include a first insulating layer INS1, a first capacitor electrode CPE1, a second insulating layer INS2, a second capacitor electrode CPE2, and a third insulating layer INS3 sequentially positioned (or stacked) along a third direction DR3. Here, the capacitor CPT may include the first capacitor electrode CPE1, the second insulating layer INS2, and the second capacitor electrode CPE2. In this case, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be the first electrode and the second electrode of the capacitor CPT, respectively.

[0117] The transistor layer TRL may include a plurality of insulating layers positioned along the third direction DR3. For example, the interlayer insulating layer of the transistor layer TRL may include a plurality of insulating layers positioned along the third direction DR3, and Figure 2 and Figure 3 A first insulating layer INS1 , a second insulating layer INS2 , and a third insulating layer INS3 among the plurality of insulating layers are shown.

[0118] Furthermore, the transistor layer TRL may include a plurality of metal layers positioned along the third direction DR3 , and each metal layer may be located between adjacent insulating layers. Figure 2 and Figure 3 A metal layer including a first capacitor electrode CPE1 and a second capacitor electrode CPE2 among a plurality of metal layers is shown. Here, the first capacitor electrode CPE1 may be located between the first and second insulating layers INS1 and INS2, and the second capacitor electrode CPE2 may be located between the second and third insulating layers INS2 and INS3.

[0119] The first insulating layer INS1 may be, for example, a layer containing silicon oxide (SiO x ) layer.

[0120] The first capacitor electrode CPE1 may be located on the first insulating layer INS1. Figure 2 and Figure 3 As shown in , the first capacitor electrode CPE1 may include a first electrode EE1 and a plurality of second electrodes EE2 .

[0121] The first electrode EE1 may extend along the first direction DR1. The first electrode EE1 may have a rectangular shape.

[0122] A plurality of second electrodes EE2 may extend from the first electrode EE1 along the second direction DR2. A plurality of second electrodes EE2 may be arranged along the first direction DR1. The second electrodes EE2 may be spaced apart from each other at equal intervals. Thus, a gap GP may be formed between adjacent second electrodes EE2. Each second electrode EE2 may have a rectangular shape. A plurality of second electrodes EE2 may be formed integrally with the first electrode EE1.

[0123] like Figure 4 As shown in , the angle θ1 (e.g., a tapered angle) formed by the bottom surface BS and the first side surface SS1 of the first capacitor electrode CPE1 may be an acute angle. The angle formed by the bottom surface BS and the second side surface SS2 of the first capacitor electrode CPE1 may also be an acute angle. The angle θ1 formed by the bottom surface BS and the first side surface SS1 of the first capacitor electrode CPE1 may be equal to the angle formed by the bottom surface BS and the second side surface SS2 of the first capacitor electrode CPE1.

[0124] The second insulating layer INS2 may be located on the first capacitor electrode CPE1. Figure 4 As shown in , the second insulating layer INS2 may be located on the top surface TS and the side surfaces SS1 and SS2 of the first capacitor electrode CPE1. Figure 4 As shown in , the second insulating layer INS2 may be located between adjacent second electrodes EE2 of the first capacitor electrode CPE1. The second insulating layer INS2 located between the second electrodes EE2 may be located on the first insulating layer INS1 positioned below the second electrode EE2. The second insulating layer INS2 located between the second electrodes EE2 may contact the first insulating layer INS1.

[0125] The second insulating layer INS2 may be located on the first capacitor electrode CPE1 to overlap the entire first capacitor electrode CPE1 .

[0126] The first capacitor electrode CPE1 may be surrounded by the second insulating layer INS2 and the first insulating layer INS1. Figure 4As shown in , the top surface TS and the side surfaces SS1 and SS2 of the first capacitor electrode CPE1 may be covered by the second insulating layer INS2, and the bottom surface BS of the first capacitor electrode CPE1 may be covered by the first insulating layer INS1. In this case, the second insulating layer INS2 may be in contact with the top surface TS and the side surfaces SS1 and SS2 of the first capacitor electrode CPE1, and the first insulating layer INS1 may be in contact with the bottom surface BS of the first capacitor electrode CPE1.

[0127] The second insulating layer INS2 may have a stepped portion that is consistent with the shape of the first capacitor electrode CPE1 located below the second insulating layer INS2. For example, the second insulating layer INS2 overlapping (or contacting) the top surface TS of the first capacitor electrode CPE1 may be positioned higher than the second insulating layer INS2 overlapping (or contacting) the first insulating layer INS1. In other words, the second insulating layer INS2 may be higher or may have a greater height in an area overlapping with the top surface TS of the first capacitor electrode CPE1 than in an area overlapping or contacting the first insulating layer INS1 (e.g., an area not overlapping with the first capacitor electrode CPE1). Here, the height of the second insulating layer INS2 may correspond to the height in the third direction DR3.

[0128] The second insulating layer INS2 may be, for example, a layer containing silicon nitride (SiN x ) layer.

[0129] The second capacitor electrode CPE2 may be located on the second insulating layer INS2. The second capacitor electrode CPE2 may be located on the second insulating layer INS2 to overlap the entire first capacitor electrode CPE1.

[0130] like Figure 4 As shown in , the second capacitor electrode CPE2 may be located on the second insulating layer INS2 to overlap with the top surface TS and the side surfaces SS1 and SS2 of the first capacitor electrode CPE1. Figure 4 As shown in , the second capacitor electrode CPE2 may be located on the second insulating layer INS2 to be positioned between adjacent second electrodes EE2 of the first capacitor electrode CPE1. In other words, at least a portion of the second capacitor electrode CPE2 may be located in the gap GP between the adjacent second electrodes EE2.

[0131] The second capacitor electrode CPE2 may have a stepped portion that is consistent with the shape of the first capacitor electrode CPE1 located below the second capacitor electrode CPE2. For example, the second capacitor electrode CPE2 located on the second insulating layer INS2 to overlap with the top surface TS of the first capacitor electrode CPE1 may be positioned higher than the second capacitor electrode CPE2 located between the second electrodes EE2, or may have a greater height than the second capacitor electrode CPE2 located between the second electrodes EE2. In other words, the second capacitor electrode CPE2 may be higher in the area overlapping with the top surface TS of the first capacitor electrode CPE1 than in the area not overlapping with the first capacitor electrode CPE1. Here, the height of the second capacitor electrode CPE2 may correspond to the height in the third direction DR3.

[0132] The end of the second capacitor electrode CPE2 and the end of the first capacitor electrode CPE1 may be spaced apart from each other in the first direction DR1. For example, the end of any one of the second electrodes EE2 of the first capacitor electrode CPE1 located at the outermost portion and the end of the second capacitor electrode CPE2 adjacent thereto may be spaced apart from each other in the first direction DR1. To this end, the end of the second capacitor electrode CPE2 may extend farther than the end of the first capacitor electrode CPE1 by a distance d (e.g., a predetermined distance) in the first direction DR1 or in a direction opposite to the first direction DR1 or in a reverse direction of the first direction DR1 (hereinafter referred to as a first reverse direction).

[0133] The third insulating layer INS3 may be located on the second capacitor electrode CPE2. The third insulating layer INS3 may have a planarized top surface regardless of a stepped portion of a pattern located below the third insulating layer INS3. The third insulating layer INS3 may be, for example, a layer including silicon oxide.

[0134] Because the gap GP exists between the second electrode EE2 of the first capacitor electrode CPE1, the second capacitor electrode CPE2 can be located in the gap GP. Therefore, the surface area of ​​the facing surface between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 can be increased. Therefore, the first side surface SS1 and the second side surface SS2 of the first capacitor electrode CPE1 and the top surface TS of the first capacitor electrode CPE1 can face the second capacitor electrode CPE2. Therefore, the capacitor CPT formed by the first capacitor electrode CPE1 and the second capacitor electrode CPE2 can have a relatively large capacitance. For example, the aforementioned capacitor CPT may include a first capacitor / capacitor Cc1 between the top surface TS of the first capacitor electrode CPE1 and the second capacitor electrode CPE2, a second capacitor / capacitor Cc2 between the first side surface SS1 of the first capacitor electrode CPE1 and the second capacitor electrode CPE2, and a third capacitor / capacitor Cc3 between the second side surface SS2 of the first capacitor electrode CPE1 and the second capacitor electrode CPE2.

[0135] Figure 5 is a cross-sectional view of a display device according to one or more embodiments.

[0136] Reference Figure 5 The capacitor CPT of the display device according to one or more embodiments may include a first capacitor electrode CPE1, a second insulating layer INS2, and a second capacitor electrode CPE2. In addition, the display device may further include a first insulating layer INS1 located below the first capacitor electrode CPE1 and a third insulating layer INS3 located above the second capacitor electrode CPE2.

[0137] like Figure 5 As shown in , the first insulating layer INS1 may include layers L11, L12, and L13 having stepped portions of different sizes (e.g., height differences or thicknesses). For example, the first insulating layer INS1 may include a first layer L11 having a first height (or a first thickness), a second layer L12 having a second height (or a second thickness), and a third layer L13 having a third height (or a third thickness).

[0138] The second layer L12 may be positioned higher than the first layer L11, and the third layer L13 may be positioned higher than the second layer L12. For example, the top surface (or uppermost surface) of the second layer L12 may be higher than the top surface (or uppermost surface) of the first layer L11, and the top surface (or uppermost surface) of the third layer L13 may be higher than the top surface (or uppermost surface) of the second layer L12.

[0139] The three layers L11 , L12 , and L13 of the first insulating layer INS1 having stepped portions of different sizes may be formed by manufacturing the first insulating layer INS1 , for example, using a half-tone mask.

[0140] The first capacitor electrode CPE1, the second insulating layer INS2, the second capacitor electrode CPE2, and the third insulating layer INS3 may be sequentially located on the first insulating layer INS1 along the third direction DR3. For example, the first capacitor electrode CPE1 may be located on the first insulating layer INS1, the second insulating layer INS2 may be located on the first capacitor electrode CPE1, the second capacitor electrode CPE2 may be located on the second insulating layer INS2, and the third insulating layer INS3 may be located on the second capacitor electrode CPE2. In this case, since the layers L11, L12, and L13 of the first insulating layer INS1 have stepped portions of different sizes, the first capacitor electrode CPE1, the second insulating layer INS2, and the second capacitor electrode CPE2 located on the first insulating layer INS1 may have stepped portions corresponding to the stepped portions of the first insulating layer INS1. Therefore, the surface area of ​​the facing surface between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be further increased. Therefore, the capacitance of the capacitor CPT formed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be further increased.

[0141] At the same time, if Figure 5 As shown in , the first capacitor electrode CPE1 may include a larger number of layers than the first insulating layer INS1 located below the first capacitor electrode CPE1. For example, the first capacitor electrode CPE1 may include four layers L21, L22, L23, and L24 having stepped portions of different sizes (e.g., height differences). For example, the first capacitor electrode CPE1 may include a first layer L21 having a first height, a second layer L22 having a second height, a third layer L23 having a third height, and a fourth layer L24 having a fourth height.

[0142] The second layer L22 may be positioned higher than the first layer L21, the third layer L23 may be positioned higher than the second layer L22, and the fourth layer L24 may be positioned higher than the third layer L23. For example, the top surface (or uppermost surface) of the second layer L22 may be positioned higher than the top surface (or uppermost surface) of the first layer L21, the top surface (or uppermost surface) of the third layer L23 may be positioned higher than the top surface (or uppermost surface) of the second layer L22, and the top surface (or uppermost surface) of the fourth layer L24 may be positioned higher than the top surface (or uppermost surface) of the third layer L23.

[0143] When the first capacitor electrode CPE1 includes four layers L21, L22, L23 and L24 having step portions of different sizes, the second insulating layer INS2 located on the first capacitor electrode CPE1 may include four layers L31, L32, L33 and L34 having step portions of different sizes. In addition, when the second insulating layer INS2 includes four layers L31, L32, L33 and L34 having step portions of different sizes, the second capacitor electrode CPE2 located on the second insulating layer INS2 may include four layers L41, L42, L43 and L44 having step portions of different sizes.

[0144] For example, four layers having stepped portions of different sizes of the first capacitor electrode CPE1 may be formed by manufacturing the first capacitor electrode CPE1 using a half-tone mask. Meanwhile, when the first capacitor electrode CPE1 is formed using a general mask other than the half-tone mask, the number of layers (e.g., three layers L21, L22, and L23) included in the first capacitor electrode CPE1 may be the same as the number of layers included in the first insulating layer INS1 located below the first capacitor electrode CPE1. For example, when the first capacitor electrode CPE1 is formed using a half-tone mask, the first capacitor electrode CPE1 may include a greater number of layers than the first insulating layer INS1 located below the first capacitor electrode CPE1.

[0145] In the plan view, Figure 5 Each of the first capacitor electrode CPE1 and the second capacitor electrode CPE2 may have the same Figure 3 The shape of the second capacitor electrode CPE2 is the same shape.

[0146] Meanwhile, the first insulating layer INS1 may include, for example, four or more layers having different heights (or thicknesses). In this case, the first capacitor electrode CPE1, the second insulating layer INS2, and the second capacitor electrode CPE2 located above the first insulating layer INS1 may include four or more layers having different heights.

[0147] Figure 6 is a plan view of a first capacitor electrode CPE1 of a display device according to one or more embodiments.

[0148] like Figure 6 As shown in , the first capacitor electrode CPE1 may include a first electrode EE1, a second electrode EE2, and a third electrode EE3. The first electrode EE1, the second electrode EE2, and the third electrode EE3 may be integrally formed.

[0149] The first electrode EE1 may have a closed curved shape or a ring shape. For example, the first electrode EE1 may have a rectangular frame shape that is longer in the first direction DR1 than in the second direction DR2. The first electrode EE1 may include, for example, a first sub-electrode SUE1, a second sub-electrode SUE2, a third sub-electrode SUE3, and a fourth sub-electrode SUE4 that are connected (e.g., electrically connected) to each other. The first sub-electrode SUE1, the second sub-electrode SUE2, the third sub-electrode SUE3, and the fourth sub-electrode SUE4 may be formed integrally.

[0150] Each of the first sub-electrode SUE1 and the second sub-electrode SUE2 may extend along the second direction DR2. The first sub-electrode SUE1 and the second sub-electrode SUE2 may face each other (eg, may be opposite to each other).

[0151] Each of the third sub-electrode SUE3 and the fourth sub-electrode SUE4 may extend along the first direction DR1. The third sub-electrode SUE3 and the fourth sub-electrode SUE4 may face each other (eg, may be opposite to each other).

[0152] The second electrode EE2 may be located in the first electrode EE1 (e.g., may be surrounded by the first electrode EE1 in a plan view). In other words, the second electrode EE2 may be located in a region surrounded by the first electrode EE1. The second electrode EE2 may extend from the inner surface of the first electrode EE1 along the second direction DR2. For example, the second electrode EE2 may extend from the inner surface of the third sub-electrode SUE3 toward the inner surface of the fourth sub-electrode SUE4 along the second direction DR2. The end of the second electrode EE2 may be spaced apart from the inner surface of the fourth sub-electrode SUE4 by a predetermined distance. A plurality of second electrodes EE2 may be provided. For one example, Figure 6 It is shown that two second electrodes EE2 are spaced apart from each other in the first electrode EE1. However, the present disclosure is not limited thereto, and three or more second electrodes EE2 may be spaced apart from each other in the first electrode EE1.

[0153] The third electrode EE3 may be located in the first electrode EE1 (e.g., may be surrounded by the first electrode EE1 in a plan view). In other words, the third electrode EE3 may be located in an area surrounded by the first electrode EE1. The third electrode EE3 may extend from the inner surface of the first electrode EE1 in a direction opposite to the second direction DR2 or in a direction opposite to the second direction DR2 (hereinafter referred to as the second reverse direction). For example, the third electrode EE3 may extend from the inner surface of the fourth sub-electrode SUE4 toward the inner surface of the third sub-electrode SUE3 in the second reverse direction. The end of the third electrode EE3 may be spaced apart from the inner surface of the third sub-electrode SUE3 by a predetermined distance. A plurality of third electrodes EE3 may be provided. For one example, Figure 6It is shown that two third electrodes EE3 are spaced apart from each other in the first electrode EE1. However, the present disclosure is not limited thereto, and three or more third electrodes EE3 may be spaced apart from each other in the first electrode EE1.

[0154] The plurality of second electrodes EE2 and the plurality of third electrodes EE3 may be alternately located in the first electrode EE1. The second electrode EE2 and the third electrode EE3 may have the same length. Here, the length of the second electrode EE2 (or the third electrode EE3) may be measured along the second direction DR2.

[0155] The second electrode EE2 and the third electrode EE3 may be positioned in parallel (eg, may be positioned substantially in parallel).

[0156] A distance between the second electrodes EE2 adjacent to each other may be equal to a distance between the third electrodes EE3 adjacent to each other.

[0157] A gap GP may exist between the second electrode EE2 and the third electrode EE3 that are adjacent to each other.

[0158] Figure 7 is a plan view of a first capacitor electrode CPE1 of a display device according to one or more embodiments.

[0159] like Figure 7 As shown in , the first capacitor electrode CPE1 may include a first electrode EE1, a second electrode EE2, and a third electrode EE3. The first electrode EE1, the second electrode EE2, and the third electrode EE3 may be integrally formed.

[0160] The first electrode EE1 may have a closed curved shape or a ring shape. For example, the first electrode EE1 may have a rectangular frame shape that is longer in the first direction DR1 than in the second direction DR2. The first electrode EE1 may include, for example, a first sub-electrode SUE1, a second sub-electrode SUE2, a third sub-electrode SUE3, and a fourth sub-electrode SUE4 that are connected to each other. The first sub-electrode SUE1, the second sub-electrode SUE2, the third sub-electrode SUE3, and the fourth sub-electrode SUE4 may be formed integrally.

[0161] Each of the first sub-electrode SUE1 and the second sub-electrode SUE2 may extend along the second direction DR2. The first sub-electrode SUE1 and the second sub-electrode SUE2 may face each other (eg, may be opposite to each other).

[0162] Each of the third sub-electrode SUE3 and the fourth sub-electrode SUE4 may extend along the first direction DR1. The third sub-electrode SUE3 and the fourth sub-electrode SUE4 may face each other (eg, may be opposite to each other).

[0163] The second electrode EE2 may be located in the first electrode EE1 (e.g., surrounded by the first electrode EE1 in a plan view). In other words, the second electrode EE2 may be located in a region surrounded by the first electrode EE1. The second electrode EE2 may extend from the inner surface of the first electrode EE1 along the first direction DR1. One side of the second electrode EE2 may be connected to the inner surface of the first sub-electrode SUE1, and the other side of the second electrode EE2 may be connected to the inner surface of the second sub-electrode SUE2. A plurality of second electrodes EE2 may be provided. For one example, Figure 7 It is shown that two second electrodes EE2 are spaced apart from each other in the first electrode EE1. However, the present disclosure is not limited thereto, and three or more second electrodes EE2 may be spaced apart from each other in the first electrode EE1. When a plurality of second electrodes EE2 are provided, the intervals between the second electrodes EE2 may be the same as each other. In this case, a gap GP may exist between adjacent second electrodes EE2.

[0164] The third electrode EE3 may be located in the first electrode EE1. In other words, the third electrode EE3 may be located in a region surrounded by the first electrode EE1. The third electrode EE3 may extend from the inner surface of the first electrode EE1 along the second direction DR2. In other words, the third electrode EE3 may cross or intersect (e.g., intersect vertically) with the aforementioned second electrode EE2. One side of the third electrode EE3 may be connected to the inner surface of the third sub-electrode SUE3, and the other side of the third electrode EE3 may be connected to the inner surface of the fourth sub-electrode SUE4. A plurality of third electrodes EE3 may be provided. For one example, Figure 7 It is shown that four third electrodes EE3 are spaced apart from each other in the first electrode EE1. However, the present disclosure is not limited thereto, and two to three or five or more third electrodes EE3 may be spaced apart from each other in the first electrode EE1. When a plurality of third electrodes EE3 are provided, the intervals between the third electrodes EE3 may be the same. In this case, a gap GP may exist between adjacent third electrodes EE3.

[0165] Figure 8 is a plan view of a first capacitor electrode CPE1 of a display device according to one or more embodiments.

[0166] like Figure 8 As shown in , the first capacitor electrode CPE1 may include a first electrode EE1, a second electrode EE2, and a third electrode EE3. The first electrode EE1, the second electrode EE2, and the third electrode EE3 may be integrally formed.

[0167] The first electrode EE1 may have a closed curved shape or a ring shape. For example, the first electrode may have a rectangular frame shape that is longer in the first direction DR1 than in the second direction DR2. The first electrode EE1 may include, for example, a first sub-electrode SUE1, a second sub-electrode SUE2, a third sub-electrode SUE3, and a fourth sub-electrode SUE4 that are connected to each other. The first sub-electrode SUE1, the second sub-electrode SUE2, the third sub-electrode SUE3, and the fourth sub-electrode SUE4 may be formed integrally.

[0168] Each of the first sub-electrode SUE1 and the second sub-electrode SUE2 may extend along the second direction DR2. The first sub-electrode SUE1 and the second sub-electrode SUE2 may face each other (eg, may be opposite to each other).

[0169] Each of the third sub-electrode SUE3 and the fourth sub-electrode SUE4 may extend along the first direction DR1. The third sub-electrode SUE3 and the fourth sub-electrode SUE4 may face each other (eg, may be opposite to each other).

[0170] The second electrode EE2 may be located in the first electrode EE1. In other words, the second electrode EE2 may be located in a region surrounded by the first electrode EE1. The second electrode EE2 may extend from the inner surface of the first electrode EE1 along a first oblique direction. Here, the first oblique direction may be defined as, for example, a direction between the first direction DR1 and the second direction DR2. A plurality of second electrodes EE2 may be provided. For one example, Figure 8 It is shown that five second electrodes EE2 are spaced apart from each other in the first electrode EE1. However, the present disclosure is not limited thereto, and two to four or six or more second electrodes EE2 may be spaced apart from each other in the first electrode EE1. When a plurality of second electrodes EE2 are provided, the intervals between the second electrodes EE2 may be the same as each other. In this case, a gap GP may exist between adjacent second electrodes EE2.

[0171] The third electrode EE3 may be located in the first electrode EE1. In other words, the third electrode EE3 may be located in a region surrounded by the first electrode EE1. The third electrode EE3 may extend from the inner surface of the first electrode EE1 along a second inclined direction. Here, the second inclined direction may be a direction that crosses or intersects (e.g., intersects substantially perpendicularly) the aforementioned first inclined direction. For example, the second inclined direction may be a direction between the first reverse direction and the second direction DR2. A plurality of third electrodes EE3 may be provided. For one example, Figure 8It is shown that four third electrodes EE3 are spaced apart from each other in the first electrode EE1. However, the present disclosure is not limited thereto, and two to three or five or more third electrodes EE3 may be spaced apart from each other in the first electrode EE1. When a plurality of third electrodes EE3 are provided, the intervals between the third electrodes EE3 may be the same. In this case, a gap GP may exist between adjacent third electrodes EE3.

[0172] Fig. 9 is a plan view of a first capacitor electrode CPE1 of a display device according to one or more embodiments.

[0173] like Fig. 9 As shown in , the first capacitor electrode CPE1 may have a spiral shape with a gap GP. For example, the first capacitor electrode CPE1 may have a spiral structure in which a plurality of first electrodes EE1 and a plurality of second electrodes EE2 extend outward while rotating in a counterclockwise direction from a central portion. Here, each first electrode EE1 may extend along a first direction DR1, and each second electrode EE2 may extend along a second direction DR2. A gap GP may be formed between adjacent first electrodes EE1, and a gap GP may be formed between adjacent second electrodes EE2. In this case, the first capacitor electrode CPE1 may have a spiral structure having a generally rectangular shape. Alternatively, the first capacitor electrode CPE1 may have a spiral structure having a generally circular shape or a generally elliptical shape.

[0174] Meanwhile, in one or more embodiments, the first capacitor electrode CPE1 may have a spiral structure extending outward while rotating in a clockwise direction from a central portion. In this case, the first capacitor electrode CPE1 may have a spiral structure having a rectangular shape as a whole. Alternatively, the first capacitor electrode CPE1 may have a spiral structure having a circular shape or an elliptical shape as a whole.

[0175] Fig.10 A diagram showing an arrangement of pixels of a display device according to one or more embodiments.

[0176] like Fig.10 As shown in , the display device may include a plurality of pixels PX1 , PX2 , PX3 , PX4 , PX5 , and PX6 .

[0177] Pixels PX1, PX2, PX3, PX4, PX5, and PX6 may be connected to data lines DL1, DL2, DL3, DL4, DL5, and DL6, respectively. For example, a first pixel PX1 and a second pixel PX2 in a first column CL1 located between a first data line DL1 and a second data line DL2 adjacent to each other may be connected to the first data line DL1 and the second data line DL2, respectively. A third pixel PX3 and a fourth pixel PX4 in a second column CL2 located between a third data line DL3 and a fourth data line DL4 adjacent to each other may be connected to the third data line DL3 and the fourth data line DL4, respectively. A fifth pixel PX5 and a sixth pixel PX6 in a third column CL3 located between a fifth data line DL5 and a sixth data line DL6 adjacent to each other may be connected to the fifth data line DL5 and the sixth data line DL6, respectively. In other words, the first pixel PX1 of the first column CL1 can be connected to the first data line DL1, the second pixel PX2 of the first column CL1 can be connected to the second data line DL2, the third pixel PX3 of the second column CL2 can be connected to the third data line DL3, the fourth pixel PX4 of the second column CL2 can be connected to the fourth data line DL4, the fifth pixel PX5 of the third column CL3 can be connected to the fifth data line DL5, and the sixth pixel PX6 of the third column CL3 can be connected to the sixth data line DL6.

[0178] Pixels arranged in the same column may provide light of the same color, and pixels arranged in different columns may provide light of different corresponding colors. For example, each of the pixels PX1 and PX2 of the first column CL1 may provide light of a first color, each of the pixels PX3 and PX4 of the second column CL2 may provide light of a second color, and each of the pixels PX5 and PX6 of the third column CL3 may provide light of a third color. In one example, the first color may be red (R), the second color may be green (G), and the third color may be blue (B). However, the present disclosure is not limited thereto, and the first color may be any one of green and blue, the second color may be any one of red and blue, and the third color may be any one of red and green.

[0179] In the display device according to one or more embodiments, a plurality of pixels arranged in the same column can be driven by two data lines, thereby improving the driving speed of the display device. For example, the display device of one or more embodiments can be driven at a frequency of about 120 Hz or higher.

[0180] Fig.11 yes Fig.10 A circuit configuration diagram of the first pixel PX1 is shown in FIG.

[0181] like Fig.11As shown in , the first pixel PX1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, a second capacitor C2, and a light emitting element ED.

[0182] The first transistor T1 may include a first gate electrode connected to a first node N1 (or gate node N1), a first source electrode connected to a driving voltage line VDL transmitting a driving voltage ELVDD, and a first drain electrode connected to a second node N2. The first drain electrode of the first transistor T1 may be connected to a pixel electrode (or anode electrode) of the light emitting element ED through a fourth transistor T4. The first transistor T1 may be used as a driving transistor, and may control the size (e.g., current amount) of a driving current flowing to the light emitting element ED by receiving a data signal DATA according to a switching operation of the second transistor T2.

[0183] The second transistor T2 may include a second gate electrode connected to the first scan line GWL, a second source electrode connected to the first data line DL1, and a second drain electrode connected to the third node N3. The second transistor T2 may be turned on according to the first scan signal GW transmitted to the first scan line GWL to electrically connect the first data line DL1 to the third node N3, and may transmit the data signal DATA transmitted to the first data line DL1 to the third node N3.

[0184] The third transistor T3 may include a third gate electrode connected to the second scan line GCL, a third source electrode connected to the first node N1, and a third drain electrode connected to the second node N2. The third transistor T3 may be turned on according to the second scan signal GC transmitted to the second scan line GCL to electrically connect the first node N1 to the second node N2.

[0185] The fourth transistor T4 may include a fourth gate electrode connected to the emission control line EML, a fourth source electrode connected to the second node N2, and a fourth drain electrode connected to a fourth node N4 (or a pixel electrode or an anode electrode). The fourth transistor T4 may be turned on or off according to an emission control signal EM transmitted to the emission control line EML.

[0186] The fifth transistor T5 may include a fifth gate electrode connected to the third scan line GRL, a fifth source electrode connected to the third node N3, and a fifth drain electrode connected to the fourth node N4. The fifth transistor T5 may be turned on according to the third scan signal GR transmitted to the third scan line GRL to electrically connect the third node N3 and the fourth node N4.

[0187] The first capacitor C1 may be connected between the first node N1 and the driving voltage line VDL.

[0188] The second capacitor C2 may be connected between the third node N3 and the first node N1.

[0189] The light emitting element ED may include a pixel electrode (or anode electrode) and a counter electrode (e.g., cathode electrode) facing the pixel electrode, and a common voltage ELVSS may be applied to the counter electrode. The counter electrode may be connected to a common voltage line VSL that transmits the common voltage ELVSS. The counter electrode may be a common electrode commonly shared by a plurality of pixels.

[0190] Fig.10 The other pixels PX2 to PX6 may also have the same Fig.11 The circuit configuration of the first pixel PX1 is the same as the circuit configuration.

[0191] At the same time, if Fig.11 As shown in FIG. , the data lines are located at both sides of a pixel, respectively, so that a first coupling capacitor Ccp1 can be formed between the first data line DL1 and the gate electrode of the driving transistor (e.g., the first transistor T1), and a second coupling capacitor Ccp2 can be formed between the second data line DL2 and the gate electrode of the driving transistor T1. The first coupling capacitor Ccp1 and the second coupling capacitor Ccp2 may cause crosstalk (e.g., vertical crosstalk), thereby deteriorating the image quality of the display device. However, by using the above-mentioned Figure 2 (or Figure 5 ) shown in the structure of the capacitor CPT, the display device according to one or more embodiments can reduce or minimize crosstalk. Fig.12 This is described in detail.

[0192] Fig.12 is a cross-sectional view of a display device according to one or more embodiments, and Fig.13 yes Fig.12 A plan view of one or more embodiments of a first-second capacitor. Fig.13 The cross-sectional view taken along line II-II' may correspond to Fig.12 The first-second capacitor C1-2.

[0193] Reference Fig.12 , the first pixel PX1 (see Fig.10 ), the first transistor T1 of the first pixel PX1 (hereinafter referred to as the first-first transistor T1-1), and the second pixel PX2 (hereinafter referred to as the first-second transistor T1-2). Fig.10 ) may be located on the base substrate SUB1.

[0194] Each of the transistors T1 - 2 , T1 - 1 , and T2 - 2 may include a gate electrode G, a source electrode S, and a drain electrode D.

[0195] The first insulating layer INS1 may be located on the base substrate SUB1.

[0196] The first-first source connection electrode SCE1 - 1 , the first gate connection electrode GCE1 , and the second-first source connection electrode SCE2 - 1 may be located on the first insulating layer INS1 .

[0197] The first-first source connection electrode SCE1 - 1 may be connected to the source electrode S of the first-second transistor T1 - 2 through a contact hole of the first insulating layer INS1 .

[0198] The first gate connection electrode GCE1 may be connected to the gate electrode G of the first-first transistor T1 - 1 through a contact hole of the first insulating layer INS1 .

[0199] The second-first source connection electrode SCE2 - 1 may be connected to the source electrode S of the second-second transistor T2 - 2 through a contact hole of the first insulating layer INS1 .

[0200] The second insulating layer INS2 may be on the first-first source link electrode SCE1 - 1 , the first gate link electrode GCE1 , and the second-first source link electrode SCE2 - 1 .

[0201] The first-second source link electrode SCE1 - 2 , the second gate link electrode GCE2 , and the second-second source link electrode SCE2 - 2 may be located on the second insulating layer INS2 .

[0202] The first-second source link electrode SCE1 - 2 may be connected to the first-first source link electrode SCE1 - 1 through a contact hole of the second insulating layer INS2 .

[0203] The second gate connection electrode GCE2 may be connected to the first gate connection electrode GCE1 through the contact hole of the second insulating layer INS2.

[0204] The second-second source link electrode SCE2-2 may be connected to the second-first source link electrode SCE2-1 through the contact hole of the second insulating layer INS2.

[0205] The third insulating layer INS3 may be located on the first-second source connection electrode SCE1-2, the second gate connection electrode GCE2, and the second-second source connection electrode SCE2-2. Figure 4 The first insulating layer INS1 is the same as or may be the same as the first insulating layer INS1 Figure 4The first insulating layer INS1 includes the same material.

[0206] The display device may include a first capacitor C1 and a second capacitor C2 on the third insulating layer INS3.

[0207] The first capacitor C1 may include a first-first capacitor C1 - 1 and a first-second capacitor C1 - 2 that are located on different layers and connected to each other.

[0208] The first-first capacitor C1 - 1 may include a first capacitor electrode CPE1 and a second-first capacitor electrode CPE2 - 1 overlapping each other in a vertical direction (eg, the third direction DR3 ).

[0209] The first-second capacitor C1-2 may include a capacitor C1-2 disposed in a horizontal direction (eg, a second direction DR2 (see Figure 2 ) and / or a first direction DR1 (see Figure 2 )) the third-first capacitor electrode CPE3-1 and the third-second capacitor electrode CPE3-2 overlapping each other.

[0210] The second capacitor C2 may include a second-first capacitor C2-1 and a second-second capacitor C2-2 located on different layers and connected to each other.

[0211] The second-first capacitor C2 - 1 may include a first capacitor electrode CPE1 and a second-second capacitor electrode CPE2 - 2 overlapping each other in a vertical direction (eg, the third direction DR3 ).

[0212] The second-second capacitor C2 - 2 may include a fourth-first capacitor electrode CPE4 - 1 and a fourth-second capacitor electrode CPE4 - 2 overlapping each other in a horizontal direction (eg, the second direction DR2 and / or the first direction DR1 ).

[0213] The structures of the first capacitor C1 and the second capacitor C2 will be described in detail.

[0214] The first capacitor electrode CPE1 may be located on the third insulating layer INS3. The first capacitor electrode CPE1 may be, for example, a first electrode of the first-first capacitor C1-1 and a first electrode of the second-first capacitor C2-1. In other words, the first capacitor electrode CPE1 may be a common capacitor electrode shared by the first-first capacitor C1-1 and the second-first capacitor C2-1. The first capacitor electrode CPE1 may be connected to the second gate connection electrode GCE2 through a contact hole of the third insulating layer INS3. For example, the first capacitor electrode CPE1 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of any one of the first capacitor electrodes CPE1 is the same shape.

[0215] The fourth insulating layer INS4 may be located on the first capacitor electrode CPE1. Figure 4 The second insulating layer INS2 is the same as or can be the same as the above Figure 4 The second insulating layer INS2 includes the same material.

[0216] The first-third source connection electrode SCE1 - 3 , the second-first capacitor electrode CPE2 - 1 , the second-second capacitor electrode CPE2 - 2 , and the second-third source connection electrode SCE2 - 3 may be located on the fourth insulating layer INS4 .

[0217] The first to third source link electrodes SCE1 - 3 may be connected to the first to second source link electrodes SCE1 - 2 through the contact holes of the fourth insulating layer INS4 .

[0218] The second-first capacitor electrode CPE2-1 may be located on the fourth insulating layer INS4 to overlap the first capacitor electrode CPE1 of the first-first capacitor C1-1. The second-first capacitor electrode CPE2-1 may be, for example, the second electrode of the first-first capacitor C1-1. In one or more embodiments, the second-first capacitor electrode CPE2-1 may be connected to a driving voltage line VDL (see Fig.11 ). For example, the second-first capacitor electrode CPE2-1 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of the second capacitor electrodes CPE2 is the same as the shape of any one of them.

[0219] The second-second capacitor electrode CPE2-2 may be located on the fourth insulating layer INS4 to overlap with the first capacitor electrode CPE1 of the second-first capacitor C2-1. The second-second capacitor electrode CPE2-2 may be, for example, the second electrode of the second-first capacitor C2-1. In one or more embodiments, the second-second capacitor electrode CPE2-2 may be connected to the drain electrode D of the first-second transistor T1-2. The second-second capacitor electrode CPE2-2 may have, for example, the same configuration as described above. Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of the second capacitor electrodes CPE2 is the same as the shape of any one of them.

[0220] The second-third source link electrode SCE2-3 may be connected to the second-second source link electrode SCE2-2 through the contact hole of the fourth insulating layer INS4.

[0221] The fifth insulating layer INS5 may be located on the first-third source connection electrode SCE1-3, the second-first capacitor electrode CPE2-1, the second-second capacitor electrode CPE2-2, and the second-third source connection electrode SCE2-3. Figure 4 The third insulating layer INS3 is the same as or may be the same as the above Figure 4 The third insulating layer INS3 includes the same material.

[0222] The first data line DL1 , the third-first capacitor electrode CPE3 - 1 , the third-second capacitor electrode CPE3 - 2 , and the second-fourth source connection electrode SCE2 - 4 may be located on the fifth insulating layer INS5 .

[0223] The first data line DL1 may be connected to the first to third source connection electrodes SCE1 - 3 through the contact holes of the fifth insulating layer INS5 .

[0224] like Fig.13 In the example shown in , the third-first capacitor electrode CPE3-1 may have a U-shape. For example, the third-first capacitor electrode CPE3-1 may include a first electrode EE1 and a plurality of second electrodes EE2 extending from the first electrode EE1. In one or more embodiments, the third-first capacitor electrode CPE3-1 may be connected to the first capacitor electrode CPE1 through a contact hole passing through the fifth insulating layer INS5 and the fourth insulating layer INS4. The third-first capacitor electrode CPE3-1 may be, for example, a first electrode of the first-second capacitor C1-2.

[0225] like Fig.13In the example shown in , the third-second capacitor electrode CPE3-2 may have a U-shape (e.g., an inverted U-shape) including a first electrode EE1 and a second electrode EE2. For example, the third-second capacitor electrode CPE3-2 may have a shape in which the third-first capacitor electrode CPE3-1 is inverted. At least one second electrode EE2 of the third-second capacitor electrode CPE3-2 may be located between the second electrode EE2 of the third-first capacitor electrode CPE3-1, and at least one second electrode EE2 of the third-first capacitor electrode CPE3-1 may be located between the second electrode EE2 of the third-second capacitor electrode CPE3-2. The capacitor C may be formed between the corresponding facing surfaces of the third-second capacitor electrode CPE3-2 and the third-first capacitor electrode CPE3-1. In one or more embodiments, the third-second capacitor electrode CPE3-2 may be connected to the second-first capacitor electrode CPE2-1 through a contact hole of the fifth insulating layer INS5. The third-second capacitor electrode CPE3-2 may be, for example, the second electrode of the first-second capacitor C1-2.

[0226] The second to fourth source link electrodes SCE2 - 4 may be connected to the second to third source link electrodes SCE2 - 3 through the contact holes of the fifth insulating layer INS5 .

[0227] The sixth insulating layer INS6 may be located on the first data line DL1, the third-first capacitor electrode CPE3-1, the third-second capacitor electrode CPE3-2, and the second-fourth source connection electrode SCE2-4. Figure 4 The third insulating layer INS3 is the same as or may be the same as the above Figure 4 The third insulating layer INS3 includes the same material.

[0228] The fourth-first capacitor electrode CPE4 - 1 , the fourth-second capacitor electrode CPE4 - 2 , and the second data line DL2 may be located on the sixth insulating layer INS6 .

[0229] The fourth-first capacitor electrode CPE4-1 may have the same shape as that of the third-first capacitor electrode CPE3-1 described above. Fig.12 As shown in , the fourth-first capacitor electrode CPE4-1 may include a larger number of second electrodes than the third-first capacitor electrode CPE3-1. In one or more embodiments, the fourth-first capacitor electrode CPE4-1 may be connected to the first capacitor electrode CPE1 through a contact hole passing through the sixth insulating layer INS6, the fifth insulating layer INS5, and the fourth insulating layer INS4. The fourth-first capacitor electrode CPE4-1 may be, for example, a first electrode of the second-second capacitor C2-2.

[0230] The fourth-second capacitor electrode CPE4-2 may have the same shape as the aforementioned third-second capacitor electrode CPE3-2. However, compared with the third-second capacitor electrode CPE3-2, the fourth-second capacitor electrode CPE4-2 may include a larger number of second electrodes. The fourth-second capacitor electrode CPE4-2 may be connected to the second-second capacitor electrode CPE2-2 through a contact hole passing through the sixth insulating layer INS6 and the fifth insulating layer INS5. The fourth-second capacitor electrode CPE4-2 may be, for example, the second electrode of the second-second capacitor C2-2.

[0231] The second data line DL2 may be connected to the second to fourth source link electrodes SCE2 - 4 through the contact holes of the sixth insulating layer INS6 .

[0232] like Fig.12 As shown in , when the angle θ1 formed by the bottom surface and one side surface of the first capacitor electrode CPE1 is defined as the first inclination angle and the angle θ2 formed by the bottom surface and one side surface of the third-first capacitor electrode CPE3-1 is defined as the second inclination angle, the first inclination angle θ1 can be smaller than the second inclination angle θ2.

[0233] Reference Fig.12 , the capacitors (e.g., the first-first capacitor C1-1 and the second-first capacitor C2-1) may be located between the first data line DL1 and the gate electrode G of the first-first transistor T1-1 and between the second data line DL2 and the gate electrode G of the first-first transistor T1-1, respectively. In other words, the capacitors (e.g., the first-first capacitor C1-1 and the second-first capacitor C2-1) may be located between the first data line DL1 and the gate node N1 (the first gate connection electrode GCE1 and the second gate connection electrode GCE2) and between the second data line DL2 and the gate node N1 (the first gate connection electrode GCE1 and the second gate connection electrode GCE2), respectively. In this case, the capacitors (e.g., the first-first capacitor C1-1 and the second-first capacitor C2-1) may overlap the first data line DL1 and the second data line DL2, respectively, in the third direction DR3. The first-first capacitor C1-1 and the second-first capacitor C2-1 may respectively reduce or prevent the formation of coupling capacitors Ccp1 and Ccp2 (see FIG. 1 ) between the data lines DL1 and DL2 and the gate node N1 (the first gate connection electrode GCE1 and the second gate connection electrode GCE2). Fig.11 Furthermore, the first-first capacitor C1-1 and the second-first capacitor C2-1 include a structure that can have a large capacitance as described above, and thus are more advantageous in eliminating the coupling capacitors Ccp1 and Ccp2 as described above.

[0234] In addition, if Fig.12 As shown in , the second data line DL2 may be located on a layer higher than the layer where the first data line DL1 is located, so that the second data line DL2 may be relatively far from the gate node N1. Therefore, the coupling capacitor Ccp2 between the second data line DL2 and the gate node N1 may be further reduced or minimized.

[0235] Meanwhile, due to the additional data line (e.g., the second data line DL2), the formation space of the second-second capacitor C2-2 located on the same layer as the second data line DL2 becomes relatively small, and therefore, the capacitance of the second-second capacitor C2-2 may be slightly reduced. However, this can be fully compensated by the first-first capacitor C1-1 and the second-first capacitor C2-1, which may have relatively large capacitances.

[0236] Fig.14 is a cross-sectional view of a display device according to one or more embodiments.

[0237] Reference Fig.14 , the first pixel PX1 (see Fig.11 ) and the second transistor T2 of the first pixel PX1 may be located on the base substrate SUB1.

[0238] Each of the transistors T1 and T2 may include a gate electrode G, a source electrode S, and a drain electrode D.

[0239] The first insulating layer INS1 may be located on the base substrate SUB1.

[0240] The display device may include a first capacitor C1 and a second capacitor C2 located on (eg, over) the first insulating layer INS1.

[0241] The first capacitor C1 may include a first-first capacitor C1 - 1 and a first-second capacitor C1 - 2 that are located on different layers and connected to each other.

[0242] The first-first capacitor C1-1 may include capacitors located on the same layer and arranged in a horizontal direction (eg, a second direction DR2 (see Figure 2 ) and / or a first direction DR1 (see Figure 2 )) on the first-first capacitor electrode CPE1-1 and the first-second capacitor electrode CPE1-2 overlap each other. The first-first capacitor C1-1 may have the same Fig.12 and Fig.13 The structures of the first-second capacitors C1-2 are basically the same structure.

[0243] The first-second capacitor C1 - 2 may include a fifth capacitor electrode CPE5 and a sixth capacitor electrode CPE6 that are located on different layers and overlap each other in a vertical direction (eg, the third direction DR3 ).

[0244] The first-second capacitor C1-2 may have the same Figure 4 The structure of capacitor CPT is the same as the structure.

[0245] The second capacitor C2 may include a second-first capacitor C2-1 and a second-second capacitor C2-2 located on different layers and connected to each other.

[0246] The second-first capacitor C2-1 may include a second-first capacitor electrode CPE2-1 and a second-second capacitor electrode CPE2-2 located on the same layer and overlapping each other in a horizontal direction (eg, second direction DR2 and / or first direction DR1). The second-first capacitor C2-1 may have the same Fig.12 and Fig.13 The structures of the first-second capacitors C1-2 are basically the same structure.

[0247] The second-second capacitor C2 - 2 may include a third capacitor electrode CPE3 and a fourth capacitor electrode CPE4 that are located on different layers and overlap each other in a vertical direction (eg, the third direction DR3 ).

[0248] The second-second capacitor C2-2 may have the same Figure 4 The structure of capacitor CPT is the same as the structure.

[0249] The structures of the first capacitor C1 and the second capacitor C2 will be described in detail.

[0250] The first gate connection electrode GCE1, the second-first capacitor electrode CPE2-1, the second-second capacitor electrode CPE2-2, and the first drain connection electrode DCE1 may be located on the first insulating layer INS1.

[0251] The first gate connection electrode GCE1 may be connected to the gate electrode G of the first transistor T1 through a contact hole of the first insulating layer INS1 .

[0252] The second-first capacitor electrode CPE2-1 may be connected to the first drain connection electrode DCE1. For example, the second-first capacitor electrode CPE2-1 and the first drain connection electrode DCE1 may be integrally formed.

[0253] The second-first capacitor electrode CPE2 - 1 may be, for example, a second electrode of the second-first capacitor C2 - 1 .

[0254] The second capacitor electrode CPE2-2 may be connected to the first gate connection electrode GCE1. For example, the second-second capacitor electrode CPE2-2 and the first gate connection electrode GCE1 may be integrally formed. The second-second capacitor electrode CPE2-2 may be, for example, a first electrode of the second-first capacitor C2-1.

[0255] The first drain connection electrode DCE1 may be connected to the drain electrode D of the second transistor T2 through a contact hole of the first insulating layer INS1 .

[0256] The second insulating layer INS2 may be located on the first gate connection electrode GCE1, the second-first capacitor electrode CPE2-1, the second-second capacitor electrode CPE2-2, and the first drain connection electrode DCE1.

[0257] The second gate connection electrode GCE2, the first-first capacitor electrode CPE1-1, the first-second capacitor electrode CPE1-2, and the second drain connection electrode DCE2 may be located on the second insulating layer INS2.

[0258] The second gate connection electrode GCE2 may be connected to the first gate connection electrode GCE1 through the contact hole of the first insulating layer INS1.

[0259] The first-first capacitor electrode CPE1-1 may be connected to the second drain connection electrode DCE2. For example, the first-first capacitor electrode CPE1-1 and the second drain connection electrode DCE2 may be integrally formed.

[0260] The first-first capacitor electrode CPE1 - 1 may be, for example, a second electrode of the first-first capacitor C1 - 1 .

[0261] The first-second capacitor electrode CPE1-2 may be connected to the second gate connection electrode GCE2. For example, the first-second capacitor electrode CPE1-2 may be integrally formed with the second gate connection electrode GCE2.

[0262] The first-second capacitor electrode CPE1 - 2 may be, for example, a first electrode of the first-first capacitor C1 - 1 .

[0263] The second drain connection electrode DCE2 may be connected to the first drain connection electrode DCE1 through the contact hole of the second insulating layer INS2.

[0264] The third insulating layer INS3 may be located on the second gate connection electrode GCE2, the first-first capacitor electrode CPE1-1, the first-second capacitor electrode CPE1-2, and the second drain connection electrode DCE2.

[0265] The third gate connection electrode GCE3 , the third capacitor electrode CPE3 , and the third drain connection electrode DCE3 may be located on the third insulating layer INS3 .

[0266] The third gate connection electrode GCE3 may be connected to the second gate connection electrode GCE2 through the contact hole of the third insulating layer INS3.

[0267] The third capacitor electrode CPE3 may be, for example, a first electrode of the second-second capacitor C2-2. The third capacitor electrode CPE3 may be connected to the third gate connection electrode GCE3. For example, the third capacitor electrode CPE3 and the third gate connection electrode GCE3 may be integrally formed. For example, the third capacitor electrode CPE3 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of any one of the first capacitor electrodes CPE1 is the same shape.

[0268] The third drain link electrode DCE3 may be connected to the second drain link electrode DCE2 through the contact hole of the third insulating layer INS3.

[0269] A fourth insulating layer INS4 may be located on the third gate connection electrode GCE3 , the third capacitor electrode CPE3 , and the third drain connection electrode DCE3 .

[0270] The fourth gate connection electrode GCE4 , the fourth capacitor electrode CPE4 , and the fourth drain connection electrode DCE4 may be located on the fourth insulating layer INS4 .

[0271] The fourth gate connection electrode GCE4 may be connected to the third gate connection electrode GCE3 through the contact hole of the fourth insulating layer INS4.

[0272] The fourth capacitor electrode CPE4 may be located on the fourth insulating layer INS4 to overlap the third capacitor electrode CPE3. The fourth capacitor electrode CPE4 may be, for example, the second electrode of the second-second capacitor C2-2. For example, the fourth capacitor electrode CPE4 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of the second capacitor electrodes CPE2 is the same as the shape of any one of them.

[0273] The fourth drain connection electrode DCE4 may be connected to the third drain connection electrode DCE3 through the contact hole of the fourth insulating layer INS4. In addition, the fourth drain connection electrode DCE4 may be connected to the fourth capacitor electrode CPE4. For example, the fourth drain connection electrode DCE4 and the fourth capacitor electrode CPE4 may be integrally formed.

[0274] A fifth insulating layer INS5 may be located on the fourth gate connection electrode GCE4 , the fourth capacitor electrode CPE4 , and the fourth drain connection electrode DCE4 .

[0275] The fifth gate connection electrode GCE5 and the fifth capacitor electrode CPE5 may be located on the fifth insulating layer INS5 .

[0276] The fifth gate connection electrode GCE5 may be connected to the fourth gate connection electrode GCE4 through the contact hole of the fifth insulating layer INS5.

[0277] The fifth capacitor electrode CPE5 may be, for example, a first electrode of the first-second capacitor C1-2. The fifth capacitor electrode CPE5 may be connected to the fifth gate connection electrode GCE5. For example, the fifth capacitor electrode CPE5 and the fifth gate connection electrode GCE5 may be integrally formed. For example, the fifth capacitor electrode CPE5 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of any one of the first capacitor electrodes CPE1 is the same shape.

[0278] A sixth insulating layer INS6 may be located on the fifth gate connection electrode GCE5 and the fifth capacitor electrode CPE5 .

[0279] The sixth capacitor electrode CPE6 may be located on the sixth insulating layer INS6 .

[0280] The sixth capacitor electrode CPE6 may be located on the sixth insulating layer INS6 to overlap with the fifth capacitor electrode CPE5. The sixth capacitor electrode CPE6 may be, for example, the second electrode of the first-second capacitor C1-2. For example, the sixth capacitor electrode CPE6 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of the sixth capacitor electrode CPE6 is the same as the shape of any one of the second capacitor electrodes CPE2. Meanwhile, the sixth capacitor electrode CPE6 may be connected to the driving voltage line VDL (see Fig.11). For example, the sixth capacitor electrode CPE6 and the driving voltage line VDL may be integrally formed.

[0281] Fig.15 is a cross-sectional view of a display device according to one or more embodiments.

[0282] Reference Fig.15 , the first pixel PX1 (see Fig.11 ) and the second transistor T2 of the first pixel PX1 may be located on the base substrate SUB1.

[0283] Each of the transistors T1 and T2 may include a gate electrode G, a source electrode S, and a drain electrode D.

[0284] The first insulating layer INS1 may be located on the base substrate SUB1.

[0285] The display device may include a first capacitor C1 and a second capacitor C2 on the first insulating layer INS1.

[0286] The first capacitor C1 may include a first-first capacitor C1 - 1 and a first-second capacitor C1 - 2 that are located on different layers and connected to each other.

[0287] The first-first capacitor C1-1 may include capacitors located on the same layer and arranged in a horizontal direction (eg, a second direction DR2 (see Figure 2 ) and / or a first direction DR1 (see Figure 2 )) on the first-first capacitor electrode CPE1-1 and the first-second capacitor electrode CPE1-2 overlap each other. The first-first capacitor C1-1 may have the same Fig.12 and Fig.13 The structures of the first-second capacitors C1-2 are basically the same structure.

[0288] The first-second capacitor C1 - 2 may include a fourth capacitor electrode CPE4 and a fifth capacitor electrode CPE5 that are located on different layers and overlap each other in a vertical direction (eg, the third direction DR3 ).

[0289] The first-second capacitor C1-2 may have the same Figure 4 The structure of capacitor CPT is the same as the structure.

[0290] The second capacitor C2 may include a second capacitor electrode CPE2 and a third capacitor electrode CPE3 located on different layers and overlapping each other in a vertical direction (eg, a third direction DR3). The second capacitor C2 may have the same Figure 4 The structure of capacitor CPT is the same as the structure.

[0291] The structures of the first capacitor C1 and the second capacitor C2 will be described in detail.

[0292] The first gate connection electrode GCE1, the first-first capacitor electrode CPE1-1, the first-second capacitor electrode CPE1-2, and the first drain connection electrode DCE1 may be located on the first insulating layer INS1.

[0293] The first gate connection electrode GCE1 may be connected to the gate electrode G of the first transistor T1 through a contact hole of the first insulating layer INS1 .

[0294] The first-first capacitor electrode CPE1-1 may be connected to the first drain connection electrode DCE1. For example, the first-first capacitor electrode CPE1-1 and the first drain connection electrode DCE1 may be integrally formed.

[0295] The first-first capacitor electrode CPE1 - 1 may be, for example, a second electrode of the first-first capacitor C1 - 1 .

[0296] The first-second capacitor electrode CPE1-2 may be connected to the first gate connection electrode GCE1. For example, the first-second capacitor electrode CPE1-2 may be integrally formed with the first gate connection electrode GCE1.

[0297] The first-second capacitor electrode CPE1 - 2 may be, for example, a first electrode of the first-first capacitor C1 - 1 .

[0298] The first drain connection electrode DCE1 may be connected to the drain electrode D of the second transistor T2 through a contact hole of the first insulating layer INS1 .

[0299] The second insulating layer INS2 may be located on the first gate connection electrode GCE1, the first-first capacitor electrode CPE1-1, the first-second capacitor electrode CPE1-2, and the first drain connection electrode DCE1.

[0300] The second gate connection electrode GCE2 , the second capacitor electrode CPE2 , and the second drain connection electrode DCE2 may be located on the second insulating layer INS2 .

[0301] The second gate connection electrode GCE2 may be connected to the first gate connection electrode GCE1 through the contact hole of the second insulating layer INS2.

[0302] The second capacitor electrode CPE2 may be, for example, a first electrode of the second capacitor C2. The second capacitor electrode CPE2 may be connected to the second gate connection electrode GCE2. For example, the second capacitor electrode CPE2 and the second gate connection electrode GCE2 may be formed integrally. For example, the second capacitor electrode CPE2 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of any one of the first capacitor electrodes CPE1 is the same shape.

[0303] The second drain connection electrode DCE2 may be connected to the first drain connection electrode DCE1 through the contact hole of the second insulating layer INS2.

[0304] The third insulating layer INS3 may be on the second gate connection electrode GCE2 , the second capacitor electrode CPE2 , and the second drain connection electrode DCE2 .

[0305] The third gate connection electrode GCE3 , the third capacitor electrode CPE3 , and the third drain connection electrode DCE3 may be located on the third insulating layer INS3 .

[0306] The third gate connection electrode GCE3 may be connected to the second gate connection electrode GCE2 through the contact hole of the third insulating layer INS3.

[0307] The third capacitor electrode CPE3 may be located on the third insulating layer INS3 to overlap with the second capacitor electrode CPE2. The third capacitor electrode CPE3 may be, for example, the second electrode of the second capacitor C2. For example, the third capacitor electrode CPE3 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of the second capacitor electrodes CPE2 is the same as the shape of any one of them.

[0308] The third drain connection electrode DCE3 may be connected to the second drain connection electrode DCE2 through the contact hole of the third insulating layer INS3. In addition, the third drain connection electrode DCE3 may be connected to the third capacitor electrode CPE3. For example, the third drain connection electrode DCE3 and the third capacitor electrode CPE3 may be integrally formed.

[0309] A fourth insulating layer INS4 may be located on the third gate connection electrode GCE3 , the third capacitor electrode CPE3 , and the third drain connection electrode DCE3 .

[0310] The fourth gate connection electrode GCE4 and the fourth capacitor electrode CPE4 may be located on the fourth insulating layer INS4 .

[0311] The fourth gate connection electrode GCE4 may be connected to the third gate connection electrode GCE3 through the contact hole of the fourth insulating layer INS4.

[0312] The fourth capacitor electrode CPE4 may be, for example, a first electrode of the first-second capacitor C1-2. The fourth capacitor electrode CPE4 may be connected to the fourth gate connection electrode GCE4. For example, the fourth capacitor electrode CPE4 and the fourth gate connection electrode GCE4 may be integrally formed. For example, the fourth capacitor electrode CPE4 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of any one of the first capacitor electrodes CPE1 is the same shape.

[0313] A fifth insulating layer INS5 may be located on the fourth gate connection electrode GCE4 and the fourth capacitor electrode CPE4 .

[0314] The fifth capacitor electrode CPE5 may be located on the fifth insulating layer INS5. The fifth capacitor electrode CPE5 may be located on the fifth insulating layer INS5 to overlap with the fourth capacitor electrode CPE4. The fifth capacitor electrode CPE5 may be, for example, the second electrode of the first-second capacitor C1-2. For example, the fifth capacitor electrode CPE5 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of the second capacitor electrode CPE2 is the same as that of any one of the second capacitor electrodes CPE2. Meanwhile, the fifth capacitor electrode CPE5 may be connected to the driving voltage line VDL (see Fig.11 ). For example, the fifth capacitor electrode CPE5 and the driving voltage line VDL may be integrally formed.

[0315] Fig.16 is a cross-sectional view of a display device according to one or more embodiments.

[0316] Reference Fig.16 , the first pixel PX1 (see Fig.11 ) and the second transistor T2 of the first pixel PX1 may be located on the base substrate SUB1.

[0317] Each of the transistors T1 and T2 may include a gate electrode G, a source electrode S, and a drain electrode D.

[0318] The first insulating layer INS1 may be located on the base substrate SUB1.

[0319] The display device may include a first capacitor C1 and a second capacitor C2 on the first insulating layer INS1.

[0320] The first capacitor C1 may include a first-first capacitor C1 - 1 and a first-second capacitor C1 - 2 that are located on different layers and connected to each other.

[0321] The first-first capacitor C1-1 may include capacitors located on the same layer and arranged in a horizontal direction (eg, a second direction DR2 (see Figure 2 ) and / or a first direction DR1 (see Figure 2 )) on the first-first capacitor electrode CPE1-1 and the first-second capacitor electrode CPE1-2 overlap each other. The first-first capacitor C1-1 may have the same Fig.12 and Fig.13 The structures of the first-second capacitors C1-2 are basically the same structure.

[0322] The first-second capacitor C1 - 2 may include a third capacitor electrode CPE3 and a fourth capacitor electrode CPE4 that are located on different layers and overlap each other in a vertical direction (eg, the third direction DR3 ).

[0323] The first-second capacitor C1-2 may have the same Figure 4 The structure of capacitor CPT is the same as the structure.

[0324] The second capacitor C2 may include a second-first capacitor electrode CPE2-1 and a second-second capacitor electrode CPE2-2 located on the same layer and overlapping each other in a horizontal direction (eg, the second direction DR2 and / or the first direction DR1). The second capacitor C2 may have the same Fig.12 and Fig.13 The structures of the first-second capacitors C1-2 are basically the same structure.

[0325] The structures of the first capacitor C1 and the second capacitor C2 will be described in detail.

[0326] The first gate connection electrode GCE1, the second-first capacitor electrode CPE2-1, the second-second capacitor electrode CPE2-2, and the first drain connection electrode DCE1 may be located on the first insulating layer INS1.

[0327] The first gate connection electrode GCE1 may be connected to the gate electrode G of the first transistor T1 through a contact hole of the first insulating layer INS1 .

[0328] The second-first capacitor electrode CPE2-1 may be connected to the first drain connection electrode DCE1. For example, the second-first capacitor electrode CPE2-1 and the first drain connection electrode DCE1 may be integrally formed.

[0329] The second-first capacitor electrode CPE2 - 1 may be, for example, a second electrode of the second capacitor C2 .

[0330] The second capacitor electrode CPE2-2 may be connected to the first gate connection electrode GCE1. For example, the second-second capacitor electrode CPE2-2 and the first gate connection electrode GCE1 may be integrally formed. The second capacitor electrode CPE2-2 may be, for example, a first electrode of the second capacitor C2.

[0331] The first drain connection electrode DCE1 may be connected to the drain electrode D of the second transistor T2 through a contact hole of the first insulating layer INS1 .

[0332] The second insulating layer INS2 may be located on the first gate connection electrode GCE1, the second-first capacitor electrode CPE2-1, the second-second capacitor electrode CPE2-2, and the first drain connection electrode DCE1.

[0333] The second gate connection electrode GCE2, the first-first capacitor electrode CPE1-1, the first-second capacitor electrode CPE1-2, and the second drain connection electrode DCE2 may be located on the second insulating layer INS2.

[0334] The second gate connection electrode GCE2 may be connected to the first gate connection electrode GCE1 through the contact hole of the second insulating layer INS2.

[0335] The first-first capacitor electrode CPE1-1 may be connected to the second drain connection electrode DCE2. For example, the first-first capacitor electrode CPE1-1 and the second drain connection electrode DCE2 may be integrally formed.

[0336] The first-first capacitor electrode CPE1 - 1 may be, for example, a second electrode of the first-first capacitor C1 - 1 .

[0337] The first-second capacitor electrode CPE1-2 may be connected to the second gate connection electrode GCE2. For example, the first-second capacitor electrode CPE1-2 may be integrally formed with the second gate connection electrode GCE2.

[0338] The first-second capacitor electrode CPE1 - 2 may be, for example, a first electrode of the first-first capacitor C1 - 1 .

[0339] The second drain connection electrode DCE2 may be connected to the first drain connection electrode DCE1 through the contact hole of the second insulating layer INS2.

[0340] The third insulating layer INS3 may be located on the second gate connection electrode GCE2, the first-first capacitor electrode CPE1-1, the first-second capacitor electrode CPE1-2, and the second drain connection electrode DCE2.

[0341] The third gate connection electrode GCE3 and the third capacitor electrode CPE3 may be located on the third insulating layer INS3 .

[0342] The third gate connection electrode GCE3 may be connected to the second gate connection electrode GCE2 through the contact hole of the third insulating layer INS3.

[0343] The third capacitor electrode CPE3 may be, for example, a first electrode of the first-second capacitor C1-2. The third capacitor electrode CPE3 may be connected to the third gate connection electrode GCE3. For example, the third capacitor electrode CPE3 and the third gate connection electrode GCE3 may be integrally formed. For example, the third capacitor electrode CPE3 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of any one of the first capacitor electrodes CPE1 is the same shape.

[0344] A fourth insulating layer INS4 may be located on the third gate connection electrode GCE3 and the third capacitor electrode CPE3 .

[0345] The fourth capacitor electrode CPE4 may be located on the fourth insulating layer INS4. The fourth capacitor electrode CPE4 may be located on the fourth insulating layer INS4 to overlap with the third capacitor electrode CPE3. The fourth capacitor electrode CPE4 may be, for example, the second electrode of the first-second capacitor C1-2. For example, the fourth capacitor electrode CPE4 may have the same Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The shape of the second capacitor electrode CPE2 is the same as that of any one of the second capacitor electrodes CPE2. Meanwhile, the fourth capacitor electrode CPE4 may be connected to the driving voltage line VDL (see Fig.11 ). For example, the fourth capacitor electrode CPE4 and the driving voltage line VDL may be integrally formed.

[0346] Fig.17yes Fig.14 An enlarged view of part A of FIG.

[0347] like Fig.17 As shown in , the third gate connection electrode GCE3 and the fifth gate connection electrode GCE5 can be connected to each other through the fourth gate connection electrode GCE4 located between the third gate connection electrode GCE3 and the fifth gate connection electrode GCE5. In other words, the fourth gate connection electrode GCE4 can be used as a bridging electrode connecting the third gate connection electrode GCE3 and the fifth gate connection electrode GCE5 to each other. In addition, the fourth gate connection electrode GCE4 can also be used to reduce or prevent the possibility of the third gate connection electrode GCE3 being damaged by an etchant during the process of forming the fifth gate connection electrode GCE5. For example, the etchant may penetrate into the third gate connection electrode GCE3 through the contact hole CT of the fourth insulating layer INS4. However, when the fourth gate connection electrode GCE4 is pre-formed before forming the fifth gate connection electrode GCE5, the fourth gate connection electrode GCE4 can block the contact hole CT of the fourth insulating layer INS4, thereby reducing or preventing the possibility of the third gate connection electrode GCE3 being exposed to the etchant.

[0348] In one or more embodiments, the third gate connection electrode GCE3 and the fifth gate connection electrode GCE5 may be directly connected without the fourth gate connection electrode GCE4 .

[0349] Fig.18 yes Fig.14 An enlarged view of part B.

[0350] like Fig.18 As shown in , the third drain connection electrode DCE3 can be connected to the fourth drain connection electrode DCE4 through the contact hole CT of the fourth insulating layer INS4. In one or more embodiments, the fourth drain connection electrode DCE4 can also be used as a bridging electrode for connecting the third drain connection electrode DCE3 and other connection electrodes (hereinafter referred to as the fifth connection electrode) to each other. In addition, the fourth drain connection electrode DCE4 can also be used to reduce or prevent the possibility of the third drain connection electrode DCE3 being damaged by an etchant during the process of forming the fifth connection electrode.

[0351] Fig.19 is a diagram illustrating effects of a display device according to one or more embodiments.

[0352] exist Fig.19 In the example, MIM may refer to a metal-insulator-metal capacitor, MOM may refer to a metal-oxide-metal capacitor, and Example 1 may refer to the above Figure 2 The capacitor CPT, and Example 2 can refer to Figure 5 The capacitor CPT.

[0353] In addition, Fig.19 In this context, the area may refer to the area of ​​facing surfaces of the first capacitor electrode and the second capacitor electrode of each capacitor located in a region of the same size (eg, one emission region).

[0354] In addition, Fig.19 In the above, the thickness of the insulating layer may refer to the thickness of the insulating layer between the first capacitor electrode and the second capacitor electrode of each capacitor, the dielectric constant may refer to the dielectric constant of the above insulating layer, and the capacitance may refer to the capacitance of each capacitor.

[0355] like Fig.19 As shown in, among MIM, MOM, Example 1 and Example 2, MOM can have the largest area. However, because MOM has a large insulating layer due to its characteristics, the capacitor CPT of Example 1 and Example 2 can have a capacitance larger than the capacitance of the MIM capacitor. For example, in an area of ​​the same size, the capacitance of the capacitor CPT of Example 1 can be about 4 times that of the MIM capacitor, and the capacitance of the capacitor CPT of Example 2 can be about 5.4 times that of the MIM capacitor. Therefore, the capacitor of the display device according to one or more embodiments can have a larger capacitance in an area of ​​the same size. Therefore, the characteristics of the pixel circuit can be stably ensured. In addition, a capacitor with a larger capacitance can be manufactured with a smaller number of metal layers.

[0356] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the aspects of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device comprises: A first data line; a first pixel connected to the first data line, and comprising a driving transistor; and A first capacitor is between the gate electrode of the driving transistor and the first data line.

2. The display device according to claim 1, wherein: The first capacitor overlaps the first data line and the gate electrode.

3. The display device according to claim 1, wherein: The display device further includes: a second data line, adjacent to the first data line; and The second pixel is connected to the second data line.

4. The display device according to claim 3, wherein: The first capacitor is between the first data line and the gate electrode and between the second data line and the gate electrode.

5. The display device according to claim 3, wherein: The second data line is farther from the gate electrode than the first data line.

6. The display device according to claim 3, wherein: The first pixel and the second pixel are between the first data line and the second data line.

7. The display device according to claim 3, wherein: The first pixel and the second pixel are configured to provide light of the same color.

8. The display device according to claim 1, wherein: The first capacitor comprises: a first capacitor electrode including a plurality of electrodes spaced apart from each other to have a gap; an insulating layer over the first capacitor electrode; and A second capacitor electrode is over the insulating layer, and the second capacitor electrode overlaps the gap and the plurality of electrodes of the first capacitor electrode.

9. The display device according to claim 8, wherein: At least a portion of the second capacitor electrode is between adjacent electrodes of the plurality of electrodes of the first capacitor electrodes.

10. The display device according to claim 8, wherein: The second capacitor electrode overlaps an entirety of the first capacitor electrode.

11. The display device according to claim 8, wherein: An end portion of the second capacitor electrode extends further in one direction than an end portion of the first capacitor electrode.

12. The display device according to claim 1, wherein: The first capacitor comprises: a first insulating layer including a plurality of layers having a plurality of stepped portions of different respective sizes; a first capacitor electrode over the first insulating layer, and the first capacitor electrode has a plurality of stepped portions corresponding to the plurality of stepped portions of the first insulating layer; a second insulating layer over the first capacitor electrode, the second insulating layer having a plurality of stepped portions corresponding to the plurality of stepped portions of the first capacitor electrode; and A second capacitor electrode is over the second insulating layer, and the second capacitor electrode has a plurality of stepped portions corresponding to the plurality of stepped portions of the second insulating layer.

13. The display device according to claim 12, wherein: The first capacitor electrode has a larger number of layers than the first insulating layer.

14. The display device according to claim 8, wherein: The first capacitor electrode comprises: a first electrode extending in a first direction; and A plurality of second electrodes extend from the first electrode in a second direction crossing the first direction, and adjacent second electrodes of the plurality of second electrodes are spaced apart such that the gap exists between the adjacent second electrodes.

15. The display device according to claim 8, wherein: The first capacitor electrode comprises: a first electrode having a closed curved shape; and A plurality of second electrodes are inside the first electrode in a plan view and extend from the first electrode in one direction, and adjacent second electrodes among the plurality of second electrodes are spaced apart so that the gap exists between the adjacent second electrodes.

16. The display device according to claim 8, wherein: The first capacitor electrode comprises: a first electrode having a closed curved shape; and a plurality of second electrodes, which are inside the first electrode in a plan view and extend from the first electrode in a first direction and a second direction, respectively, wherein a second electrode in the first direction among the plurality of second electrodes and a second electrode in the second direction among the plurality of second electrodes cross each other perpendicularly, and Wherein, adjacent second electrodes among the plurality of second electrodes are spaced apart such that the gap exists between the adjacent second electrodes.

17. The display device according to claim 8, wherein: The first capacitor electrode comprises: a first electrode having a closed curved shape; and a plurality of second electrodes, which are inside the first electrode in a plan view and extend from the first electrode in a first oblique direction and a second oblique direction, respectively, wherein a second electrode in the first oblique direction among the plurality of second electrodes and a second electrode in the second oblique direction among the plurality of second electrodes cross each other perpendicularly, and Wherein, adjacent second electrodes among the plurality of second electrodes are spaced apart such that the gap exists between the adjacent second electrodes.

18. The display device according to claim 8, wherein: the first capacitor electrode includes a plurality of first electrodes and a plurality of second electrodes, the plurality of first electrodes and the plurality of second electrodes having a spiral structure extending outward while rotating in a counterclockwise direction from a central portion, wherein adjacent first electrodes among the plurality of first electrodes are spaced apart so that the gap exists between the adjacent first electrodes, and Wherein, adjacent second electrodes among the plurality of second electrodes are spaced apart such that the gap exists between the adjacent second electrodes.

19. The display device according to claim 1, wherein: The display device also includes a second capacitor above the first capacitor.

20. The display device according to claim 19, wherein: The second capacitor is at the same layer as the first data line.

21. The display device according to claim 19, wherein: The second capacitor comprises: a first capacitor electrode; and A second capacitor electrode is adjacent to the first capacitor electrode, and the second capacitor electrode is at the same layer as the first capacitor electrode.

22. The display device according to claim 21, wherein: The first capacitor includes a first capacitor electrode and a second capacitor electrode facing each other on different layers, and The inclination angle of the first capacitor electrode in the first capacitor is smaller than the inclination angle of the first capacitor electrode in the second capacitor.

23. The display device according to claim 8, wherein: The display device further includes: a first connecting electrode connected to the first capacitor electrode; a second connecting electrode, above the first connecting electrode; and The third connection electrode connects the first connection electrode to the second connection electrode, and the third connection electrode is between the first connection electrode and the second connection electrode.

24. A display device, wherein: The display device comprises: substrate; a transistor, over the substrate; a first data line above the transistor; and A capacitor is provided between the gate electrode of the transistor and the first data line.

25. The display device according to claim 24, wherein: The capacitor overlaps the first data line and the gate electrode.

26. The display device according to claim 25, wherein: The display device also includes a second data line adjacent to the first data line.

27. The display device according to claim 26, wherein: The capacitor is between the first data line and the gate electrode and between the second data line and the gate electrode.

28. The display device according to claim 26, wherein: The second data line is farther from the gate electrode than the first data line.

29. The display device according to claim 24, wherein: The capacitor comprises: a first capacitor electrode including a plurality of electrodes spaced apart from each other to have a gap; an insulating layer over the first capacitor electrode; and A second capacitor electrode is over the insulating layer to overlap the gap and the plurality of electrodes of the first capacitor electrode.

30. The display device according to claim 29, wherein: At least a portion of the second capacitor electrode is between adjacent electrodes of the plurality of electrodes of the first capacitor electrodes.

Images