Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a storage region; a plurality of memory gate grooves located in the memory region, wherein the memory gate grooves are separated from each other and are paired; the storage gate structures are at least partially located in the storage gate grooves, and each storage gate structure comprises floating gate dielectric layers located on the side walls and the bottom surfaces of the storage gate grooves, floating gates at least partially located on the surfaces of the floating gate dielectric layers in the storage gate grooves, control gate dielectric layers located on the surfaces of the floating gates and control gates located on the surfaces of the control gate dielectric layers; the first doped region is positioned in the storage region between the paired storage gate structures; the erasing gate dielectric layer is positioned on the surface of the first doped region; the erasing gate is located on the surface of the erasing gate dielectric layer, and the bottom surface of the erasing gate is lower than or flush with the top surface of the floating gate; and the second doped regions are positioned in the storage regions on the two sides of the paired storage gate structures. According to the semiconductor structure and the forming method thereof, the writing efficiency and the erasing efficiency of a memory are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Embedded flash memory (flash) is a non-volatile memory widely used in the automotive, consumer and other fields. With the rapid increase in market demand for new energy vehicles in recent years, the demand for chip storage and processing performance and cost has also increased rapidly. Various research institutions are focusing on the layout and development of flash memory devices with higher write and erase performance.

[0003] At present, common flash memory devices have a floating gate, an oxide-nitride-oxide dielectric layer located on the floating gate, and a control gate located on the dielectric layer. The sidewalls and bottom of the floating gate have a tunnel dielectric layer, and the substrate on both sides of the floating gate also has a source line and a drain line. When programming, a large voltage difference is applied between the source line and the drain line to generate a conduction current, and a high voltage is applied to the control gate, so that electrons pass through the tunnel dielectric layer into the floating gate to achieve signal writing. When erasing, the electrons in the floating gate flow out by controlling the voltage difference, thereby reducing the threshold voltage for opening the channel under the floating gate, and achieving signal erasure.

[0004] However, in the prior art, due to the limitations of process window and device structure, there is still much room for improvement in the writing efficiency and erasing efficiency of flash memory. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the writing efficiency and erasing efficiency of a flash memory.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a storage area; a plurality of storage gate grooves located in the storage area, the storage gate grooves are separated from each other, and two of the storage gate grooves form a pair; a storage gate structure at least partially located in the storage gate grooves, and the storage gate structures in the paired storage gate grooves form a pair, each storage gate structure comprising: a floating gate dielectric layer located on the side wall and bottom surface of the storage gate groove, a floating gate located at least partially on the surface of the floating gate dielectric layer in the storage gate groove, a control gate dielectric layer located on the surface of the floating gate, and a control gate located on the surface of the control gate dielectric layer; a first doped region located in the storage area between the paired storage gate structures; an erase gate dielectric layer located on the surface of the first doped region; an erase gate located on the surface of the erase gate dielectric layer, the bottom surface of the erase gate being lower than or flush with the top surface of the floating gate; and a second doped region located in the storage area on both sides of the paired storage gate structures.

[0007] Optionally, a first opening is defined in the floating gate, and the control gate dielectric layer and the control gate are located in the first opening.

[0008] Optionally, the floating gate includes a first floating gate structure and a second floating gate structure located around the first floating gate structure, and the first opening is located between the second floating gate structures and exposes a surface of the first floating gate structure.

[0009] Optionally, a top surface of the first floating gate structure and a sidewall surface of the second floating gate structure are perpendicular to each other, and a top surface of the first floating gate structure is parallel to a surface of the storage region.

[0010] Optionally, the top of the second floating gate structure is higher than the top of the erase gate dielectric layer.

[0011] Optionally, a top surface of the second floating gate structure is flush with a top surface of the erase gate.

[0012] Optionally, it also includes: word line structures located on both sides of the paired storage gate structures, the two word line structures are respectively located on the sidewall surfaces of the two storage gate structures away from the erase gate, and each word line structure is located between the storage gate structure and the second doping region.

[0013] Optionally, a top surface of the word line structure, a top surface of the control gate, and a top surface of the erase gate are flush with each other.

[0014] Optionally, the substrate further includes a logic region; the semiconductor structure further includes: a gate oxide layer located on a surface of the logic region and a gate located on a surface of the gate oxide layer.

[0015] Optionally, a top surface of the gate, a top surface of the control gate, and a top surface of the erase gate are flush with each other.

[0016] Optionally, the center of the top surface of the erase gate dielectric layer is higher than the edge of the top surface of the erase gate dielectric layer, so that the bottom surface of the erase gate protrudes in a direction away from the substrate surface.

[0017] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a storage area; forming a plurality of storage gate grooves in the storage area, the storage gate grooves being separated from each other, and two of the storage gate grooves forming a pair; forming a storage gate structure in the storage gate groove, the storage gate structure being at least partially located in the storage gate groove, each storage gate structure comprising: a floating gate dielectric layer located on the sidewall and bottom surface of the storage gate groove, a floating gate located at least partially on the surface of the floating gate dielectric layer in the storage gate groove, a control gate dielectric layer located on the surface of the floating gate, and a control gate located on the surface of the control gate dielectric layer; forming a first doped region in the storage area between the paired storage gate structures; forming a second doped region in the storage areas on both sides of the paired storage gate structures; forming an erase gate dielectric layer on the surface of the first doped region; forming an erase gate on the surface of the erase gate dielectric layer, the bottom surface of the erase gate being lower than or flush with the top surface of the floating gate.

[0018] Optionally, the method for forming the storage gate structure includes: forming a floating gate dielectric layer at the bottom and side wall surface of the storage gate groove; forming a floating gate on the floating gate dielectric layer in the storage gate groove, wherein the floating gate has a first opening; forming a control gate dielectric layer at the bottom of the first opening, the side wall of the first opening, the side wall of the floating gate and the top surface of the floating gate; and forming a control gate on the surface of the control gate dielectric layer in the first opening.

[0019] Optionally, the method for forming the floating gate includes: forming a floating gate material layer in the storage gate groove and on the surface of the storage area; forming a first mask layer on the surface of the floating gate material layer, the first mask layer at least exposing a portion of the surface of the floating gate material layer in the storage gate groove; using the first mask layer as a mask, etching the floating gate material layer to form a floating gate at least partially located on the sidewalls and bottom surface of the storage gate groove, and forming a first opening in the floating gate.

[0020] Optionally, it also includes: forming word line structures on the surfaces of the storage areas on both sides of the paired storage gate structures, the two word line structures are respectively located on the sidewall surfaces of the two storage gate structures away from the erase gate, and each word line structure is located between the storage gate structure and the second doping region.

[0021] Optionally, an erase gate and a word line structure are formed simultaneously with forming the control gate, and the top surface of the control gate, the top surface of the erase gate, the top surface of the floating gate and the top surface of the word line structure are flush with each other.

[0022] Optionally, the method for forming the control gate, erase gate and word line structure includes: forming a first material layer in the first opening, on the surface of the floating gate and on the surface of the storage area; flattening the first material layer until the top surface of the floating gate is exposed to form the control gate, and the top surface of the control gate is flush with the top surface of the floating gate; etching the first material layer on the surface of the storage area on both sides of the paired storage gate structure to form a word line structure.

[0023] Optionally, the ion doping concentration at the center of the first doping region is greater than the ion doping concentration at the edge of the first doping region.

[0024] Optionally, the process of forming the erase gate dielectric layer includes an oxidation process.

[0025] Optionally, the center of the top surface of the erase gate dielectric layer is higher than the edge of the top surface of the erase gate dielectric layer, so that the bottom surface of the erase gate protrudes in a direction away from the substrate surface.

[0026] Optionally, the substrate also includes a logic area; the method for forming the semiconductor structure also includes: before forming the erase gate, forming a gate oxide layer on the surface of the logic area; after forming the gate oxide layer, forming a gate on the surface of the gate oxide layer.

[0027] Optionally, the gate oxide layer and the erase gate dielectric layer are formed simultaneously.

[0028] Optionally, the gate is formed simultaneously with the control gate and the erase gate, and the top surface of the gate is flush with the top surfaces of the control gate and the erase gate.

[0029] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0030] In the semiconductor structure provided by the technical solution of the present invention, at least part of the floating gate is located in the storage gate groove in the substrate, so that part of the side wall of the floating gate is located in the substrate. Therefore, when the semiconductor structure is working, the floating gate has a higher coupling voltage, so that after the coupling voltage is on the floating gate, an electric field perpendicular to the side wall of the floating gate can be formed; and in the process of the electrons flowing from the second doping region to the first doping region, the direction of the electron flow is also perpendicular to the side wall of the floating gate. Since the direction of the electron flow is parallel to the direction of the electric field of the floating gate side wall, the buried floating gate structure increases the tunneling efficiency of the electrons at the floating gate side wall and improves the writing efficiency of the memory.

[0031] Furthermore, since the bottom surface of the erase gate is lower than or flush with the top surface of the floating gate, and the bottom surface of the erase gate protrudes away from the substrate surface, the bottom edge of the erase gate has a sharp corner, which is beneficial to the concentration of the electric field at this location, thereby enhancing the tunneling efficiency of electrons and improving the erasing efficiency of the device.

[0032] Furthermore, the floating gate has a first opening, and the control gate dielectric layer and the control gate are located in the first opening. Since the floating gate is located around the control gate, the bottom and sidewalls of the control gate can form a capacitor structure with the floating gate, thereby greatly increasing the working area of ​​the capacitor plate and increasing its capacitance value. When the device performs a write operation, pressure is applied to the control gate. Since the relative area between the floating gate and the control gate is larger, the voltage obtained by coupling on the floating gate is larger, thereby also enhancing the electric field, improving the efficiency of electron tunneling, and improving the write efficiency of the device. When the device performs an erase operation, the control gate is connected to 0V and the erase gate is connected to a high voltage. At this time, the voltage obtained by coupling the floating gate is negatively correlated with the capacitance value between the floating gate and the control gate. Since the relative area between the floating gate and the control gate is larger, the voltage obtained by coupling the floating gate is correspondingly reduced, thereby increasing the potential difference between the floating gate and the erase gate, thereby increasing the efficiency of electron tunneling and improving the erase efficiency.

[0033] In the method for forming a semiconductor structure provided by the technical solution of the present invention, at least part of the floating gate is formed in a storage gate groove in a substrate, so that part of the side wall of the floating gate is located in the substrate. When the semiconductor structure is working, the floating gate has a high coupling voltage, so that an electric field perpendicular to the side wall of the floating gate can be formed, and in the process of the electrons flowing from the second doping region to the first doping region, the direction of the electron flow is also perpendicular to the side wall of the floating gate. Since the direction of the electron flow is parallel to the direction of the electric field of the floating gate side wall, the buried floating gate structure increases the tunneling efficiency of the electrons at the floating gate side wall and improves the writing efficiency of the memory.

[0034] Furthermore, since the floating gate has a first opening, a control gate dielectric layer is formed on the top surface of the floating gate, the control gate is located in the first opening, and part of the floating gate is buried in the substrate, the height difference between the floating gate, the control gate and the word line structure can be controlled by controlling the depth of the floating gate buried in the substrate, and the top of the floating gate, the control gate, the erase gate, the word line structure and the gate can be ensured to be flush through a planarization process, and the floating gate, the control gate and the word line structure have the required overall height difference. Therefore, the etching stop process of the word line structure and the control gate surface is omitted, the number of deposition and patterning processes is saved, and the use of a planarization process can better control the height and morphology of the floating gate, the control gate, the erase gate, the word line structure and the gate, and increase the controllability of the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a cross-sectional schematic diagram of a semiconductor structure;

[0036] Figures 2 to 10 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, under current technology, due to the limitations of process window and device structure, there is still much room for improvement in the write efficiency and erase efficiency of flash memory.

[0038] Figure 1 It is a cross-sectional schematic diagram of a semiconductor structure.

[0039] Please refer to Figure 1 The semiconductor structure includes: a substrate 100; two storage gate structures (not labeled) separated from each other and located on the surface of the substrate 100, with a first opening (not labeled) between the two storage gate structures, each storage gate structure including a floating gate dielectric layer 101, a floating gate 103, a control gate dielectric layer 113 and a control gate 120 located on the control gate dielectric layer 113; a tunneling dielectric layer 126 located on the surface of the floating gate 103 and the surface of the control gate 120 exposed by the first opening; a first doped region 126 located in the bottom of the substrate 100; 141; an erase gate dielectric layer 150 located on the surface of the first doped region 141; an erase gate 131 located in the first opening; a second doped region 140 located in the substrate 100 on both sides of the paired storage gate structure; a word line structure 130 located on the surface of the substrate 100 on both sides of the paired storage gate structure, the word line structure 130 being located between the storage gate structure and the second doped region 140; a plug 160 electrically connected to the second doped region 140, the word line structure 130, the control gate 120, the erase gate 131 and the source line doped region 141.

[0040] In this embodiment, the surface of the control gate 120 further has a mask structure 125. The floating gate dielectric layer 101 includes a first silicon oxide layer 110, a silicon nitride layer 111 located on the first silicon oxide layer 110, and a second silicon oxide layer 112 located on the silicon nitride layer 111.

[0041] In this embodiment, the sidewall surfaces of the floating gate 103 and the control gate 120 further include a first sidewall spacer 121 and a second sidewall spacer 122 .

[0042] When the semiconductor structure performs a write operation, a voltage is applied to the second doping region 140 and the first doping region 141 to form a potential difference between the second doping region 140 and the first doping region 141, so that electrons flow from the drain line doping region 140 to the source line doping region 141 (e.g. Figure 1 At the same time, a high voltage is applied to the control gate 120 to form an electric field perpendicular to the floating gate 103, and then under the action of the electric field, the electrons passing through are tunneled into the floating gate 103 (as shown in FIG. Figure 1 However, since the electron flow direction is perpendicular to the tunneling electric field direction, the electron tunneling efficiency is low and the memory writing efficiency is low.

[0043] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein in the formation method, at least a portion of the floating gate is formed in a storage gate groove in the substrate, so that a portion of the sidewall of the floating gate is located in the substrate. When the semiconductor structure is working, the floating gate has a high coupling voltage, so that an electric field perpendicular to the sidewall of the floating gate can be formed, and in the process of the electrons flowing from the second doping region to the first doping region, the direction of the electron flow is also perpendicular to the sidewall of the floating gate. Since the direction of the electron flow is parallel to the direction of the electric field of the floating gate sidewall, the buried floating gate structure increases the tunneling efficiency of the electrons at the sidewall of the floating gate, thereby improving the writing efficiency of the memory.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 2 to 10 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0046] Please refer to Figure 2 , providing a substrate 200, wherein the substrate 200 includes a storage area I and a logic area II; forming a plurality of storage gate grooves 202 in the storage area I, wherein the storage gate grooves 202 are separated from each other, and two of the storage gate grooves 202 form a pair.

[0047] The material of the substrate 200 includes silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), etc. Specifically, in this embodiment, the material of the substrate 200 is silicon.

[0048] In this embodiment, the storage area I provides a platform for a storage gate structure, a word line structure and an erase gate to be formed subsequently; and the logic area II provides a platform for a gate oxide layer and a gate to be formed subsequently.

[0049] In this embodiment, the storage gate groove 202 provides space for a storage gate structure to be formed subsequently.

[0050] Specifically, the method for forming the storage gate groove 202 includes: forming an initial mask layer (not shown) on the surface of the storage area I, the initial mask layer exposing a portion of the surface of the storage area I; etching the storage area I using the initial mask layer as a mask to form the storage gate groove 202.

[0051] In this embodiment, an isolation structure 201 is further formed in the logic region II. The isolation structure 201 is used to electrically isolate the logic devices on the logic region II.

[0052] After the storage gate groove 202 and the isolation structure 201 are formed, a floating gate dielectric layer 203 is formed on the surface of the storage area I, the surface of the logic area II, the bottom surface and the sidewall surface of the storage gate groove 202 .

[0053] Please refer to Figure 3 A floating gate material layer 205 is formed in the storage gate groove 202, on the surface of the storage area I and on the surface of the logic area II.

[0054] In this embodiment, the floating gate material layer 205 is made of polysilicon.

[0055] The floating gate material layer 205 provides raw materials for the floating gate formed subsequently.

[0056] Please refer to Figure 4 , the floating gate material layer 205 is etched to form a floating gate 210 on the floating gate dielectric layer 203 in the storage gate groove 202 , wherein the floating gate 210 has a first opening 213 .

[0057] In this embodiment, the first opening 213 provides space for a control gate dielectric and a control gate to be formed subsequently.

[0058] In this embodiment, the floating gate 210 includes a first floating gate structure 211 and a second floating gate structure 212 located around the first floating gate structure 211 . The first opening 213 is located between the second floating gate structures 212 and exposes the surface of the first floating gate structure 211 . The floating gate 210 is “U-shaped”.

[0059] The top surface of the first floating gate structure 211 and the side wall surface of the second floating gate structure 212 are perpendicular to each other, and the top surface of the first floating gate structure 211 is parallel to the surface of the storage area I.

[0060] In this embodiment, the cross-sections of the first floating gate structure 211 and the second floating gate structure 212 in a direction perpendicular to the surface of the storage area I are both rectangular.

[0061] In other embodiments, the cross-sections of the first floating gate structure and the second floating gate structure in a direction perpendicular to the surface of the storage region may be trapezoidal, elliptical, or parallelogram.

[0062] Specifically, in the present embodiment, the method for forming the floating gate 210 includes: forming a first mask layer (not shown) on the surface of the floating gate material layer 205, the first mask layer exposing at least a portion of the surface of the floating gate material layer 205 within the storage gate groove 202; using the first mask layer as a mask, etching the floating gate material layer 205 to form a floating gate 210 at least partially located on the sidewalls and bottom surface of the storage gate groove 202, and forming a first opening 213 in the floating gate 210.

[0063] Please refer to Figure 5 Through deposition and etching processes, a control gate dielectric layer 218 is formed at the bottom of the first opening 213, the sidewalls of the first opening 213, the sidewalls of the floating gate 210 and the top surface of the floating gate 210; a first doped region 222 is formed in the storage area I between the paired storage gate grooves 202; a word line doped region 221 is formed in the storage area I on both sides of the paired storage gate grooves 202; and a first well region 223 and a second well region 224 are formed in the logic area II on both sides of the isolation structure 201.

[0064] The control gate dielectric layer 218 includes: a first oxide layer 215 , a first nitride layer 216 located on the surface of the first oxide layer 215 , and a second oxide layer 217 located on the surface of the first nitride layer 216 .

[0065] In this embodiment, the first doping region 222 is a source line doping region, and the word line doping region 221 is used to control the formation of a channel.

[0066] Specifically, the first doping region 222 contains N-type doping ions, and the word line doping region 221 contains P-type doping ions. The ion doping concentration in the first doping region 222 is greater than the ion doping concentration in the word line doping region 221 .

[0067] The first doping region 222 and the word line doping region 221 are formed by ion implantation. Since the ion concentration is higher in the center of the implanted region during the ion implantation process, the ion doping concentration in the center of the first doping region 222 is greater than the ion doping concentration at the edge of the first doping region 222.

[0068] In this embodiment, the first well region 223 and the second well region 224 are inverted, so as to form different types of MOS transistors, wherein the first well region 223 has N-type doping ions, and the second well region 224 has P-type doping ions.

[0069] Please refer to Figure 6 , remove the floating gate dielectric layer 203 on the surface of the first doped region 222 and the logic region II; form an erase gate dielectric layer 238 on the surface of the first doped region 222, and form a gate oxide layer 232 on the surface of the logic region II.

[0070] In this embodiment, the erase gate dielectric layer 238 and the gate oxide layer 232 are formed simultaneously; the materials of the erase gate dielectric layer 238 and the gate oxide layer 232 include silicon oxide. The process of forming the erase gate dielectric layer 238 and the gate oxide layer 232 includes an oxidation process.

[0071] In other embodiments, the erase gate dielectric layer and the gate oxide layer may be formed successively.

[0072] In this embodiment, the ion doping concentration at the center of the first doping region 222 is greater than the ion doping concentration at the edge of the first doping region 222. When the erase gate dielectric layer 238 is formed by oxidation on the surface of the first doping region 222, the center of the first doping region 222 is more damaged by ion implantation. Therefore, the density of the silicon substrate 200 at the center is reduced, which is beneficial to the diffusion of oxygen and consumes more silicon substrate 200, so that the erase gate dielectric layer 238 formed on the surface of the center of the first doping region 222 is thicker.

[0073] In this embodiment, the center of the top surface of the erase gate dielectric layer 238 finally formed is higher than the edge of the top surface of the erase gate dielectric layer 238 , so that the top surface of the erase gate dielectric layer 238 bulges away from the surface of the substrate 200 .

[0074] In this embodiment, the top surface of the erase gate dielectric layer 238 is lower than the top surface of the floating gate 210 .

[0075] In other embodiments, the top surface of the erase gate dielectric layer 238 is flush with the top surface of the floating gate 210 .

[0076] Please refer to Figure 7 A first material layer 220 is formed on the surface of the control gate dielectric layer 218 , the surface of the floating gate 210 , the surface of the storage area I and the surface of the logic area II in the first opening 213 .

[0077] The material of the first material layer 220 includes polysilicon. The first material layer 220 provides raw materials for the word line structure, control gate, erase gate and gate formed subsequently.

[0078] Please refer to Figure 8, planarizing the first material layer 220 until the top surface of the floating gate 210 is exposed, forming the control gate 232 and the erase gate 231, and the top surface of the control gate 232, the top surface of the erase gate 231 and the top surface of the floating gate 210 are flush.

[0079] In the process of planarizing the first material layer 220 , the control gate dielectric layer 218 on the top surface of the floating gate 210 acts as an etch stop layer to regulate the position of the end point of the planarization process of the first material layer 220 .

[0080] Among them, since the top surface of the erase gate dielectric layer 238 is convex in the direction away from the surface of the substrate 200, the erase gate dielectric layer 238 regulates the morphology of the bottom of the erase gate 231 formed thereon, so that the bottom surface of the erase gate 231 formed is also convex in the direction away from the surface of the substrate 200. Therefore, the edge of the erase gate 231 has a sharp corner protruding downward (such as Figure 8 In addition, since the sharp corner is formed when the erase gate 231 is formed, and the erase gate 231 is formed after the oxidation process of the erase gate dielectric layer 238 and the gate oxide layer 232, the sharp corner is prevented from being oxidized and affecting the morphology. When the semiconductor device performs an erase operation, the electric field at the sharp corner of the edge of the erase gate 231 is more concentrated, so that it is easier to draw electrons in the floating gate 210 to the erase gate 231 under the action of a strong electric field, thereby improving the tunneling efficiency of the electrons and the erasing efficiency of the device.

[0081] In this embodiment, the bottom surface of the erase gate 231 is lower than the top surface of the floating gate 210 .

[0082] In other embodiments, the bottom surface of the erase gate is flush with the top surface of the floating gate.

[0083] Please refer to Fig. 9 , etch the first material layer 220 on the surface of the storage area I on both sides of the paired storage gate structure, and form a word line structure 233 on the surface of the storage area I on both sides of the paired storage gate structure; etch the first material layer 220 on the surface of the logic area II, and form a gate 235 on the surface of the gate oxide layer 232.

[0084] The two word line structures 233 are respectively located on the sidewall surfaces of the two storage gate structures away from the erase gate 231 .

[0085] In this embodiment, the top surface of the control gate 232 , the top surface of the erase gate 231 , the top surface of the floating gate 210 , the word line structure 233 , and the top surface of the gate 235 are flush with each other.

[0086] In the present embodiment, since the floating gate 210 has a first opening 213, a control gate dielectric layer 218 is formed on the top surface of the floating gate 210, the control gate 232 is located in the first opening 213, and part of the floating gate 210 is buried in the substrate 200. Therefore, the height difference between the floating gate 210, the control gate 232 and the word line structure 233 can be controlled by controlling the depth of the floating gate 210 buried in the substrate 200. By planarizing, the control gate dielectric layer 218 on the top of the floating gate 210 is used as an etching stop layer, and the control gate 232, the erase gate 231, the word line structure 233 and the gate 235 can be formed at the same time, and the tops of the floating gate 210, the control gate 232, the erase gate 231, the word line structure 233 and the gate 235 are ensured to be flush, and the floating gate 210, the control gate 232 and the word line structure 233 have the required overall height difference. Therefore, this process omits the etching stop process on the surface of the word line structure 233 and the control gate 232, reduces the process difficulty, expands the process window, saves the number of deposition and graphic processes, and adopts a planarization process to better control the height and morphology of the floating gate 210, the control gate 232, the erase gate 231, the word line structure 233 and the gate 235, thereby increasing the controllability of the process.

[0087] After forming the control gate 232 and the erase gate 231, the floating gate 210 dielectric layer 203, the floating gate 210, the control gate dielectric layer 218 and the control gate 232 constitute a storage gate structure. Specifically, as described in the above steps, the storage gate structure is at least partially located in the storage gate groove 202, and each storage gate structure includes: the floating gate dielectric layer 203 located on the sidewall and bottom surface of the storage gate groove 202, the floating gate 210 at least partially located on the surface of the floating gate dielectric layer 203 in the storage gate groove 202, the control gate dielectric layer 218 located on the surface of the floating gate 210, and the control gate 232 located on the surface of the control gate dielectric layer 218.

[0088] Please refer to Fig.10 A second doping region 243 is formed in the word line doping region 221 on both sides of the word line structure 233 , a fourth doping region 241 is formed in the first well region 223 on both sides of the gate 235 , and a fifth doping region 242 is formed in the second well region 224 .

[0089] Each of the word line structures 233 is located between the storage gate structure and the second doping region 243 , and the second doping region 243 is a bit line doping region.

[0090] In this embodiment, the doping ions in the fourth doping region 241 are anti-type to the doping ions in the first well region 223, and the doping ions in the fifth doping region 242 are anti-type to the doping ions in the second well region 224. The fourth doping region 241 and the fifth doping region 242 serve as source and drain regions.

[0091] Next, an interlayer dielectric layer (not shown) is formed on the surface of the substrate 200, the surface of the word line structure 233, the surface of the storage gate structure, the surface of the erase gate 231, and the surface of the gate 235; a conductive plug 260 is formed in the interlayer dielectric layer and is located on the surface of the second doping region 243, the surface of the word line structure 233, the surface of the control gate 232, the surface of the erase gate 231, the surface of the first doping region 222, the surface of the gate 235, the fourth doping region 241, and the surface of the fifth doping region 242. The conductive plug 260 provides voltage to the second doping region 243, the word line structure 233, the control gate 232, the erase gate 231, the first doping region 222, the gate 235, the fourth doping region 241, and the fifth doping region 242, so that the semiconductor structure can perform the functions of writing, erasing, and logic operations.

[0092] In this embodiment, when the storage gate structure on the storage area I performs a write operation, a voltage of 1V is applied to the word line structure 233, a voltage of 10.5V is applied to the control gate 232, a voltage of 4.5V is applied to the erase gate 231, and a voltage is applied to the second doping area 243 and the first doping area 222 to form a larger potential difference between the two.

[0093] After the voltage is applied, a channel is opened in the word line doping region 221 below the word line structure 233, and a conduction current is generated due to the potential difference between the second doping region 243 and the first doping region 222, so that electrons flow from the second doping region 243 to the first doping region 222 (e.g. Fig.10 In addition, the high voltage on the control gate 232 is coupled to the floating gate 210, thereby forming an electric field perpendicular to the surface direction of the floating gate 210 between the floating gate 210 and the substrate 200. Since part of the floating gate 210 is located in the storage gate groove 202 in the substrate 200, a partially buried floating gate 210 is formed, and the electric field direction at the sidewall of the floating gate 210 is perpendicular to the sidewall surface of the floating gate 210 (the electric field direction is shown in FIG. Fig.10 In the process of electrons flowing from the second doping region 243 to the first doping region 222, the direction of electron flow is also perpendicular to the side wall of the floating gate 210, that is, the direction of electron flow is parallel to the electric field direction of the side wall of the floating gate 210, thereby increasing the tunneling efficiency of electrons at the side wall of the floating gate 210 and improving the writing efficiency of the memory.

[0094] Secondly, the voltage V of the floating gate 210 FG It is coupled through voltage on other structures, which can be specifically expressed as:

[0095] C tot =C CG +C EG +CWL +C SL ;

[0096] Among them, Q FG is the amount of charge stored in the floating gate 210, V CG is the voltage applied to the control gate 232, V EG is the voltage applied to the erase gate 231, V WL is the voltage applied to the word line structure 233, V SL is the voltage applied to the first doping region 222, C CG is the capacitance formed by the control gate 232 and the floating gate 210, C EG is the capacitance value formed by the erase gate 231 and the floating gate 210, C WL is the capacitance formed by the word line structure 233 and the floating gate 210, C SL is the capacitance value formed by the first doped region 222 and the floating gate 210 .

[0097] In this embodiment, since the floating gate 210 has a first opening 213, and the control gate 232 is located in the first opening 213, the floating gate 210 is located around the control gate 232. Therefore, the bottom and sidewall of the control gate 232 can form a capacitor structure with the floating gate 210, thereby greatly increasing the working area of ​​the capacitor plate and increasing the capacitance value C formed by the control gate 232 and the floating gate 210. CG Since the voltage V applied to the control gate 232 CG The highest, therefore, C CG The increase of C CG XV CG There is a significant improvement, thereby increasing the voltage V of the floating gate 210 FG , which makes the electric field on the sidewall of the floating gate 210 stronger, and the tunneling probability of electrons is greater, thus improving the writing efficiency. FG The boost can be achieved at a smaller control gate 232 voltage V CG Under this condition, a certain electron tunneling efficiency can still be guaranteed, thereby reducing power consumption.

[0098] Again, at the bottom of the first floating gate structure 211 extending in a direction parallel to the surface of the storage area I, there is still an electric field perpendicular to the surface of the storage area I (the direction of the electric field is as shown in FIG. Fig.10 This part of the electric field also causes the electrons passing through to tunnel into the floating gate 210, thereby contributing to the writing efficiency.

[0099] When the storage gate structure on the storage area I performs an erase operation, 0V is connected to the word line structure 233, the control gate 232, the first doping region 222 and the second doping region 243, and a voltage of 12V is applied to the erase gate 231. The voltage VFG Specifically, it can be manifested as:

[0100] C tot =C CG +C EG +C WL +C SL ;

[0101] Since the relative area between the floating gate 210 and the control gate 232 is larger, the capacitance C formed by the control gate 232 and the floating gate 210 is increased. CG , so that C tot increases, while other components have no significant changes, thus reducing V FG , thereby increasing the potential difference between the control gate 232 and the floating gate 210, enhancing the electric field, improving the electron tunneling efficiency, and improving the erase efficiency.

[0102] Secondly, the bottom surface of the erase gate 231 is convex in a direction away from the surface of the substrate 200, so that the bottom edge of the erase gate 231 has a sharp corner. Since the sharp corner is formed when the erase gate 231 is formed, and the erase gate 231 is formed after the oxidation process of the erase gate dielectric layer 238 and the gate 235 dielectric layer, the sharp corner is prevented from being oxidized and affecting the morphology, which is conducive to the concentration of the electric field at this location, thereby improving the tunneling efficiency of electrons and improving the erasing efficiency of the device.

[0103] In this embodiment, part of the floating gate 210 is buried in the substrate 200, and the rest is located on the surface of the storage area I. In other embodiments, the floating gate may be completely buried in the substrate.

[0104] In this embodiment, the floating gate 210 has a first opening 213, and the control gate 232 and the control gate dielectric layer 218 are located in the first opening 213. In other embodiments, the floating gate may not have a first opening, the control gate dielectric layer is directly located on the top surface of the floating gate, and the control gate is located on the top surface of the control gate dielectric layer.

[0105] In this embodiment, the top of the gate 235 is flush with the tops of the control gate 232, the erase gate 231, the floating gate 210 and the word line structure 233. In other embodiments, the top of the gate may be higher or lower than the tops of the control gate, the erase gate, the floating gate and the word line structure.

[0106] It should be noted that, for ease of understanding, Fig.10 The interlayer dielectric layer is omitted.

[0107] In this embodiment, before forming the second doping region 243 , the fourth doping region 241 and the fifth doping region 242 , a spacer structure 261 is formed on the sidewall surface of the word line structure 233 and the sidewall surface of the gate 235 .

[0108] In this embodiment, before forming the conductive plug 260 , an etch stop protection layer 240 is formed on the surface of the storage gate structure, the word line structure 233 , the erase gate 231 and the gate 235 . The etch stop protection layer 240 is used as an etch stop layer during the formation of the conductive plug 260 .

[0109] In this embodiment, the device structure on the storage area I can be applied to Norflash storage devices including 28nm, 40nm, 55nm, 70nm and other various technology nodes, and can be compatible with logic processes or other mature processes of various technology nodes.

[0110] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by adopting the above method.

[0111] Please continue to refer to Fig.10 The semiconductor structure comprises: a substrate 200, wherein the substrate 200 comprises a storage area I; a plurality of storage gate grooves 202 located in the storage area I, wherein the storage gate grooves 202 are separated from each other and two of the storage gate grooves 202 form a pair; a storage gate structure at least partially located in the storage gate grooves 202, wherein the storage gate structures in the paired storage gate grooves 202 form a pair, wherein each storage gate structure comprises: a floating gate dielectric layer 203 located on the sidewall and bottom surface of the storage gate groove 202, and a floating gate dielectric layer 203 located at least partially in the storage gate groove 202. 03 surface, a floating gate 210 located on the surface of the floating gate 210, a control gate dielectric layer 218 located on the surface of the floating gate 210, and a control gate 232 located on the surface of the control gate dielectric layer 218; a first doped region 222 located in the storage region I between the paired storage gate structures; an erase gate dielectric layer 238 located on the surface of the first doped region 222; an erase gate 231 located on the surface of the erase gate dielectric layer 238, the bottom surface of the erase gate 231 is lower than or flush with the top surface of the floating gate 210; and a second doped region 243 located in the storage region I on both sides of the paired storage gate structures.

[0112] In this embodiment, the floating gate 210 has a first opening 213 therein, and the control gate dielectric layer 218 and the control gate 232 are located in the first opening 213 .

[0113] In this embodiment, the floating gate 210 includes a first floating gate structure 211 and a second floating gate structure 212 located around the first floating gate structure 211 . The first opening 213 is located between the second floating gate structures 212 and exposes the surface of the first floating gate structure 211 .

[0114] In this embodiment, the top surface of the first floating gate structure 211 and the sidewall surface of the second floating gate structure 212 are perpendicular to each other, and the top surface of the first floating gate structure 211 is parallel to the surface of the storage area I.

[0115] In this embodiment, the top of the second floating gate structure 212 is higher than the top of the erase gate dielectric layer 238 .

[0116] In this embodiment, the top surface of the second floating gate structure 212 is flush with the top surface of the erase gate 231 .

[0117] In this embodiment, the semiconductor structure also includes: word line structures 233 located on both sides of the paired storage gate structures, the two word line structures 233 are respectively located on the side wall surfaces of the two storage gate structures away from the erase gate 231, and each word line structure 233 is located between the storage gate structure and the second doping region 243.

[0118] In this embodiment, the top surface of the word line structure 233 , the top surface of the control gate 232 , and the top surface of the erase gate 231 are flush with each other.

[0119] In this embodiment, the substrate 200 further includes a logic region II; the semiconductor structure further includes: a gate oxide layer 232 located on the surface of the logic region II and a gate 235 located on the surface of the gate oxide layer 232 .

[0120] In this embodiment, the top surface of the gate 235 , the top surface of the control gate 232 , and the top surface of the erase gate 231 are flush with each other.

[0121] In this embodiment, the center of the top surface of the erase gate dielectric layer 238 is higher than the edge of the top surface of the erase gate dielectric layer 238 , so that the bottom surface of the erase gate 231 bulges away from the surface of the substrate 200 .

[0122] Among them, first, at least part of the floating gate 210 is located in the storage gate groove 202 in the substrate 200, so that part of the sidewall of the floating gate 210 is located in the substrate 200. Therefore, when the semiconductor structure is working, the floating gate 210 has a higher coupling voltage, so that after the floating gate 210 has a coupling voltage, an electric field perpendicular to the sidewall of the floating gate 210 can be formed; and in the process of the electrons flowing from the second doping region 243 to the first doping region 222, the direction of the electron flow is also perpendicular to the sidewall of the floating gate 210. Since the direction of the electron flow is parallel to the direction of the electric field of the sidewall of the floating gate 210, the buried floating gate 210 structure increases the tunneling efficiency of the electrons at the sidewall of the floating gate 210, and improves the writing efficiency of the memory.

[0123] Second, since the bottom surface of the erase gate 231 is lower than or flush with the top surface of the floating gate 210, and the bottom surface of the erase gate 231 protrudes away from the surface of the substrate 200, the bottom edge of the erase gate 231 has a sharp corner, which is beneficial to the concentration of the electric field at this location, thereby enhancing the tunneling efficiency of electrons and improving the erasure efficiency of the device.

[0124] Third, the floating gate 210 has a first opening 213, and the control gate dielectric layer 218 and the control gate 232 are located in the first opening 213. Since the floating gate 210 is located around the control gate 232, the bottom and side walls of the control gate 232 can form a capacitor structure with the floating gate 210, thereby greatly increasing the working area of ​​the capacitor plate and increasing its capacitance. When the device is performing a write operation, pressure is applied to the control gate 232. Since the relative area between the floating gate 210 and the control gate 232 is larger, the voltage coupled to the floating gate 210 is larger, thereby also enhancing the electric field, improving the efficiency of electron tunneling, and improving the write efficiency of the device. When the device performs an erase operation, the control gate 232 is connected to 0V and the erase gate 231 is connected to a high voltage. At this time, the voltage obtained by coupling the floating gate 210 is negatively correlated with the capacitance value between the floating gate 210 and the control gate 232. Since the relative area of ​​the floating gate 210 and the control gate 232 is larger, the voltage obtained by coupling the floating gate 210 is correspondingly reduced, thereby increasing the potential difference between the floating gate 210 and the erase gate 231, thereby increasing the electron tunneling efficiency and improving the erase efficiency.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising a storage area; A plurality of storage gate grooves located in the storage area, the storage gate grooves are separated from each other, and two of the storage gate grooves form a pair; A memory gate structure at least partially located in the memory gate groove, and the memory gate structures in the paired memory gate grooves form a pair, each memory gate structure comprising: a floating gate dielectric layer located on the sidewall and bottom surface of the memory gate groove, a floating gate located at least partially on the surface of the floating gate dielectric layer in the memory gate groove, a control gate dielectric layer located on the surface of the floating gate, and a control gate located on the surface of the control gate dielectric layer; a first doped region located in a storage region between the paired storage gate structures; An erase gate dielectric layer located on the surface of the first doped region; An erase gate located on the surface of the erase gate dielectric layer, wherein the bottom surface of the erase gate is lower than or flush with the top surface of the floating gate; The second doped regions are located in the storage regions on both sides of the paired storage gate structures.

2. The semiconductor structure according to claim 1, wherein: The floating gate has a first opening therein, and the control gate dielectric layer and the control gate are located in the first opening.

3. The semiconductor structure according to claim 2, wherein: The floating gate includes a first floating gate structure and a second floating gate structure located around the first floating gate structure. The first opening is located between the second floating gate structures and exposes a surface of the first floating gate structure.

4. The semiconductor structure according to claim 3, characterized in that The top surface of the first floating gate structure and the sidewall surface of the second floating gate structure are perpendicular to each other, and the top surface of the first floating gate structure is parallel to the surface of the storage area.

5. The semiconductor structure according to claim 3, wherein: The top of the second floating gate structure is higher than the top of the erase gate dielectric layer.

6. The semiconductor structure according to claim 3, characterized in that A top surface of the second floating gate structure is flush with a top surface of the erase gate.

7. The semiconductor structure according to claim 1, wherein: Also includes: The word line structures are located on both sides of the paired storage gate structures. The two word line structures are respectively located on the sidewall surfaces of the two storage gate structures away from the erase gate. Each word line structure is located between the storage gate structure and the second doping region.

8. The semiconductor structure according to claim 7, wherein: A top surface of the word line structure, a top surface of the control gate, and a top surface of the erase gate are flush with each other.

9. The semiconductor structure according to claim 1, wherein: The substrate further comprises a logic region; the semiconductor structure further comprises: a gate oxide layer located on the surface of the logic region and a gate located on the surface of the gate oxide layer.

10. The semiconductor structure according to claim 9, wherein: The top surface of the gate, the top surface of the control gate and the top surface of the erase gate are flush with each other.

11. The semiconductor structure according to claim 1, wherein: The center of the top surface of the erase gate dielectric layer is higher than the edge of the top surface of the erase gate dielectric layer, so that the bottom surface of the erase gate is raised in a direction away from the substrate surface.

12. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a storage area; forming a plurality of storage gate grooves in the storage area, wherein the storage gate grooves are separated from each other and two of the storage gate grooves form a pair; A storage gate structure is formed in the storage gate groove, wherein the storage gate structure is at least partially located in the storage gate groove, and each storage gate structure includes: a floating gate dielectric layer located on the sidewall and bottom surface of the storage gate groove, a floating gate located at least partially on the surface of the floating gate dielectric layer in the storage gate groove, a control gate dielectric layer located on the surface of the floating gate, and a control gate located on the surface of the control gate dielectric layer; forming a first doped region in a storage region between the paired storage gate structures; forming a second doped region in the storage region on both sides of the paired storage gate structures; forming an erase gate dielectric layer on the surface of the first doped region; An erase gate is formed on the surface of the erase gate dielectric layer, and a bottom surface of the erase gate is lower than or flush with a top surface of the floating gate.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the storage gate structure comprises: forming a floating gate dielectric layer at the bottom and sidewall surface of the storage gate groove; A floating gate is formed on the floating gate dielectric layer in the storage gate groove, wherein the floating gate has a first opening; a control gate dielectric layer is formed at the bottom of the first opening, the sidewalls of the first opening, the sidewalls of the floating gate and the top surface of the floating gate; and a control gate is formed on the surface of the control gate dielectric layer in the first opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the floating gate includes: forming a floating gate material layer in the storage gate groove and on the surface of the storage area; forming a first mask layer on the surface of the floating gate material layer, wherein the first mask layer at least exposes a portion of the floating gate material layer surface in the storage gate groove; using the first mask layer as a mask, etching the floating gate material layer to form a floating gate at least partially located on the sidewall and bottom surface of the storage gate groove, and forming a first opening in the floating gate.

15. The method for forming a semiconductor structure according to claim 13, wherein: Also includes: Word line structures are formed on the surfaces of the storage areas on both sides of the paired storage gate structures. The two word line structures are respectively located on the sidewall surfaces of the two storage gate structures away from the erase gate. Each word line structure is located between the storage gate structure and the second doping region.

16. The method for forming a semiconductor structure according to claim 15, wherein: An erase gate and a word line structure are formed simultaneously with forming the control gate, and the top surface of the control gate, the top surface of the erase gate, the top surface of the floating gate and the top surface of the word line structure are flush with each other.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the control gate, erase gate and word line structure includes: forming a first material layer in the first opening, on the surface of the floating gate and on the surface of the storage area; flattening the first material layer until the top surface of the floating gate is exposed to form the control gate, and the top surface of the control gate is flush with the top surface of the floating gate; etching the first material layer on the surface of the storage area on both sides of the paired storage gate structure to form a word line structure.

18. The method for forming a semiconductor structure according to claim 12, wherein: The ion doping concentration at the center of the first doping region is greater than the ion doping concentration at the edge of the first doping region.

19. The method for forming a semiconductor structure according to claim 12, wherein: The process of forming the erase gate dielectric layer includes an oxidation process.

20. The method for forming a semiconductor structure according to claim 12, wherein: The center of the top surface of the erase gate dielectric layer is higher than the edge of the top surface of the erase gate dielectric layer, so that the bottom surface of the erase gate is raised in a direction away from the substrate surface.

21. The method for forming a semiconductor structure according to claim 12, wherein: The substrate also includes a logic area; the method for forming the semiconductor structure also includes: before forming the erase gate, forming a gate oxide layer on the surface of the logic area; after forming the gate oxide layer, forming a gate on the surface of the gate oxide layer.

22. The method for forming a semiconductor structure according to claim 21, wherein: The gate oxide layer and the erase gate dielectric layer are formed simultaneously.

23. The method for forming a semiconductor structure according to claim 21, wherein: The gate is formed simultaneously with the control gate and the erase gate, and the top surface of the gate is flush with the top surfaces of the control gate and the erase gate.

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