Clock frequency limiter

Abstract

A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. Embodiments of the receiver circuit include a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors the frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust the frequency of the clock signal.

Description

Background Technology Technical Field

[0002] The embodiments described herein relate to communication data links for integrated circuits, and more specifically, to techniques for limiting the increase in frequency of clocks generated by receiver circuitry.

[0003] Related technical descriptions

[0004] Modern computer systems may include multiple circuit blocks designed to perform various functions. For example, such circuit blocks may include a processor and / or a processor core configured to execute software or program instructions. Additionally, circuit blocks may include memory circuitry, mixed-signal or analog circuitry, etc. Circuit blocks may also include transmitter and receiver circuitry for transmitting data between the computer system and external devices or other computer systems. A variety of different protocols and formats can be used to transmit data. For example, serial data can be sent and received via a Universal Serial Bus (USB) connection.

[0005] Circuit blocks within a computer system use clock signals to control the timing of their operation. Clock generating circuitry may be included in a computer system to generate clock signals used by circuit blocks throughout the system. Some receiver circuitry generates clock signals by recovering clock information from an incoming serial data stream. In some cases, such clock recovery circuitry generates clock signals by recovering clock information embedded in the incoming data stream. Clock recovery circuitry may also generate a clock signal that is then aligned with transitions in a data stream that do not have embedded clock information during a process called clock and data recovery (CDR). This disclosure relates to such CDR circuitry. Attached Figure Description

[0006] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0007] Figure 1 This is a block diagram of the implementation scheme for the receiver circuit.

[0008] Figure 2 This is a block diagram of the implementation scheme for the clock generator circuit.

[0009] Figure 3 This is a block diagram of the implementation scheme for the measurement circuit.

[0010] Figure 4 This is a block diagram of the implementation scheme for the comparator circuit.

[0011] Figure 5A It is a diagram depicting an example waveform associated with the operation of the clock generation circuit in the presence of an incoming data stream.

[0012] Figure 5BIt is a diagram depicting an example waveform associated with the operation of the clock generation circuit when the incoming data stream is interrupted.

[0013] Figure 6 This is a flowchart illustrating an embodiment of a method for operating a device including receiver circuitry.

[0014] Figure 7 This is a block diagram illustrating the transmission of a serial data stream to a device including receiver circuitry.

[0015] Figure 8 It is a block diagram of a system-on-a-chip that includes receiver circuitry.

[0016] Figure 9 It can be a block diagram of various implementation schemes of a computer system that may include receiver circuitry.

[0017] Figure 10 Examples of non-transitory computer-readable storage media for storing circuit design information are provided. Detailed Implementation

[0018] The operation of computer systems requires the transfer of data between integrated circuits. This chip-to-chip communication can occur between circuits in independent devices or systems, or between circuits within the same device or system. Communication links can be parallel links, where multiple channels simultaneously transmit partial data. For example, eight parallel lines can be used to transmit an eight-bit word, with each line carrying one bit. Additional lines or channels in a parallel communication link can carry other information, such as clock or control signals. Parallel communication links can transmit data quickly, but multiple data channels increase power consumption, increase cost, and occupy scarce space on integrated circuits or circuit boards within a device or system. Parallel data channels can also experience crosstalk interference or distortion that affects individual channels differently, especially over longer distances.

[0019] Due to the limitations of parallel communication links such as those mentioned above, serial communication links are often used as an alternative. A serial communication link transmits data as a series of symbols over a single channel, where each symbol corresponds to one or more data bits. The data is serialized and encoded into symbols for transmission, and then decoded and deserialized once received. Because a serial communication link does not include a separate channel for the clock signal, the clock signal is "recovered" from the serial data stream itself by the receiver to sample the signal received on the serial communication link. Popular types of clock recovery circuits use phase-locked loop (PLL) circuits to align the transitions in the output of the oscillator circuit with the transitions in the serial data stream, generating a local clock signal that can be used by the receiver-side circuitry.

[0020] A sudden interruption of the data flow to a PLL-based clock recovery circuit (such as by unplugging a Universal Serial Bus (USB) connection) removes the data transition, leaving only noise for the PLL circuitry to align. This can cause a significant increase in the frequency of the oscillator circuitry's output as the phase detector within the PLL circuitry offsets the oscillator circuitry's frequency in an attempt to locate the transition in the noise. This increase in oscillator circuitry frequency can cause the local clock signal to exceed the operating frequency limit of the circuitry using that clock signal. If the clock signal is allowed to exceed the operating frequency, logic states in the circuitry may be lost, and errors may be introduced due to setup and / or hold time failures, etc. In some circuits, the frequency increase caused by a data interruption can cause state loss in associated circuitry to occur very rapidly. For example, in some cases, state loss may occur within approximately 0.5 microseconds after the loss of incoming data. Methods involving using PLL operation to counteract this frequency increase may be too slow to prevent the loss of logic states due to the time required for the PLL circuitry to converge.

[0021] The technique described in this disclosure allows for the rapid determination of the frequency of a local clock signal and comparison of that frequency with a threshold. If an increase in frequency exceeding the threshold is detected, the clock frequency is adjusted. This solution allows the clock frequency to be maintained below levels where circuit blocks using the clock signal might experience loss of logic state. Detection of clock signal frequencies at or above the threshold can serve as an indication that an incoming data stream has been disconnected and can initiate an orderly shutdown of circuit blocks using the local clock signal.

[0022] Figure 1 A block diagram illustrating an embodiment of the receiver circuit is shown. As illustrated, the receiver circuit 100 includes a front-end circuit 102, a clock generator circuit 104, and a measurement circuit 106.

[0023] Front-end circuitry 102 is configured to receive a set of signals 108 that encode a serial data stream comprising multiple symbols 110. Symbols, as used herein, represent the state of a communication channel, such as the amplitude, phase, or frequency of a waveform, used to transmit one or more data bits. Circuitry 102 performs an equalization process to restore the balance between the frequency components of the signals 108, correcting for signal degradation or distortion caused by phenomena such as reflections along the communication link or channel. In one embodiment, circuitry 102 performs continuous-time linear equalization (CTLE). The equalization signal 112 (which may be a set of multiple signals) is generated by front-end circuitry 102.

[0024] Clock generator circuit 104 is configured to use equalization signal 112 to generate clock signal 114. (As per this document...) Figure 2Further, the clock generator circuit 104 samples the equalization signal 112 to locate transitions in the signal 112, such that the transitions of the clock generated using a voltage-controlled oscillator (VCO) are phase-aligned with the transitions in the signal 112. The resulting clock signal 114 is provided to additional circuit blocks, such as those for processing data recovered from the equalization signal 112. In one embodiment, the clock generator circuit 104 is a clock and data recovery (CDR) circuit that generates, in addition to the clock signal 114, a recovered data signal (…). Figure 1 (Not shown in the image).

[0025] Because the clock generator circuit 104 operates by aligning the transitions of the clock signal 114 with the transitions of the equalization signal 112, errors can occur when the input data stream encoded by the input signal 108 is interrupted. For example, this could happen due to unplugging a USB connection. If the incoming data signal is lost, the clock generator circuit 104 attempts to align the transitions of the clock signal 114 with the transitions in the incoming signal, which is merely noise. This can lead to a rapid increase in the frequency of the clock signal 114 or an "out-of-control" condition. When the frequency of the clock signal 114 increases beyond a threshold frequency associated with the timing requirements of the circuit blocks that use the clock signal 114 for processing, it can cause signal errors and loss of state in those circuit blocks.

[0026] Measurement circuit 106 is used to address the problem of clock frequency runaway when incoming data is interrupted. Measurement circuit 106 is configured to monitor the frequency of clock signal 114 and, in response to determining that the frequency of clock signal 114 exceeds a threshold frequency, generate indication signal 116 and transmit it to clock generator circuit 104. Clock generator circuit 104 is configured to use indication signal 116 to adjust the frequency of clock signal 114. Therefore, receiver circuit 100 has the potential to stop the increase in the frequency of clock signal 114 in response to loss of input data before the frequency increases sufficiently to cause state loss in the circuit block using clock signal 114.

[0027] Go to Figure 2 The figure shows a block diagram of an embodiment of the clock generator circuit 104. As illustrated, the clock generator circuit 104 includes a phase detector circuit 204, a charge pump and loop filter circuit 206, a frequency control circuit 208, a VCO circuit 210, and a frequency divider circuit 212.

[0028] The phase detector circuit 204 is configured to sample the equalization signal 112 using a clock signal. Figure 2In one embodiment, phase detector circuit 204 samples equalization signal 112 using feedback signal 222, which is a divided version of clock signal 114 generated by VCO circuit 210. Equalization signal 112 is sampled using multiple transitions of feedback signal 222 occurring at different times, thereby generating multiple samples. In one embodiment, comparisons between samples are used to determine whether a clock transition is "earlier" or "later" than a transition of incoming data in equalization signal 112. Error signal 216 includes pulses characterizing the alignment error between signals 222 and 112, such as pulses indicating whether the clock is running earlier or later than the data. In one embodiment, phase detector circuit 204 includes a bang-bang phase detector, such as an Alexander phase detector. In other embodiments, other types of phase detectors may be used. In one embodiment, in addition to error signal 216, phase detector circuit 204 uses samples of equalization signal 112 to generate a recovered data signal (…). Figure 2 (Not shown in the image).

[0029] The charge pump and loop filter circuit 206 is configured to convert the error signal 216 into an analog VCO control voltage 218. In one embodiment, the loop filter includes a capacitor connected between the output node of the charge pump and loop filter circuit 206 and ground, such that the VCO control voltage 218 appears across the capacitor. In such embodiments, the charge pump may include a first current source connected between the supply voltage and the output node of the charge pump and loop filter circuit 206 via a first switch controlled by the error signal 216, and a second current source connected between the output node of the charge pump and loop filter circuit and ground via a second switch controlled by the error signal 216. Depending on whether the transition of the feedback signal 222, indicated by the error signal 216, occurs earlier or later than the transition of the equalization signal 112, the charge pump switch is set to add charge to the loop filter capacitor or discharge some of the charge from the capacitor to ground. This charge flow will adjust the value of the VCO control voltage 218.

[0030] VCO circuit 210 is an oscillator circuit having a frequency controlled by voltage 218. In one embodiment, VCO circuit 210 includes an LC oscillator whose resonant frequency is adjusted using VCO control voltage 218. For example, VCO control voltage 218 can be applied to a control input of a transistor or other switching element that sets a bias current for the LC oscillator circuit. In other embodiments, VCO circuit 210 can be implemented using other types of oscillator circuits, such as ring oscillator circuits in which VCO control voltage 218 is used to adjust the bias current of a ring oscillator stage and thus adjust its propagation speed. Depending on the frequency range of VCO circuit 210 and the frequency of equalization signal 112, frequency divider circuit 212 can divide the frequency of clock signal 114 by any number (including 1), or may not be present in some embodiments. In one embodiment, frequency divider circuit 212 is configured to provide integer division, fractional division, or combinations thereof implemented using one or more flip-flops, counters, or other combinations or sequential logic circuits. In some embodiments, level shifting or scaling circuitry for increasing the voltage swing of the clock signal generated by VCO circuit 210 may also be included within or after VCO circuit 210. In some embodiments, a frequency divider circuit may also be included within or after VCO circuit 210, such that clock signal 114 is a divided version of the VCO output.

[0031] During the operation of clock generator circuit 104, where incoming data is present in equalization signal 112, an error signal 216, converted into VCO control voltage 218, causes a change in the frequency of clock signal 114 generated by VCO circuit 210. This changes the frequency of feedback signal 222, which phase detector circuit 204 uses to continue sampling equalization signal 112 to determine if the transition of signal 222 is aligned with the transition in signal 112. As the process continues, the PLL implemented by phase detector circuit 204, charge pump and loop filter circuit 206, VCO circuit 210, and frequency divider circuit 212 will be "locked" so that feedback signal 222, and therefore clock signal 114, are phase aligned with the incoming data.

[0032] However, when the incoming data in the equalization signal 112 suddenly disappears, the phase detector circuit 204 does not perform a data transition to attempt to align the transition in the feedback signal 222 with it. Instead, the samples obtained by the phase detector circuit 204 only sample noise on the incoming signal line. In one embodiment, the phase detector circuit 204 responds to data loss by indicating via error signal 216 that the transition in feedback 222 is too late to align with the transition in the data signal. This causes the control voltage 218 to increase the clock signal 114 generated by the VCO circuit 210. In some embodiments, the residual frequency offset in the phase detector circuit 204 can drive the behavior of the detector in the absence of incoming data.

[0033] The phase detector circuit 204's continuous indication of a clock transition being too late can cause a rapid increase in the frequency of the clock signal 114, exceeding the timing limits of the circuit block utilizing the clock signal 114 (or its divided version). This "frequency runaway" effect can be particularly strong in single-loop clock generator circuit architectures where the output clock signal is generated directly from the VCO, such as... Figure 2 As shown. Other architectures that generate the output clock signal using additional loops (e.g., phase interpolator circuits that mix different phases of the clock signal generated by the VCO) may be more constrained in terms of the amount of frequency drift they exhibit, but these architectures may have disadvantages in other areas, such as the effective bandwidth of the CDR circuit and the complexity of its implementation. Frequency control circuit 208 helps limit the increase in clock signal frequency caused by data interruptions.

[0034] The frequency control circuit 208 is configured to adjust the frequency of the clock signal 114 in response to receiving the indication signal 116. Figure 2In one embodiment, control circuit 208 is interposed between charge pump and loop filter circuit 206 and VCO circuit 210. If indicator signal 116 is absent or in an "off" state, control circuit 208 delivers VCO control voltage 218 to VCO circuit 210, causing normal PLL operation. However, when indicator signal 116 is present or in an "on" state, control circuit 208 disconnects the connection between charge pump and filter circuit 206 and VCO circuit 210, providing an alternative control signal to VCO circuit 210. In one embodiment, reference frequency signal 220 is in the form of a control voltage designed to set VCO 210 to a specific output frequency of clock signal 114. In such embodiments, frequency control circuit 208 can be implemented as a switch connecting the voltage control input of VCO circuit 210 to VCO control voltage 218 or reference frequency signal 220, wherein indicator signal 116 is used to control the switch. Such switches can be implemented as transmission gates, single metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), or any other suitable switching device or element.

[0035] It should be noted that Figure 2 The clock generator circuit described herein is merely an example implementation of the clock generator circuit disclosed herein. For example, in some embodiments, the frequency control circuit 208 may be configured to completely bypass the VCO circuit 210 in response to the indication signal 116 by using a multiplexed circuit to connect a reference clock signal instead of the output of the VCO circuit 210 as the clock signal 114. Furthermore, in various embodiments, some or all of the analog elements of the PLL formed using the phase detector circuit 204, the charge pump and filter circuit 206, the VCO circuit 210, and the frequency divider circuit 212 may be implemented as digital elements.

[0036] Figure 3 This is a block diagram illustrating an embodiment of the measurement circuit 106. As illustrated, the measurement circuit 106 includes a counter circuit 302, a filter circuit 304, and a comparator circuit 306. Figure 3 In one implementation, the measurement circuit 106 continuously monitors the frequency of the incoming clock signal 308 by counting the number of cycles of the clock signal in one or more cycles of the reference clock signal 310. This count is filtered to reduce the effects of noise and compared with a threshold 316 to detect the extent to which the frequency increases beyond the threshold frequency.

[0037] Counter circuit 302 is configured to continuously count the number of cycles of clock signal 308 occurring within one or more cycles of reference clock signal 310. In various embodiments, clock signal 308 may be a clock signal 114 generated by clock generator circuit 104, feedback signal 222 delivered to phase detector circuit 204, or a divided version of either. In one embodiment, clock signal 308 is a 20-division version of feedback signal 222. Reference clock signal 310 is an external clock signal having a known frequency lower than the frequency of clock signal 308. In one embodiment, multiple cycles of clock signal 308 occur during one or two cycles of reference clock signal 310.

[0038] In one embodiment, counter circuit 302 counts the number of cycles of clock signal 308 within one or more cycles of reference clock 310 by sampling a continuous counter of the cycles of clock signal 308, wherein samples are obtained at intervals of one or more reference clock cycles. The continuous counter has a width sufficient to allow multiple samples to be obtained before the counter output “wraps back” and restarts. The continuous counter of the cycles of clock signal 308 can be implemented in various ways, which will be understood by those skilled in the art of digital circuit design in light of this disclosure. For example, the continuous counter may comprise a sequence of cascaded flip-flops timing with clock signal 308. The continuous counter may also be implemented using an adder circuit having one input bound to logic “1” followed by a register timing with clock signal 308, wherein the output of the register is fed back to the other input of the adder. The counters, adders, flip-flops, registers and other digital circuits mentioned herein may comprise logic gates formed of switching devices or any other suitable transconductance devices of any suitable technology, including field-effect and bipolar transistor technology. Any suitable transistor type can be used, including multi-gate or three-dimensional metal-oxide-semiconductor field-effect transistors (MOSFETs), such as FinFETs or gate-all-around FETs (GAAFETs).

[0039] The number of cycles of the clock signal 308 occurring during one or more cycles of the reference clock 310 can be obtained by subtracting consecutive samples of a continuous counter obtained at intervals of one or more reference clock cycles. In one embodiment, the counter is caused to pass through a register that times the clock signal 308 with a gated version, such that the register outputs the current counter value only at intervals of one or more cycles of the reference clock signal 310. A digital subtraction circuit can then be used to find the difference between the counter samples using the gated and ungated clock signals 308 to obtain the number of cycles of the clock signal 308 during a selected number of cycles of the reference clock signal 310. This output in Figure 3This is shown as loop counting signal 312. In one embodiment, a gated version of clock signal 308 is used to time the difference circuit.

[0040] In one embodiment, an integrated clock gating (ICG) circuit with an enable signal is used to generate a gated version of the clock signal 308, which is configured to cause the clock signal 308 to cycle once during a selected number of cycles of the reference clock signal 310. For example, the enable signal can be generated by performing an XOR operation between a divided version of the reference clock signal 310 and the same signal delayed by one cycle of the clock signal 308. In one embodiment, a synchronizer circuit timing the clock signal 308 is first used to synchronize the divided version of the reference clock signal 310 with the clock signal 308.

[0041] The number of cycles of the reference clock signal 310, which the counter operates between samples, can be selected based on the relative frequencies of the clock signal 308 and the reference clock signal 310. Generally, fewer cycles of the clock signal 310 can be used as sampling intervals for higher frequencies of the clock signal 308, while more cycles can be used for lower frequencies. In one embodiment, a single cycle of the reference clock signal 310 is used as a sampling interval for higher frequencies of the clock signal 308, corresponding to a higher data rate of incoming serial data to the receiver 100. Using a single reference clock cycle provides faster operation of the measurement circuitry 106, allowing for faster detection of clock frequency runaway and preventing state loss in associated circuit blocks. For lower frequencies of the clock signal 308, two or more cycles of the reference clock signal 310 can be used as sampling intervals, allowing the synchronizer circuitry to operate appropriately. In an example embodiment using a reference clock signal 310 with a frequency of approximately 100 MHz, when the clock signal 308 has a frequency in the range of approximately 400 MHz to 1 GHz, a single cycle of the reference clock signal 310 is used as the sampling interval, while when the clock signal 308 has a frequency between 250 MHz and 400 MHz, two cycles of the reference clock signal 310 are used as the sampling interval. Frequency measurement by the measurement circuit 106 becomes less effective when the frequency of the clock signal 308 is close to the frequency of the reference clock signal 310.

[0042] Filter circuit 304 is configured to digitally filter the loop count signal 312 to produce a filtered signal 314. Filter circuit 304 reduces the impact of noise in the loop count signal 312 (such as quantization noise due to sampling in counter circuit 302), thereby improving the accuracy of measurement circuit 106 in determining that the frequency of clock signal 308 has exceeded a threshold frequency. In one embodiment, filter circuit 304 is configured to provide high resolution to measurement circuit 106 while having relatively low delay, allowing for rapid detection of frequency runaway conditions. For example, a two-stage ligand integrator comb (CIC) decimation filter can provide a suitable balance between delay and stopband characteristics. The decimation ratio of such a filter can be selected to match the number of cycles of the reference clock signal 310 that constitutes an acceptable delay for the filter. In one embodiment of such a filter, a sampling ratio of 20 is used. In some embodiments, parallel groups of differential (or “comb”) stages can be used to improve the throughput of such CIC decimation filters, where each parallel stage includes a decimator (for a second-order filter) before two comb elements and is timed by different phases of the filter’s clock. Multiplexers can be used to continuously select individual phase outputs to form a filtered output signal. In one implementation of the CIC decimation filter, four parallel differential stages are used.

[0043] In one embodiment, filter circuit 304 uses a clock for timing, which is gated using one or more cycles of reference clock signal 310. In another embodiment, filter circuit 304 is timed using a gated clock generated by counter circuit 302 when generating cycle count signal 312. In some embodiments, an additional "dropout compensation" filter for improving the flatness of the filter's frequency response, in order to improve the filter's delay, is omitted in filter circuit 304. Using the filtered signal 314 in the threshold comparison of measurement circuit 106 does not require any additional compensation filter.

[0044] Figure 3 The comparator circuit 306 is configured to use a filtered signal 314 and a threshold 316 when determining whether a threshold has been exceeded. In one embodiment, exceeding the threshold 316 is an indication that the frequency of the clock signal 308 has exceeded a threshold frequency. If the threshold 316 is exceeded, the comparator circuit 306 is configured to generate or set to an "on" state (such as a logic high value) indication signal 116. The indication signal 116 is then used to adjust the frequency of the clock signal 308, as in combination with... Figure 2 The description of the clock generator circuit 104 is as discussed.

[0045] Figure 4A block diagram illustrating an embodiment of the comparator circuit 306 is shown. As illustrated, this embodiment of the comparator circuit 306 includes a scaling circuit 402, a difference circuit 404, and a comparator circuit 406.

[0046] Scaling circuit 402 is configured to appropriately scale the filtered signal 314 for comparison with frequency word 410, thereby producing a scaled filtered signal 408. In one embodiment, frequency word 410 is presented as a ratio of the link rate of the communication link or channel that introduces input signal 108 into receiver circuit 100 to a known reference rate. Frequency word 410 may also include a scaling factor. In one embodiment, based on known characteristics of the transmitter and / or communication link, frequency word 410 may be considered to represent the expected clock rate of the received data. Scaling circuit 402 scales the filtered signal 314 (which represents the ratio of the rate of clock signal 308 to the rate of reference clock signal 310) for comparison with frequency word 410. Factors considered by scaling circuit 402 may include, for example, one or more of the following: any difference between the reference rate for frequency word 410 and the frequency of reference clock signal 310, the clock signal 308 and... Figure 2 Any frequency division factor between the feedback signal 222 used by the phase detector circuit 204, whether the filtered signal 314 is generated by counting the cycles of the clock signal 308 through one or more cycles of the reference clock signal 310, and any scaling factor included in the determined frequency word 410.

[0047] The difference circuit 404 is configured to find the difference between the scaled and filtered signal 408 and the frequency word 410. In one embodiment, the difference circuit 404 subtracts the frequency word 410 from the scaled and filtered signal 408. In some embodiments, the difference circuit 404 includes bit-by-bit subtraction circuitry. The difference signal 412 represents the difference between the scaled and filtered signal 408 and the frequency word 410.

[0048] Comparator circuit 406 is configured to compare the difference signal 412 with a threshold 316. In one embodiment, if the difference signal 412 exceeds the threshold 316, comparator circuit 406 sets indicator signal 116 to a logic high value. In some embodiments, comparator circuit 406 includes a digital-to-macro comparator circuit.

[0049] exist Figure 4In one implementation, threshold 316 represents an amount by which the frequency of the clock signal generated by receiver 100 (e.g., normalized to a reference clock frequency) and reflected in the scaled, filtered signal 408 may differ from the link rate of the channel reflected in frequency word 410 (e.g., normalized to a reference rate). In one implementation, threshold 316 is set low enough that the frequency of the generated clock does not increase to the point of causing a circuit block using the generated clock to lose its logic state, but is set high enough that the generated clock frequency is not adjusted due to small or temporary clock frequency offsets that are insufficient to cause a loss of logic state in the circuit block. In some implementations, threshold 316 may be set at a level that causes clock frequency adjustment of the generated clock in response to clock frequency runaway caused by an interruption of the incoming data stream to the receiver, rather than in response to other types of clock frequency offsets. Determining threshold 316 may include taking into account the timing requirements of the circuit block configured to use the generated clock.

[0050] Figure 4 The illustrated comparison process (where the difference between a number representing the normalized clock frequency and the normalized link rate is compared with a threshold) advantageously allows for adjustment of the clock frequency when the incoming data stream is interrupted, without interrupting the clock generator circuitry for minor changes in the clock frequency caused by other conditions or events. The use of the normalized frequency value for the comparison process also allows the measurement circuitry 106 to handle incoming data streams with various frequency ranges corresponding to various communication interfaces or protocols. Figure 3 The illustrated measurement process allows for rapid determination of whether the frequency of clock signal 308 has exceeded the threshold frequency corresponding to the frequency exceeded by threshold 316.

[0051] It should be noted that Figure 3 and Figure 4 The circuit shown is merely an example implementation, and other methods can be used in other implementations. For example, when using circuits with... Figure 4 In some implementations of the comparator circuit 306 with different configurations, the threshold 316 may be in the form of a frequency value or a normalized frequency value. For example, based on the values ​​of the filtered signal 314 and the frequency word 410, the comparator circuit 306 is otherwise similar to... Figure 4 In some implementations, scaling circuit 402 may not be required. For Figure 3 and Figure 4 In some embodiments, the functions of circuits described as independent circuits, as well as all other circuits disclosed herein, may be combined in one circuit, or the functions of circuits described as single circuits may be separated among multiple circuits.

[0052] Go to Figure 5A and Figure 5BThe diagram shows an example waveform associated with the operation of the clock generator circuit 104. Figure 5A The waveform illustration shows an example of the equalization signal 112 and feedback signal 222 as a function of time t when there is an incoming data stream and the PLL within the clock generator circuit 104 is locked, aligning the transition of feedback signal 222 with the transition of equalization signal 112. Figure 5A In one implementation, the phase detector circuit 204 uses “data” (“D”) samples 502 and “edge” (“E”) samples 504 of the equalization signal 112 obtained at the transition of the feedback signal 222 to determine whether the transition of the signal 222 is “early” or “late” relative to the transition of the equalization signal 112.

[0053] Figure 5A The sampling method shown corresponds to sampling performed by an Alexander phase detector. Using this method, the amplitude of signal 112 in data sample 502 can be converted to a logic level and used to generate the recovered data signal. The amplitude of signal 112 in each edge sample 504 is compared with the amplitudes of the immediately preceding and following data samples. If the edge sample amplitude is the same as the amplitude of the preceding data sample, the phase detector determines that the corresponding clock transition occurs earlier than the data transition. If the edge sample amplitude is the same as the amplitude of the following data sample, the corresponding clock transition occurs later than the data transition. (Reference) Figure 2 The clock generator circuit 104 determines these "early" or "late" values, which are reflected in the error signal 216 and cause the VCO circuit 210 to adjust its frequency until the feedback signal 222 and the equalization signal 112 are phase-aligned. It should be noted that in other embodiments, different phase detectors utilizing different sampling methods may be used. Generally, sampling of the equalization signal 112 is used to generate a clock signal with a transition aligned with the transition of the incoming data.

[0054] Figure 5B Example waveforms are shown that relate to the operation of clock generator circuit 104 when the incoming data stream is interrupted. Figure 5B In the example, the incoming data stream is interrupted at time t1, for example, by unplugging the USB connection. After time t1, the equalization signal 112 takes the form of random noise signal 506. The lack of clear logic values ​​associated with samples 502 and 504 obtained after time t1 causes the phase detector to generate an error signal, which changes the clock frequency in an attempt to locate the transition in the noise signal. The clock signal frequency can then increase rapidly and reach levels exceeding the operational limits of the circuit block using the clock signal. The disclosed solution addresses this problem by detecting the frequency increase and adjusting the clock frequency before it reaches a level that would cause processing errors or loss of state.

[0055] In summary, an apparatus for limiting the frequency of a clock signal is disclosed. In one embodiment, the apparatus includes a front-end circuit, a clock generator circuit, and a measurement circuit. The front-end circuit is configured to generate an equalized signal comprising multiple signals encoding a serial data stream, wherein the serial data stream includes multiple symbols. The clock generator circuit is configured to generate a clock signal using multiple samples of the equalized signal. The measurement circuit is configured to monitor the frequency of the clock signal and generate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit is further configured to adjust the frequency of the clock signal using the indication signal.

[0056] One embodiment of the measurement circuit is configured to determine the number of cycles of a clock signal occurring during at least one cycle of a reference clock signal in order to monitor the frequency of the clock signal. The measurement circuit may also filter the number of cycles of the clock signal occurring during at least one cycle of the reference clock signal to generate a filtered signal. In another embodiment, the measurement circuit is configured to determine the difference between the filtered signal and the ratio of the data rate of the communication link to a reference data rate, and to perform a comparison between this difference and a threshold.

[0057] One embodiment of the clock generator circuit includes an oscillator circuit configured to generate an oscillator signal using a control signal, and configured to reduce the frequency of the oscillator signal to generate a clock signal. In another embodiment, the clock generator circuit is configured to set the control signal to a specific value corresponding to a reference frequency in response to activation of an indication signal, thereby adjusting the frequency of the clock signal.

[0058] Go to Figure 6 A flowchart illustrating an embodiment of a method for operating a device including receiver circuitry is provided. This method can be applied to various receiver circuits (such as...). Figure 1 The illustrated receiver circuit 100 is a device.

[0059] Method 600 includes receiving at least one signal via a communication link in block 602, wherein the at least one signal encodes a serial data stream comprising a plurality of data symbols. Figure 1 The input signal 108 represents an example of at least one signal encoding a serial data stream. The method also includes sampling the at least one signal at multiple time points to generate multiple samples (box 604). Figure 5A An example of this type of sampling is illustrated, which illustrates the generation of multiple samples including data sample 502 and edge sample 504. In one embodiment, sampling is performed using a clock generator circuit, such as clock generator circuit 104.

[0060] The method also includes generating a clock signal using multiple samples in block 606. In one embodiment, generating the clock signal includes generating an oscillator signal using oscillator circuitry and aligning transitions in the oscillator signal with transitions in at least one signal using multiple samples. Generating the clock signal may also include reducing the frequency of the oscillator signal. In one embodiment, generating the clock signal is accomplished using clock generator circuitry such as clock generator circuitry 104.

[0061] Method 600 also includes monitoring the frequency of a clock signal (block 608). In one embodiment, monitoring the frequency of the clock signal includes determining the number of cycles of the clock signal that occur during at least one cycle of a reference clock signal. In some embodiments, frequency monitoring is accomplished using measurement circuitry such as measurement circuitry 106.

[0062] The method also includes adjusting the frequency of the clock signal in response to determining that the frequency of the clock signal exceeds a threshold frequency (block 610). In one embodiment, adjusting the frequency of the clock signal includes setting an oscillator circuit to a reference frequency. In some embodiments, adjusting the frequency of the clock signal is accomplished using a clock generator circuit, such as clock generator circuit 104.

[0063] In some embodiments, monitoring the frequency of a clock signal includes determining the number of cycles of the clock signal that occur during at least one cycle of a reference clock signal. The method may also include filtering the clock signal for that number of cycles to generate a filtered signal. In various embodiments, the method may further include determining the difference between the filtered signal and the ratio of the data rate of the communication link to a reference data rate, and comparing that difference to a threshold.

[0064] In various embodiments, the method for operating a device including receiver circuitry may further include processing data recovered using multiple samples using a clock signal. This processing may be performed by a circuit block that receives the clock signal and the recovered data from clock and data recovery (CDR) circuitry. Such CDR circuitry may include clock generator circuitry, such as clock generator circuitry 104. The method may also include initiating a shutdown of the processing circuitry used to process the data recovered using multiple samples in response to determining that the frequency of the clock signal exceeds a threshold frequency. Initiating the shutdown process when clock frequency runaway is detected can allow power savings in the absence of incoming data. The circuit block using the recovered data is also able to preserve information associated with the last processed valid data and prevent corruption of such information.

[0065] Figure 7The diagram illustrates a block diagram of communication of a serial data stream between two devices. As shown, sending device 702 transmits an encoded serial data stream 708 to receiving device 704 over communication link 706. Link 706 can be a wired or wireless communication link or channel. Devices 702 and 704 are computer systems, which can each take various forms, such as those described herein. Figure 9 Any of those forms described. Device 702 includes circuit block 710 and transmitter circuitry 712. In one embodiment, circuit block 710 includes memory circuitry for storing data, which can be encoded into an encoded serial data stream 708 and transmitted using transmitter circuitry 712. Circuit block 710 may include other types of circuitry, and device 702 may include additional circuit blocks, including receiver circuitry, not shown.

[0066] The receiver device 704 includes receiver circuitry 714 and circuit block 716. Receiver circuitry 714 is similar to that described herein. Figure 1 The receiver circuit 100 is described above. Figure 7 In one embodiment, receiver circuitry 714 includes CDR circuitry and provides clock signal 718 and recovered data 720 to circuit block 716. In one embodiment, circuit block 712 includes data processing circuitry for processing the recovered data 720 using clock signal 718. Such processing may include, for example, deserialization of data recovered from serial data stream 708. Circuit block 716 may include other types of circuitry, and device 704 may include additional circuit blocks, including transmitter circuitry, not shown. Clock signal 718 and recovered data 720 may be combined as described herein (e.g.) Figure 2 and Figure 5A It is generated as described.

[0067] An interruption to the data stream 708 (such as by unplugging a USB connection carrying the data stream from device 704) may cause an uncontrolled increase in the frequency of the clock signal 718, as described elsewhere herein. This frequency increase may lead to a violation of the timing requirements of the logic gates within circuit block 716, resulting in logic errors and state loss. The frequency limiter circuitry and techniques described herein allow for the detection of uncontrolled frequency of the clock signal 718 and, in response, adjustment of the frequency of the signal 718. In one embodiment, the uncontrolled frequency is detected before errors and loss of logic state occur. This allows for the initiation of an orderly shutdown process of circuit block 716 when the flow of recovered data 720 is stopped.

[0068] exist Figure 8A block diagram of a system-on-a-chip (SoC) is illustrated. In the illustrated embodiment, SoC 800 includes processor circuitry 801, memory circuitry 802, analog / mixed-signal circuitry 803, and input / output circuitry 804. Input / output circuitry 804 includes receiver circuitry 100.

[0069] In various implementations, processor circuitry 801 may represent a general-purpose processor that performs computational operations. For example, processor circuitry 801 may be a central processing unit (CPU) such as a microprocessor, microcontroller, application-specific integrated circuit (ASIC), or field-programmable gate array (FPGA).

[0070] In various embodiments, memory circuitry 802 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. It should be noted that, although in Figure 8 The illustration shows a single memory circuit, but in other implementations, any suitable number of memory circuits may be used.

[0071] The analog / mixed-signal circuit 803 may include a crystal oscillator circuit, a phase-locked loop circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit (all not shown).

[0072] The input / output circuitry 804 can be configured to coordinate data transfer between the SoC 800 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., magnetic or optical media-based storage devices, including hard disk drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some implementations, the input / output circuitry 804 may be configured to implement the Universal Serial Bus (USB) protocol or IEEE 1394. Protocol version. As described elsewhere in this document, receiver circuitry 100 can be configured to receive a serial data stream using a protocol such as USB, generate a clock signal aligned with transitions in the data stream, and adjust the frequency of the clock signal if its frequency exceeds a threshold frequency due to an interruption in the data stream.

[0073] The input / output circuitry 804 can also be configured to coordinate data transfer between the SoC 800 and one or more devices (e.g., other computing systems or integrated circuits) coupled to the SoC 800 via a network. In one embodiment, the input / output circuitry 804 may be configured to perform the data processing necessary to implement Ethernet (IEEE 802.3) networking standards such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, but it is contemplated that any suitable networking standard can be implemented. In some embodiments, the input / output circuitry 804 may be configured to implement multiple discrete network interface ports.

[0074] Now go to Figure 9 This illustrates various types of systems that may include any of the circuits, devices, or systems described above. The system or device 900, which may utilize one or more of the techniques described herein in combination with or otherwise, can be used in a wide range of fields. For example, the system or device 900 may be used as part of the hardware of a system such as a desktop computer 910, a laptop computer 920, a tablet computer 930, a cellular or mobile phone 940, or a television 950 (or a set-top box coupled to a television).

[0075] Similarly, the disclosed components can be used in wearable devices 960, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can perform a variety of different functions—for example, access to email, cellular services, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, implantable devices, and glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality.

[0076] System or device 900 can also be used in a variety of other contexts. For example, system or device 900 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware implementing cloud-based services 970. Furthermore, system or device 900 can be implemented in a wide range of dedicated everyday devices, including common household devices 980 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Components can also be implemented in various modes of transportation. For example, system or device 900 can be used in control systems, guidance systems, entertainment systems, etc., of various types of vehicles 990.

[0077] Figure 9The applications illustrated are merely exemplary and are not intended to limit the potential future applications of the disclosed systems or devices. Other example applications include, but are not limited to, portable gaming devices, music players, data storage devices, and unmanned aerial vehicles.

[0078] Figure 10 This is a block diagram illustrating an example non-transitory computer-readable storage medium for storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1020 is configured to process design information 1015 stored on a non-transitory computer-readable storage medium 1010 and to manufacture an integrated circuit 1030 based on the design information 1015.

[0079] The non-transitory computer-readable storage medium 1010 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1010 may be an installation medium, such as a CD-ROM, floppy disk, or magnetic tape device; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory, magnetic media, etc., such as hard disk drives or optical storage devices; registers, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 1010 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1010 may include two or more memory media that may reside in different locations, such as different computer systems connected via a network.

[0080] Design information 1015 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1015 can be used by semiconductor manufacturing system 1020 to manufacture at least a portion of integrated circuit 1030. The format of design information 1015 can be recognized by at least one semiconductor manufacturing system (such as, for example, semiconductor manufacturing system 1020). In some embodiments, design information 1015 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during the logic synthesis of circuits included in integrated circuit 1030 may also be included in design information 1015. Such cell libraries may include information indicating device or transistor-level netlists, mask design data, characterization data, etc., indicating cells included in the cell library.

[0081] In various implementations, integrated circuit 1030 may include one or more custom macrocells, such as memory, analog or mixed-signal circuitry, etc. In this case, design information 1015 may include information associated with the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0082] The semiconductor manufacturing system 1020 may include any of the various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or modifying the dielectric constant using ultraviolet light treatment), etc. The semiconductor manufacturing system 1020 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0083] In various embodiments, integrated circuit 1030 is configured to operate according to a circuit design specified by design information 1015, which may include performing any of the functions described herein. For example, integrated circuit 1030 may include any of the various elements shown or described herein. Additionally, integrated circuit 1030 may be configured to perform various functions described herein in conjunction with other components. Furthermore, the functionality described herein may be performed by multiple interconnected integrated circuits.

[0084] As used herein, a phrase in the form of “design information specifying the design of a circuit configured to…” does not imply that the circuit in question must be manufactured in order to satisfy this element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated action or will include the specified components.

[0085] ***

[0086] This disclosure includes references to “implementations”, which are non-limiting specific implementations of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” “some implementations,” “various implementations,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including the specific implementations detailed herein, as well as modifications or alternatives falling within the substance or scope of this disclosure. Not all of these implementations will necessarily exhibit any or all of the potential advantages described herein.

[0087] Unless otherwise indicated, the specific embodiments are not intended to limit the scope of the claims drafted based on the disclosure of the present disclosure, even if only a single example is described for a particular feature. Thus, the disclosed embodiments are intended to be illustrative rather than restrictive, without any statement to the contrary. This application is intended to cover such alternative forms, modifications, and equivalent forms, which will be apparent to those skilled in the art who benefit from the present disclosure.

[0088] A particular feature, structure, or characteristic may be combined in any suitable manner consistent with the present disclosure. Thus, the present disclosure is intended to include any feature or combination of these features (explicitly or implicitly) disclosed herein, or any generalization thereof. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority therefrom) for any such combination of features. Specifically, referring to the appended claims, the features of the dependent claims may be combined with the features of the independent claims, and the features from the respective independent claims may be combined in any appropriate manner rather than only by the specific combinations recited in the appended claims.

[0089] For example, although the appended dependent claims are drafted such that each dependent claim depends on a single other claim, additional dependencies are also contemplated. In appropriate cases, it is also contemplated that a claim drafted in one statutory type (e.g., apparatus) may inspire a corresponding claim in another statutory type (e.g., method).

[0090] ***

[0091] Because the present disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. It is hereby announced that the following paragraphs and the definitions provided throughout the present disclosure will be used to determine how to interpret the claims drafted based on the present disclosure.

[0092] Unless the context clearly indicates otherwise, references to singular forms such as "a," "an," and "the" are intended to mean "one or more." Thus, a reference to an "item" in a claim does not exclude additional instances of that item.

[0093] The word "may" is used herein in an allowable sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0094] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0095] When the term “or” is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the expression “x or y” is equivalent to “x or y, or both,” covering x but not y, y but not x, and both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0096] The phrases “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Therefore, the phrase “...at least one of w, x, y, and z” means at least one element in the set [w, x, y, z], thus covering all possible combinations in the list of options. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0097] In this disclosure, various “labels” may precede nouns. Unless the context otherwise provides, different labels used for features (e.g., “first circuit”, “second circuit”, “specific circuit”, “given circuit”, etc.) refer to different instances of the feature. Unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to a particular feature.

[0098] Within this disclosure, different entities (which may be referred to differently as “cells,” “circuits,” other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Therefore, an entity described or represented as “configured” to perform a task refers to a physical thing used to perform that task, such as a device, circuit, memory storing executable program instructions, etc. This phrase is not used herein to refer to intangible things.

[0099] The term "configured as" is not intended to mean "configurable as". For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function.

[0100] The formulation structure in the appended claims is “configured” to perform one or more tasks and is explicitly intended not to invoke 35 U.SC § 112(f) for that claim element. If the applicant wishes to invoke part 112(f) during the application process, they will use the “component for [performing a function]” structure to formulate the claim element.

[0101] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on certain other factors such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0102] The phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors might influence or otherwise trigger the effect. That is, the effect may respond solely to these factors, or it may respond to the specified factors as well as other unspecified factors. Consider the phrase "execute A in response to B." This phrase specifies that B is the factor that triggers the performance of A. This phrase does not exclude the possibility that the execution of A may also respond to certain other factors, such as C. This phrase is also intended to cover implementations where A is executed solely in response to B.

Claims

1. An apparatus, the apparatus comprising: A front-end circuit configured to generate an equalization signal using multiple signals that encode a serial data stream comprising multiple data symbols; A clock generator circuit configured to generate a clock signal using multiple samples of the equalization signal; and Measurement circuit, the measurement circuit being configured as follows: Generate a filtered signal that reflects the number of cycles that occur during at least one cycle of the reference clock signal; The difference between the filtered signal and the frequency word is determined based on a reference data rate, wherein the frequency word is also related to the link rate of the channel carrying the serial data stream; as well as In response to determining that the difference exceeds a threshold, an indication signal is activated; and The clock generator circuit is further configured to set the frequency of the clock signal to a predetermined frequency in response to activation of the indication signal.

2. The apparatus of claim 1, wherein the clock generator circuit includes an oscillator circuit configured to generate an oscillator signal using a control signal, and wherein, in order to set the frequency of the clock signal to the predetermined frequency, the clock generator circuit is further configured to set the control signal to a predetermined value corresponding to the predetermined frequency in response to activation of the indication signal.

3. The apparatus of claim 1, wherein the threshold is set to a level that causes a response to a frequency runaway condition caused by an interruption of the serial data stream.

4. The apparatus according to claim 1, wherein: The clock generator circuit includes an oscillator circuit; and The clock generator circuit is configured to provide a reference clock signal in response to activation of the indication signal, instead of providing the output of the oscillator circuit as the clock signal.

5. The apparatus according to claim 1, wherein: The measurement circuit is further configured to scale the filtered signal to generate a scaled filtered signal; and Determining the difference includes determining the difference between the frequency word and the scaled filtered signal.

6. A method, the method comprising: Receive at least one signal via a communication link, wherein the at least one signal encodes a serial data stream comprising multiple data symbols; The at least one signal is sampled at multiple time points to generate multiple samples; A clock signal is generated using the multiple samples; Generate a filtered signal that reflects the number of cycles that occur during at least one cycle of the reference clock signal; The difference between the filtered signal and the frequency word is determined based on a reference data rate, wherein the frequency word is also related to the link rate of the channel carrying the serial data stream; as well as In response to determining that the difference exceeds a threshold, the frequency of the clock signal is set to a predetermined frequency.

7. The method of claim 6, wherein setting the frequency of the clock signal to the predetermined frequency includes setting the oscillator circuit to the predetermined frequency.

8. The method of claim 6, further comprising processing the data recovered using the plurality of samples using the clock signal.

9. The method of claim 8, further comprising, in response to determining that the difference exceeds the threshold, initiating the shutdown of processing circuitry used in processing the data recovered using the plurality of samples.

10. The method of claim 6, wherein setting the frequency of the clock signal to the predetermined frequency comprises: Provide a reference clock instead of the output of the oscillator circuit as the clock signal.

11. The method of claim 6, further comprising scaling the filtered signal to generate a scaled filtered signal, wherein determining the difference includes determining the difference between the scaled filtered signal and the frequency word.

12. An apparatus comprising: Receiver circuitry coupled to a communication link, wherein the receiver circuitry is configured to: Receive at least one signal that encodes a serial data stream comprising multiple data symbols; The at least one signal is sampled at multiple time points to generate multiple samples; A clock signal is generated using the multiple samples; Multiple recovered data symbols are generated using the clock signal and the multiple samples; Generate a filtered signal that reflects the number of cycles that occur during at least one cycle of the reference clock signal; The difference between the filtered signal and the frequency word is determined based on a reference data rate, wherein the frequency word is also related to the link rate of the channel carrying the serial data stream; as well as In response to determining that the difference exceeds a threshold, the frequency of the clock signal is set to a predetermined frequency; as well as A circuit block configured to perform one or more processing operations using the clock signal and the plurality of recovered data symbols.

13. The apparatus of claim 12, wherein the receiver circuitry includes an oscillator circuitry configured to generate an oscillator signal using a control signal, and wherein, in order to generate the clock signal, the receiver circuitry is further configured to reduce the frequency of the oscillator signal.

14. The apparatus of claim 13, wherein, in order to set the clock signal to the predetermined frequency, the receiver circuit is further configured to set the control signal to a predetermined value corresponding to the predetermined frequency.

15. The apparatus of claim 12, wherein the receiver circuit includes a phase-locked loop circuit, the phase-locked loop circuit including a feedback loop, and wherein, in order to set the frequency of the clock signal to the predetermined frequency, the receiver circuit is further configured to disable the feedback loop of the phase-locked loop circuit.

16. The apparatus according to claim 12, wherein: The receiver circuit includes an oscillator circuit; and In order to set the clock signal to the predetermined frequency, the receiver circuit is further configured to provide a reference clock signal instead of the output of the oscillator circuit as the clock signal.

17. The apparatus of claim 12, wherein the receiver circuitry is further configured to initiate the shutdown of the circuit block in response to determining that the difference exceeds the threshold.

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