DDR PHY planar arrangement

Abstract

A double data rate (DDR) physics (PHY) provides an interface between a memory controller and a dynamic random access memory (DRAM). The DDR PHY includes a first set of core logic components configured to convert data between a single data rate and a double data rate; and a first data I / O block on a first side of the first set of core logic components. The first data I / O block interfaces with the first set of core logic components and the DRAM. The DDR PHY also includes a second set of core logic components configured to process CA information; and a first CA I / O sub-block on a second side of the first set of core logic components. The first CA I / O sub-block interfaces with the second set of core logic components and the DRAM. The DDR PHY also includes a first set of power switches adjacent to at least one side of the first CA I / O sub-block. The first set of power switches is coupled to the first set of core logic components and the second set of core logic components.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. patent application serial number 17 / 664,567, filed on May 23, 2022, entitled “DDR PHY FLOOR PLAN,” which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to layout structures, and more particularly, to double data rate (DDR) physical (PHY) floorplans. Background Art

[0004] A double data rate (DDR) physical (PHY) provides an interface between a memory controller and a dynamic random access memory (DRAM). There is an ongoing need to reduce power consumption, improve performance, and reduce the footprint of a DDR PHY. Summary of the invention

[0005] In one aspect of the present disclosure, an integrated circuit (IC) includes a first set of core logic components configured to convert data between a single stream and a dual stream. The IC also includes a first data input or output (I / O) block located on a first side of the first set of core logic components. The first data I / O block interfaces with the first set of core logic components. The first data I / O block includes a plurality of I / O circuits for interfacing with DRAM. The first data I / O block is in a column. The IC also includes a second set of core logic components configured to process command and address (CA) information. The IC also includes a first CA I / O sub-block located on a second side of the first set of core logic components. The first CA I / O sub-block interfaces with the second set of core logic components. The first CA I / O sub-block includes a plurality of I / O circuits for interfacing with DRAM. The IC also includes a first set of power switches adjacent to at least one side of the first CA I / O sub-block. The first set of power switches is coupled to the first set of core logic components and the second set of core logic components.

[0006] In one configuration, the IC also includes a third group of core logic components, which are configured to convert data between a single stream and a dual stream. In this configuration, the IC also includes a second data I / O block located on a first side of the third group of core logic components. The second data I / O block interfaces with the third group of core logic components. The second data I / O block includes a plurality of I / O circuits for interfacing with DRAM. The second data I / O block is in a column. In this configuration, the IC also includes a second CA I / O sub-block located on a second side of the third group of core logic components. The second CA I / O sub-block interfaces with the second group of core logic components. The second CA I / O sub-block includes a plurality of I / O circuits for interfacing with DRAM. The first CA I / O sub-block and the second CA I / O sub-block together serve as a folded dual-column I / O block. In this configuration, the IC also includes a second group of power switches adjacent to at least one side of the second CA I / O sub-block. The second group of power switches is coupled to the third group of core logic components and the second group of core logic components. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating a DDR PHY interfaced between a memory controller and a DRAM.

[0008] Figure 2 is a diagram illustrating a first configuration of a DDR PHY planar arrangement.

[0009] Figure 3 is a diagram illustrating a second configuration of a DDR PHY planar arrangement. DETAILED DESCRIPTION

[0010] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. In order to provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it is apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid blurring these concepts. The apparatus and method will be described in the following detailed description and may be illustrated in the accompanying drawings by various boxes, modules, components, circuits, steps, processes, algorithms, elements, etc.

[0011] Figure 1 1 is a diagram 100 illustrating a DDR PHY 106 (also referred to as a DDR PHY block or DDR PHY macro) interfacing between a memory controller 104 and an external memory device 110. Figure 1As illustrated, the system on chip (SoC) 102 includes a memory controller 104 and a DDR PHY 106 packaged together on a printed circuit board (PCB). The DDR PHY 106 may also be referred to as a DDR PHY interface (DFI). The DDR PHY 106 connects the memory controller 104 and an external memory device 110 (e.g., DRAM). The DDR PHY 106 is a high-speed critical data interface. The DDR PHY 106 communicates data and command and address (CA) information with the external memory device 110 across the package and PCB 108 based on the DRAM data transfer protocol. The DDR PHY 106 provides several functions, one of which is to convert a single data rate to a double data rate.

[0012] In advanced technology nodes, data transmission rates have increased to 6400Mbps. It is extremely difficult to meet such high-speed data rates with any layout. Parameters such as clock jitter, clock delay, critical instance current (I) * resistance (R) drop (i.e., also referred to as voltage drop or IR drop) and decoupling capacitance requirements are important for DDR PHY operation, and any layout should optimize these metrics. In the case of not meeting the above metrics, DDR PHY will not work as expected, and major layout changes will be necessary to meet the metrics. If it is found that any specifications are not met at the end of the project, the project delivery expectations may not be met. Therefore, a lot of effort is usually spent on evaluating the DDR PHY layout and ensuring that the layout meets all requirements. Once the layout is selected, for similar generations of PHY implementations, the layout is usually carrier-forward.

[0013] The key parameters that should be met to achieve high-speed data transmission include clock jitter, wiring length, power-gated switches, decoupling capacitors, clock delay / insertion, and spatial variability. Higher clock jitter leads to challenges in meeting the timing requirements of high-speed logic components. Longer wiring lengths starting from input / output (IO) pads may lead to signal integrity challenges. With power-gated switches, it may be difficult to meet the strict IR drop requirements of high-speed key logic components. Decoupling capacitor requirements can be a function of operating speed. Higher operating speeds require higher decoupling capacitors, and vice versa. Decoupling capacitors may have limitations in terms of available placement close to a sink with significant switching. Jitter and power are proportional to clock delay. As the die size increases, clock delay (i.e., the total clock traversal time from the phase-locked loop (PLL) to the core logic component) may increase. Since higher delays adversely affect jitter and power, it is important to minimize the delay in the plane layout. In order to better delay matching on all data bits, the spatial variability caused by custom analog circuits should be minimal. In a small area, custom analog circuits can be placed in short distances to reduce spatial variability across different data bits and clocks. It is difficult to meet the above key metrics with an arbitrary floor plan. Therefore, specific placement of analog macros, IO pads, and key logic components may be required to meet the above key metrics. Figure 2 , Figure 3 This floorplan is provided that meets the key metrics described above.

[0014] Figure 2 2 is a diagram illustrating a first configuration of a DDR PHY planar arrangement. Figure 2As illustrated, the DDR PHY includes a first set of core logic components 212 (also referred to as "key logic components") configured to convert data between a single stream and a dual stream. Specifically, the first set of core logic components 212 is configured to convert data for writing from a single data rate to a double data rate, and to convert data for reading from a double data rate to a single data rate. The DDR PHY also includes a first data I / O block 202 located on a first side of the first set of core logic components 212. In one example, the first data I / O block 202 provides 8 data read / write bits (i.e., one byte) and one data mask (DM) bit. The first data I / O block 202 interfaces with the first set of core logic components 212. The first data I / O block 202 includes a plurality of I / O circuits for interfacing with an external memory / DRAM 110. The first data I / O block 202 is in one column (or a single row) rather than in multiple columns (rows), such as in a "butterfly" or "folded" configuration. In this way, columns 0, 1 of the "butterfly" / "folded" configuration interface block are combined into one column for the first data I / O block 202. The DDR PHY also includes a second set of core logic components 214 configured to process CA information. The DDR PHY also includes a first CA I / O sub-block 206 located on a second side of the first set of core logic components 212. In one example, the first CA I / O sub-block 206 provides 3 CA bits and 1 clock enable bit. The first CA I / O sub-block 206 interfaces with the second set of core logic components 214. The first CA I / O sub-block 206 includes a plurality of I / O circuits for interfacing with the external memory / DRAM 110. The DDR PHY also includes a first set of power switches 218 adjacent to at least one side of the first CA I / O sub-block 206. The first set of power switches 218 are coupled to the first set of core logic components 212 and the second set of core logic components 214. The first set of power switches 218 gates power to the first set of core logic components 212 and the second set of core logic components 214 so that power can be saved when the DDR PHY is not in operation.

[0015] like Figure 2 As illustrated, the first set of power switches 218 is adjacent to at least one side of the first CA I / O sub-block 206. In one configuration, the first set of power switches 218 is adjacent to both sides of the first CA I / O sub-block 206, and at least a portion of the first set of power switches 218 is located between the first CA I / O sub-block 206 and the first set of core logic components 212.

[0016] like Figure 2As illustrated, the DDR PHY also includes a third group of core logic components 216, which is configured to convert data between a single stream and a dual stream. Specifically, the third group of core logic components 216 is configured to convert data for writing from a single data rate to a double data rate, and to convert data for reading from a double data rate to a single data rate. The DDR PHY also includes a second data I / O block 204 located on a first side of the third group of core logic components 216. In one example, the second data I / O block 204 provides 8 data read / write bits (i.e., one byte) and one DM bit. The second data I / O block 204 interfaces with the third group of core logic components 216. The second data I / O block 204 includes a plurality of I / O circuits for interfacing with an external memory / DRAM 110. The second data I / O block 204 is in a column and has a configuration similar to the first data I / O block 202. The DDR PHY also includes a second CA I / O sub-block 208 located on a second side of the third group of core logic components 216. In one example, the second CA I / O sub-block 208 provides 3 CA bits, 1 clock bit, and 1 inverted clock bit. The second CA I / O sub-block 208 interfaces with the second group of core logic components 214. The second CA I / O sub-block 208 includes a plurality of I / O circuits for interfacing with the external memory / DRAM 110. The first CA I / O sub-block 206 and the second CA I / O sub-block 208 together serve as a folded dual-rank I / O block in a "butterfly" configuration. The DDR PHY also includes a second group of power switches 220 adjacent to at least one side of the second CA I / O sub-block 208. The second group of power switches 220 are coupled to the third group of core logic components 216 and the second group of core logic components 214. The second group of power switches 220 gate power to the third group of core logic components 216 and the second group of core logic components 214 so that power can be saved when the DDR PHY is not in operation.

[0017] like Figure 2 As illustrated, the second set of power switches 220 is adjacent to at least one side of the second CA I / O sub-block 208. In one configuration, the second set of power switches 220 is adjacent to both sides of the second CA I / O sub-block 208, and at least a portion of the second set of power switches 220 is located between the second CA I / O sub-block 208 and the third set of core logic components 216.

[0018] The DDR PHY may also include a PLL 210 located on a first side of the second set of core logic components 214 and between the first CA I / O sub-block 206 and the second CA I / O sub-block 208. The PLL is configured to provide a clock signal to the first set of core logic components 212, the second set of core logic components 214, and the third set of core logic components 216 through a clock path 222. Figure 2 As can be seen in FIG. 1 , the first group of core logic components 212 and the third group of core logic components 216 are approximately equidistant from the PLL. Therefore, the clock path length of the clock path 222 for carrying the clock signal between the PLL 210 and the first group of core logic components 212 is approximately equal to the clock path length for carrying the clock signal between the PLL 210 and the third group of core logic components 216.

[0019] Figure 3 3 is a diagram illustrating a second configuration of a DDR PHY planar arrangement. Figure 3 , the DDR PHY further includes at least one set of decoupling capacitors 324 adjacent to one of the first data I / O block 202 or the first CA I / O sub-block 206. In one configuration, the at least one set of decoupling capacitors 324 is adjacent to one of the first data I / O block 202, the first CA I / O sub-block 206, the second CA I / O sub-block 208, or the second data I / O block 204. In one configuration, the at least one set of decoupling capacitors is adjacent to each of the first data I / O block 202, the first CA I / O sub-block 206, the second CA I / O sub-block 208, and the second data I / O block 204.

[0020] Reference again Figure 2 , Figure 3, the power switch groups 218, 220 occupy all layers for routing. By locating the power switch groups 218, 220 in close proximity to the CA I / O sub-blocks 206, 208 (which themselves occupy all layers for routing), the overall routing constraints (global and internal routing across the DDR PHY and internal routing within the DDR PHY) can be reduced because the power switch groups 218, 220 and the CA I / O sub-blocks 206, 208 (which are effectively walls for routing) are located together. In addition, locating the power switch groups 218, 220 near the core logic component groups 212, 214, 216 reduces IR drop and improves the performance of the power distribution network (PDN). Positioning the power switch groups 218, 220 close to the core logic component groups 212, 214, 216 reduces the resistance from the output of the power switch groups 218, 220 to the power / ground grid (which supplies power / ground to the core logic component groups 212, 214, 216), which in turn reduces the power supply voltage drop. In addition, by utilizing a single column data I / O block 202, 204 and positioning the PLL 210 between the CA I / O sub-blocks 206, 208, the PLL clock routing length can be reduced and made uniform, which reduces jitter, duty cycle distortion, and clock insertion delay. In addition, in the provided planar layout, the voltage regions are clearly separated, which reduces the complexity of the redistribution layer (RDL) (or top layer PDN). Finally, the provided planar layout provides at least 13% reduction in occupied area. Further reduction in occupied area can be achieved by removing some decoupling capacitor groups 324.

[0021] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not limited to the various aspects described herein, but should be given the full scope consistent with the language claims. Unless otherwise specified, reference to an element in the singular form does not mean "one and only one", but "one or more". Terms such as "if", "when ..." and "while" do not mean a direct temporal relationship or reaction. That is, these phrases, such as "when ...", do not mean an immediate action in response to the occurrence of an action or during the occurrence of an action, but only mean that if the conditions are met, the action will occur, but no specific or immediate time limit is required for the occurrence of the action. The wording "exemplary" is used herein to mean "used as an example, instance or illustration". Any aspect described as "exemplary" herein is not necessarily interpreted as being preferred or having advantages over other aspects. Unless otherwise specified, the term "some" refers to one or more. Combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may contain one or more members of A, B, or C. A set should be interpreted as a set of elements, where the number of elements is one or more. Thus, for a set of X, X will include one or more elements. If the first device receives data from the second device or sends data to the second device, data can be directly received / sent between the first device and the second device, or data can be indirectly received / sent between the first device and the second device by a collection of devices. All structural and functional equivalents that are known or will be known later to those of ordinary skill in the art throughout the elements of the various aspects described in this disclosure are expressly incorporated herein by reference, and are covered by the claims. In addition, anything disclosed herein is not intended to be dedicated to the public, regardless of whether such disclosures are explicitly stated in the claims. Words such as "module", "mechanism", "element", "equipment" cannot replace the word "component". Therefore, no claim element will be interpreted as a functional component unless the element is explicitly described using the phrase "component for...".As used herein, the phrase "based on" should not be interpreted as referring to a closed set of information, one or more conditions, one or more factors, etc. In other words, the phrase "based on A" (where "A" can be information, a condition, a factor, etc.) should be interpreted as "based at least on A" unless specifically stated differently.

[0022] The following examples are merely illustrative and may be combined with aspects of other implementations or teachings described herein without limitation.

[0023] Aspect 1 is an IC, comprising: a first group of core logic components, the first group of core logic components being configured to convert data between a single stream and a dual stream; a first data I / O block located on a first side of the first group of core logic components, the first data I / O block being interfaced with the first group of core logic components, the first data I / O block comprising a plurality of I / O circuits for interfacing with a DRAM, the first data I / O block being in a column; a second group of core logic components, the second group of core logic components being configured to process CA information; a first CA I / O sub-block located on a second side of the first group of core logic components, the first CA I / O sub-block being interfaced with the second group of core logic components, the first CA I / O sub-block comprising a plurality of I / O circuits for interfacing with the DRAM; and a first group of power switches adjacent to at least one side of the first CA I / O sub-block, the first group of power switches being coupled to the first group of core logic components and the second group of core logic components.

[0024] Aspect 2 is the IC of aspect 1, wherein the first set of power switches is immediately adjacent to the at least one side of the first CA I / O sub-block.

[0025] Aspect 3 is an IC according to any one of Aspects 1 and 2, wherein the first group of power switches are adjacent to both sides of the first CA I / O sub-block, and at least a portion of the first group of power switches is located between the first CA I / O sub-block and the first group of core logic components.

[0026] Aspect 4 is an IC according to any one of Aspects 1 to 3, wherein the IC further includes: a third group of core logic components, the third group of core logic components being configured to convert data between a single stream and a dual stream; a second data I / O block located on a first side of the third group of core logic components, the second data I / O block being interfaced with the third group of core logic components, the second data I / O block including a plurality of I / O circuits for interfacing with the DRAM, the second data I / O block being in one column; a second CA I / O sub-block located on a second side of the third group of core logic components, the second CA I / O sub-block being interfaced with the second group of core logic components, the second CA I / O sub-block including a plurality of I / O circuits for interfacing with the DRAM, the first CA I / O sub-block and the second CA I / O sub-block together serving as a folded dual-rank I / O block; and a second group of power switches adjacent to at least one side of the second CA I / O sub-block, the second group of power switches being coupled to the third group of core logic components and the second group of core logic components.

[0027] Aspect 5 is the IC of aspect 4, wherein the second set of power switches is immediately adjacent to the at least one side of the second CA I / O sub-block.

[0028] Aspect 6 is an IC according to any one of Aspects 4 and 5, wherein the second group of power switches is adjacent to both sides of the second CA I / O sub-block, and at least a portion of the second group of power switches is located between the second CA I / O sub-block and the third group of core logic components.

[0029] Aspect 7 is an IC according to any one of Aspects 4 to 6, wherein the IC also includes a PLL located on the first side of the second group of core logic components and between the first CA I / O sub-block and the second CA I / O sub-block, and the PLL is configured to provide a clock signal to the first group of core logic components, the second group of core logic components, and the third group of core logic components.

[0030] Aspect 8 is an IC according to aspect 7, wherein a clock path length for carrying the clock signal between the PLL and the first group of core logic components is approximately equal to a clock path length for carrying the clock signal between the PLL and the third group of core logic components.

[0031] Aspect 9 is an IC according to any one of Aspects 4 to 8, wherein the IC also includes at least one set of decoupling capacitors adjacent to one of the first data I / O block, the first CA I / O sub-block, the second CA I / O sub-block, or the second data I / O block.

[0032] Aspect 10 is an IC according to aspect 9, wherein the at least one set of decoupling capacitors is adjacent to each of the first data I / O block, the first CA I / O sub-block, the second CA I / O sub-block, and the second data I / O block.

[0033] Aspect 11 is an IC according to any one of aspects 1 to 10, the IC further comprising at least one set of decoupling capacitors adjacent to one of the first data I / O block or the first CA I / O sub-block.

[0034] Aspect 12 is an IC according to any one of aspects 1 to 11, wherein the IC is a DDR PHY block.

Claims

1. An integrated circuit (IC), comprising: a first set of core logic components configured to convert data between a single stream and a dual stream; a first data input or output (I / O) block located on a first side of the first set of core logic components, the first data I / O block interfacing with the first set of core logic components, the first data I / O block including a plurality of I / O circuits for interfacing with a dynamic random access memory (DRAM), the first data I / O block being in a column; a second set of core logic components configured to process command and address (CA) information; a first CA I / O sub-block located on a second side of the first set of core logic components, the first CA I / O sub-block interfacing with the second set of core logic components, the first CA I / O sub-block including a plurality of I / O circuits for interfacing with the DRAM; and A first set of power switches is adjacent to at least one side of the first CA I / O sub-block, the first set of power switches being coupled to the first set of core logic components and the second set of core logic components. 2 . The IC of claim 1 , wherein the first set of power switches is immediately adjacent to the at least one side of the first CA I / O sub-block.

3. The IC of claim 1 , wherein the first set of power switches is adjacent to both sides of the first CA I / O sub-block, and at least a portion of the first set of power switches is located between the first CA I / O sub-block and the first set of core logic components.

4. The IC of claim 1 , further comprising: a third set of core logic components configured to convert data between the single stream and the dual stream; a second data I / O block located on a first side of the third group of core logic components, the second data I / O block being interfaced with the third group of core logic components, the second data I / O block comprising a plurality of I / O circuits for interfacing with the DRAM, the second data I / O block being in a column; a second CA I / O sub-block located on a second side of the third group of core logic components, the second CA I / O sub-block interfacing with the second group of core logic components, the second CA I / O sub-block including a plurality of I / O circuits for interfacing with the DRAM, the first CA I / O sub-block and the second CA I / O sub-block together functioning as a folded dual rank I / O block; and A second set of power switches is adjacent to at least one side of the second CA I / O sub-block, the second set of power switches being coupled to the third set of core logic components and the second set of core logic components. 5 . The IC of claim 4 , wherein the second set of power switches is immediately adjacent to the at least one side of the second CA I / O sub-block.

6. The IC of claim 4, wherein the second set of power switches is adjacent to both sides of the second CA I / O sub-block, and at least a portion of the second set of power switches is located between the second CA I / O sub-block and the third set of core logic components.

7. The IC of claim 4 , further comprising a phase-locked loop (PLL) located on a first side of the second group of core logic components and between the first CA I / O sub-block and the second CA I / O sub-block, the PLL being configured to provide a clock signal to the first group of core logic components, the second group of core logic components, and the third group of core logic components.

8. The IC of claim 7, wherein a clock path length for carrying the clock signal between the PLL and the first set of core logic components is approximately equal to a clock path length for carrying the clock signal between the PLL and the third set of core logic components.

9. The IC of claim 4, further comprising at least one set of decoupling capacitors adjacent to one of the first data I / O block, the first CA I / O sub-block, the second CA I / O sub-block, or the second data I / O block.

10. The IC of claim 9, wherein the at least one set of decoupling capacitors is adjacent to each of the first data I / O block, the first CA I / O sub-block, the second CA I / O sub-block, and the second data I / O block.

11. The IC of claim 1, further comprising at least one set of decoupling capacitors adjacent to one of the first data I / O block or the first CA I / O sub-block.

12. The IC of claim 1, wherein the IC is a double data rate (DDR) physical (PHY) block.

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