Display device and method for manufacturing same

Abstract

The display device includes: a first electrode and a second electrode spaced apart from each other; third and fourth electrodes crossing the first and second electrodes and spaced apart from each other; and light emitting elements disposed between the first electrode and the second electrode, in which a first end of each of the light emitting elements faces the third electrode and a second end of each of the light emitting elements faces the fourth electrode.

Description

Technical Field

[0001] The present invention relates to a display device and a method of manufacturing the display device. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices are being continuously conducted. Summary of the invention

[0003] Technical issues

[0004] An object to be solved by the disclosure is to provide a display device capable of improving alignment of light emitting elements (eg, degree of alignment of light emitting elements) and a method of manufacturing the display device.

[0005] The disclosed purposes are not limited to the above-mentioned purposes, and other technical purposes not described will be clearly understood by those skilled in the art through the following description.

[0006] Technical Solution

[0007] According to the disclosed embodiment for solving the above-mentioned purpose, a display device includes: a first electrode and a second electrode, which are spaced apart from each other; a third electrode and a fourth electrode, which intersect the first electrode and the second electrode and are spaced apart from each other; and a light-emitting element, which is arranged between the first electrode and the second electrode. A first end of each of the light-emitting elements faces the third electrode, and a second end of each of the light-emitting elements faces the fourth electrode.

[0008] The first and second electrodes may be spaced apart from each other in the first direction and may extend in the second direction, and the third and fourth electrodes may be spaced apart from each other in the second direction and may extend in the first direction.

[0009] The light emitting elements may be arranged in the second direction.

[0010] The first electrode and the second electrode may be disposed on the third electrode and the fourth electrode.

[0011] The display device may further include an insulating layer between the first and second electrodes and the third and fourth electrodes.

[0012] The display device may further include: a first connection electrode electrically contacting the first end of each of the light emitting elements; and a second connection electrode electrically contacting the second end of each of the light emitting elements.

[0013] The first connection electrode may be electrically connected to the first electrode, and the second connection electrode may be electrically connected to the second electrode.

[0014] The third electrode and the fourth electrode may be disposed on the first electrode and the second electrode.

[0015] The light emitting element may be electrically connected to the third electrode and the fourth electrode.

[0016] A side portion of each of the light emitting elements between the first end and the second end may face the first electrode and the second electrode.

[0017] According to the disclosed embodiment, a method for manufacturing a display device for solving the above-mentioned object includes: applying a first alignment signal to the first alignment electrodes to initially align light emitting elements between first alignment electrodes; and applying a second alignment signal to second alignment electrodes crossing the first alignment electrodes to second align the light emitting elements. The second alignment electrodes extend in a first direction and are spaced apart from each other in a second direction, and the light emitting elements are aligned in the second direction in the secondary alignment of the light emitting elements.

[0018] The frequency of the first alignment signal may be different from the frequency of the second alignment signal.

[0019] The second alignment electrode may include a first sub-alignment electrode and a second sub-alignment electrode spaced apart from each other in the second direction, a first end of each of the light emitting elements may face the first sub-alignment electrode, and a second end of each of the light emitting elements may face the second sub-alignment electrode.

[0020] The first sub-alignment electrodes and the second sub-alignment electrodes may be alternately arranged in the second direction.

[0021] A side portion of each of the light emitting elements between the first end and the second end may face the first alignment electrode.

[0022] The method may further include forming a connection electrode on the light emitting element.

[0023] The connection electrode may be electrically connected to the first alignment electrode.

[0024] The first alignment electrode may be formed on the second alignment electrode.

[0025] The connection electrode may be electrically connected to the second alignment electrode.

[0026] The second alignment electrode may be formed on the first alignment electrode.

[0027] Details of other embodiments are included in the detailed description and accompanying drawings.

[0028] Beneficial Effects

[0029] According to the above embodiment, since the position and direction of the light emitting element can be accurately controlled by aligning the position of the light emitting element using the first alignment electrode and aligning the direction of the light emitting element using the second alignment electrode, the alignment of the light emitting element can be improved.

[0030] The effects according to the embodiment are not limited to the contents shown above, and more various effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0032] Figure 2 and Figure 3 are schematic diagrams each showing an equivalent circuit of a sub-pixel according to the embodiment.

[0033] Figure 4 and Figure 5 are schematic plan views each showing a sub-pixel according to an embodiment.

[0034] Figure 6 and Figure 7 It is along Figure 4 A schematic cross-sectional view taken along line AA'.

[0035] Figure 8 It is along Figure 4 A schematic cross-sectional view taken along line BB'.

[0036] Fig. 9 is a schematic plan view showing a sub-pixel according to an embodiment.

[0037] Fig.10 It is along Fig. 9 A schematic cross-sectional view taken along line CC'.

[0038] Fig.11 It is along Fig. 9 A schematic cross-sectional view taken along line D-D'.

[0039] Fig.12 and Fig.13 are schematic cross-sectional views each showing a pixel unit according to an embodiment.

[0040] Fig.14 is a schematic perspective view showing a light emitting element according to an embodiment.

[0041] Fig.15 is a schematic cross-sectional view showing a light emitting element according to the embodiment.

[0042] Figures 16 to 21 is a schematic plan view of each process step of a method for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0043] The advantages and features of the disclosure and methods for achieving them will become apparent with reference to the embodiments described in detail below and the accompanying drawings. However, the disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms. The embodiments are provided so that the disclosure will be more thorough and complete, and those skilled in the art can understand the scope of the disclosure.

[0044] The terms used in the specification are used to describe the embodiments and are not intended to limit the disclosure. In the specification, unless otherwise specified, the singular form also includes the plural form. The terms "comprise" and / or "include" do not exclude the presence of one or more other components, steps, operations and / or elements or the addition of one or more other components, steps, operations and / or elements to the described components, steps, operations and / or elements.

[0045] The term "connected" or "coupled" may refer to a physical and / or electrical connection. The term may refer to a direct or indirect connection or an integral or non-integral connection.

[0046] When an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer, or intervening elements or layers may be present. Throughout the specification, the same reference numerals refer to the same components.

[0047] Although terms such as first, second, etc. are used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the disclosed technical spirit, the first component described below can be the second component.

[0048] Hereinafter, disclosed embodiments are described in detail with reference to the accompanying drawings.

[0049] Figure 1 is a schematic plan view showing a display device according to an embodiment. Figure 1 A display panel PNL provided in a display device is shown.

[0050] exist Figure 1 , the structure of the display panel PNL is briefly shown based on the display area DA. However, according to an embodiment, at least one driving circuit unit (or driving circuit portion) (for example, at least one of a scan driver and a data driver), a line and / or a pad (or referred to as a "pad") not shown may be further provided on the display panel PNL.

[0051] Reference Figure 1The display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA which is not the display area DA. The display area DA may construct a screen on which an image is displayed, and the non-display area NDA may be a remaining area except for the display area DA.

[0052] The pixel unit (or pixel) PXU may be arranged in the display area DA. The pixel unit PXU may include a first sub-pixel SPX1, a second sub-pixel SPX2, and / or a third sub-pixel SPX3. Hereinafter, when at least one sub-pixel among the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 is arbitrarily referred to, or when two or more types of sub-pixels among the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are collectively referred to, the at least one sub-pixel or the two or more types of sub-pixels are referred to as "sub-pixel SPX" or "plurality of sub-pixels SPX".

[0053] The sub-pixel SPX can be arranged in a stripe structure or a PENTILE TM However, the arrangement structure of the sub-pixels SPX is not limited thereto, and the sub-pixels SPX may be arranged in the display area DA in various structures and / or methods.

[0054] According to an embodiment, two or more types of sub-pixels SPX emitting light of different colors may be arranged in the display area DA. For example, in the display area DA, a first sub-pixel SPX1 emitting light of a first color, a second sub-pixel SPX2 emitting light of a second color, and a third sub-pixel SPX3 emitting light of a third color may be arranged. At least one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 disposed adjacent to each other may construct a pixel unit PXU capable of emitting light of various colors. For example, each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be a sub-pixel emitting light of a predetermined color. According to an embodiment, the first sub-pixel SPX1 may be a red sub-pixel emitting red light, the second sub-pixel SPX2 may be a green sub-pixel emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel emitting blue light, but is not limited thereto.

[0055] In an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include light-emitting elements that emit light of the same color, and may include color conversion layers and / or color filter layers of different colors disposed on each light-emitting element to emit light of a first color, a second color, and a third color, respectively. In another embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a light-emitting element of a first color, a light-emitting element of a second color, and a light-emitting element of a third color as light sources to emit light of a first color, a light of a second color, and a light of a third color, respectively. However, the color, type, number, etc. of the sub-pixels SPX that construct each pixel unit PXU are not particularly limited. That is, the color of the light emitted by each sub-pixel SPX may be changed differently.

[0056] The sub-pixel SPX may include at least one light source driven by a control signal (e.g., a scan signal and a data signal) and / or a power source (e.g., a first power source and a second power source). In an embodiment, the light source may include at least one light-emitting element, for example, an ultra-small columnar light-emitting element having a size as small as nanometer to micrometer. However, the disclosure is not limited thereto, and various types of light-emitting elements may be used as the light source of the sub-pixel SPX.

[0057] In an embodiment, each sub-pixel SPX may be configured as an effective sub-pixel. However, the type, structure and / or driving method of the sub-pixel SPX applicable to the display device are not particularly limited. For example, each sub-pixel SPX may be configured as a sub-pixel of a passive light-emitting display device or an active light-emitting display device having various structures and / or driving methods.

[0058] Figure 2 and Figure 3 are schematic diagrams each showing an equivalent circuit of a sub-pixel according to the embodiment.

[0059] According to an embodiment, Figure 2 and Figure 3 The sub-pixel SPX shown in FIG. 1 may be arranged in Figure 1 Any one of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 in the display panel PNL of the display panel PNL. The first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have structures substantially the same as or similar to each other.

[0060] Reference Figure 2 and Figure 3 , the sub-pixel SPX may include a light source unit (or light source portion) LSU for generating light of brightness corresponding to the data signal and a pixel circuit PXC for driving the light source unit LSU.

[0061] The light source unit LSU may include at least one light emitting element LD electrically connected between a first power supply VDD and a second power supply VSS. The first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD emits light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. The potential difference between the first power supply VDD and the second power supply VSS may be set to be substantially equal to or greater than a threshold voltage of the light emitting element LD at least during an emission period of the sub-pixel SPX.

[0062] The light emitting element LD may emit light having a brightness corresponding to the driving current supplied by the pixel circuit PXC. The light emitting element LD may be constructed of an organic light emitting diode, or an inorganic light emitting diode such as a micro light emitting diode or a quantum dot light emitting diode. In an embodiment, the light emitting element LD may be a light emitting diode of an ultra-small size (e.g., a size as small as nanometer to micrometer) including a material of an inorganic crystal structure.

[0063] In an embodiment, the light source unit LSU may include light emitting elements LD connected in parallel to each other. Figure 3 As shown in , the light source unit LSU may include a first connection electrode CNE1 electrically connected to a first power source VDD via a pixel circuit PXC and a first power source line PL1, a second connection electrode CNE2 electrically connected to a second power source VSS through a second power source line PL2, and a light emitting element LD electrically connected in the same direction between the first connection electrode CNE1 and the second connection electrode CNE2. In an embodiment, the first connection electrode CNE1 may be an anode electrode or may correspond to an anode electrode, and the second connection electrode CNE2 may be a cathode electrode or may correspond to a cathode electrode.

[0064] The light emitting element LD may include a first terminal (e.g., a p-type terminal) electrically connected to the first power source VDD through the first connection electrode CNE1 and / or the pixel circuit PXC and a second terminal (e.g., an n-type terminal) electrically connected to the second power source VSS through the second connection electrode CNE2. For example, the light emitting element LD may be connected in parallel in a forward direction between the first connection electrode CNE1 and the second connection electrode CNE2. Each of the light emitting elements LD connected in the forward direction between the first power source VDD and the second power source VSS may construct each effective light source, and the effective light sources may be collected to construct the light source unit LSU of the sub-pixel SPX.

[0065] A first end of the light emitting element LD may be commonly connected to the pixel circuit PXC through one electrode (e.g., the first connection electrode CNE1) of the light source unit LSU, and may be electrically connected to the first power source VDD through the pixel circuit PXC and the first power source line PL1. A second end of the light emitting element LD may be commonly connected to the second power source VSS through another electrode (e.g., the second connection electrode CNE2) of the light source unit LSU and the second power source line PL2.

[0066] According to an embodiment, the light source unit LSU may include light emitting elements LD connected in series. The light source unit LSU may include at least one series connection. Each series connection may include a pair of electrodes (e.g., two electrodes) and at least one light emitting element LD connected in a forward direction between the pair of electrodes. Here, the number of series connections configuring the light source unit LSU and the number of light emitting elements LD configuring each series connection are not particularly limited. For example, the number of light emitting elements LD configuring each series connection may be the same as or different from each other, and the number of light emitting elements LD is not particularly limited.

[0067] In the case where the light emitting elements LD are connected in series / parallel, power efficiency can be improved compared to the case where the same number of light emitting elements LD are connected only in parallel. In the sub-pixel SPX in which the light emitting elements LD are connected in series / parallel, even if a short circuit defect or the like occurs in some series stages, since brightness can be expressed by the light emitting elements LD of the remaining series stages, the possibility of a black spot defect in the sub-pixel SPX can be reduced. However, the disclosure is not limited thereto, and the light source unit LSU can be constructed by connecting only the light emitting elements LD in series, or the light source unit LSU can be constructed by connecting only the light emitting elements LD in parallel.

[0068] The pixel circuit PXC may be electrically connected between the first power supply VDD and the light source unit LSU. The pixel circuit PXC may be electrically connected to the scan line Si (or gate line) and the data line Dj. The pixel circuit PXC may also be electrically connected to the sensing control line SSi and the sensing line SLj. For example, in the case where the sub-pixel SPX is arranged on the i-th (i is a natural number greater than 0) horizontal line (row or sub-pixel row) and the j-th (j is a natural number greater than 0) vertical line (column or sub-pixel column) of the display area DA, the pixel circuit PXC of the sub-pixel SPX may be electrically connected to the i-th scan line Si, the i-th sensing control line SSi, the j-th data line Dj and the sensing line SLj of the display area DA.

[0069] According to an embodiment, the pixel circuit PXC may include a transistor and at least one capacitor. For example, the pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0070] The first transistor T1 may be electrically connected between the first power supply VDD and the light source unit LSU. For example, a first electrode (e.g., a drain electrode) of the first transistor T1 may be electrically connected to the first power supply VDD, and a second electrode (e.g., a source electrode) of the first transistor T1 may be electrically connected to an electrode (e.g., an anode electrode) of the light source unit LSU. A gate electrode of the first transistor T1 may be electrically connected to a first node N1. A back gate electrode of the first transistor T1 may be electrically connected to a second node N2. The first transistor T1 may control a driving current supplied to the light source unit LSU in response to a voltage of the first node N1. For example, the first transistor T1 may be a driving transistor that controls a driving current of the sub-pixel SPX.

[0071] The second transistor T2 may be electrically connected between the data line Dj and the first node N1. For example, the first electrode (e.g., source electrode) of the second transistor T2 may be electrically connected to the data line Dj, and the second electrode (e.g., drain electrode) of the second transistor T2 may be electrically connected to the first node N1. The gate electrode of the second transistor T2 may be electrically connected to the scan line Si. The second transistor T2 may be turned on in the case of a scan signal SCi supplying a gate-on voltage (e.g., a high-level voltage) from the scan line Si, so that the data line Dj and the first node N1 are electrically connected. In each frame period, a data signal DSj of a corresponding frame may be supplied to the data line Dj, and the data signal DSj may be transmitted to the first node N1 by the second transistor T2 turned on during the period of the scan signal SCi supplying the gate-on voltage. For example, the second transistor T2 may be a switching transistor for transmitting each data signal DSj to the inside of the sub-pixel SPX.

[0072] The third transistor T3 may be electrically connected between the first transistor T1 and the sensing line SLj. For example, the first electrode of the third transistor T3 may be electrically connected to the sensing line SLj, and the second electrode of the third transistor T3 may be electrically connected to the second node N2 (or the second electrode of the first transistor T1). The gate electrode of the third transistor T3 may be connected to the sensing control line SSi. In the case where the sensing control line SSi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si (the previous scan line in the row before the scan line Si or the next scan line in the row after the scan line Si). The third transistor T3 may be turned on by the sensing control signal SSCi of the gate-on voltage supplied to the sensing control line SSi during the sensing period to electrically connect the sensing line SLj and the first transistor T1.

[0073] According to an embodiment, the sensing period may be a period in which the characteristics of the sub-pixel SPX set in the display area DA (for example, the threshold voltage of the first transistor T1, etc.) are extracted. During the sensing period, a reference voltage that can turn on the first transistor T1 may be supplied to the first node N1 through the data line Dj and the second transistor T2, or each sub-pixel SPX may be connected to a current source, etc. to turn on the first transistor T1. Since the third transistor T3 is turned on by supplying a sensing control signal SSCi of a gate-on voltage to the third transistor T3, the first transistor T1 may be electrically connected to the sensing line SLj. Thereafter, the sensing signal SENj may be output to an external device through the sensing line SLj, and the characteristics of each sub-pixel SPX including the threshold voltage of the first transistor T1, etc. may be detected by using the sensing signal SENj.

[0074] A first electrode of the storage capacitor Cst may be electrically connected to the second node N2, and a second electrode of the storage capacitor Cst may be electrically connected to the first node N1. The storage capacitor Cst may be charged with a voltage corresponding to the data signal DSj supplied to the first node N1 during each frame period.

[0075] exist Figure 2 and Figure 3 In the embodiment, all transistors (e.g., the first transistor T1, the second transistor T2, and the third transistor T3) included in the pixel circuit PXC are N-type transistors, but the disclosure is not limited thereto. At least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a P-type transistor. In addition, the pixel circuit PXC may be constructed by pixel circuits of various structures and / or driving methods.

[0076] Figure 4 and Figure 5 are schematic plan views each showing a sub-pixel according to an embodiment. Figure 6 and Figure 7 It is along Figure 4 A cross-sectional view taken along line AA'. Figure 8 It is along Figure 4 A cross-sectional view taken along line BB'.

[0077] For example, Figure 4 and Figure 5 Can be a construct Figure 1 Any one of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 of the pixel unit PXU, the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 may have the same or similar structures as each other.

[0078] Reference Figure 4 and Figure 5, the sub-pixel SPX may include a first alignment electrode ELA, a second alignment electrode ELB, a light emitting element LD and / or a connection electrode CNE.

[0079] The first alignment electrodes ELA may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The first alignment electrodes ELA may include a first alignment line ELA1, a second alignment line ELA2, and a third alignment line ELA3 that are spaced apart from each other. The second alignment line ELA2 may be disposed between the first alignment line ELA1 and the third alignment line ELA3. The first alignment line ELA1, the second alignment line ELA2, and the third alignment line ELA3 may be sequentially arranged along the first direction (X-axis direction). The first alignment electrode ELA may receive a first alignment signal in the step of aligning the position of the light emitting element LD. For example, the first alignment electrode ELA may be used as an alignment electrode for aligning the position of the light emitting element LD. Refer to the following Figures 16 to 21 Describe its detailed description.

[0080] A portion of the first alignment electrode ELA may be connected to the Figure 2 For example, the first alignment line ELA1 may be connected to the pixel circuit PXC and / or the first power line PL1 through a contact hole, and the second alignment line ELA2 may be connected to the second power line PL2 through a contact hole, but the disclosure is not limited thereto.

[0081] The second alignment electrodes ELB may extend in the first direction (X-axis direction) and may be spaced apart from each other in the second direction (Y-axis direction). The second alignment electrode ELB may cross (or intersect) with the first alignment electrode ELA. In the accompanying drawings, a case is shown where the first alignment electrode ELA extends in the second direction (Y-axis direction) and the second alignment electrode ELB extends in the first direction (X-axis direction) to cross each other, but the extension direction of the first alignment electrode ELA and the second alignment electrode ELB, the angle at which the first alignment electrode ELA and the second alignment electrode ELB cross each other, etc. may be changed differently in consideration of the arrangement of the light emitting element LD in the sub-pixel SPX.

[0082] The second alignment electrode ELB may receive a second alignment signal in the step of aligning the direction of the light emitting element LD. For example, the second alignment electrode ELB may be used as a direction alignment electrode for aligning the direction of the light emitting element LD. Figures 16 to 21 Describe its detailed description.

[0083] The second alignment electrode ELB may include first sub-alignment electrodes ELB1 and second sub-alignment electrodes ELB2 spaced apart from each other. The first sub-alignment electrodes ELB1 and the second sub-alignment electrodes ELB2 may be alternately arranged in the second direction (Y-axis direction).

[0084] The first sub-alignment electrodes ELB1 may be connected to each other through the first connection wires CNL1, and the second sub-alignment electrodes ELB2 may be connected to each other through the second connection wires CNL2. The first connection wires CNL1 and the second connection wires CNL2 may extend in the second direction (Y-axis direction). The first connection wires CNL1 may be formed integrally with the first sub-alignment electrodes ELB1 (or integrally with the first sub-alignment electrodes ELB1), but are not limited thereto. The second connection wires CNL2 may be formed integrally with the second sub-alignment electrodes ELB2, but are not limited thereto.

[0085] The light emitting element LD may be positioned between the first alignment electrodes ELA. For example, the light emitting element LD may be positioned between the first alignment line ELA1 and the second alignment line ELA2 and between the second alignment line ELA2 and the third alignment line ELA3. The light emitting element LD may be arranged in the second direction (Y-axis direction) between the first alignment electrodes ELA.

[0086] The light emitting element LD may be offset aligned between the second alignment electrodes ELB. For example, the first end EP1 of the light emitting element LD may face the first sub-alignment electrode ELB1. The second end EP2 of the light emitting element LD may face the second sub-alignment electrode ELB2. The side portion SP between the first end EP1 and the second end EP2 of the light emitting element LD may face the first alignment electrode ELA. Since the position and direction of the light emitting element LD may be precisely controlled by aligning the position of the light emitting element LD by using the first alignment electrode ELA and aligning the direction of the light emitting element LD by using the second alignment electrode ELB as described above, the alignment degree of the light emitting element LD may be improved.

[0087] The light emitting element LD may be electrically connected to the connection electrode CNE. The connection electrodes CNE may extend in a first direction (X-axis direction) and may be spaced apart from each other in a second direction (Y-axis direction). The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 spaced apart from each other. The first connection electrode CNE1 and the second connection electrode CNE2 may be alternately arranged in the second direction (Y-axis direction). The first connection electrode CNE1 may overlap with a first end EP1 of the light emitting element LD and may be electrically connected to the first end EP1 of the light emitting element LD. The second connection electrode CNE2 may overlap with a second end EP2 of the light emitting element LD and may be electrically connected to the second end EP2 of the light emitting element LD.

[0088] According to an embodiment, the first connection electrode CNE1 may overlap the first alignment line ELA1 and may be electrically connected to the first alignment line ELA1 through a contact hole. The second connection electrode CNE2 may overlap the second alignment line ELA2 and may be electrically connected to the second alignment line ELA2 through a contact hole. Therefore, the first connection electrode CNE1 may electrically connect the light emitting element LD and the first alignment line ELA1, and the second connection electrode CNE2 may electrically connect the light emitting element LD and the second alignment line ELA2. According to an embodiment, the first connection electrode CNE1 may be electrically connected to the first alignment line ELA1 through a first bridge electrode, and the second connection electrode CNE2 may be electrically connected to the second alignment line ELA2 through a second bridge electrode.

[0089] The connection electrode CNE may be formed of (or include) a conductive layer. Figure 4 As shown in , the first connection electrode CNE1 may be formed of a first conductive layer, and the second connection electrode CNE2 may be formed of a second conductive layer. As another example, Figure 5 As shown, the first connection electrode CNE1 and the second connection electrode CNE2 may be formed of the same conductive layer. As described above, in the case where the first connection electrode CNE1 and the second connection electrode CNE2 are formed of the same conductive layer, the number of masks may be reduced and the manufacturing process may be simplified.

[0090] According to an embodiment, the first connection electrode CNE1 may be connected to each other through the third connection line CNL3. The second connection electrode CNE2 may be connected to each other through the fourth connection line CNL4. The third connection line CNL3 and the fourth connection line CNL4 may extend in the second direction (Y-axis direction). The first connection electrode CNE1 may be integrally formed with the third connection line CNL3, but is not limited thereto. The second connection electrode CNE2 may be integrally formed with the fourth connection line CNL4, but is not limited thereto.

[0091] In the following, reference is made to Figures 6 to 8 The cross-sectional structure of the sub-pixel SPX is described in detail. Figures 6 to 8 , a cross-sectional structure of a sub-pixel SPX is schematically shown based on a first alignment line ELA1 (or first electrode) and a second alignment line ELA2 (or second electrode) of a first alignment electrode ELA and a first sub-alignment electrode ELB1 (or third electrode) and a second sub-alignment electrode ELB2 (or fourth electrode) of a second alignment electrode ELB. Figures 6 to 8 The structure is shown in Figure 2The first transistor T1 among various circuit elements of the pixel circuit PXC is referred to as “transistor T”, and in the case where the first transistor T1, the second transistor T2, and the third transistor T3 do not need to be individually specified, the first transistor T1, the second transistor T2, and the third transistor T3 are referred to as “transistor T”. Meanwhile, the structure of the transistor T, the position of each layer, etc. are not limited to Figures 6 to 8 The embodiments shown in FIG. 1 and may be variously changed according to the embodiments.

[0092] The sub-pixel SPX according to the embodiment may include a pixel circuit layer PCL disposed on the base layer BSL and a display element layer DPL disposed on the pixel circuit layer PCL.

[0093] The base layer BSL may construct a base member, and may be a rigid or flexible substrate or film. For example, the base layer BSL may be a rigid substrate formed of glass or tempered glass, a flexible substrate (or film) of a plastic or metal material, or at least one insulating layer. There is no particular limitation on the material and / or physical properties of the base layer BSL. In an embodiment, the base layer BSL may be transparent. Here, transparent may mean that light can be transmitted with a certain transmittance or greater. In another embodiment, the base layer BSL may be translucent or opaque. The base layer BSL may include a reflective material according to the embodiment.

[0094] The pixel circuit layer PCL may be disposed on the base layer BSL. The lower conductive layer BML and the first power conductive layer PL2a may be disposed on the base layer BSL. The lower conductive layer BML and the first power conductive layer PL2a may be disposed on the same layer. For example, the lower conductive layer BML and the first power conductive layer PL2a may be formed simultaneously in the same process, but are not limited thereto. The first power conductive layer PL2a may be constructed as shown in FIG. Figure 2 Described second power line PL2 etc.

[0095] Each of the lower conductive layer BML and the first power conductive layer PL2a can be formed as a single layer or a multilayer formed of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn) and their oxides or alloys.

[0096] The buffer layer BFL may be disposed on the lower conductive layer BML and the first power conductive layer PL2a. The buffer layer BFL may prevent impurities from diffusing into the circuit element. The buffer layer BFL may be configured as a single layer, but may also be configured as a multilayer of at least two layers. In the case where the buffer layer BFL is formed as a multilayer, each layer may be formed of the same material, or at least some layers may be formed of different materials.

[0097] The semiconductor patterns SCP may be disposed on the buffer layer BFL. For example, each semiconductor pattern SCP may include a first region contacting the first transistor electrode TE1, a second region contacting the second transistor electrode TE2, and a channel region between the first region and the second region. According to an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0098] According to an embodiment, the semiconductor pattern SCP may be formed of polysilicon, amorphous silicon, oxide semiconductor, etc. The channel region of the semiconductor pattern SCP may be an intrinsic semiconductor as a semiconductor pattern not doped with impurities, and each of the first and second regions of the semiconductor pattern SCP may be a semiconductor doped with impurities.

[0099] The gate insulating layer GI may be disposed on the buffer layer BFL and the semiconductor pattern SCP. For example, the gate insulating layer GI may be disposed between the semiconductor pattern SCP and the gate electrode GE. The gate insulating layer GI may be disposed between the buffer layer BFL and the second power conductive layer PL2b. The gate insulating layer GI may be configured as a single layer or multiple layers, and may include a silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ) various types of inorganic materials.

[0100] The gate electrode GE and the second power conductive layer PL2b of the transistor T may be disposed on the gate insulating layer GI. The gate electrode GE and the second power conductive layer PL2b may be disposed on the same layer. For example, the gate electrode GE and the second power conductive layer PL2b may be formed simultaneously in the same process, but is not limited thereto. The gate electrode GE may be disposed to overlap the semiconductor pattern SCP in a third direction (Z-axis direction) on the gate insulating layer GI. The second power conductive layer PL2b may be disposed to overlap the first power conductive layer PL2a in a third direction (Z-axis direction) on the gate insulating layer GI. The second power conductive layer PL2b may be constructed together with the first power conductive layer PL2a for reference. Figure 2 The second power line PL2 described in the above description.

[0101] Each of the gate electrode GE and the second power conductive layer PL2b may be formed as a single layer or multiple layers of (or including) molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), or oxides or alloys thereof. For example, each of the gate electrode GE and the second power conductive layer PL2b may be formed of a plurality of layers in which titanium (Ti), copper (Cu), and / or indium tin oxide (ITO) are sequentially or repeatedly stacked.

[0102] The interlayer insulating layer ILD may be disposed on the gate electrode GE and the second power conductive layer PL2b. For example, the interlayer insulating layer ILD may be disposed between the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2. The interlayer insulating layer ILD may be disposed between the second power conductive layer PL2b and the third power conductive layer PL2c.

[0103] The interlayer insulating layer ILD may be constructed as a single layer or a multi-layer, and may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ) various types of inorganic materials.

[0104] The first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T and the third power conductive layer PL2c may be disposed on the interlayer insulating layer ILD. The first transistor electrode TE1 and the second transistor electrode TE2 and the third power conductive layer PL2c may be disposed on the same layer. For example, the first transistor electrode TE1 and the second transistor electrode TE2 and the third power conductive layer PL2c may be formed simultaneously in the same process, but are not limited thereto.

[0105] The first transistor electrode TE1 and the second transistor electrode TE2 may be arranged to overlap with the semiconductor pattern SCP in a third direction (Z-axis direction). The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to the semiconductor pattern SCP. For example, the first transistor electrode TE1 may be electrically connected to the first region of the semiconductor pattern SCP through a contact hole passing through the interlayer insulating layer ILD. The first transistor electrode TE1 may be electrically connected to the lower conductive layer BML through a contact hole passing through the interlayer insulating layer ILD and the buffer layer BFL. The second transistor electrode TE2 may be electrically connected to the second region of the semiconductor pattern SCP through a contact hole passing through the interlayer insulating layer ILD. According to an embodiment, any one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0106] The third power conductive layer PL2c can be arranged to overlap with the first power conductive layer PL2a and / or the second power conductive layer PL2b in a third direction (Z-axis direction). The third power conductive layer PL2c can be electrically connected to the first power conductive layer PL2a and / or the second power conductive layer PL2b. For example, the third power conductive layer PL2c can be electrically connected to the first power conductive layer PL2a through a contact hole passing through the interlayer insulating layer ILD and the buffer layer BFL. The third power conductive layer PL2c can be electrically connected to the second power conductive layer PL2b through a contact hole passing through the interlayer insulating layer ILD. The third power conductive layer PL2c can be constructed together with the first power conductive layer PL2a and / or the second power conductive layer PL2b. Figure 2 The second power line PL2 described in the above description.

[0107] The first transistor electrode TE1 and the second transistor electrode TE2 and the third power conductive layer PL2c can be formed as a single layer or a multilayer formed of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn) and their oxides or alloys.

[0108] The protective layer PSV may be disposed on the first transistor electrode TE1 and the second transistor electrode TE2 and the third power conductive layer PL2c. The protective layer PSV may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x) various types of inorganic materials.

[0109] The via layer VIA may be disposed on the protective layer PSV. The via layer VIA may be formed of an organic material to flatten the step difference below. For example, the via layer VIA may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB). However, the disclosure is not limited thereto, and the via layer VIA may include an organic material including silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ) various types of inorganic materials.

[0110] The display element layer DPL may be disposed on the via layer VIA. The second alignment electrode ELB may be disposed on the via layer VIA. The second alignment electrodes ELB may be spaced apart from each other. The second alignment electrodes ELB may be disposed on the same layer. For example, the second alignment electrodes ELB may be formed simultaneously in the same process, but are not limited thereto.

[0111] The second alignment electrode ELB may receive a second alignment signal in the direction alignment step of the light emitting element LD. Therefore, an electric field may be formed between the second alignment electrodes ELB, and thus the light emitting element LD provided to each of the sub-pixels SPX may be bias-aligned between the second alignment electrodes ELB.

[0112] The second alignment electrode ELB may include at least one conductive material. For example, the second alignment electrode ELB may include at least one metal among various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo) or copper (Cu), including alloys thereof), conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO) or gallium tin oxide (GTO)) and conductive polymers (such as PEDOT) at least one conductive material, but is not limited thereto.

[0113] The bank pattern BNP may be disposed on the second alignment electrode ELB. The bank pattern BNP may be used to form a step difference so that the light emitting element LD is easily aligned. Each of the bank patterns BNP may be disposed under at least one first alignment electrode ELA. Since the bank pattern BNP is disposed under one region of each of the first alignment electrodes ELA, one region of each of the first alignment electrodes ELA may protrude in an upper direction, for example, in a third direction (Z-axis direction) of the sub-pixel SPX. In the case where the bank pattern BNP and / or the first alignment electrode ELA include a reflective material, a reflective wall structure may be formed around the light emitting element LD. Therefore, since the light emitted from the light emitting element LD may be emitted in an upper direction of the sub-pixel SPX (for example, a front surface direction of the display panel PNL including a viewing angle range), the light output efficiency of the display panel PNL may be improved. However, the position of the bank pattern BNP is not limited thereto and may be changed differently, such as under the second alignment electrode ELB or on the first alignment electrode ELA.

[0114] The bank pattern BNP may include at least one organic material and / or inorganic material. For example, the bank pattern BNP may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the disclosure is not limited thereto, and the bank pattern BNP may include an organic material including silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ) various types of inorganic materials.

[0115] The first insulating layer INS1 may be disposed on the bank pattern BNP. The first insulating layer INS1 may be configured as a single layer or a multi-layer, and may include a layer including silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ) various types of inorganic materials.

[0116] The first alignment electrodes ELA may be disposed on the bank pattern BNP and the first insulating layer INS1. The first alignment electrodes ELA may be spaced apart from each other. The first alignment electrodes ELA may be disposed on the same layer. For example, the first alignment electrodes ELA may be simultaneously formed in the same process, but are not limited thereto.

[0117] The first alignment electrode ELA may at least partially cover the side surface and / or the upper surface of the dyke pattern BNP. The first alignment electrode ELA may have a shape corresponding to the dyke pattern BNP. For example, the first alignment electrode ELA may include an inclined surface or a curved surface having a shape corresponding to the shape of the dyke pattern BNP. In this case, since the dyke pattern BNP and the first alignment electrode ELA can reflect the light emitted from the light emitting element LD as a reflective member to guide the light in the front surface direction of the sub-pixel SPX (for example, in the third direction (Z-axis direction)), the light output efficiency of the display panel PNL can be improved.

[0118] The first alignment electrode ELA may receive a first alignment signal in the position alignment step of the light emitting element LD. Therefore, an electric field may be formed between the first alignment electrodes ELA, and thus the light emitting element LD provided to each of the sub-pixels SPX may be aligned in the space between the first alignment electrodes ELA.

[0119] The first alignment electrode ELA may include at least one conductive material. For example, the first alignment electrode ELA may include at least one metal among various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo) and copper (Cu), alloys containing them), conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO) or gallium tin oxide (GTO)) and conductive polymers (such as PEDOT) at least one conductive material, but is not limited thereto.

[0120] The second insulating layer INS2 may be disposed on the first alignment electrode ELA. The second insulating layer INS2 may be configured as a single layer or a multi-layer, and may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x) or titanium oxide (TiO x ) various types of inorganic materials.

[0121] The light emitting element LD may be disposed on the second insulating layer INS2. The light emitting element LD may be disposed between the bank patterns BNP.

[0122] The light emitting element LD may be prepared in a dispersed form in the light emitting element ink, and may be supplied to each of the sub-pixels SPX by an inkjet printing method, etc. For example, the light emitting element LD may be dispersed in a volatile solvent and supplied to each of the sub-pixels SPX. Subsequently, when a first alignment signal is supplied to the first alignment electrodes ELA, an electric field may be formed between the first alignment electrodes ELA, and thus the light emitting element LD may be first aligned in the space between the first alignment electrodes ELA.

[0123] Subsequently, when a second alignment signal is supplied to the second alignment electrode ELB, an electric field may be formed between the second alignment electrodes ELB, and thus the light emitting element LD may be secondarily aligned between the second alignment electrodes ELB. For example, the first end EP1 of the light emitting element LD may face the first sub-alignment electrode ELB1. The second end EP2 of the light emitting element LD may face the second sub-alignment electrode ELB2. The side portion SP between the first end EP1 and the second end EP2 of the light emitting element LD may face the first alignment electrode ELA. As described above, since the position and direction of the light emitting element LD may be precisely controlled by aligning the position of the light emitting element LD by using the first alignment electrode ELA and aligning the direction of the light emitting element LD by using the second alignment electrode ELB, the alignment degree of the light emitting element LD may be improved. Refer to the following. Figures 16 to 21 Describe its detailed description.

[0124] The third insulating layer INS3 may be disposed on the light emitting element LD. For example, the second insulating layer INS2 may be partially disposed on the light emitting element LD and may expose the first end EP1 and the second end EP2 of the light emitting element LD. When the third insulating layer INS3 is formed on the light emitting element LD after the alignment of the light emitting element LD is completed, the light emitting element LD may be prevented from being separated from the aligned position.

[0125] The third insulating layer INS3 may be configured as a single layer or multiple layers, and may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x) or titanium oxide (TiO x ) various types of inorganic materials.

[0126] The connection electrode CNE may be disposed on the first end EP1 and the second end EP2 of the light emitting element LD exposed by the third insulating layer INS3. The first connection electrode CNE1 may be directly disposed on the first end EP1 of the light emitting element LD to contact the first end EP1 of the light emitting element LD. The second connection electrode CNE2 may be directly disposed on the second end EP2 of the light emitting element LD to contact the second end EP2 of the light emitting element LD.

[0127] In an embodiment, the connection electrode CNE may be formed of a conductive layer. Figure 6 As shown in FIG. 1 , the first connection electrode CNE1 and the second connection electrode CNE2 may be formed of different conductive layers, and a fourth insulating layer INS4 may be formed between the first connection electrode CNE1 and the second connection electrode CNE2 .

[0128] As described above, when the fourth insulating layer INS4 is disposed between the connection electrodes CNE formed of different conductive layers, since the connection electrodes CNE can be stably separated by the fourth insulating layer INS4, electrical stability between the first end EP1 and the second end EP2 of the light emitting element LD can be ensured.

[0129] The fourth insulating layer INS4 may be configured as a single layer or multiple layers, and may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ) various types of inorganic materials.

[0130] In another embodiment, the connection electrode CNE may be formed by the same conductive layer. Figure 7 As shown in , the first connection electrode CNE1 and the second connection electrode CNE2 may be formed of the same conductive layer. For example, the first connection electrode CNE1 and the second connection electrode CNE2 may be simultaneously formed in the same process. As described above, in the case where the first connection electrode CNE1 and the second connection electrode CNE2 are simultaneously formed, the number of masks may be reduced and the manufacturing process may be simplified.

[0131] The connection electrode CNE may be formed of various transparent conductive materials. For example, the connection electrode CNE may include at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), and gallium tin oxide (GTO), and may be implemented as transparent or translucent to satisfy transmittance. Therefore, light emitted from both ends EP1 and EP2 of the light emitting element LD may pass through the connection electrode CNE and may be emitted to the outside of the display panel PNL.

[0132] Hereinafter, another embodiment is described. In the following embodiment, the same configuration as that already described is denoted by the same reference numerals, and the repeated contents are omitted or the description is brief.

[0133] Fig. 9 is a schematic plan view showing a sub-pixel according to an embodiment. Fig.10 It is along Fig. 9 A schematic cross-sectional view taken along line CC'. Fig.11 It is along Fig. 9 A schematic cross-sectional view taken along line D-D'.

[0134] Reference Figures 9 to 11 , the first alignment electrode ELA may be disposed on the via layer VIA. The bank pattern BNP and the first insulating layer INS1 may be disposed on the first alignment electrode ELA.

[0135] The second alignment electrode ELB may be disposed on the embankment pattern BNP and the first insulating layer INS1. The second alignment electrode ELB may at least partially cover the side surface and / or the upper surface of the embankment pattern BNP. The second alignment electrode ELB may have a shape corresponding to the embankment pattern BNP. For example, the second alignment electrode ELB may include an inclined surface or a curved surface having a shape corresponding to the shape of the embankment pattern BNP. In this case, since the embankment pattern BNP and the second alignment electrode ELB may reflect light emitted from the light emitting element LD as a reflective member to guide the light in the front surface direction of the sub-pixel SPX (e.g., the third direction (Z-axis direction)), the light output efficiency of the display panel PNL may be improved.

[0136] The second insulating layer INS2 may be disposed on the second alignment electrode ELB. In an embodiment, the first connection electrode CNE1 may overlap the first sub-alignment electrode ELB1 and may be electrically connected to the first sub-alignment electrode ELB1 through a contact hole. The second connection electrode CNE2 may overlap the second sub-alignment electrode ELB2 and may be electrically connected to the second sub-alignment electrode ELB2 through a contact hole. The first connection electrode CNE1 may electrically connect the light emitting element LD and the first sub-alignment electrode ELB1, and the second connection electrode CNE2 may electrically connect the light emitting element LD and the second sub-alignment electrode ELB2. In this case, the first sub-alignment electrode ELB1 may be connected to the pixel circuit PXC and / or the first power line PL1 through a contact hole, and the second sub-alignment electrode ELB2 may be connected to the second power line PL2 through a contact hole, but the disclosure is not limited thereto.

[0137] According to an embodiment, the first connection electrode CNE1 may be electrically connected to the first sub-alignment electrode ELB1 through the first bridge electrode, and the second connection electrode CNE2 may be electrically connected to the second sub-alignment electrode ELB2 through the second bridge electrode.

[0138] Fig.12 and Fig.13 2 is a schematic cross-sectional view showing a pixel unit according to an embodiment. For ease of description, the respective configurations of the pixel circuit layer PCL and the display element layer DPL are briefly described in Fig.12 and Fig.13 middle.

[0139] Reference Fig.12 , the light emitting element LD disposed in each of the sub-pixels SPX1, SPX2, and SPX3 may emit light of the same color. For example, the sub-pixels SPX1, SPX2, and SPX3 may include a light emitting element LD that emits light of a third color (e.g., blue light). The color conversion layer CCL and / or the color filter layer CFL may be disposed in the sub-pixels SPX1, SPX2, and SPX3 to display a full-color image. However, the disclosure is not limited thereto, and the sub-pixels SPX1, SPX2, and SPX3 may include light emitting elements LD that emit light of different colors.

[0140] like Fig.12 As shown in , the color conversion layer CCL and the display element layer DPL may be disposed on the same layer. For example, the color conversion layer CCL may be disposed between the banks BNK.

[0141] The bank BNK may be located in the non-emission area NEA of the sub-pixels SPX1, SPX2, and SPX3. The bank BNK may be formed between the sub-pixels SPX1, SPX2, and SPX3 to surround each emission area EMA. The bank BNK may include an opening overlapping the emission area EMA of each of the sub-pixels SPX1, SPX2, and SPX3. The bank BNK may serve as a dam structure that prevents a solution for forming the color conversion layer CCL from flowing into the emission area EMA of adjacent sub-pixels SPX1, SPX2, and SPX3 and / or controls a constant amount of solution to be supplied to each emission area EMA.

[0142] The bank BNK may include an organic material or an inorganic material, and according to an embodiment, the bank BNK may include a black matrix material (or a light shielding material).

[0143] The color conversion layer CCL may include a first color conversion layer WCP1, a second color conversion layer WCP2, a light transmitting layer LTP, and a first capping layer CAP1.

[0144] The first color conversion layer WCP1 may be disposed to overlap with the emission area EMA of the first sub-pixel SPX1. The second color conversion layer WCP2 may be disposed to overlap with the emission area EMA of the second sub-pixel SPX2. The light transmission layer LTP may be disposed to overlap with the emission area EMA of the third sub-pixel SPX3. Each of the first color conversion layer WCP1, the second color conversion layer WCP2, and the light transmission layer LTP may be disposed in an opening of the bank BNK overlapping with the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0145] In an embodiment, the first color conversion layer WCP1 may include first color conversion particles that convert light of a third color emitted from the light emitting element LD into light of a first color. For example, when the light emitting element LD is a blue light emitting element that emits blue light and the first sub-pixel SPX1 is a red pixel, the first color conversion layer WCP1 may include first quantum dots that convert blue light emitted from the blue light emitting element into red light.

[0146] For example, the first color conversion layer WCP1 may include first quantum dots dispersed in a matrix material such as a matrix resin. The first quantum dots may absorb blue light and shift the wavelength according to energy transition to emit red light. In the case where the first sub-pixel SPX1 is a pixel of another color, the first color conversion layer WCP1 may include first quantum dots corresponding to the color of the first sub-pixel SPX1.

[0147] In an embodiment, the second color conversion layer WCP2 may include second color conversion particles that convert light of a third color emitted from the light emitting element LD into light of a second color. For example, when the light emitting element LD is a blue light emitting element that emits blue light and the second sub-pixel SPX2 is a green pixel, the second color conversion layer WCP2 may include second quantum dots that convert blue light emitted from the blue light emitting element into green light.

[0148] For example, the second color conversion layer WCP2 may include second quantum dots dispersed in a matrix material such as a base resin. The second quantum dots may absorb blue light and shift the wavelength according to energy transition to emit green light.

[0149] The first quantum dot and the second quantum dot may have nanoparticles, nanotubes, nanowires, nanofibers, nanoplates, etc. in the shape of spheres, pyramids, multi-arms or cubes, but are not limited thereto, and the shapes of the first quantum dot and the second quantum dot may be variously changed.

[0150] In an embodiment, the absorption coefficient of the first quantum dot and the second quantum dot can be increased by causing blue light having a relatively short wavelength in the visible light region to be incident on the first quantum dot and the second quantum dot. Therefore, the efficiency of light emitted from the first sub-pixel SPX1 and the second sub-pixel SPX2 can be improved, and excellent color reproducibility can be ensured. By constructing the sub-pixel SPX using a light-emitting element LD of the same color (e.g., a blue light-emitting element), the manufacturing efficiency of the display device can be improved.

[0151] In an embodiment, the light transmission layer LTP may be configured to effectively utilize the light of the third color emitted from the light emitting element LD. For example, when the light emitting element LD is a blue light emitting element emitting blue light and the third sub-pixel SPX3 is a blue pixel, the light transmission layer LTP may include at least one type of light scattering particles to effectively utilize the light emitted from the light emitting element LD.

[0152] For example, the light transmission layer LTP may include light scattering particles dispersed in a matrix material such as a matrix resin. For example, the light transmission layer LTP may include light scattering particles such as silicon dioxide, but the construction material of the light scattering particles is not limited thereto. According to an embodiment, the light scattering particles may also be included in the first color conversion layer WCP1 and / or the second color conversion layer WCP2.

[0153] The first cap layer CAP1 may seal (or cover) the first color conversion layer WCP1, the second color conversion layer WCP2, and the light transmission layer LTP. The first cap layer CAP1 may be disposed between the low refractive layer LRL and the display element layer DPL. The first cap layer CAP1 may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3. The first cap layer CAP1 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color conversion layer CCL.

[0154] In an embodiment, the first capping layer CAP1 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x ) and is constructed as a single layer or multiple layers, but is not limited to this.

[0155] The optical layer OPL may include a low refractive layer LRL and a second cover layer CAP2. The optical layer OPL may be disposed on the color conversion layer CCL. The optical layer OPL may be disposed on the display element layer DPL.

[0156] The low refractive layer LRL may be disposed between the color conversion layer CCL and the color filter layer CFL. The low refractive layer LRL may be disposed between the first capping layer CAP1 and the second capping layer CAP2. The low refractive layer LRL may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3.

[0157] The low refraction layer LRL may serve to improve light efficiency by recycling light provided from the color conversion layer CCL through total reflection. To this end, the low refraction layer LRL may have a refractive index relatively lower than that of the color conversion layer CCL.

[0158] In an embodiment, the low refractive layer LRL may include a matrix resin and hollow particles dispersed in the matrix resin. The hollow particles may include hollow silica particles. As another example, the hollow particles may be pores formed by a porogen, but are not limited thereto. The low refractive layer LRL may include zinc oxide (ZnO) particles, titanium dioxide (TiO 2 ) particles and nano-silicate particles, but not limited thereto.

[0159] The second cap layer CAP2 may be disposed on the low refractive layer LRL. The second cap layer CAP2 may be disposed between the color filter layer CFL and the low refractive layer LRL. The second cap layer CAP2 may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3. The second cap layer CAP2 may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the low refractive layer LRL. The second cap layer CAP2 and the first cap layer CPA1 may include the same material, or the second cap layer CAP2 may include one or more materials selected from the materials that may be used to form the first cap layer CPA1 (e.g., as discussed herein). For example, the second cap layer CAP2 may be formed by including silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x ) and is constructed as a single layer or multiple layers, but is not limited to this.

[0160] The color filter layer CFL may be disposed on the second capping layer CAP2. The color filter layer CFL may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3. The color filter layer CFL may include color filters CF1, CF2, and CF3, a planarization layer PLA, and an overcoat layer OC.

[0161] In an embodiment, color filters CF1, CF2, and CF3 may be disposed on the second capping layer CAP2. The color filters CF1, CF2, and CF3 may overlap the emission areas EMA of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, respectively.

[0162] The first color filter CF1 may transmit light of the first color, and may not transmit light of the second color and light of the third color. The second color filter CF2 may transmit light of the second color, and may not transmit light of the first color and light of the third color. The third color filter CF3 may transmit light of the third color, and may not transmit light of the first color and light of the second color.

[0163] In an embodiment, a planarization layer PLA may be disposed on the color filters CF1, CF2, and CF3. The planarization layer PLA may cover the color filters CF1, CF2, and CF3 (or overlap the color filters CF1, CF2, and CF3). The planarization layer PLA may planarize the step difference generated by the color filters CF1, CF2, and CF3. The planarization layer PLA may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3.

[0164] The planarization layer PLA may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the disclosure is not limited thereto, and the planarization layer PLA may include an organic material including silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) or titanium oxide (TiO x ) various types of inorganic materials.

[0165] The overcoat layer OC may be disposed on the planarization layer PLA. The overcoat layer OC may be disposed between the upper film layer UFL and the planarization layer PLA. The overcoat layer OC may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3. The overcoat layer OC may cover the lower component including the color filter layer CFL. The overcoat layer OC may prevent moisture or air from penetrating into the above-mentioned lower component. The overcoat layer OC may protect the above-mentioned lower component from foreign substances such as dust.

[0166] The overcoat layer OC may include an organic material or an inorganic material. For example, the overcoat layer OC may include one or more materials selected from materials that may be used to form a planarization layer PLA (eg, as discussed herein).

[0167] The upper film layer UFL may be disposed on the color filter layer CFL. The upper film layer UFL may be disposed outside the display device to reduce external influences on the display device. The upper film layer UFL may be disposed throughout the sub-pixels SPX1, SPX2, and SPX3.

[0168] In an embodiment, the upper film layer UFL may include an AR coating layer (anti-reflective coating). The AR coating layer may refer to a structure in which a material having an anti-reflective function is applied to one surface of a specific structure. Here, the applied material may have a low reflectivity. For example, the material for the AR coating layer may include silicon oxide (SiO x ), aluminum oxide (AlO x ) and titanium oxide (TiO x ), but not limited to these.

[0169] In another embodiment, if Fig.13As shown in , the color conversion layer CCL may be disposed on the display element layer DPL. For example, the first cap layer CAP1 may seal (or cover) a region in which the light emitting element LD is disposed, and the color conversion layer CCL may be disposed on the first cap layer CAP1.

[0170] In an embodiment, the color conversion layer CCL may further include a light blocking layer LBL (or a light blocking pattern). The light blocking layer LBL may be disposed on the display element layer DPL. The light blocking layer LBL may be disposed between the first cover layer CAP1 and the second cover layer CAP2. The light blocking layer LBL may be disposed to surround the first color conversion layer WCP1, the second color conversion layer WCP2, and the light transmission layer LTP at the boundaries between the sub-pixels SPX1, SPX2, and SPX3.

[0171] The light blocking layer LBL may overlap the non-emission area NEA. The light blocking layer LBL may surround the emission area EMA of the sub-pixels SPX1, SPX2, and SPX3. The light blocking layer LBL may be formed of an organic material including at least any one of graphite, carbon black, a black pigment, and a black dye, or may be formed of a metal material including chromium (Cr), but is not limited as long as the light blocking layer LBL is a material that can block and absorb light.

[0172] The second cover layer CAP2 may seal (or cover) the first color conversion layer WCP1 , the second color conversion layer WCP2 , and the light transmission layer LTP.

[0173] The low refractive layer LRL may be disposed between the second capping layer CAP2 and the third capping layer CAP3. The third capping layer CAP3 may include the same material as the first capping layer CPA1, or may include one or more materials selected from materials that may be used to form the first capping layer CPA1 (eg, as discussed herein).

[0174] Fig.14 is a schematic perspective view showing a light emitting element according to an embodiment. Fig.15 is a schematic cross-sectional view showing a light emitting element according to the embodiment. Fig.14 and Fig.15 A columnar light emitting element LD is shown, but the type and / or shape of the light emitting element LD is not limited thereto.

[0175] Reference Fig.14 and Fig.15 , the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, in the case where the extension direction of the light emitting element LD is the length L direction, the light emitting element LD may include the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 sequentially stacked along the length L direction.

[0176] The light emitting element LD may be provided in a column shape extending in one direction. The light emitting element LD may have a first end EP1 and a second end EP2. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the first end EP1 of the light emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the second end EP2 of the light emitting element LD.

[0177] According to the embodiment, the light emitting element LD may be a light emitting element manufactured into a columnar shape by an etching method or the like. In the present specification, the columnar shape includes a rod-like shape or a strip-like shape (such as a cylinder or a polygonal column) that is long in the length L direction (for example, the aspect ratio is greater than 1), and the shape of its cross section is not particularly limited. For example, the length L of the light emitting element LD may be greater than the diameter D (or the width of the cross section).

[0178] The light emitting element LD may have a size as small as nanometer to micrometer. For example, each light emitting element LD may have a diameter D (or width) and / or a length L ranging from nanometer to micrometer. However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be changed differently according to the design conditions of various devices (e.g., display devices) that use a light emitting device using the light emitting element LD as a light source.

[0179] The first semiconductor layer 11 may be a semiconductor layer of the first conductivity type. For example, the first semiconductor layer 11 may include an n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and may include an n-type semiconductor layer doped with a first conductivity type dopant such as Si, Ge, and Sn. However, the material constituting the first semiconductor layer 11 is not limited thereto, and various other materials may constitute the first semiconductor layer 11.

[0180] The active layer 12 may be disposed on the first semiconductor layer 11 and may be formed in a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 may be variously changed according to the type of the light emitting element LD.

[0181] A cladding layer (not shown) doped with a conductive dopant may be formed on the active layer 12 and / or below the active layer 12. For example, the cladding layer may be formed of AlGaN or InAlGaN. According to embodiments, materials such as AlGaN, InAlGaN, etc. may be used to form the active layer 12, and various other materials may construct the active layer 12.

[0182] The second semiconductor layer 13 may be disposed on the active layer 12, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include a p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive type dopant such as Mg. However, the material configuring the second semiconductor layer 13 is not limited thereto, and various other materials may configure the second semiconductor layer 13.

[0183] When a voltage equal to or greater than the threshold voltage is applied to both ends of the light emitting element LD, electron-hole pairs are recombined in the active layer 12, so the light emitting element LD emits light. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source for various light emitting devices including pixels of a display device.

[0184] The light emitting element LD may further include an insulating film INF disposed on the surface. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer circumferential surface of the active layer 12 and may also surround one region of the first semiconductor layer 11 and the second semiconductor layer 13 .

[0185] According to an embodiment, the insulating film INF may expose ends (e.g., both ends) of the light emitting element LD having different polarities. For example, the insulating film INF may expose ends of each of the first semiconductor layer 11 and the second semiconductor layer 13 positioned at the first end EP1 and the second end EP2 of the light emitting element LD. In another embodiment, the insulating film INF may expose side portions of the first semiconductor layer 11 and the second semiconductor layer 13 adjacent to the first end EP1 and the second end EP2 of the light emitting element LD having different polarities.

[0186] According to an embodiment, the insulating film INF may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x ) and can be constructed as a single layer or multiple layers (for example, made of aluminum oxide (AlO x ) and silicon oxide (SiO x ) formed of a double layer), but is not limited thereto. According to an embodiment, the insulating film INF may be omitted.

[0187] When the insulating film INF is provided to cover the surface of the light emitting element LD (particularly the outer circumferential surface of the active layer 12), short circuit between the active layer 12 and electrodes described below can be prevented. Therefore, the electrical stability of the light emitting element LD can be ensured.

[0188] When the insulating film INF is provided on the surface of the light emitting element LD, surface defects of the light emitting element LD can be minimized, thereby improving life and efficiency. In addition, even when the light emitting elements LD are provided in close contact with each other, undesirable short circuits between the light emitting elements LD can be prevented.

[0189] In an embodiment, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and / or the insulating film INF surrounding them, the light emitting element LD may further include additional components. For example, the light emitting element LD may further include at least one phosphor layer, an active layer, a semiconductor layer and / or an electrode layer disposed on one end side of the first semiconductor layer 11 and / or the second semiconductor layer 13. For example, a contact electrode layer may be disposed at each of the first end EP1 and the second end EP2 of the light emitting element LD. Although in Fig.15 , a columnar light emitting element LD is shown as an example, but the type, structure, shape, etc. of the light emitting element LD may be variously changed. For example, the light emitting element LD may be formed as a core-shell structure having a polygonal cone shape.

[0190] The light emitting device including the above-mentioned light emitting element LD can be used for various types of devices (including display devices) that require a light source. For example, the light emitting element LD can be provided in each sub-pixel SPX of the above-mentioned display panel PNL, and the light emitting element LD can be used as a light source for each sub-pixel SPX. However, the application field of the light emitting element LD is not limited to the above-mentioned example. For example, the light emitting element LD can also be used for other types of devices (such as lighting devices) that require a light source.

[0191] Subsequently, a method of manufacturing the display device according to the above-described embodiment is described.

[0192] Figures 16 to 21 is a schematic plan view of each process step of a method for manufacturing a display device according to an embodiment. Figures 16 to 21 Schematically shows the Figure 4 The planar structure of the first alignment line ELA1 (or the first electrode) and the second alignment line ELA2 (or the second electrode) of the first alignment electrode ELA and the first sub-alignment electrode ELB1 (or the third electrode) and the second sub-alignment electrode ELB2 (or the fourth electrode). Figures 1 to 15 Substantially the same components are denoted by the same reference numerals, and the detailed reference numerals are omitted.

[0193] Reference Fig.16 , forming a first alignment electrode ELA and a second alignment electrode ELB that intersect each other. The first alignment electrodes ELA may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The second alignment electrodes ELB may extend in the first direction (X-axis direction) and may be spaced apart from each other in the second direction (Y-axis direction). Figures 6 to 8 As described above, the first alignment electrode ELA may be formed on the second alignment electrode ELB. As another example, as shown in FIG. Fig.10 and Fig.11 As described, the second alignment electrode ELB may be formed on the first alignment electrode ELA.

[0194] Reference Fig.17 , and then, the light emitting element LD is provided. The light emitting element LD may be prepared in a dispersed form in the light emitting element ink, and may be supplied by an inkjet printing method, etc. For example, the light emitting element LD may be dispersed in a volatile solvent and provided.

[0195] Reference Fig.18 , so that the position of the light emitting element LD is aligned for the first time. The first alignment signal can be applied to the first alignment electrode ELA to align the position of the light emitting element LD. When the first alignment signal is applied to the first alignment electrode ELA, an electric field Ea can be formed between the first alignment electrodes ELA, so that the light emitting element LD can move to the space between the first alignment electrodes ELA.

[0196] Reference Fig.19 , and then, the direction of the light emitting element LD is secondarily aligned. The second alignment signal may be applied to the second alignment electrode ELB to align the direction of the light emitting element LD. In the case where the second alignment signal is applied to the second alignment electrode ELB, an electric field Eb may be formed between the second alignment electrodes ELB, and thus the light emitting element LD may be biasedly aligned. The light emitting element LD may be biasedly aligned so that the first end EP1 faces the first sub-alignment electrode ELB1, the second end EP2 faces the second sub-alignment electrode ELB2, and the side SP between the first end EP1 and the second end EP2 faces the first alignment electrode ELA. In an embodiment, the frequency of the second alignment signal and the frequency of the first alignment signal may be different from each other, but are not limited thereto.

[0197] According to an embodiment, Fig. 20 As shown in , the first alignment signal can be applied to the first alignment electrode ELA in the process of second-aligning the light-emitting element LD. Therefore, the light-emitting element LD can be aligned in a biased manner while maintaining the position of the light-emitting element LD aligned for the first time. In this case, the first alignment signal can be applied to the first alignment electrode ELA by adjusting the intensity of the first alignment signal.

[0198] Reference Fig.21 , so that the position and direction of the light emitting element LD are aligned three times. The first alignment signal may be applied to the first alignment electrode ELA, and the second alignment signal may be applied to the second alignment electrode ELB to stably maintain the position and direction of the light emitting element LD. In this case, the first alignment signal and the second alignment signal may be applied, and then the application of the first alignment signal and the second alignment signal may be stopped at a constant time interval by adjusting the intensity of the first alignment signal and the second alignment signal. According to an embodiment, the third alignment step may be omitted, and the first alignment step or the second alignment step may be repeated depending on the degree of alignment of the light emitting element LD. Subsequently, the light emitting element LD may be stably arranged by volatilizing the solvent or removing the solvent in another way.

[0199] Subsequently, the display device can be completed by forming a connection electrode CNE and the like on the light emitting element LD. Figure 4 and Figure 5 As described above, each of the connection electrodes CNE may be electrically connected to at least one of the first alignment electrodes ELA. Fig. 9 As described, each of the connection electrodes CNE may be electrically connected to at least one of the second alignment electrodes ELB.

[0200] According to the above embodiment, since the position and direction of the light emitting element LD can be accurately controlled by aligning the position of the light emitting element LD using the first alignment electrode ELA and aligning the direction of the light emitting element LD using the second alignment electrode ELB, the alignment degree of the light emitting element LD can be improved.

[0201] The above description is an example of the disclosed technical features, and the technicians in the field of the disclosure will be able to make various modifications and changes. Therefore, the embodiments disclosed in the disclosure are not intended to limit the disclosed technical spirit, but to describe the disclosed technical spirit, and the scope of the disclosed technical spirit is not limited by these embodiments. The disclosed protection scope should be interpreted by the claims, and should be interpreted as all technical spirits within the equivalent scope are included in the disclosed scope.

Claims

1. A display device, comprising: a first electrode and a second electrode, spaced apart from each other; a third electrode and a fourth electrode crossing the first electrode and the second electrode and spaced apart from each other; as well as a light emitting element disposed between the first electrode and the second electrode, wherein a first end of each of the light emitting elements faces the third electrode, and A second end of each of the light emitting elements faces the fourth electrode.

2. The display device according to claim 1, wherein: The first electrode and the second electrode are spaced apart from each other in a first direction and extend in a second direction, and The third electrode and the fourth electrode are spaced apart from each other in the second direction and extend in the first direction.

3. The display device according to claim 2, wherein: The light emitting elements are arranged in the second direction.

4. The display device according to claim 1, wherein: The first electrode and the second electrode are disposed on the third electrode and the fourth electrode.

5. The display device according to claim 4, further comprising: An insulating layer is between the first electrode, the second electrode, and the third electrode and the fourth electrode.

6. The display device according to claim 4, further comprising: a first connection electrode in electrical contact with the first end of each of the light emitting elements; as well as A second connection electrode is electrically connected to the second end of each of the light emitting elements.

7. The display device according to claim 6, wherein: The first connecting electrode is electrically connected to the first electrode, and The second connection electrode is electrically connected to the second electrode.

8. The display device according to claim 1, wherein: The third electrode and the fourth electrode are disposed on the first electrode and the second electrode.

9. The display device according to claim 8, wherein: The light emitting element is electrically connected to the third electrode and the fourth electrode.

10. The display device according to claim 1, wherein: A side portion of each of the light emitting elements between the first end and the second end faces the first electrode and the second electrode.

11. A method for manufacturing a display device, the method comprising: aligning the light emitting element for the first time between the first alignment electrodes by applying a first alignment signal to the first alignment electrodes; as well as The light emitting element is secondarily aligned by applying a second alignment signal to a second alignment electrode intersecting the first alignment electrode, wherein the second alignment electrodes extend in the first direction and are spaced apart from each other in the second direction, and The light emitting elements are aligned in the second direction in the secondary alignment of the light emitting elements.

12. The method according to claim 11, wherein: The frequency of the first alignment signal is different from the frequency of the second alignment signal.

13. The method according to claim 11, wherein: The second alignment electrode includes a first sub-alignment electrode and a second sub-alignment electrode spaced apart from each other in the second direction, A first end of each of the light emitting elements faces the first sub-alignment electrode, and A second end of each of the light emitting elements faces the second sub-alignment electrode.

14. The method according to claim 13, wherein: The first sub-alignment electrodes and the second sub-alignment electrodes are alternately arranged in the second direction.

15. The method according to claim 13, wherein: A side portion of each of the light emitting elements between the first end and the second end faces the first alignment electrode.

16. The method according to claim 11, further comprising: A connection electrode is formed on the light emitting element.

17. The method according to claim 16, wherein: The connection electrode is electrically connected to the first alignment electrode.

18. The method according to claim 17, wherein: The first alignment electrode is formed on the second alignment electrode.

19. The method according to claim 16, wherein: The connection electrode is electrically connected to the second alignment electrode.

20. The method according to claim 19, wherein: The second alignment electrode is formed on the first alignment electrode.

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