Reference clock frequency correction by mixing with digitally controlled low frequency compensation signal

Abstract

A system for reference clock frequency correction is described. The system includes a compensation module configured to (i) receive an oscillator signal and one or more control signals as inputs, (ii) generate a compensation signal based on the oscillator signal and the one or more control signals, where the generated compensation signal is a discretized sinusoidal signal having a controllable frequency, and (ii) generate a compensation signal based on the one or more control signals. And (iii) outputting the generated compensation signal. The system also includes a mixer block configured to (i) receive the generated compensation signal and the oscillator signal as inputs, and (ii) generate an output clock signal by mixing the generated compensation signal with the oscillator signal. A soft handover method that reduces the effects of quantization noise is also described.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 330,542, filed on April 13, 2022, entitled “Reference Clock Frequency Correction By Mixing With Digitally-Controlled Low-Frequency Compensation Signal,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure herein relates to clocks in electrical systems. Background Art

[0004] Modern electrical and electronic systems often contain timing devices that allow them to: (1) synchronize their external operation with other devices and the rest of the world, and (2) synchronize their internal operation between different subsystems or sub-blocks within the same system. For this timekeeping and synchronization purpose, very accurate clock signal sources such as quartz crystal oscillators, microelectromechanical systems (MEMS) oscillators, or bulk acoustic wave (BAW) oscillators are most often used.

[0005] However, all of these clock signal sources have small deviations from their exact target operating frequency, which are called frequency offsets.

[0006] Frequency offsets can arise from many sources, including manufacturing defects, temperature drift, device aging, and physical stress. These small frequency shifts can cause errors in system synchronization over sufficient time due to phase error accumulation. Therefore, in situations where the system clock frequency needs to be very accurate, a form of clock signal frequency compensation is usually required to correct for these effects. Summary of the invention

[0007] A common example of clock signal frequency compensation can be found in temperature compensated crystal oscillator (TCXO) systems. The quartz crystals used in these systems typically have low dynamic impedance, which means that loading them with another electrically controllable impedance can significantly change (pull) their resonant frequency. Typically, within a TCXO system, a temperature sensing element is responsible for monitoring the temperature, and the crystal loading is adjusted accordingly to compensate.

[0008] In general, the TCXO feedback loop is used to cancel temperature-dependent frequency drift, thereby producing a stable TCXO frequency over a specific temperature range.

[0009] However, when the frequency shift range becomes too wide for the feedback loop to handle (e.g., 100ppm or more), this method for frequency compensation becomes difficult to handle. In MEMS oscillators, due to the manufacturing tolerances and significantly larger frequency temperature coefficients of silicon compared to quartz, the range of frequency shifts can be as high as several thousand ppm. In addition, for the resonators with high dynamic impedance used in most MEMS oscillators, the above-mentioned electrical feedback loop is impossible. This is because for very high dynamic impedance, the electrical load has a negligible effect on the resonant frequency. In contrast, the existing methods for frequency compensation in oscillators with high dynamic impedance resonators or wide range of frequency shifts (or both) involve using a phase-locked loop (PLL) to correct the frequency shift before the source clock oscillator signal is distributed to the system. The PLL contains an internal voltage-controlled oscillator (VCO) for creating another clock signal at a different (usually much higher) frequency. Then, the new signal is "phase-locked" to the source clock oscillator signal to synchronize the signal and reduce the VCO phase noise. By modifying the ratio between the source clock oscillator frequency and the frequency of the PLL VCO, the frequency shift in the source clock oscillator signal can be easily corrected.

[0010] PLL is practical in systems where the required operating frequency is very high (e.g., in the GHz range). For example, if low noise operation is required, the PLL VCO almost inevitably must be designed as an LC oscillating loop (where L is the inductance and C is the capacitance value), and since the actual inductance and capacitance values ​​are very low in integrated technology, the LC oscillating loop VCO resonant frequency is usually in the GHz range by default. However, also due to the limitations of very large scale integration (VLSI) technology, the quality factor (Q factor) of this integrated LC oscillating loop is very low compared to typical source clock oscillators such as quartz crystals and MEMS oscillators. The lower Q factor of the LC oscillating loop leads to higher noise of the newly created signal, making it necessary to invest additional power in the PLL to achieve the required phase noise performance. Therefore, it is power inefficient to use a PLL in a system where a source clock oscillator signal in the kHz or MHz range needs to be corrected, and therefore eliminating the need for a PLL in such a system will be beneficial. Eliminating the PLL will allow the exclusive use of a high Q factor source clock oscillator signal without generating a new signal from a lower Q factor VCO. It will also eliminate the need to generate any power-consuming GHz-range signals, which will further improve power efficiency.

[0011] Accordingly, the present disclosure is directed to alternative systems and methods that help solve these and other problems.

[0012] The system in one embodiment includes a compensation module for generating and controlling a low frequency compensation signal and a mixer for mixing an oscillator clock with the compensation signal to provide reference frequency correction.

[0013] In yet another embodiment, a system receives an oscillator signal from a MEMS resonator.

[0014] The method in one embodiment uses a passive mixer to implement the mixing function.

[0015] The method in another embodiment includes a soft switching technique in the compensation module (after the digital decoder) to produce a more accurate low frequency sinusoidal shape of the compensation signal and thus reduce the impact of quantization noise on system performance.

[0016] The method in yet another embodiment mixes the compensation signal with the oscillator signal using passive mixers arranged in a quadrature mixing topology.

[0017] A method in yet another embodiment uses a digitally controlled variable gain amplifier (VGA) as a passive mixer to achieve quadrature mixing.

[0018] In yet another embodiment, a method uses a switched capacitor front end with variable impedance to control the gain of a mixer VGA.

[0019] In yet another embodiment, a method uses a digital counter in a compensation module.

[0020] In yet another embodiment, a method uses an integer N value fed into a counter to control a compensation signal frequency.

[0021] In yet another embodiment, a method sets the compensation signal frequency equal to f osc / N, where f osc is the frequency of the oscillator clock signal.

[0022] In yet another embodiment, a method uses a digital decoder in a compensation module.A digital decoder herein is any digital module for generating a sinusoidal low frequency signal waveform based on an input signal given thereto.

[0023] In yet another embodiment, a method includes a digital-to-analog converter (DAC) at an output of a compensation module.

[0024] In yet another embodiment, a method includes an active mixer for implementing a quadrature mixing function.

[0025] In yet another embodiment, a method includes a digital frequency divider with or in place of a counter and / or a digital look-up table and / or a memory block with or in place of a digital decoder in a compensation module.

[0026] In one embodiment, a system provides a clock signal at the output of a mixer as its final corrected reference clock output signal.

[0027] In another embodiment, a system includes a post divider at an output for use when the output reference clock frequency is significantly less than an oscillator frequency.

[0028] Other aspects and embodiments of the present disclosure will become apparent from the following detailed description, which, when taken in conjunction with the accompanying drawings, illustrates, by way of example, the principles of the present disclosure.

[0029] BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of an example reference clock frequency compensation system is depicted.

[0031] Figure 2 An example reference clock frequency compensation system is depicted in which a compensation signal having a digital amplitude is provided to a passive mixer.

[0032] Figure 3 An example reference clock frequency compensation system is depicted in which a compensation signal having an analog amplitude is provided to an active mixer.

[0033] Figure 4 The quantized discrete-time compensation signal is depicted.

[0034] Figure 5 A schematic diagram of an example low frequency quadrature mixer is depicted.

[0035] Figure 6 An example of a VGA-based passive mixer implementation is depicted.

[0036] Figure 7 A schematic diagram depicting an example soft handoff concept.

[0037] Figure 8 Waveform diagram depicting the concept of soft switching.

[0038] Fig. 9 Depicted is a system in which a set of VGAs are used as quadrature passive mixers.

[0039] Detailed Description

[0040] The following disclosure refers to the accompanying drawings and several example embodiments. It should be understood by those skilled in the art that such references are for illustrative purposes only and are therefore not meant to be limiting. Part or all of the disclosed systems, devices, and methods may be rearranged, combined, added, and / or removed in various ways, and various ways are contemplated herein.

[0041] The present disclosure provides an example method and system for generating a reference clock signal by mixing an oscillator clock signal with a low-frequency compensation signal. In such an example, the frequency of the reference clock signal can be adjusted relative to the oscillator clock frequency by controlling the frequency and shape of the compensation signal. The compensation signal is generated from the oscillator clock signal itself, which allows the entire system to always use a high-Q factor oscillator clock signal and eliminates the need for a PLL containing a low-Q factor VCO. As a result, power savings are achieved because no additional power needs to be consumed to improve the signal-to-noise ratio of the low-Q factor VCO or to process signals in the GHz frequency range that are typically required in an integrated VCO. As a result, according to the present disclosure, frequency offsets of the oscillator clock signal caused by manufacturing defects, process offsets, and temperature drift can all be corrected in terms of lower power and lower noise.

[0042] In the example system, the system is designed considering a specific oscillator so that the target reference frequency matches the oscillator frequency. Therefore, the only difference between the two frequencies is due to manufacturing defects and the temperature instability of the oscillator. Therefore, the frequency error that needs to be compensated is very small compared to the frequency of the input signal (i.e., the oscillator clock signal) or the frequency of the output signal (i.e., the target reference clock signal). In this case, frequency compensation can be achieved by generating a low-frequency error signal (usually described as a ppm ratio relative to the target reference signal frequency), and then mixing the low-frequency error signal with the oscillator clock signal to perform compensation. As used herein, the low-frequency error signal is also referred to as a "compensation signal". The compensation signal is generated by a compensation module.

[0043] In conventional radio frequency (RF) designs, the mixing signal (which is called a carrier in RF) has a very high frequency (e.g., GHz range) and is also typically the highest frequency signal in the system. In such a case, where the mixing signal has a frequency much higher than the operating frequency of every other device in the system, any operation performed on the signal is extremely expensive in terms of overall system power. However, in the new method described herein, the situation is the opposite. The compensation signal herein plays a similar role to the RF carrier by acting as a mixing signal, which is at an extremely low frequency compared to the operating frequency of other devices in the system. Therefore, any manipulation performed on the mixing signal will be performed at a very small cost in terms of overall system power. Therefore, the method for generating the compensation signal can be very different from conventional RF circuits.

[0044] In another aspect, the present disclosure relates to mixer design. Mixer nonlinearity is one of the main bottlenecks in mixer design. In active mixers, the available voltage margin and nonlinear characteristics of the transistors limit the achievable linearity of the mixer. In switching-based passive mixers, nonlinearity is introduced by the nonlinear nature of the switching rather than the nonlinearity of the transistors themselves, because the switching essentially multiplies the signal with a square wave containing odd harmonics. In many recent RF applications, passive mixers are chosen for simplicity and device linearity, while the harmonic problem is solved by implementing multiphase mixing. In such an implementation, multiple phases of the mixing signal are required, which very quickly becomes power inefficient when the mixing signal itself is at high (e.g., GHz range) frequencies.

[0045] In the present disclosure, since the frequency of the compensation signal is low relative to the power consumption of the rest of the system, it is not power expensive to generate a large number of phases and perform multiphase mixing. In addition, the compensation signal can be generated by dividing the oscillator clock signal frequency by N (or counting to N) so that N phases are inherently available. For example, if the oscillator clock signal frequency is to be corrected by 100 ppm (i.e., 10 2 / 10 6 The ratio between the oscillator clock signal frequency and the compensation signal frequency is the inverse of this ratio, which is equal to N = 10 6 / 10 2 =10 4 . Thus, in this example, 10,000 phases of the mixing (compensation) signal are readily available, and for smaller ppm numbers (higher accuracy), N can be made larger at negligible power cost. For comparison, conventional RF mixers typically use only 4, 8, and in some cases 16 phases. For example, 8-phase mixers are commonly used because they allow the 3rd and 5th harmonics of a square wave to be cancelled. However, when the mixing signal operates at high (e.g., GHz range) frequencies, even such a low number of phases can represent a significant power optimization and performance challenge in RF applications.

[0046] For polyphase mixing, generating the desired output of the mixer amounts to multiplying the input signal by an effective sine function that is discrete in amplitude (quantized) and also discrete in time with a step size of T. s =T com p / N, where N is the ratio between the oscillator clock signal frequency and the compensation signal frequency, and T com p is the period of the compensation signal. Therefore, there are two discretization errors, one in amplitude and one in time (or phase). Since N is also equal to the number of available phases (i.e., available time resolution), nonlinearity can be pushed below the phase noise floor if N is large enough and there is a large enough number of amplitude quantization levels.

[0047] In another aspect, the present disclosure relates to generation and digital control of an extremely low frequency sinusoidal compensation signal. In one embodiment, the system includes a compensation module for generating and controlling the low frequency compensation signal and a quadrature mixer for mixing an oscillator clock signal with the compensation signal, thereby producing a corrected frequency of a reference clock signal at an output.

[0048] Figure 1 The schematic diagram of the reference clock frequency compensation system according to the exemplary embodiment of the present disclosure is explained. As shown in the figure, the system includes a compensation module 100 and a mixer block 102. The oscillator clock signal is provided to both the compensation module 100 and the mixer block 102. Based on one or more input control signals, the compensation module 100 generates a digital or analog low-frequency compensation signal. The frequency of the compensation signal must be programmable so that it reflects the value of the actual frequency offset or frequency shift that needs to be corrected as accurately as possible. Whether the compensation signal is digital or analog in amplitude depends on the type of mixer used, that is, the digital output amplitude is used with a passive mixer, and the analog output amplitude is used with an active mixer. In either case, since the compensation signal is generated digitally, the amplitude level is discrete, meaning that the compensation signal amplitude (AQ) has a limited number of quantization levels. The compensation signal generated by the compensation module 100 is output and fed to the mixer block 102 to perform frequency correction of the reference clock signal.

[0049] like Figure 1 As further shown in FIG. 1 , in some example embodiments, the system may further include a post divider 104 configured to divide the output signal of the mixer block 102. This may be useful in examples where the oscillator clock signal frequency to be compensated is much higher than the expected output (reference clock signal) frequency.

[0050] Figure 2 Explained Figure 1 An example embodiment of a reference clock frequency compensation system is depicted in FIG. Figure 2The embodiment depicted in generates a digital discrete time compensation signal using a digital counter 202 and a digital decoder 204 in the compensation module 100. The compensation signal AQ-cos(27ik / N) is a digital number that is used to directly control a switching-based passive mixer 206. In this embodiment, the frequency of the sinusoidal compensation signal is controlled by a digital number N, which is used as an input control signal to the digital counter 202. The digital decoder 204 generates a sine or cosine waveform as a function of k / N, where k is the output of the digital counter 202. The digital decoder 204 can calculate the sine function directly, or use a memory block or a lookup table to perform the function. As used throughout this disclosure, the term "sine" refers to any signal shaped to resemble a sine wave or a phase shift thereof. For example, a sinusoidal signal may take the form of a sine wave, a cosine wave, or a phase shifted sine or cosine wave. Such sinusoidal signals may be analog signals, or they may be discretized versions of analog signals, as described below in conjunction with Figure 4 described in further detail.

[0051] Figure 3 Explained Figure 1 Another example embodiment of a reference clock frequency compensation system is depicted in FIG. Figure 2 In a similar way, Figure 3 The embodiment depicted in FIG. 1 generates a digital discrete time compensation signal using a digital counter 202 and a digital decoder 204 in the compensation module 100. However, in this embodiment, the compensation signal is then fed through a digital-to-analog converter (DAC) 308, thereby converting the digital compensation signal into an analog compensation signal suitable for use with an active mixer 306. As a result, the amplitude A of the compensation signal is Q is an analog value, and this value is used to control the active mixer 306. In this embodiment, the frequency of the sinusoidal compensation signal is again controlled by the digital number N, which is used as the input control signal of the digital counter 202. The digital decoder 204 generates a sinusoidal waveform as a function of k / N, where k is the output of the digital counter 202. The digital decoder 204 can calculate the sinusoidal function directly, or use a memory block or a lookup table to perform this function.

[0052] Figure 4 The digitally generated compensation signal waveform output from the digital decoder 204 is illustrated. The compensation signal is digitally synthesized to simulate an ideal sine wave or cosine wave with a quantized discrete-time sine signal. Since the oscillator clock signal is used as the "sampling clock" of the digital decoder 204, the time step Ts is equal to l / f osc , where f oscis the oscillator clock frequency. When the compensation signal frequency is low compared to the oscillator clock signal frequency (e.g., up to several thousand ppm), the compensation signal frequency can be generated with sufficiently high accuracy by dividing the frequency of the oscillator clock signal by an integer N, so T comp = l / f comp =N / f osc =N*Ts, where f comp is the frequency of the compensation signal. Since the frequency offset of the oscillator clock signal is usually very small compared to the oscillator clock signal frequency, the condition that N is a large number is satisfied by default. Therefore, either a counter or a divider can be used for this purpose. In a counter-based implementation, one method of generating the amplitude of the sinusoidal signal is to track the counter value k and generate the amplitude of the sinusoidal signal based on the ratio k / N using the digital decoder 204 at each cycle of the oscillator clock signal Ts. Due to the k / N ratio (k / N=k*Ts / T comp , k=[0, N]) can be explicitly mapped to the phase of a sinusoidal signal, so the required amplitude can be directly calculated by the digital decoder 204, or extracted from a lookup table for each k from 0 to N. The number of amplitude quantization levels can be selected based on the desired phase noise performance of the final reference clock signal.

[0053] Figure 5 Explained Figure 1 Another example embodiment of a mixer 102 in a reference clock frequency compensation system is depicted in FIG. Figure 5 In the embodiment depicted in FIG. 1 , the mixer 102 uses an orthogonal mixer to achieve mixing of the oscillator clock signal and the low-frequency compensation signal. The high-frequency oscillator clock signal and the low-frequency compensation signal are mixed to generate a high-frequency oscillator clock signal f osc The two sideband images of the frequency and f osc The offset compensation signal f comp To remove one of the images, two mixers are used for quadrature mixing; in one mixer, the frequency is f osc The oscillator clock signal is related to f comp The compensation signal tone (in-phase component) is mixed, and in the second mixer, the oscillator clock signal is mixed with f comp The compensating signal tone (quadrature component) is mixed with the offset 90° offset signal tone (quadrature component). The proper recombination of the two mixer outputs, where the quadrature output is offset 90 degrees and added or subtracted from the in-phase output, removes one of the images. As a result, only the desired tone remains in the final reference clock signal (output). Therefore, the reference clock signal f ref The frequency is equal to the compensation signal frequency f comp Corrected f osc . Because f ref =f osc ±fcomp , by controlling f comp The value of f can be added with an exact correction to offset osc any deviations in the

[0054] Figure 6 Explained Figure 1 Another example embodiment of the mixer 102 of the reference clock frequency compensation system is depicted in FIG. Figure 6 In the embodiment depicted in , mixer 102 is implemented as a passive mixer. In some examples, a digitally controlled variable gain amplifier (VGA) with an M-bit digital input b can be used as a passive mixer. Figure 6 The passive mixer depicted in FIG. 1 includes a front-end bank and a summing amplifier. Each unit in the front-end bank consists of a differential switch pair and a unit capacitor C unit In this embodiment, capacitors can provide better performance than resistors due to their better scaling, matching, and low noise characteristics. The VGA gain is defined as the ratio of the feedback impedance to the front-end impedance. The feedback impedance is fixed at Z FB , while the front-end differential admittance can be digitally controlled at -M co C unit / 2 and +M a >C unit / 2, where co is the angular frequency of the input signal. Therefore, the gain of the proposed amplifier can be changed by scaling its input impedance based on the input digital code. For each digital bit b[Ml:0], there is a switch cp in each unit of the front-end group connected to the positive or negative input (V IN+ or V IN- ), and its complementary switch ip is connected to the opposite input. This differential structure allows both negative and positive gain by simple bit twisting. In this particular example, thermometric encoding is used so that M bits produce (M+l) quantization levels. However, any other encoding (such as binary, grayscale, etc.) can be used without loss of generality or functionality.

[0055] Figure 7 An example embodiment of a soft switching technique is illustrated, which the compensation module 100 can use to reduce the amplitude quantization error in the generation of a sinusoidal compensation signal for mixing. cnt ) changes in a step-like manner, the compensation signal will also change in a similar step-like manner, which is referred to as "hard switching" in this article. Soft switching technology can be used to slow down V cnt This is accomplished by adjusting the edge rate in the oscillator so that the transition from the lowest impedance to the highest impedance occurs gradually within one cycle of the oscillator clock signal. As a result, the compensation signal will better approximate an ideal sinusoidal signal, a technique referred to herein as "soft switching."

[0056] Figure 8 The resulting soft switching waveform is illustrated. If the switching is gradual rather than abrupt, this results in a piecewise linear approximation of an ideal sinusoidal signal, rather than a staircase approximation as in the hard switching case.

[0057] Fig. 9 Explained Figure 1 Another example embodiment of a reference clock frequency compensation system is depicted in FIG. Fig. 9 In the embodiment depicted in , two digitally controlled VGAs are used as intrinsic (I) and quadrature (Q) mixers. Sine digital decoder 902 and cosine digital decoder 904 are used to effectively shape the gain of the VGA into one all-digital counter 202 cycle (k=0 to N) to generate the sine and cosine functions respectively.

[0058] The outputs of the I and Q mixers are offset by 90° from each other and summed. Both the phase shifting and summing circuits are fairly common and depend on the specific topology, so the implementation details will not be discussed.

[0059] Example embodiments of the disclosed innovations have been described above. However, those skilled in the art will appreciate that changes and modifications may be made to the described embodiments without departing from the true scope and spirit of the invention, which will be defined by the claims. For example, while certain variations are discussed in conjunction with one or more examples of the present disclosure, these variations may also be applied to various other examples of the present disclosure.

Claims

1. A system comprising: a compensation module configured to (i) receive an oscillator signal and one or more control signals as input, (ii) generate a discretized sinusoidal signal having a controllable frequency based on the oscillator signal and the one or more control signals, (iii) determine a compensation signal based on the discretized sinusoidal signal, and (iv) output the compensation signal; as well as A mixer block is configured to (i) receive the compensation signal and the oscillator signal as inputs, and (ii) generate an output clock signal by mixing the compensation signal with the oscillator signal.

2. The system according to claim 1, characterized in that The compensation module is configured to receive the oscillator signal from a MEMS resonator.

3. The system according to claim 1, characterized in that The mixer block includes a passive mixer.

4. The system according to claim 3, characterized in that Determining the compensation signal based on the discretized sinusoidal signal includes using a soft switching technique to reduce amplitude quantization noise of the discretized sinusoidal signal.

5. The system according to claim 3, characterized in that The passive mixer is arranged in a quadrature mixing topology for mixing the compensation signal with the oscillator signal.

6. The system according to claim 5, characterized in that The passive mixer includes one or more digitally controlled variable gain amplifiers (VGAs) for mixing the compensation signal with the oscillator signal.

7. The system according to claim 6, characterized in that The one or more VGAs include a switched capacitor front end having a variable impedance, and wherein a gain of the one or more VGAs is controlled by the variable impedance of the switched capacitor front end.

8. The system of claim 1, wherein: The compensation module comprises a digital counter configured to receive the one or more control signals as input, wherein the one or more control signals represent an integer N, and wherein the digital counter is configured to generate a count signal for counting to the integer N at the frequency of the oscillator clock signal.

9. The system according to claim 8, characterized in that The controllable frequency of the discretized sinusoidal signal is based on the integer N.

10. The system according to claim 9, characterized in that The controllable frequency of the discretized sinusoidal signal is equal to f osc / N, where f osc is the frequency of the oscillator clock signal.

11. The system according to claim 8, characterized in that The compensation module also includes a digital decoder configured to (i) receive the count signal as input and (ii) generate the discretized sinusoidal signal based on the count signal.

12. The system according to claim 11, characterized in that The compensation module further includes a digital-to-analog converter (DAC), and wherein determining the compensation signal includes converting the discretized sinusoidal signal generated by the digital decoder into an analog signal having an analog amplitude through the DAC.

13. The system of claim 12, wherein: The mixer block includes active mixers arranged in a quadrature mixing topology for mixing the analog signal with the resonator clock signal.

14. The system of claim 8, wherein: The compensation module further includes a lookup table or memory block identifying a plurality of values ​​of a theoretical sinusoidal signal, and wherein generating the discretized sinusoidal signal includes mapping values ​​of the count signal to values ​​of the theoretical sinusoidal signal.

15. The system of claim 1, wherein: The compensation module comprises a digital divider configured to receive the one or more control signals as input, wherein the one or more control signals represent an integer N, and wherein generating the discretized sinusoidal signal comprises dividing the frequency of the oscillator signal by the integer N by the digital divider.

16. The system of claim 15, wherein: The compensation module also includes a lookup table or memory block identifying multiple values ​​of the theoretical sinusoidal signal, and wherein generating the discretized sinusoidal signal further includes, for each corresponding integer between 0 and N, mapping the corresponding integer to a corresponding value among the multiple values ​​of the theoretical sinusoidal signal.

17. The system of claim 1, wherein: The output clock signal comprises a corrected reference clock signal directly from the mixer output.

18. The system of claim 1, wherein: Also included is a post divider configured to divide the mixer output clock signal to generate a corrected reference clock signal.

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