Self-identification switching DIP type packaging device testing device

Abstract

The invention discloses a self-identification switching DIP type packaging device test device, which comprises a clamping test circuit, a control circuit, a DAC output circuit, an ADC sampling circuit and a channel selection circuit, and is characterized in that the clamping test circuit comprises an IC clamping seat J2, a gate pole connecting end, a drain electrode connecting end and a source electrode connecting end; the IC clamping seat is used for placing a chip to be detected, and the gate electrode connecting end, the drain electrode connecting end and the source electrode connecting end are respectively connected with a source meter. According to the DIP type packaging device testing device capable of automatically identifying and switching, the testing circuit can be automatically switched for G pole identification, the problem that manual identification is needed in the testing scheme is solved, and the whole testing process is lower in risk and higher in efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of DIP type package device testing, and in particular relates to a self-identifying and switching DIP type package device testing device. Background Art

[0002] Electrical performance testing is a key step in detecting the performance of electronic components. It tests the performance of components by testing some specific parameter indicators, thereby evaluating the performance of electrical equipment and electronic products. Electrical performance testing is an important means to ensure the reliability and stability of electrical equipment and electronic products. For example, in order to ensure the normal operation of MOSFET and meet the specification requirements, an effective method is to determine its characteristics by tracing its IV curve. By setting the source meter Vstart initial voltage and Vstep step voltage for step voltage input, and connecting the gate G or drain D of the device under test, measuring its leakage current electrical parameters, and verifying the device's voltage resistance characteristics and leakage current conditions, the quality of the device under test can be judged.

[0003] At present, due to the requirement of the number of tests in the reliability test standard and the chip design verification to reduce the cost, a Testkey (structure for testing integrated circuits) is placed in the scribe line or chip, and each Testkey may have two or more identical structure connections or each DIP package has two Testkeys with different Split structures connecting the pad and leading out the electrodes through the leads. During the IV electrical test, each test structure in the DIP package needs to be electrically tested to compare the electrical performance under different Splits and verify the reliability of the device. Since each Testkey in the DIP package has two identical structures ( Figure 1 ) or encapsulates two Testkeys ( Figure 2 ), and for the requirement of test quantity, the test structures need to be measured separately. When the wires are bonded on different Pads, the test fixture board needs to be replaced to perform the corresponding IV measurement of the front and rear test structures, and the DIP packaged device needs to be removed and installed on another fixture board, which greatly increases the test time. The plugging and unplugging of the line also makes the IV test subject to the risk of human operation errors, resulting in static breakdown of the device and line connection errors. Summary of the invention

[0004] The main purpose of the present invention is to provide a self-identifying and switching DIP type packaged device testing device, which can identify the G pole and automatically switch the test circuit, thereby solving the problem of the test scheme requiring manual identification, making the entire test process less risky and more efficient.

[0005] To achieve the above objectives, the present invention provides a self-identification switching DIP type package device testing device, comprising a clamping test circuit, a control circuit, a DAC output circuit, an ADC sampling circuit and a channel selection circuit, wherein:

[0006] The clamping test circuit includes an IC clamping seat J2, a gate connection terminal (T7 / T10), a drain connection terminal (T8 / T11) and a source connection terminal (T9 / T12), wherein the gate, drain and source connection terminals are source meter test ports, the IC clamping seat is used to place the chip to be tested, and the gate connection terminal, the drain connection terminal and the source connection terminal are respectively connected to the source meter;

[0007] The channel selection circuit includes a relay K1, a relay K2, a relay K3, a relay K4 and a relay K5, the control circuit includes a controller U2, the DAC output circuit includes a relay K6, the ADC sampling circuit includes a relay K7, and the drain connection end is electrically connected to the 2nd pin of the relay K4 through the resistor R24 ​​in one way and is electrically connected to the 1st pin of the relay K7 in the other way;

[0008] One of the source connection ends is electrically connected to pin 1 of the relay K3, pin 2 of the relay K3 is electrically connected to pin 1 of the IC clamp J2, and pin 3 of the relay K3 is electrically connected to pin 5 of the IC clamp J2; the other of the source connection ends is electrically connected to pin 2 of the relay K5;

[0009] One of the gate connection ends is electrically connected to pin 1 of the relay K1, pin 2 of the relay K1 is electrically connected to pin 28 of the IC clamp J2, and pin 3 of the relay K1 is electrically connected to pin 3 of the IC clamp J2; the other gate connection end is electrically connected to pin 1 of the relay K6.

[0010] As a further preferred technical solution of the above technical solution, the 4th pin of the relay K1 is electrically connected to the collector of the transistor Q1, and the base of the transistor Q1 is electrically connected to the 46th pin of the controller U2 through the resistor R1;

[0011] Pin 4 of the relay K2 is electrically connected to the collector of the transistor Q2, and the base of the transistor Q2 is electrically connected to pin 49 of the controller U2 through the resistor R4; pin 1 of the relay K2 is electrically connected to pin 26 of the IC clamping seat J2;

[0012] The 4-pin of the relay K3 is electrically connected to the collector of the transistor Q3, and the base of the transistor Q3 is electrically connected to the 50-pin of the controller U2 through the resistor R7;

[0013] The 4th pin of the relay K4 is electrically connected to the collector of the transistor Q6, and the base of the transistor Q6 is electrically connected to the 22nd pin of the controller U2 through the resistor R15;

[0014] Pin 4 of the relay K5 is electrically connected to the collector of the transistor Q7 , and the base of the transistor Q7 is electrically connected to pin 23 of the controller U2 via the resistor R18 .

[0015] As a further preferred technical solution of the above technical solution, the 4th pin of the relay K6 is electrically connected to the collector of the transistor Q8, and the base of the transistor Q8 is electrically connected to the 41st pin of the controller U2 through the resistor R21;

[0016] Pin 2 of the relay K6 is respectively connected to the emitter of transistor Q4 and the collector of transistor Q5 through resistor R14, the base of the transistor Q4 and the base of the transistor Q5 are both connected to the output end of the operational amplifier U3 through resistor R13, and the positive input end of the operational amplifier U3 is electrically connected to pin 20 of the controller U2.

[0017] As a further preferred technical solution of the above technical solution, one of the pins 2 of the relay K7 is grounded through a resistor R28 and the other is electrically connected to the pin 14 of the controller U2;

[0018] Pin 4 of the relay K7 is electrically connected to the collector of the transistor Q9 , and the base of the transistor Q9 is electrically connected to pin 42 of the controller U2 via the resistor R25 .

[0019] As a further preferred technical solution of the above technical solution, the relays K1-K3 are single-pole double-throw switches, which are used to select the path for the source meter to connect to the chip;

[0020] Relays K4-K7 are single-pole single-throw switches used for gate position detection.

[0021] As a further preferred technical solution of the above technical solution, when the test chip is inserted into the IC clamping seat J2, the test is carried out, and the test is specifically implemented as follows:

[0022] Step S1: gate position detection is performed, and relays K4-K7 are all closed through the control circuit, and relays K1-K3 are in the first position;

[0023] Step S2: The DAC output circuit works, and after voltage following and amplification, it is loaded to the Gate1 position (pin 28) of the IC clamping seat (DIP28) through relays K6 and K1;

[0024] Step S3: The ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct preset value (0.7V), it means that the initial position of the test chip inserted into the IC clamp is correct (that is, the gate position of the test chip is just inserted into the Gate1 position) and the gate detection of the test chip is qualified, then step S7 is executed. If the voltage collected by the ADC is greater than the fault threshold (2V+), it means that the current position of the test chip inserted into the IC clamp is incorrect (that is, the gate position of the test chip is not at the Gate1 position, but at the Gate2 position) or (when the gate position Gate1 is correct) the test chip is damaged, then step S4 is executed;

[0025] Step S4: The DAC output circuit is turned off by controlling the circuit, and the relays K1-K3 are switched to the second position;

[0026] Step S5: The DAC output circuit works, and after voltage following and amplification, it is loaded to the Gate2 position (pin 3) of the IC clamping seat (DIP28) through relays K6 and K1;

[0027] Step S6: The ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct threshold, it means that the gate position of the test chip is the Gate2 position and the gate detection of the test chip is qualified. Then, step S7 is continued. If the voltage collected by the ADC is still greater than the fault threshold, it indicates that the test chip is damaged.

[0028] Step S7: the DAC output circuit is turned off, relays K4-K7 are all disconnected, and the IV test procedure in the source meter is executed (ie, the IV test of the test chip is performed in the source meter).

[0029] As a further preferred technical solution of the above technical solution, when the relays K1-K3 are in the first position, the 1st and 2nd pins of the relay K1 are connected, the 1st and 2nd pins of the relay K2 are connected, and the 1st and 2nd pins of the relay K3 are connected; the Source2 (5th pin) and the Gate2 (3rd pin) of the IC clamp J2 (DIP28) are suspended, the Source1 (1st pin) and the B terminal (26th pin) are short-circuited and connected to the source connection terminal (T9, T12), the Drain (22nd pin) is connected to the drain connection terminal, and the Gate1 (28th pin) is connected to the gate connection terminal;

[0030] When relays K1-K3 are switched to the second position, pins 1 and 3 of relay K1 are connected, pins 1 and 3 of relay K2 are connected, and pins 1 and 3 of relay K3 are connected; Source1 and Gate1 of IC clamp J2 (DIP28) are suspended, Gate2 and B terminals are short-circuited and connected to the gate connection terminal, Drain is connected to the drain connection terminal, and Source2 is connected to the source connection terminal.

[0031] As a further preferred technical solution of the above technical solution, when the gate position of the test chip is aligned with Gate1 or Gate2 of the IC clamp J2 (DIP28), that is, the gate of the test chip is loaded with a turn-on voltage, the test chip will be turned on, and the drain of the test chip (connected to pin 22 of J2) will be pulled to a low level. The voltage collected by the ADC acquisition circuit is the junction voltage of the test chip, and the value is less than the correct preset value. When the collected voltage is greater than the fault threshold (2.3V), it means that the test chip is not turned on (damaged). BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic diagram of the device packaging of an existing Testkey.

[0033] Figure 2 This is a schematic diagram of the device packaging of two existing Testkeys.

[0034] Figure 3 It is a structural schematic diagram of the present invention.

[0035] Figure 4 It is the clamping test circuit diagram of the present invention.

[0036] Figure 5 It is a control circuit diagram of the present invention.

[0037] Figure 6 It is a DAC output circuit diagram of the present invention.

[0038] Figure 7 It is the ADC sampling circuit diagram of the present invention.

[0039] Figure 8 It is the channel selection circuit diagram of the present invention. DETAILED DESCRIPTION

[0040] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0041] The present invention discloses a self-identifying and switching DIP type package device testing device. The specific embodiments of the invention are further described below in conjunction with preferred embodiments.

[0042] In the embodiments of the present invention, those skilled in the art will note that the chip and source meter etc. involved in the present invention may be regarded as prior art.

[0043] Preferred embodiments.

[0044] like Figure 1-8 As shown, the present invention discloses a self-identification switching DIP type package device testing device, including a clamping test circuit, a control circuit, a DAC output circuit, an ADC sampling circuit and a channel selection circuit, wherein:

[0045] The clamping test circuit comprises an IC clamping seat J2, a gate connection terminal (T7 / T10), a drain connection terminal (T8 / T11) and a source connection terminal (T9 / T12), wherein the IC clamping seat is used to place the chip to be tested and the gate connection terminal, the drain connection terminal and the source connection terminal are respectively connected to a source meter (providing a test voltage and testing the leakage current of the chip);

[0046] The channel selection circuit includes a relay K1, a relay K2, a relay K3, a relay K4 and a relay K5, the control circuit includes a controller U2 (MCU), the DAC output circuit includes a relay K6, the ADC sampling circuit includes a relay K7, and the drain connection end is electrically connected to the 2nd pin of the relay K4 through the resistor R24 ​​in one way and is electrically connected to the 1st pin of the relay K7 in the other way;

[0047] One of the source connection ends is electrically connected to pin 1 of the relay K3, pin 2 of the relay K3 is electrically connected to pin 1 of the IC clamp J2, and pin 3 of the relay K3 is electrically connected to pin 5 of the IC clamp J2; the other of the source connection ends is electrically connected to pin 2 of the relay K5;

[0048] One of the gate connection ends is electrically connected to pin 1 of the relay K1, pin 2 of the relay K1 is electrically connected to pin 28 of the IC clamp J2, and pin 3 of the relay K1 is electrically connected to pin 3 of the IC clamp J2; the other gate connection end is electrically connected to pin 1 of the relay K6.

[0049] Specifically, the 4th pin of the relay K1 is electrically connected to the collector of the transistor Q1, and the base of the transistor Q1 is electrically connected to the 46th pin of the controller U2 through the resistor R1;

[0050] Pin 4 of the relay K2 is electrically connected to the collector of the transistor Q2, and the base of the transistor Q2 is electrically connected to pin 49 of the controller U2 through the resistor R4; pin 1 of the relay K2 is electrically connected to pin 26 of the IC clamping seat J2;

[0051] The 4-pin of the relay K3 is electrically connected to the collector of the transistor Q3, and the base of the transistor Q3 is electrically connected to the 50-pin of the controller U2 through the resistor R7;

[0052] The 4th pin of the relay K4 is electrically connected to the collector of the transistor Q6, and the base of the transistor Q6 is electrically connected to the 22nd pin of the controller U2 through the resistor R15;

[0053] Pin 4 of the relay K5 is electrically connected to the collector of the transistor Q7 , and the base of the transistor Q7 is electrically connected to pin 23 of the controller U2 via the resistor R18 .

[0054] More specifically, the 4th pin of the relay K6 is electrically connected to the collector of the transistor Q8, and the base of the transistor Q8 is electrically connected to the 41st pin of the controller U2 through the resistor R21;

[0055] Pin 2 of the relay K6 is respectively connected to the emitter of transistor Q4 and the collector of transistor Q5 through resistor R14, the base of the transistor Q4 and the base of the transistor Q5 are both connected to the output end of the operational amplifier U3 through resistor R13, and the positive input end of the operational amplifier U3 is electrically connected to pin 20 of the controller U2.

[0056] Furthermore, one path of the pin 2 of the relay K7 is grounded through the resistor R28 and the other path is electrically connected to the pin 14 of the controller U2;

[0057] Pin 4 of the relay K7 is electrically connected to the collector of the transistor Q9 , and the base of the transistor Q9 is electrically connected to pin 42 of the controller U2 via the resistor R25 .

[0058] Furthermore, relays K1-K3 are single-pole double-throw switches used to select the path through which the source meter is connected to the chip;

[0059] Relays K4-K7 are single-pole single-throw switches used for gate position detection.

[0060] Preferably, after the test chip is inserted into the IC clamping seat J2, the test is performed, and the test is specifically implemented by the following steps:

[0061] Step S1: gate position detection is performed, and relays K4-K7 are all closed through the control circuit, and relays K1-K3 are in the first position;

[0062] Step S2: The DAC output circuit works, and after voltage following and amplification, it is loaded to the Gate1 position (pin 28) of the IC clamping seat (DIP28) through relays K6 and K1;

[0063] Step S3: The ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct preset value (0.7V), it means that the initial position of the test chip inserted into the IC clamp is correct (that is, the gate position of the test chip is just inserted into the Gate1 position) and the gate detection of the test chip is qualified, then step S7 is executed. If the voltage collected by the ADC is greater than the fault threshold (2V+), it means that the current position of the test chip inserted into the IC clamp is incorrect (that is, the gate position of the test chip is not at the Gate1 position, but at the Gate2 position) or (when the gate position Gate1 is correct) the test chip is damaged, then step S4 is executed;

[0064] Step S4: The DAC output circuit is turned off by controlling the circuit, and the relays K1-K3 are switched to the second position;

[0065] Step S5: The DAC output circuit works, and after voltage following and amplification, it is loaded to the Gate2 position (pin 3) of the IC clamping seat (DIP28) through relays K6 and K1;

[0066] Step S6: The ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct threshold, it means that the gate position of the test chip is the Gate2 position and the gate detection of the test chip is qualified. Then, step S7 is continued. If the voltage collected by the ADC is still greater than the fault threshold, it indicates that the test chip is damaged.

[0067] Step S7: the DAC output circuit is turned off, relays K4-K7 are all disconnected, and the IV test procedure in the source meter is executed (ie, the IV test of the test chip is performed in the source meter).

[0068] Preferably, when the relays K1-K3 are in the first position, the pins 1 and 2 of the relay K1 are connected, the pins 1 and 2 of the relay K2 are connected, and the pins 1 and 2 of the relay K3 are connected; the Source2 (pin 5) and Gate2 (pin 3) of the IC clamp J2 (DIP28) are suspended, the Source1 (pin 1) and the B terminal (pin 26) are short-circuited and connected to the source connection terminals (T9, T12), the Drain (pin 22) is connected to the drain connection terminal, and the Gate1 (pin 28) is connected to the gate connection terminal;

[0069] When relays K1-K3 are switched to the second position, pins 1 and 3 of relay K1 are connected, pins 1 and 3 of relay K2 are connected, and pins 1 and 3 of relay K3 are connected; Source1 and Gate1 of IC clamp J2 (DIP28) are suspended, Gate2 and B terminals are short-circuited and connected to the gate connection terminal, Drain is connected to the drain connection terminal, and Source2 is connected to the source connection terminal.

[0070] Preferably, when the gate position of the test chip is aligned with Gate1 or Gate2 of the IC clamp J2 (DIP28), that is, the gate of the test chip is loaded with a turn-on voltage, the test chip will be turned on, and the drain of the test chip (connected to pin 22 of J2) will be pulled to a low level. The voltage collected by the ADC acquisition circuit is the junction voltage of the test chip, and the value is less than the correct preset value. When the collected voltage is greater than the fault threshold (2.3V), it means that the test chip is not turned on (damaged).

[0071] For the present invention:

[0072] Before the source meter loads the test voltage, the tooling (T7-T12) of the present invention first loads the conduction voltage to the pins where the G pole position may exist. When the gate voltage VGS is greater than VGS (th), the device under test will be in the conduction state. The detection of the drain voltage by ADC can determine whether the gate position of the IC is correct, thereby determining which Testkey structure chip the device belongs to. If the device under test does not detect conduction after the conduction voltage is loaded, a channel selection circuit is provided to switch the connection route of the tooling until it is confirmed that the device under test can detect conduction when the G pole VGS is greater than VGS (th). The tooling sends an indication signal indicating that the currently selected connection route is in line with the connection required by the current device under test, and finally the tester loads the test program by operating the source meter. The tooling using the G pole detection circuit and the automatic switching circuit greatly shortens the tediousness of testing two structures in the same package, and reduces the various risks caused by manually distinguishing chips. The IV electrical performance test of the two structures can be completed by automatic identification.

[0073] The present invention tests two chips with different gate packages. The Drain terminals of the two chips are at the same PIN pin. Two wires are drawn out from the drain connection terminal, one end of which is connected to a 5V high level through a relay K4, and the other end of which is connected to an ADC sampling circuit through a relay K7. The chip Source pin (source) has two position options, which are Source1 and Source2 marked on an IC clamp (DIP28). Two wires are drawn out from the source connection terminal, one of which is connected to two possible positions (Source1 and Source2) of Source in DIP28 through a relay K3, and the other end of which is connected to an MCU ground through a relay K5. The chip Gate terminal (gate) also has two position options, which are Gate1 and Gate2 marked on an IC clamp (DIP28). Two wires are drawn out from the gate connection terminal, one of which is connected to two possible positions (Source1 and Source2) of Gate in an IC clamp (DIP28) through a relay K1, and the last wire is connected to a DAC output circuit through a relay K6. Relays K1-K3 are single-pole double-throw switches, used to select the path for the source meter to connect to the chip. Relays K4-K7 are single-pole single-throw switches, used to detect the gate position.

[0074] It is worth mentioning that the technical features such as chips and source meters involved in the patent application of this invention should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional methods in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated.

[0075] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A self-identification switching DIP type package device testing device, characterized in that: It includes a clamping test circuit, a control circuit, a DAC output circuit, an ADC sampling circuit and a channel selection circuit, wherein: The clamping test circuit includes an IC clamping seat J2, a gate connection terminal, a drain connection terminal and a source connection terminal, wherein the IC clamping seat is used to place the chip to be tested and the gate connection terminal, the drain connection terminal and the source connection terminal are respectively connected to a source meter; The channel selection circuit includes a relay K1, a relay K2, a relay K3, a relay K4 and a relay K5, the control circuit includes a controller U2, the DAC output circuit includes a relay K6, the ADC sampling circuit includes a relay K7, and the drain connection end is electrically connected to the 2nd pin of the relay K4 through the resistor R24 ​​in one way and is electrically connected to the 1st pin of the relay K7 in the other way; One of the source connection ends is electrically connected to pin 1 of the relay K3, pin 2 of the relay K3 is electrically connected to pin 1 of the IC clamp J2, and pin 3 of the relay K3 is electrically connected to pin 5 of the IC clamp J2; the other of the source connection ends is electrically connected to pin 2 of the relay K5; One of the gate connection ends is electrically connected to pin 1 of the relay K1, pin 2 of the relay K1 is electrically connected to pin 28 of the IC clamp J2, and pin 3 of the relay K1 is electrically connected to pin 3 of the IC clamp J2; the other gate connection end is electrically connected to pin 1 of the relay K6.

2. A self-identifying and switching DIP type package device testing device according to claim 1, characterized in that: The 4th pin of the relay K1 is electrically connected to the collector of the transistor Q1, and the base of the transistor Q1 is electrically connected to the 46th pin of the controller U2 through the resistor R1; Pin 4 of the relay K2 is electrically connected to the collector of the transistor Q2, and the base of the transistor Q2 is electrically connected to pin 49 of the controller U2 through the resistor R4; pin 1 of the relay K2 is electrically connected to pin 26 of the IC clamping seat J2; The 4-pin of the relay K3 is electrically connected to the collector of the transistor Q3, and the base of the transistor Q3 is electrically connected to the 50-pin of the controller U2 through the resistor R7; The 4th pin of the relay K4 is electrically connected to the collector of the transistor Q6, and the base of the transistor Q6 is electrically connected to the 22nd pin of the controller U2 through the resistor R15; Pin 4 of the relay K5 is electrically connected to the collector of the transistor Q7 , and the base of the transistor Q7 is electrically connected to pin 23 of the controller U2 via the resistor R18 .

3. A self-identifying and switching DIP type package device testing device according to claim 2, characterized in that: The 4th pin of the relay K6 is electrically connected to the collector of the transistor Q8, and the base of the transistor Q8 is electrically connected to the 41st pin of the controller U2 through the resistor R21; Pin 2 of the relay K6 is respectively connected to the emitter of transistor Q4 and the collector of transistor Q5 through resistor R14, the base of the transistor Q4 and the base of the transistor Q5 are both connected to the output end of the operational amplifier U3 through resistor R13, and the positive input end of the operational amplifier U3 is electrically connected to pin 20 of the controller U2.

4. A self-identifying and switching DIP type package device testing device according to claim 3, characterized in that: One of the pins 2 of the relay K7 is grounded via a resistor R28 and the other is electrically connected to the pin 14 of the controller U2; Pin 4 of the relay K7 is electrically connected to the collector of the transistor Q9 , and the base of the transistor Q9 is electrically connected to pin 42 of the controller U2 via the resistor R25 .

5. A self-identification switching DIP type package device testing device according to claim 4, characterized in that: Relays K1-K3 are single-pole double-throw switches used to select the path for the source meter to connect to the chip; Relays K4-K7 are single-pole single-throw switches used for gate position detection.

6. A self-identification switching DIP type package device testing device according to claim 5, characterized in that: When the test chip is inserted into the IC clamp J2, the test is carried out. The test is specifically implemented as follows: Step S1: gate position detection is performed, and relays K4-K7 are all closed through the control circuit, and relays K1-K3 are in the first position; Step S2: The DAC output circuit works, and after voltage following and amplification, it is loaded to the Gate1 position of the IC clamping seat through relays K6 and K1; Step S3: the ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct preset value, it means that the initial position of the test chip inserted into the IC clamp is correct and the gate detection of the test chip is qualified, and then step S7 is executed. If the voltage collected by the ADC is greater than the fault threshold, it means that the current position of the test chip inserted into the IC clamp is incorrect or the test chip is damaged, and step S4 is executed; Step S4: The DAC output circuit is turned off by controlling the circuit, and the relays K1-K3 are switched to the second position; Step S5: The DAC output circuit works, and after voltage following and amplification, it is loaded to the Gate2 position of the IC clamping seat through relays K6 and K1; Step S6: The ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct threshold, it means that the gate position of the test chip is the Gate2 position and the gate detection of the test chip is qualified. Then, step S7 is continued. If the voltage collected by the ADC is still greater than the fault threshold, it indicates that the test chip is damaged. Step S7: The DAC output circuit is turned off, relays K4-K7 are all disconnected, and the IV test procedure on the source meter is executed.

7. A self-identifying switching DIP type packaged device testing device according to claim 6, when the relays K1-K3 are in the first position, the 1st and 2nd pins of the relay K1 are connected, the 1st and 2nd pins of the relay K2 are connected, and the 1st and 2nd pins of the relay K3 are connected; Source2 and Gate2 of the IC clamp J2 are suspended, Source1 and B terminals are short-circuited and connected to the source connection terminal, Drain is connected to the drain connection terminal, and Gate1 is connected to the gate connection terminal; When relays K1-K3 are switched to the second position, pins 1 and 3 of relay K1 are connected, pins 1 and 3 of relay K2 are connected, and pins 1 and 3 of relay K3 are connected; Source1 and Gate1 of IC clamp J2 are suspended, Gate2 and B are short-circuited and connected to the gate connection terminal, Drain is connected to the drain connection terminal, and Source2 is connected to the source connection terminal.

8. According to the self-identifying and switching DIP type packaged device testing device of claim 7, when the gate position of the test chip is aligned with Gate1 or Gate2 of the IC clamping seat J2, that is, the gate of the test chip is loaded with a turn-on voltage, the test chip will be turned on, and the drain of the test chip will be pulled to a low level. The voltage collected by the ADC acquisition circuit is the junction voltage of the test chip, and the value is less than the correct preset value. When the collected voltage is greater than the fault threshold, it means that the test chip is not turned on.

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