A low-ripple fast-response digital LDO circuit and control method

Abstract

The present invention relates to the field of integrated circuit technology, and in particular to a low-ripple, fast-response digital LDO circuit and control method. The circuit comprises: a clock-controlled comparator for real-time monitoring of the deviation between the feedback voltage VFB and the reference voltage VREF and outputting a comparison signal; a partial stability detection circuit comprising a counter and a sequence detector, both of which are digitally designed; the counter, based on the continuity of the comparison signal, emits a Cnt signal for detecting the continuity of the output signal; the sequence detector, based on the output mode of the output signal, emits a mode signal for evaluating whether the output signal has reached a preset target stable state; and a shift control circuit, based on the Cnt and mode signals provided by the partial stability detection circuit, dynamically controls and adjusts a PMOS switch array to achieve voltage regulation. The present invention can solve the ripple problem of traditional digital LDOs, ensuring fast response while improving the accuracy of the output voltage. It avoids the use of window comparators and multiple reference voltages, and eliminates errors caused by offsets between multiple comparators.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-ripple, fast-response digital LDO circuit and a control method. Background Art

[0002] Digital LDOs (DLDOs) have attracted significant attention due to their low-voltage operation and excellent process scalability. Compared to traditional analog LDOs (ALDOs), digital LDOs require a smaller power transistor area to handle the same load current and have fewer stability issues. However, despite their widespread use in high-efficiency power management systems for digital circuits, digital LDOs still suffer from issues such as steady-state ripple and low power supply rejection ratio.

[0003] Currently, two main technical solutions are used to address steady-state ripple and power supply rejection in digital LDOs. The first involves adding large capacitors to the output of traditional digital LDOs to effectively buffer voltage fluctuations caused by load variations, thereby reducing steady-state ripple. However, while this solution is effective, it comes with large space requirements, limited dynamic response, and potential stability issues. The second approach is to implement coarse- and fine-loop regulation in the digital LDO, using two sets of PMOS arrays of different sizes to achieve fast response and low ripple. However, this solution increases design complexity and power consumption and may affect system accuracy. Summary of the Invention

[0004] The purpose of the present invention is to address the above technical problems and propose a low-ripple, fast-response digital LDO circuit and control method, which can solve the ripple problem of traditional digital LDOs and improve the accuracy of the output voltage while ensuring fast response. The purpose of the present invention can be achieved through the following technical solutions:

[0005] The present invention provides a low-ripple fast-response digital LDO circuit, comprising: a clock-controlled comparator, a partial stability detection circuit, a shift-control switch circuit, and an asynchronous control loop;

[0006] A clock-controlled comparator for monitoring the deviation between the feedback voltage VFB and the reference voltage VREF in real time and outputting a comparison signal;

[0007] The partial stability detection circuit, including a counter and a sequence detector, is digitally designed. The counter generates a Cnt signal based on the continuity of the comparison signal to detect the continuity of the output signal. The sequence detector generates a mode signal based on the output mode of the output signal to evaluate whether the output signal has reached the preset target stable state.

[0008] The shift control circuit dynamically controls the coarse and fine loops and adjusts the PMOS switch array to achieve voltage regulation based on the Cnt and mode signals provided by the partial stability detection circuit and the internal carry signal FD. When the shift control circuit detects the carry signal FD, it switches from fine loop regulation to coarse loop regulation to speed up regulation.

[0009] The input end of the clock control comparator is respectively connected to the feedback voltage VFB and the reference voltage VREF, and the output end is respectively connected to the shift control circuit and the counter and sequence detector in the partial stability monitoring circuit for outputting a comparison signal; the shift control circuit is connected to the partial stability monitoring circuit and the clock control comparator, and determines whether the voltage state is stable according to the output mode signal and Cnt signal. When the voltage state has not reached the stable state, the small-size array of PMOS switches is used for fine-loop adjustment. When the small-size array of PMOS switches has completed adjustment but has not reached the stable state, the carry signal FD is triggered, and the coarse-loop adjustment of the output voltage is performed in combination with the large-size array of PMOS switches to quickly respond to changes in the feedback voltage VFB, and switch to fine-loop adjustment according to the mode signal to achieve a stable state.

[0010] The input of the asynchronous control loop is connected to the output voltage VOUT, and the output of the asynchronous control loop is connected to the shift controller. When the output voltage reaches a preset value, a large undershoot is detected and an asynchronous control signal AS_ctrl is output. The asynchronous control signal AS_ctrl directly sets the coarse-ring PMOS large-size array to half of the maximum adjustment range. The asynchronous control signal has no effect on the current state of the shift controller and is used to quickly provide high current.

[0011] Furthermore, the negative input terminal of the clock-controlled comparator is connected to the reference voltage VREF, and the positive input terminal is connected to the feedback voltage VFB; the output terminal is based on a comparison signal of the reference voltage VREF and the feedback voltage VFB, and the comparison signal is signal 0 or signal 1. Signal 0 means that the feedback voltage VFB is less than the reference voltage VREF, otherwise signal 1 is output; wherein, the feedback voltage VFB is the voltage obtained by the output voltage VOUT to the grounded voltage regulator.

[0012] Furthermore, a counter in the partial stability detection circuit receives a comparison signal from the clock-controlled comparator and monitors the consistency of the comparison signal within two consecutive clock cycles;

[0013] When the comparison signal is inconsistent within two consecutive clock cycles, the counter's count value is reset to 0; when the comparison signal is continuously consistent, the counter increases its count value; based on whether the count value exceeds the preset threshold, the corresponding Cnt signal is output, and the shift control circuit is quickly or slowly adjusted according to the Cnt signal.

[0014] Furthermore, the sequence detector in the partial stability detection circuit is used to analyze the comparison signal of the clock control comparator, determine whether the set sequence state is met according to the output sequence of the comparison signal, and output the corresponding mode signal to analyze the stability state of the circuit.

[0015] Furthermore, the shift control circuit includes a shift controller, a small-size array of PMOS switches, and a large-size array of PMOS switches; the input end of the shift controller is respectively connected to a counter, a sequence detector, and a clock-controlled comparator, for obtaining a current comparison signal, a Cnt signal, and a mode signal; the output end of the shift controller is connected to the PMOS switch array, wherein a coarse-loop adjustment control in the shift controller is connected to the large-size array of PMOS switches, and a fine-loop adjustment control is connected to the small-size array of PMOS switches; and when the small-size array of PMOS switches is adjusted, a carry signal FD is triggered, and the coarse-loop adjustment control is entered to perform coarse-loop adjustment until the mode signal enters a stable state, and then the fine-loop adjustment control is switched back to perform fine-loop adjustment.

[0016] Furthermore, the fine loop adjustment control includes a fine loop slow adjustment unit and a fine loop fast adjustment unit, which performs fast adjustment and slow adjustment according to the Cnt signal when the carry signal FD is not triggered or the coarse loop adjustment is switched to the fine loop adjustment; wherein,

[0017] When the Cnt signal does not reach the preset threshold, slow adjustment is performed, and the adjustment step of the small-size array of PMOS switches is reset to the minimum step size of 1 according to the comparison signal;

[0018] When the Cnt signal reaches a preset threshold, rapid adjustment is performed, and the adjustment step length of the small-size PMOS switch array is set to a fixed step length according to the comparison signal, and the fixed step length is a natural number greater than 1.

[0019] Furthermore, the coarse loop adjustment control includes a coarse loop slow adjustment unit and a coarse loop fast adjustment unit. When the carry signal FD is triggered, fast adjustment and slow adjustment are performed according to the Cnt signal.

[0020] When the Cnt signal does not reach the preset threshold, slow adjustment is performed, and the adjustment step size of the large-size PMOS switch array is reset to the minimum step size of 1 according to the comparison signal, and the step size of the small-size PMOS switch array is set to half of the total step size;

[0021] When the Cnt signal reaches the preset threshold, rapid adjustment is performed. The adjustment step size of the large-size PMOS switch array is set to a fixed step size according to the comparison signal, and the fixed step size is a natural number greater than 1; and the step size of the small-size PMOS switch array is set to half of the total step size.

[0022] Furthermore, two groups of feedforward auxiliary PMOS are included, and corresponding small-sized or large-sized feedforward auxiliary PMOS are used according to the fine loop adjustment unit or the coarse loop adjustment unit in the shift control circuit to prevent the oscillation mode from being too high to be detected by the sequence detector.

[0023] Furthermore, a load capacitor and a load resistor are included to smooth the output voltage VOUT and reduce high-frequency noise.

[0024] Based on the same inventive concept, the present invention provides a low-ripple, fast-response digital LDO circuit control method, which uses the fast-response digital LDO circuit described above for control. The method includes:

[0025] Step S1: obtaining a comparison signal of a clock-controlled comparator comparing a feedback voltage VFB and a reference voltage VREF, wherein the feedback voltage VFB is obtained by dividing the output voltage VOUT; a counter and a sequence detector in the partial stability detection circuit obtain corresponding Cnt signals and mode signals according to the comparison signal;

[0026] Step S2: Determine whether the mode signal output by the sequence detection is 1;

[0027] Step S3: When the mode signal is 1, the circuit is in a stable state; when the mode signal is 0, the shift control circuit performs fine loop adjustment, determines the adjustment speed and logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a small-sized feedforward auxiliary PMOS; wherein,

[0028] When the Cnt signal is 0, the counter value does not reach the preset threshold and slow adjustment is performed, resetting the adjustment step of the small-size PMOS switch array to the minimum step of 1; until the mode signal is 1 and reaches a stable state or the Cnt signal is 1 and enters the fast adjustment of the fine loop adjustment;

[0029] When the Cnt signal is 1, the counter value reaches the preset threshold value and is quickly adjusted. The adjustment step of the PMOS switch small-size array is set to a fixed step size, which is a natural number greater than 1 and the step size is the number of switches. When the Cnt signal is 0 and the fine-loop adjustment is slow, or when all switches in the PMOS switch small-size array are in the open state, the carry signal FD is triggered.

[0030] Step S3: The shift control circuit switches from fine loop regulation to coarse loop regulation according to the detected carry signal FD; the regulation speed and logic are determined according to the Cnt signal and the comparison signal, and steady-state oscillation is suppressed by a large-sized feedforward auxiliary PMOS; wherein,

[0031] When the Cnt signal is 0, the counter value does not reach the preset threshold and slow adjustment is performed, resetting the adjustment step of the large-size PMOS switch array to the minimum step of 1; and setting the number of switches in the small-size PMOS switch array to half of the total number; until the Cnt signal is 1 and enters the fast adjustment of the coarse loop adjustment or reaches the mode signal 1 to return to the fine loop adjustment, reaching a stable state.

[0032] When the Cnt signal is 1, the counter value reaches the preset threshold and is quickly adjusted. The adjustment step size of the small-size array of PMOS switches is set to a fixed step size, which is a natural number greater than 1, and the number of switches in the small-size array of PMOS switches is set to half of the total number; the adjustment is switched to slow adjustment of the coarse loop adjustment until the mode signal is 1 and returns to the fine loop adjustment to reach a stable state.

[0033] Step S4: During the adjustment process, the asynchronous control loop outputs an asynchronous control signal AS_ctrl according to the detected output voltage VOUT drop reaching a preset value, and directly sets the large-size array of PMOS switches to open half without affecting the state of the shift controller.

[0034] Compared with the prior art, the present invention has at least one of the following technical effects:

[0035] This invention solves the ripple problem of traditional digital LDOs while simultaneously improving output voltage accuracy while ensuring fast response. A sequence detector implemented via a digital circuit determines whether a stable state has been reached, switching from coarse-loop regulation to fine-loop regulation with lower ripple, achieving low-ripple output. A counter counts the number of identical comparator outputs, Comp_out, to determine the magnitude of load changes and adaptively adjust the step size of the corresponding loop shift control logic for fast response. This eliminates the need for window comparators and multiple reference voltages, simplifying design and eliminating errors caused by offsets between multiple comparators. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments:

[0037] Figure 1 A circuit diagram of a low-ripple, fast-response digital LDO circuit according to the present invention;

[0038] Figure 2 This is a flowchart of the steps of the fast response digital LDO circuit control method of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0040] Example 1

[0041] Digital LDOs (LDOs) play a key role in modern electronic devices, particularly in applications requiring precise voltage control. Compared to traditional analog LDOs (ALDOs), digital LDOs are favored due to their smaller power transistor area, better process scalability, and fewer stability issues when handling the same load current. However, a major challenge facing digital LDOs is their high steady-state ripple and relatively low power supply rejection ratio (PSRR), which limits their application in high-precision power management systems.

[0042] Traditional digital LDOs consist of a clocked comparator, a bidirectional shift register, and a PMOS switch array. The clocked comparator compares the output voltage (VOUT) with the reference voltage (VREF). The comparison result is then sent to the bidirectional shift register, which controls the shift direction and outputs a digital '0' or '1'. This adjusts the output voltage by turning one PMOS transistor in the array on or off at a time. The PMOS array consists of uniformly sized PMOS transistors that operate in the linear region when on and in the cutoff region when off.

[0043] In view of the limitations of existing technologies, there are currently two technical solutions to solve this problem:

[0044] The first solution is to add a large capacitor to the output of a traditional digital LDO to reduce ripple. While this method is simple and effective, it has significant drawbacks: the capacitor occupies a large area, requiring even more chip space if implemented internally. Furthermore, adding a large external capacitor may affect the user experience of the IP. Furthermore, the added output capacitor may shift the circuit's pole position, affecting stability.

[0045] The second approach is a low-ripple, fast-response digital LDO. Based on traditional digital LDOs, this approach typically adds coarse and fine-loop regulation modes, using two PMOS arrays of different sizes. The coarse loop uses large PMOS for fast response, while the fine loop uses small PMOS for low ripple. Mode switching is controlled by a voltage window detector consisting of two clocked comparators and an XOR gate. Coarse-loop regulation is performed when the output voltage VOUT is outside the voltage window, and fine-loop regulation is performed when it is within the window. While this approach improves performance and reduces ripple, it also increases design complexity and power consumption. In particular, the need for additional reference voltages and multiple comparators increases overall circuit cost and implementation difficulty. For example, the need for two additional clocked comparators increases power consumption, and the presence of different offset voltages between the clocked comparators reduces accuracy. Furthermore, two additional reference voltages, VREFH and VREFL, are required as inputs to the additional clocked comparators. These additional reference voltages must be generated through additional circuitry, further increasing design complexity.

[0046] Based on an in-depth analysis and understanding of the problems in the prior art, the inventors have proposed a low-ripple, fast-response digital LDO circuit and control method. Digital control logic is used in combination with a clock-controlled comparator, a partial stability detection circuit, a shift switch circuit, and an asynchronous control loop to improve response speed and stability while reducing ripple. The core idea of ​​the invention is to dynamically adjust the coarse and fine loops of voltage regulation through digital signal processing, so as to quickly adapt to load changes and maintain voltage stability. Analysis by the counter and sequence detector can more accurately determine whether the current state is stable, and select the most appropriate regulation strategy (thin loop or coarse loop regulation) to achieve efficient voltage management. In addition, the use of complex window comparators and multiple reference voltages is avoided, which simplifies the circuit design and reduces the number of components. The specific implementation plan is as follows:

[0047] like Figure 1 As shown, the present invention provides a low ripple fast response digital LDO circuit, comprising: a clock control comparator, a partial stability detection circuit, a shift control switch circuit and an asynchronous control loop;

[0048] A clock-controlled comparator for monitoring the deviation between the feedback voltage VFB and the reference voltage VREF in real time and outputting a comparison signal;

[0049] The partial stability detection circuit, including a counter and a sequence detector, is digitally designed. The counter generates a Cnt signal based on the continuity of the comparison signal to detect the continuity of the output signal. The sequence detector generates a mode signal based on the output mode of the output signal to evaluate whether the output signal has reached the preset target stable state.

[0050] The shift control circuit dynamically controls the coarse and fine loops and adjusts the PMOS switch array to achieve voltage regulation based on the Cnt and mode signals provided by the partial stability detection circuit and the internal carry signal FD. When the shift control circuit detects the carry signal FD, it switches from fine loop regulation to coarse loop regulation to speed up regulation.

[0051] The input end of the clock control comparator is respectively connected to the feedback voltage VFB and the reference voltage VREF, and the output end is respectively connected to the shift control circuit and the counter and sequence detector in the partial stability monitoring circuit for outputting a comparison signal; the shift control circuit is connected to the partial stability monitoring circuit and the clock control comparator, and determines whether the voltage state is stable according to the output mode signal and Cnt signal. When the voltage state has not reached the stable state, the small-size array of PMOS switches is used for fine-loop adjustment. When the small-size array of PMOS switches has completed adjustment but has not reached the stable state, the carry signal FD is triggered, and the coarse-loop adjustment of the output voltage is performed in combination with the large-size array of PMOS switches to quickly respond to changes in the feedback voltage VFB, and switch to fine-loop adjustment according to the mode signal to achieve a stable state.

[0052] The input of the asynchronous control loop is connected to the output voltage VOUT, and the output of the asynchronous control loop is connected to the shift controller. When the output voltage reaches a preset value, a large undershoot is detected and an asynchronous control signal AS_ctrl is output. The asynchronous control signal AS_ctrl directly sets the coarse-ring PMOS large-size array to half of the maximum adjustment range. The asynchronous control signal has no effect on the current state of the shift controller and is used to quickly provide high current.

[0053] Furthermore, the negative input terminal of the clock-controlled comparator is connected to the reference voltage VREF, and the positive input terminal is connected to the feedback voltage VFB; the output terminal is based on a comparison signal of the reference voltage VREF and the feedback voltage VFB, and the comparison signal is signal 0 or signal 1. Signal 0 means that the feedback voltage VFB is less than the reference voltage VREF, otherwise signal 1 is output; wherein, the feedback voltage VFB is the voltage obtained by the output voltage VOUT to the grounded voltage regulator.

[0054] Furthermore, a counter in the partial stability detection circuit receives a comparison signal from the clock-controlled comparator and monitors the consistency of the comparison signal within two consecutive clock cycles;

[0055] When the comparison signal is inconsistent within two consecutive clock cycles, the counter's count value is reset to 0; when the comparison signal is continuously consistent, the counter increases its count value; based on whether the count value exceeds the preset threshold, the corresponding Cnt signal is output, and the shift control circuit is quickly or slowly adjusted according to the Cnt signal.

[0056] Furthermore, the sequence detector in the partial stability detection circuit is used to analyze the comparison signal of the clock control comparator, determine whether the set sequence state is met according to the output sequence of the comparison signal, and output the corresponding mode signal to analyze the stability state of the circuit.

[0057] Furthermore, the shift control circuit includes a shift controller, a small-size array of PMOS switches, and a large-size array of PMOS switches; the input end of the shift controller is respectively connected to a counter, a sequence detector, and a clock-controlled comparator, for obtaining a current comparison signal, a Cnt signal, and a mode signal; the output end of the shift controller is connected to the PMOS switch array, wherein a coarse-loop adjustment control in the shift controller is connected to the large-size array of PMOS switches, and a fine-loop adjustment control is connected to the small-size array of PMOS switches; and when the small-size array of PMOS switches is adjusted, a carry signal FD is triggered, and the coarse-loop adjustment control is entered to perform coarse-loop adjustment until the mode signal enters a stable state, and then the fine-loop adjustment control is switched back to perform fine-loop adjustment.

[0058] Furthermore, the fine loop adjustment control includes a fine loop slow adjustment unit and a fine loop fast adjustment unit, which performs fast adjustment and slow adjustment according to the Cnt signal when the carry signal FD is not triggered or the coarse loop adjustment is switched to the fine loop adjustment; wherein,

[0059] When the Cnt signal does not reach the preset threshold, slow adjustment is performed, and the adjustment step size of the small-size array of PMOS switches is reset to the minimum step size of 1 according to the comparison signal;

[0060] When the Cnt signal reaches a preset threshold, rapid adjustment is performed, and the adjustment step length of the small-size PMOS switch array is set to a fixed step length according to the comparison signal, and the fixed step length is a natural number greater than 1.

[0061] Furthermore, the coarse loop adjustment control includes a coarse loop slow adjustment unit and a coarse loop fast adjustment unit. When the carry signal FD is triggered, fast adjustment and slow adjustment are performed according to the Cnt signal.

[0062] When the Cnt signal does not reach the preset threshold, slow adjustment is performed, and the adjustment step size of the large-size PMOS switch array is reset to the minimum step size of 1 according to the comparison signal, and the step size of the small-size PMOS switch array is set to half of the total step size;

[0063] When the Cnt signal reaches the preset threshold, rapid adjustment is performed. The adjustment step size of the large-size PMOS switch array is set to a fixed step size according to the comparison signal, and the fixed step size is a natural number greater than 1; and the step size of the small-size PMOS switch array is set to half of the total step size.

[0064] Furthermore, two groups of feedforward auxiliary PMOS are included, and corresponding small-sized or large-sized feedforward auxiliary PMOS are used according to the fine loop adjustment unit or the coarse loop adjustment unit in the shift control circuit to prevent the oscillation mode from being too high to be detected by the sequence detector.

[0065] Furthermore, a load capacitor and a load resistor are included to smooth the output voltage VOUT and reduce high-frequency noise.

[0066] Example 2

[0067] Based on the same inventive concept, the present invention provides a low-ripple, fast-response digital LDO circuit control method, which uses the fast-response digital LDO circuit described above for control. The method includes:

[0068] Step S1: obtaining a comparison signal of a clock-controlled comparator comparing a feedback voltage VFB and a reference voltage VREF, wherein the feedback voltage VFB is obtained by dividing the output voltage VOUT; a counter and a sequence detector in the partial stability detection circuit obtain corresponding Cnt signals and mode signals according to the comparison signal;

[0069] Step S2: Determine whether the mode signal output by the sequence detection is 1;

[0070] Step S3: When the mode signal is 1, the circuit is in a stable state; when the mode signal is 0, the shift control circuit performs fine loop adjustment, determines the adjustment speed and logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a small-sized feedforward auxiliary PMOS; wherein,

[0071] When the Cnt signal is 0, the counter value does not reach the preset threshold and slow adjustment is performed, resetting the adjustment step of the small-size PMOS switch array to the minimum step of 1; until the mode signal is 1 and reaches a stable state or the Cnt signal is 1 and enters the fast adjustment of the fine loop adjustment;

[0072] When the Cnt signal is 1, the counter value reaches the preset threshold value and is quickly adjusted. The adjustment step of the PMOS switch small-size array is set to a fixed step size, which is a natural number greater than 1 and the step size is the number of switches. When the Cnt signal is 0 and the fine-loop adjustment is slow, or when all switches in the PMOS switch small-size array are in the open state, the carry signal FD is triggered.

[0073] Step S3: The shift control circuit switches from fine loop regulation to coarse loop regulation according to the detected carry signal FD; the regulation speed and logic are determined according to the Cnt signal and the comparison signal, and steady-state oscillation is suppressed by a large-sized feedforward auxiliary PMOS; wherein,

[0074] When the Cnt signal is 0, the counter value does not reach the preset threshold and slow adjustment is performed, resetting the adjustment step of the large-size PMOS switch array to the minimum step of 1; and setting the number of switches in the small-size PMOS switch array to half of the total number; until the Cnt signal is 1 and enters the fast adjustment of the coarse loop adjustment or reaches the mode signal 1 to return to the fine loop adjustment, reaching a stable state.

[0075] When the Cnt signal is 1, the counter value reaches the preset threshold and is quickly adjusted. The adjustment step size of the small-size array of PMOS switches is set to a fixed step size, which is a natural number greater than 1, and the number of switches in the small-size array of PMOS switches is set to half of the total number; the adjustment is switched to slow adjustment of the coarse loop adjustment until the mode signal is 1 and returns to the fine loop adjustment to reach a stable state.

[0076] Step S4: During the adjustment process, the asynchronous control loop outputs an asynchronous control signal AS_ctrl according to the detected output voltage VOUT drop reaching a preset value, and directly sets the large-size array of PMOS switches to open half without affecting the state of the shift controller.

[0077] Example 3

[0078] like Figure 1 、 2 As shown, referring to the flowchart showing the steps of an embodiment of the present invention, the present invention will be described in more detail below. This embodiment is provided to fully and completely disclose the present technology so that those skilled in the art can fully understand the scope of application and implementation details of the present invention, and to enable more people in the relevant technical field to fully understand the scope of the present invention.

[0079] like Figure 1 As shown, this embodiment 1 proposes a low-ripple, fast-response digital LDO circuit, which includes: a clock-controlled comparator, a counter, a sequence detector, a shift controller (a coarse-loop adjustment control and a fine-loop adjustment control), two groups of PMOS switch arrays, two groups of feedforward auxiliary PMOS (two in number each), an asynchronous control loop, and a load capacitor and a load resistor; wherein,

[0080] Counters, sequence detectors, and shift controllers are designed using digital code, specifically:

[0081] The clocked comparator has a negative input connected to a reference voltage, VREF, and a positive input connected to a feedback voltage, VFB. Its output is connected to a counter, a sequence detector, a shift controller, and a feedforward auxiliary PMOS. The clocked comparator compares the input feedback voltage with the reference voltage at a predetermined clock cycle and generates an output signal based on the comparison result. This process is triggered at a specific time point in each clock cycle, ensuring operational synchronization and timing accuracy.

[0082] The counter accumulates counts based on the output signal comp_out of the clock-controlled comparator. If the previous and next comparison results are the same, the counter increments by 1. When the count value exceeds the set value, a cnt = '1' signal is output to increase the shift step size of the shift control logic. If the Comp_out values ​​of the two clock cycles are different, cnt = '0', and the step size is reset to the minimum step size of 1. This step size is directly related to the switching operation of the PMOS switch array. That is, the step size indicates the number of PMOS switches adjusted in each regulation cycle, thereby adjusting for fast or slow changes in the output voltage.

[0083] The feedforward auxiliary PMOS is used to reduce steady-state oscillation modes, preventing them from being too high to be detected by the sequence detector. Depending on the control running in the shift controller, a large or small feedforward PMOS is selected. Specifically, a large feedforward PMOS is selected for coarse-loop control, while a small feedforward PMOS is selected for fine-loop control.

[0084] The sequence detector checks whether the comp_out signal matches the set sequence state. For example, if the comparison result matches the sequence 101010, it outputs a Mode = 1 signal to determine whether the circuit has entered a stable state. The shift controller selects either the coarse or fine control loop based on the Mode signal and whether the carry signal FD is triggered. It then outputs the corresponding Ctrl signal, changing the switching state of the corresponding PMOS array. The shift step size is selected based on the Cnt signal. The PMOS array comes in two sizes: the larger PMOS_L is designed for fast regulation, while the smaller PMOS_S is designed for low ripple. The asynchronous control loop is an asynchronous loop and is used to monitor VOUT changes in real time.

[0085] The shift controller dynamically adjusts coarse and fine loop control and adjusts the PMOS switch array to achieve voltage regulation based on the Cnt and mode signals provided by the bias-stability detection circuit. Upon detecting a carry signal (FD), it rapidly switches from fine to coarse loop regulation, significantly improving regulation speed and reducing ripple. This allows the digital LDO circuit of the present invention to provide fast response while significantly reducing output voltage ripple, optimizing overall circuit performance, particularly in terms of low ripple and fast response. Furthermore, this design simplifies circuit construction, reduces manufacturing costs, and improves circuit reliability and stability.

[0086] It should be specifically noted that, in this circuit diagram, the signal for switching the coarse and thin rings is based on the mode signal and the carry signal FD. When switching from the thin ring to the coarse ring adjustment, the adjustment is based on the carry signal FD, and when switching from the coarse ring to the fine ring adjustment, the switching is based on the mode signal switching back to 1.

[0087] Therefore, the shift controller controls the adjustment process of the thick and thin loops by specifically adjusting and switching according to the mode signal, comparison signal, Cnt signal, and carry signal FD. When the mode signal is 0 and unstable, the Cnt signal is 0 and enters the cyclic slow adjustment. When the Cnt signal is 0 and the mode signal is 1, it enters the stable state. When the Cnt signal reaches 1, it enters the fast adjustment of the thin loop, and the shift step of the small-size PMOS switch array increases until the Cnt signal reaches 0 and enters the slow adjustment step of the thin loop; or all the switches in the small-size PMOS switch array are turned on, the Cnt signal reaches 0 and triggers the carry signal FD, and enters the thick loop adjustment process. During this process, half of the switches in the small-size PMOS switch array are set to be turned on, and corresponding fast and slow adjustments are performed. In the digital LDO, this shift controller is used to adjust the state of the PMOS switch array according to the output signal of the comparator. The shift operation is synchronized with the clock signal, and the entire circuit operates according to the clock cycle. Ensure the sequentiality and timeliness of the voltage adjustment action.

[0088] For the specific step process, please refer to <* Figure 2 , such as Figure 2 shown. The specific voltage regulation process is as follows: Initially, it is in the stable state of the thin loop. When a small change occurs in the output voltage VOUT due to load changes, if VFB < VREF at this time, Comp_out outputs '0'. At this time, both the counter and the sequence detector output '0', and it enters the slow adjustment mode of the thin loop. The Comp_out signal controls the shift control logic to shift the output of Ctrl_F by one '0', that is, turn on a small-size PMOS. If VOUT is still less than VREF, this process is repeated in the next clock cycle; after multiple executions, if the number of consecutive '0's counted by the counter exceeds the set value (8), then Cnt = '1', and it enters the fast adjustment mode of the thin loop. The shift step of Ctrl_F increases (increases to 4), and continues to adjust until the output signal of the comparator flips, Cnt becomes '0' again, and the step size also becomes the minimum step size. Continue to adjust until the sequence detector detects the sequence of 101010, indicating that it has entered the stable state of the thin loop, and the Mode signal is set to '1', and the adjustment ends.

[0089] When the fine loop adjustment range fails to meet the requirements and the fine loop has not returned to its stable state, all M PMOS_Ss in the small-size PMOS switch array are adjusted and turned on, triggering the FD carry signal. According to the shift control logic, the coarse loop is switched and the fine loop control signal is set to turn on half of the PMOS_Ss. The subsequent adjustment process is exactly the same as the fine loop, except that the output signal becomes Ctrl_C. After several cycles, when the sequence detector detects the 101010 sequence, it indicates that the coarse loop has reached a stable state. Mode = '1', and the shift control logic is switched back to the fine loop, that is, the Ctrl_F signal is output. After the fine loop is adjusted, it enters a stable state here, reducing the output voltage ripple.

[0090] During the entire regulation process, when the output voltage VOUT drops rapidly and significantly, it indicates that the LDO needs to provide a large current. Therefore, the asynchronous control loop outputs the asynchronous control signal As_ctrl to control the coarse-loop shift logic, directly opening the coarse-loop PMOS by half to quickly provide current and prevent a large undershoot voltage.

[0091] Specifically, the asynchronous control loop monitors the real-time value of the output voltage VOUT and sets a threshold. For example, if the output voltage VOUT drops by more than a specific percentage or absolute value (e.g., 5% or 0.1V) within a short, set timeframe (e.g., a few microseconds to milliseconds), the asynchronous control loop is triggered to output a control signal, which adjusts the PMOS array to the appropriate state to quickly compensate for the voltage drop, thereby ensuring power supply stability.

[0092] During the shift controller's full-process adjustment of the coarse and fine loops, the PMOS switch array and the asynchronous control loop adjust independently, without interfering with each other. While the shift controller regulates the PMOS switch array based on clock control, the asynchronous control loop operates independently of this clock control process, designed to handle sudden high current demands or rapid voltage drops. The asynchronous control loop monitors the output voltage in real time and, upon detecting a voltage drop below a preset threshold, rapidly issues a short pulse of control signal to directly manipulate a portion of the large PMOS array to provide the necessary current. This process, with its extremely short response time—typically less than one clock cycle—does not interfere with the regular regulation of the clocked fine and coarse loops. Therefore, the asynchronous control loop can react quickly and adjust the PMOS array to accommodate sudden voltage changes, but its independent control mechanism ensures that it does not affect the stable regulation of the fine and coarse loops, ensuring a smooth return to normal regulation after emergency intervention. This seamless switching ensures stable system operation under varying demands, maintaining performance even in the face of extreme voltage fluctuations.

[0093] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

Claims

1. A low ripple fast response digital LDO circuit, characterized in that: include: Clock controlled comparator, partial stability detection circuit, shift control switch circuit and asynchronous control loop; The clock-controlled comparator is used to monitor the deviation between the feedback voltage VFB and the reference voltage VREF in real time and output a comparison signal; The partial stability detection circuit includes a counter and a sequence detector, both of which are digitally designed; wherein the counter sends a Cnt signal based on the continuity of the comparison signal to detect the continuity of the output signal; and the sequence detector sends a mode signal based on the output mode of the output signal to evaluate whether the output signal has reached a preset target stable state; a shift control circuit that dynamically controls and adjusts the PMOS switch array between coarse and fine loops based on the Cnt signal and the mode signal provided by the partial stability detection circuit and an internal carry signal FD to achieve voltage regulation. When the shift control circuit detects the carry signal FD, it switches from fine loop regulation to coarse loop regulation to speed up regulation. The input end of the clock-controlled comparator is respectively connected to the feedback voltage VFB and the reference voltage VREF, and the output end is respectively connected to the shift control circuit and the counter and the sequence detector in the partial stability detection circuit, for outputting the comparison signal; the shift control circuit is connected to the partial stability detection circuit and the clock-controlled comparator, and determines whether the voltage state is stable according to the output mode signal and the Cnt signal. When the voltage state has not reached the stable state, the small-size array of PMOS switches is subjected to fine-loop regulation. When the small-size array of PMOS switches has completed regulation and has not reached the stable state, the carry signal FD is triggered, and the coarse-loop output voltage is regulated in combination with the large-size array of PMOS switches to quickly respond to changes in the feedback voltage VFB, and switches to fine-loop regulation according to the mode signal to reach the stable state. The input of the asynchronous control loop is connected to the output voltage VOUT, and the output of the asynchronous control loop is connected to the shift controller. When the output voltage reaches a preset value, a significant undershoot is detected and an asynchronous control signal AS_ctrl is output. The asynchronous control signal AS_ctrl directly sets the coarse-ring PMOS large-size array to half of its maximum adjustment range. The asynchronous control signal has no effect on the current state of the shift controller and is used to quickly provide high current.

2. The fast response digital LDO circuit according to claim 1, characterized in that: The negative input terminal of the clock-controlled comparator is connected to the reference voltage VREF, and the positive input terminal is connected to the feedback voltage VFB; the output terminal is based on a comparison signal between the reference voltage VREF and the feedback voltage VFB, and the comparison signal is signal 0 or signal 1. The signal 0 indicates that the feedback voltage VFB is less than the reference voltage VREF, otherwise the signal 1 is output; wherein, the feedback voltage VFB is the voltage obtained by connecting the output voltage VOUT to the grounded voltage regulator.

3. The fast response digital LDO circuit according to claim 2, characterized in that: The counter in the partial stability detection circuit receives the comparison signal of the clock control comparator and monitors the consistency of the comparison signal in two consecutive clock cycles; When the comparison signal is inconsistent in the two consecutive clock cycles, the count value of the counter is reset to 0; when the comparison signal is continuously consistent, the counter increases its count value; The corresponding Cnt signal is output based on whether the count value exceeds a preset threshold, and the shift control circuit is quickly adjusted or slowly adjusted according to the Cnt signal.

4. The fast response digital LDO circuit according to claim 2, characterized in that: The sequence detector in the partial stability detection circuit is used to analyze the comparison signal of the clock control comparator, determine whether the set sequence state is met according to the output sequence of the comparison signal, and output the corresponding mode signal to analyze the stability state of the circuit.

5. The fast response digital LDO circuit according to claim 2, characterized in that: The shift control circuit includes the shift controller, the small-size PMOS switch array, and the large-size PMOS switch array; the input end of the shift controller is respectively connected to the counter, the sequence detector, and the clock control comparator, for obtaining the current comparison signal, the Cnt signal, and the mode signal; the output end of the shift controller is connected to the PMOS switch array, wherein the coarse loop adjustment control in the shift controller is connected to the large-size PMOS switch array, and the fine loop adjustment control is connected to the small-size PMOS switch array; and when the small-size PMOS switch array is adjusted, the carry signal FD is triggered, the coarse loop adjustment control is entered to perform the coarse loop adjustment until the mode signal enters the stable state, and the fine loop adjustment control is switched back to perform the fine loop adjustment.

6. The fast response digital LDO circuit according to claim 3, characterized in that: The fine loop adjustment control includes a fine loop slow adjustment unit and a fine loop fast adjustment unit, and when the carry signal FD is not triggered or the coarse loop adjustment is switched to the fine loop adjustment, the fast adjustment and the slow adjustment are performed according to the Cnt signal; wherein, When the Cnt signal does not reach the preset threshold, the slow adjustment is performed, and the adjustment step of the small-size PMOS switch array is reset to a minimum step of 1 according to the comparison signal; When the Cnt signal reaches the preset threshold, the rapid adjustment is performed, and the adjustment step length of the PMOS switch small-size array is set to a fixed step length according to the comparison signal, and the fixed step length is a natural number greater than 1.

7. The fast response digital LDO circuit according to claim 3, characterized in that: The coarse loop adjustment control includes a coarse loop slow adjustment unit and a coarse loop fast adjustment unit. When the carry signal FD is triggered, the fast adjustment and the slow adjustment are performed according to the Cnt signal. When the Cnt signal does not reach the preset threshold, the slow adjustment is performed, and the adjustment step size of the large-size PMOS switch array is reset to a minimum step size of 1 according to the comparison signal, and the step size of the small-size PMOS switch array is set to half of the total step size; When the Cnt signal reaches the preset threshold, the rapid adjustment is performed, and the adjustment step size of the large-size array of PMOS switches is set to a fixed step size according to the comparison signal, and the fixed step size is a natural number greater than 1; and the step size of the small-size array of PMOS switches is set to half of the total step size.

8. The fast response digital LDO circuit according to claim 1, characterized in that: It also includes two groups of feedforward auxiliary PMOS, which use corresponding small or large-sized feedforward auxiliary PMOS according to the fine loop adjustment unit or the coarse loop adjustment unit in the shift control circuit to prevent the oscillation mode from being too high to be detected by the sequence detector.

9. The fast response digital LDO circuit according to claim 1, characterized in that: A load capacitor and a load resistor are also included to smooth the output voltage VOUT and reduce high-frequency noise.

10. A low ripple fast response digital LDO circuit control method, characterized in that: The fast response digital LDO circuit according to any one of claims 1 to 9 is used for control, and the method comprises: Step S1: obtaining a comparison signal of a clock-controlled comparator comparing a feedback voltage VFB and a reference voltage VREF, wherein the feedback voltage VFB is obtained by dividing the output voltage VOUT; a counter and a sequence detector in a partial stability detection circuit obtain corresponding Cnt signals and mode signals according to the comparison signal; Step S2: determining whether the mode signal output by the sequence detection is 1; Step S3: When the mode signal is 1, the circuit is in a stable state; when the mode signal is 0, the shift control circuit performs fine loop adjustment, determines the adjustment speed and logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a small-sized feedforward auxiliary PMOS; wherein, When the Cnt signal is 0, the counter value does not reach the preset threshold value and performs slow adjustment, resetting the adjustment step of the PMOS switch small-size array to the minimum step of 1; until the mode signal is 1 and reaches a stable state or the Cnt signal is 1 and enters the fast adjustment of the fine loop adjustment; When the Cnt signal is 1, the value of the counter reaches the preset threshold and performs rapid adjustment, and the adjustment step of the PMOS switch small-size array is set to a fixed step, where the fixed step is a natural number greater than 1 and the step is the number of switches; until the Cnt signal is 0 and enters the slow adjustment of the fine loop adjustment or all switches in the PMOS switch small-size array are in the open state, the carry signal FD is triggered; Step S3: the shift control circuit switches from the fine loop regulation to the coarse loop regulation according to the detected carry signal FD; determines the regulation speed and the logic according to the Cnt signal and the comparison signal, and suppresses steady-state oscillation through a large-sized feedforward auxiliary PMOS; wherein, When the Cnt signal is 0, the counter value does not reach the preset threshold value, and the slow adjustment is performed, and the adjustment step size of the large-size PMOS switch array is reset to the minimum step size of 1; and the number of switches in the small-size PMOS switch array is set to half of the total number; until the Cnt signal is 1 and the fast adjustment of the coarse loop adjustment is entered, or the mode signal is 1 and the fine loop adjustment is returned, and the stable state is reached; When the Cnt signal is 1, the value of the counter reaches the preset threshold value, the fast adjustment is performed, the adjustment step size of the PMOS switch small-size array is set to a fixed step size, the fixed step size is the natural number greater than 1, and the number of switches in the PMOS switch small-size array is set to half of the total number; the adjustment is switched to the slow adjustment of the coarse loop adjustment until the mode signal is 1 and the fine loop adjustment is returned to reach the stable state; Step S4: During the adjustment process, the asynchronous control loop outputs the asynchronous control signal AS_ctrl according to the detected output voltage VOUT drop reaching a preset value, and directly sets the large-size array of PMOS switches to half open without affecting the state of the shift controller.

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