Pulse excitation signal generator
By designing a pulse excitation signal generator, using a clock controller, waveform generator and pulse excitation unit, the problems of insufficient frequency matching and poor mode compatibility in traditional ultrasonic excitation systems are solved, and the excitation signal generation of different frequencies and modes is achieved. Requirements for a variety of ultrasonic application scenarios.
Patent Information
- Application Number
- CN202411382540.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2024-12-31
AI Technical Summary
Traditional ultrasonic excitation systems have problems such as insufficient frequency matching and poor mode compatibility in different ultrasonic application scenarios, making it difficult to effectively generate excitation pulse signals of different frequencies and modes.
A pulse excitation signal generator is designed, including a clock controller, a first waveform generator and a first pulse excitation unit. Through the clock controller, the basic clock signal is converted into a waveform of a characteristic frequency to generate a clock signal. The first waveform generator is It is converted into logic control signals of different modes, and the first pulse excitation unit generates pulse excitation signals of different modes at characteristic frequencies according to these signals, thereby realizing the generation of excitation signals of different frequencies and modes.
It realizes flexible response to different ultrasonic application scenarios, generates pulse excitation signals of different frequencies and modes, improves frequency matching and mode compatibility, and meets the needs of a variety of ultrasonic applications.
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Figure CN119225473A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of pulse excitation signal generation, and in particular to a pulse excitation signal generator. Background Art
[0002] In the medical field, phased array technology is widely used in ultrasonic diagnosis and ultrasonic therapy. Ultrasonic diagnosis is a very important medical examination method. It can understand the specific data and morphology of the internal tissue structure of the human body through the propagation and reflection of ultrasonic waves in human tissues, so as to diagnose human diseases. Ultrasonic therapy is the application of phased array ultrasonic technology to the human body to achieve the effect of treating certain diseases of the human body;
[0003] In the field of industrial inspection, ultrasonic phased array technology can detect and locate internal defects of various materials, which is convenient for workers to conduct qualitative and quantitative analysis. However, there are some problems with traditional ultrasonic excitation systems when dealing with different ultrasonic application scenarios, such as insufficient frequency matching and poor mode compatibility. That is, there are currently higher requirements on how to realize the excitation pulse signal generator for different ultrasonic application scenarios. Summary of the invention
[0004] The invention provides a pulse excitation signal generator to realize the generation of excitation pulse signals of different frequencies and different modes.
[0005] To achieve the above objectives, an embodiment of the present invention provides a pulse excitation signal generator, the pulse excitation signal generator comprising: a clock controller, a first waveform generator and a first pulse excitation unit;
[0006] The clock controller is used to convert the basic clock signal into a waveform of a characteristic frequency to generate a clock signal;
[0007] The first waveform generator is used to convert the waveform generating clock signal of the characteristic frequency into a first logic control signal of a different mode at the characteristic frequency and a second logic control signal of a different mode at the characteristic frequency;
[0008] The first pulse excitation unit is used to generate pulse excitation signals of different modes under characteristic frequencies according to the first logic control signals of different modes under characteristic frequencies and the second logic control signals of different modes under characteristic frequencies.
[0009] Optionally, the first waveform generator includes: an N-bit counter, a comparator, an odd-even separator, a first signal output unit and a second signal output unit;
[0010] The N-bit counter is used to accumulate from 0 to N under the control of the waveform generating clock signal;
[0011] The comparator is used to compare the size of the accumulated number of bits with the preset number of bits, and output a separation signal to the odd-even separator when the accumulated number of bits is smaller than the preset number of bits;
[0012] The odd-even separator is used to separate the accumulated bits into odd and even bits and output odd bits and even bits;
[0013] The first signal output unit is used to generate a first logic control signal according to the odd number of bits;
[0014] The second signal output unit is used to generate a second logic control signal according to the even-numbered bit number.
[0015] Optionally, the first pulse excitation unit includes: a first logic control switch and a second logic control switch;
[0016] The control end of the first logic control switch receives the first logic control signal; the control end of the second logic control switch receives the second logic control signal; the first end of the first logic control switch is electrically connected to the positive high voltage source; the second end of the first logic control switch and the first end of the second logic control switch serve as the output ends of the pulse excitation unit to output the pulse excitation signal; the second end of the second logic control switch is electrically connected to the negative high voltage source.
[0017] Optionally, the clock controller includes: a pre-frequency division counter, a phase-frequency detector, a loop filter, a voltage-controlled oscillator and a post-frequency division counter;
[0018] The pre-frequency division counter is used to divide the basic clock signal by N bits;
[0019] The phase-frequency detector is used to detect the phase size of the basic clock signal after the frequency division process and the output reference frequency size of the basic clock signal; and is also used to detect the phase size of the feedback clock signal and the frequency size of the feedback clock signal; wherein the feedback clock signal is the clock signal output after the basic clock signal after the frequency division process passes through the phase-frequency detector, the loop filter and the voltage-controlled oscillator;
[0020] The loop filter is used to output an offset elimination control signal to the voltage-controlled oscillator according to a phase difference between a phase size of the basic clock signal and a phase size of the feedback signal, and a frequency difference between an output reference frequency size of the basic clock signal and a frequency size of the feedback signal;
[0021] The voltage-controlled oscillator is used to output a stable clock signal according to the offset elimination control signal; wherein the output frequency of the stable clock signal is the same as the output reference frequency of the basic clock signal after the frequency division process;
[0022] The post-frequency division counter is used to perform M-bit frequency division processing on the output frequency of the stable clock signal.
[0023] Optionally, the pulse excitation signal generator further includes: a plurality of second pulse excitation units;
[0024] Each of the second pulse excitation units is used to generate pulse excitation signals of different modes according to the first logic control signals of different modes and the second logic control signals of different modes;
[0025] Optionally, the second pulse excitation unit has the same structure as the first pulse excitation unit.
[0026] Optionally, the pulse excitation signal generator further includes: a plurality of second waveform generators and a plurality of third pulse excitation units; each of the second waveform generators corresponds to each of the third pulse excitation units one by one;
[0027] Each of the second waveform generators is used to convert the waveform generation clock signal into a first logic control signal of a different mode and a second logic control signal of a different mode, and output them to the corresponding third pulse excitation unit;
[0028] Each of the third pulse excitation units is used to generate pulse excitation signals of different modes according to the first logic control signals of different modes and the second logic control signals of different modes outputted by the corresponding second waveform generator.
[0029] Optionally, the second waveform generator has the same structure as the first waveform generator; and the third pulse excitation unit has the same structure as the first pulse excitation unit.
[0030] Optionally, the N-bit counter is specifically used to generate a trigger signal when the waveform generates a clock signal, and accumulate from 0 to N under the control of the trigger signal.
[0031] In an embodiment of the present invention, a basic clock signal is converted into a waveform generating clock signal of a characteristic frequency through a clock controller; a first waveform generator converts the waveform generating clock signal of the characteristic frequency into a first logic control signal of different modes under the characteristic frequency and a second logic control signal of different modes under the characteristic frequency; a first pulse excitation unit generates a pulse excitation signal of different modes under the characteristic frequency according to the first logic control signal of different modes under the characteristic frequency and the second logic control signal corresponding to the different modes under the characteristic frequency, thereby realizing the generation of excitation pulse signals of different frequencies and different modes. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1is a structural schematic diagram of a pulse excitation signal generator provided by an embodiment of the present invention;
[0033] Figure 2 is a schematic diagram of a waveform generating clock signal, a first logic control signal and a second logic control signal provided in an embodiment of the present invention;
[0034] Figure 3 is a schematic diagram of a specific structure of a pulse excitation signal generator provided by an embodiment of the present invention;
[0035] Figure 4 It is a schematic diagram of a first logic control signal of a single pulse mode, a second logic control signal of a single pulse mode, and a pulse excitation signal of a single pulse mode provided by an embodiment of the present invention;
[0036] Figure 5 It is a schematic diagram of a first logic control signal of a continuous pulse mode with an adjustable duty cycle, a second logic control signal of a continuous pulse mode with an adjustable duty cycle, and a pulse excitation signal of a continuous pulse mode with an adjustable duty cycle provided by an embodiment of the present invention;
[0037] Figure 6 It is a schematic diagram of a first logic control signal of a continuous pulse mode, a second logic control signal of a continuous pulse mode, and a pulse excitation signal of a continuous pulse mode provided by an embodiment of the present invention;
[0038] Figure 7 is a schematic diagram of a trigger signal provided by an embodiment of the present invention;
[0039] Figure 8 is a schematic structural diagram of another pulse excitation signal generator provided by an embodiment of the present invention;
[0040] Fig. 9 It is a structural schematic diagram of another pulse excitation signal generator provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.
[0042] Figure 1 is a schematic diagram of the structure of a pulse excitation signal generator provided by an embodiment of the present invention, Figure 2 is a schematic diagram of a waveform generating clock signal, a first logic control signal and a second logic control signal provided in an embodiment of the present invention; Figure 1 and 2As shown, the pulse excitation signal generator includes: a clock controller 10, a first waveform generator 20 and a pulse excitation unit 30; the clock controller 10 is used to convert the basic clock signal into a waveform generating clock signal of a characteristic frequency; the first waveform generator 20 is used to convert the waveform generating clock signal of the characteristic frequency into a first logic control signal IN_P of different modes under the characteristic frequency and a second logic control signal IN_N of different modes under the characteristic frequency; the first pulse excitation unit 30 is used to generate a pulse excitation signal OUT of different modes under the characteristic frequency according to the first logic control signal IN_P of different modes under the characteristic frequency and the second logic control signal IN_N of different modes under the characteristic frequency. Figure 2 Only the first logic control signal IN_P of the single pulse mode, the second logic control signal IN_N of the single pulse mode and the pulse excitation signal OUT of the single pulse mode are illustrated.
[0043] The clock controller 10 can divide or multiply the input basic clock signal to generate a clock signal by outputting a waveform with adjustable frequency; specifically, the clock controller 10 can convert the basic clock signal into a waveform with a characteristic frequency by setting the parameters of the frequency division and the frequency multiplication to generate the clock signal;
[0044] The first waveform generator 20 converts the waveform generating clock signal into the first logic control signal of different modes under the characteristic frequency and the second logic control signal of different modes under the characteristic frequency; wherein the first logic control signal of different modes includes three modes: single pulse, continuous pulse with adjustable duty cycle and continuous pulse; the second logic control signal of different modes includes three modes: single pulse, continuous pulse with adjustable duty cycle and continuous pulse; the first logic control signal and the second logic control signal after the waveform generating clock signal is simultaneously converted have the same mode; exemplarily, the waveform generating clock signal can be simultaneously converted into the first logic control signal of the single pulse mode and the second logic control signal of the single pulse mode; the waveform generating clock signal can be simultaneously converted into the first logic control signal of the continuous pulse mode and the second logic control signal of the continuous pulse mode; since the frequency of the waveform generating clock signal is adjustable, the frequency of the first logic control signal of each mode is adjustable; the frequency of the second logic control signal of each mode is adjustable;
[0045] The first pulse excitation unit 30 generates pulse excitation signals of different modes from first logic control signals of different modes and second logic control signals of different modes; wherein the pulse excitation signals of different modes include three modes: single pulse, continuous pulse with adjustable duty cycle and continuous pulse; the mode correspondence of the pulse excitation signal generated by the first logic control signal and the second logic control signal is the same as the mode correspondence of the first logic control signal and the mode correspondence of the second logic control signal; illustratively, the first pulse excitation unit 30 generates a pulse excitation signal of a single pulse mode from the first logic control signal of a single pulse mode and the second logic control signal of a single pulse mode; since the frequencies of the second logic control signal of each mode and the first logic control signal of each mode are adjustable, the frequencies of the corresponding pulse excitation signals of each mode are adjustable;
[0046] In this embodiment, the basic clock signal is converted into a waveform generating clock signal of a characteristic frequency by the clock controller 10; the first waveform generator 20 converts the waveform generating clock signal of the characteristic frequency into a first logic control signal of different modes under the characteristic frequency and a second logic control signal of different modes under the characteristic frequency; the first pulse excitation unit 30 generates a pulse excitation signal of different modes under the characteristic frequency according to the first logic control signal of different modes under the characteristic frequency and the second logic control signal corresponding to the different modes under the characteristic frequency, thereby realizing the generation of excitation pulse signals of different frequencies and different modes.
[0047] Optionally, based on the above embodiment, further refinement is performed: Figure 3 is a specific structural diagram of a pulse excitation signal generator provided by an embodiment of the present invention, Figure 4 It is a schematic diagram of a first logic control signal of a single pulse mode, a second logic control signal of a single pulse mode, and a pulse excitation signal of a single pulse mode provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of a first logic control signal of a continuous pulse mode with an adjustable duty cycle, a second logic control signal of a continuous pulse mode with an adjustable duty cycle, and a pulse excitation signal of a continuous pulse mode with an adjustable duty cycle provided by an embodiment of the present invention; Figure 6 Schematic diagram of a first logic control signal of a continuous pulse mode, a second logic control signal of a continuous pulse mode and a pulse excitation signal of a continuous pulse mode provided by an embodiment of the present invention; Figure 3 As shown, the first waveform generator 20 includes: an N-bit counter 21, a comparator 22, a parity separator 23, a first signal output unit 24 and a second signal output unit 25;
[0048] An N-bit counter 21, used for accumulating from 0 to N under the control of the waveform generation clock signal;
[0049] The comparator 22 is used to compare the accumulated number of bits n with the preset number of bits num, and output a separation signal to the odd-even separator 23 when the accumulated number of bits n is smaller than the preset number of bits num;
[0050] An odd-even separator 23 is used for separating the accumulated number of bits n into odd and even numbers and outputting odd and even numbers of bits;
[0051] A first signal output unit 24, configured to generate a first logic control signal IN_P according to an odd number of bits;
[0052] The second signal output unit 25 is used to generate a second logic control signal IN_N according to an even number of bits.
[0053] Among them, the first signal output unit 24 and the second signal output unit 25 can be D flip-flops; the specific principle of the first waveform generator 20 converting the waveform generation clock signal into the first logic control signal IN_P and the second logic control signal IN_N is: the N-bit counter 11 accumulates from 0 to N under the control of the waveform generation clock, when the N-bit counter 21 outputs the accumulated bit number n (1<n<N), the comparator 22 compares the accumulated bit number n with the preset bit number num, and when the accumulated bit number n is less than the preset bit number num, the separation signal is output to the parity separator 23; the parity separator 23 confirms the accumulated bit number n as an odd number, and generates the first logic control signal IN_P; the parity separator 23 confirms the accumulated bit number n as an even number, and generates the second logic control signal IN_N; and when the accumulated bit number n is greater than the preset bit number num, the output signal is stopped, and the N-bit counter 21 is cleared and restarted to accumulate; thus, the parameter num can be set to control the number of pulses of each logic control signal, thereby realizing the output mode of each logic control signal (such as Figure 4 As shown, for example, when N is 100 and num=1, each logic control signal and pulse excitation signal of the single pulse mode are output; Figure 5 As shown, when N is 100 and num=2-99, the logic control signals and pulse excitation signals of the continuous pulse mode with adjustable duty cycle are output; Figure 6 As shown, when N is 100, num=100, the logic control signals and pulse excitation signals of the continuous pulse mode are output).
[0054] In addition, the width of a pulse in each logic control signal is one cycle of the waveform generating clock signal; the time at which the high levels of the first logic control signal and the second logic control signal appear differs by one pulse width; since the frequency of the waveform generating clock signal is adjustable and one cycle of the waveform generating clock signal is adjustable, the width of a pulse in the logic control signal in each mode is adjustable, and the frequency of each logic control signal in each mode is adjustable.
[0055] Optionally, in some embodiments, Figure 7 Schematic diagram of a trigger signal provided by an embodiment of the present invention; N-bit counter 21 is specifically used to generate a trigger signal trig from a waveform generating clock signal, and accumulate from 0 to N under the control of the trigger signal trig. When the trigger signal trig rises, the first logic control signal IN_P generates a pulse.
[0056] Optional, continue to refer to Figure 3 The first pulse excitation unit 30 includes: a first logic control switch 31 and a second logic control switch 32; the control end of the first logic control switch 31 receives a first logic control signal; the control end of the second logic control switch 32 receives a second logic control signal; the first end of the first logic control switch 31 is electrically connected to the positive high voltage source VPP; the second end of the first logic control switch 31 and the first end of the second logic control switch 32 serve as the output end of the first pulse excitation unit 30 to output the pulse excitation signal; the second end of the second logic control switch 32 is electrically connected to the negative high voltage source VNN.
[0057] Among them, the first logic control switch 31 and the second logic control switch 32 can be logic switches such as transistor MOSFET, triode, etc.; the first logic control switch 31 and the second logic control switch 32 respectively control the introduction of the positive high voltage power supply VPP and the negative high voltage power supply VNN; specifically, the first logic control signal controls the opening and closing of the first logic control switch 31 on the positive high voltage side, and the second logic control signal controls the opening and closing of the second logic control switch 32 on the positive high voltage side. When the first logic control signal outputs a high level and the second logic control signal outputs a low level, the first logic control switch 31 is in the on state and the second logic control switch 32 is in the off state, then the positive high voltage is output, otherwise, the negative high voltage is output. In this way, the two logic control switches are alternately turned on and off, and an alternating pulse excitation signal OUT can be generated. In addition, the power amplification of the pulse excitation signal can be achieved by using the external input voltage of the positive high voltage power supply VPP and the negative high voltage power supply VNN.
[0058] Optional, see Figure 3 The clock controller 10 includes: a pre-frequency division counter 11, a phase-frequency detector 12, a loop filter 13, a voltage-controlled oscillator 14 and a post-frequency division counter 15; the pre-frequency division counter 11 is used to divide the basic clock signal by N bits (f in is the input frequency of the basic clock signal, and the output reference frequency of the basic clock signal after frequency division is ); a phase-frequency detector 12, used to detect the phase size of the basic clock signal after the frequency division processing and the output reference frequency size of the basic clock signal; and also used to detect the phase size of the feedback clock signal and the frequency size of the feedback clock signal; wherein the feedback clock signal is the clock signal output after the basic clock signal after the frequency division processing passes through the phase-frequency detector, the loop filter and the voltage-controlled oscillator (generally, since the frequency and phase of the clock signal output after the basic clock signal after the frequency division processing passes through the phase-frequency detector, the loop filter and the voltage-controlled oscillator have a certain deviation from the frequency and phase of the basic clock signal after the frequency division processing); a loop filter 13, used to output an offset elimination control signal to the voltage-controlled oscillator 14 according to the phase difference between the phase size of the basic clock signal and the phase size of the feedback signal, and the frequency difference between the output reference frequency size of the basic clock signal and the frequency size of the feedback signal; the voltage-controlled oscillator 14, used to output a stable clock signal according to the offset elimination control signal; wherein the output frequency of the stable clock signal is the same as the output reference frequency of the basic clock signal after the frequency division processing (f REF The post-frequency division counter 15 is used to divide the output frequency of the stable clock signal by M bits to output waveforms of different frequencies to generate clock signals (f REF / M is the output frequency of the stable clock signal after the M-bit frequency division process), so this embodiment can make the frequency of the basic clock signal after the frequency division process stable output through the phase-frequency detector 12, the loop filter 13, and the voltage-controlled oscillator 14, further improving the stable output of the subsequent pulse excitation signal; through the pre-frequency division counter 11 and the post-frequency division counter 15, the input frequency of the basic clock signal is converted into a waveform with different frequencies to generate a clock signal, so that the frequency of the first logic control signal of each mode is adjustable; the frequency of the second logic control signal of each mode is adjustable; finally, the multi-frequency output of the pulse excitation signal is achieved.
[0059] Optionally, further optimization is performed based on the above embodiment. Figure 8 is a schematic diagram of the structure of another pulse excitation signal generator provided by an embodiment of the present invention. Figure 8 As shown, in some embodiments, the pulse excitation signal generator also includes: multiple second pulse excitation units 40; each second pulse excitation unit 40 is used to generate a pulse excitation signal of different modes at a specific frequency according to a first logic control signal of different modes at a specific frequency and a second logic control signal of different modes at a specific frequency.
[0060] Among them, when the first waveform generator 20 outputs the first logic control signal and the second logic control signal, the first logic control signal and the second logic control signal are simultaneously output to multiple second pulse excitation units 40, and each second pulse excitation unit 40 generates a pulse excitation signal according to the first logic control signal and the second logic control signal, thereby realizing the output of multiple pulse excitation signals and realizing the multi-channel output of the pulse excitation signal generator; it can be understood that the output of each channel pulse excitation signal can also output pulse excitation signals of different modes; the pulse excitation signals of different modes are generated by the second pulse excitation unit 40 according to the first logic control signals of different modes and the second logic control signals of different modes. In addition, since the clock controller 10 outputs waveforms of different frequencies to generate clocks, the frequencies of the pulse excitation signals of each channel are also adjustable.
[0061] Optional, see Figure 3 and Figure 8 The second pulse excitation unit 40 has the same structure as the first pulse excitation unit 30. The second pulse excitation unit 40 is composed of two logic control switches; the specific connection relationship is the same as the connection relationship of each logic control switch in the first pulse excitation unit 30, which will not be repeated here.
[0062] Optionally, in some other embodiments, Fig. 9 is a schematic diagram of the structure of another pulse excitation signal generator provided by an embodiment of the present invention. Fig. 9 As shown, the pulse excitation signal generator also includes: a plurality of second waveform generators 50 and a plurality of third pulse excitation units 60; each second waveform generator 50 corresponds to each third pulse excitation unit 60 one by one; each second waveform generator 50 is used to convert a waveform generation clock signal at a specific frequency into a first logic control signal of a different mode at a specific frequency and a second logic control signal of a different mode at a specific frequency, and output them to the corresponding third pulse excitation unit 60; each third pulse excitation unit 60 is used to generate a pulse excitation signal of a different mode at a specific frequency according to the first logic control signal of a different mode at a specific frequency and the second logic control signal of a different mode at a specific frequency output by the corresponding second waveform generator.
[0063] Among them, the waveform generation clock signal output by the clock controller 10 can be output to each second waveform generator 50 at the same time, and each second waveform generator 50 converts the waveform generation clock signal into a first logic control signal and a second logic control signal, and outputs it to the corresponding third pulse excitation unit 60; each third pulse excitation unit 60 generates a pulse excitation signal according to the first logic control signal and the second logic control signal output by the corresponding second waveform generator, thereby realizing the multi-channel output of the pulse excitation signal and the multi-channel output of the pulse excitation signal generator;
[0064] It can be understood that the output of each channel pulse excitation signal can also output pulse excitation signals of different modes; the pulse excitation signals of different modes are generated by the third pulse excitation unit 50 according to the first logic control signals of different modes and the second logic control signals of different modes output by the second waveform generator 50. In addition, since the clock controller 10 outputs waveform generation clocks of different frequencies, the frequencies of the pulse excitation signals of each channel can also be adjusted.
[0065] Optional, see Figure 3 and Fig. 9 , the second waveform generator 50 has the same structure as the first waveform generator 20; the third pulse excitation unit 60 has the same structure as the first pulse excitation unit 30. Among them, the third pulse excitation unit 40 is composed of two logic control switches; the specific connection relationship is the same as the connection relationship of each logic control switch in the first pulse excitation unit 30, which will not be repeated here. The second waveform generator 50 is composed of an N-bit counter 21, a comparator 22, an odd-even separator 23, a first signal output unit 24 and a second signal output unit 25, and the specific functions are the same as those in the first waveform generator 20, which will not be repeated here.
[0066] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A pulse excitation signal generator, characterized in that: include: A clock controller, a first waveform generator and a first pulse excitation unit; The clock controller is used to convert the basic clock signal into a waveform of a characteristic frequency to generate a clock signal; The first waveform generator is used to convert the waveform generating clock signal of the characteristic frequency into a first logic control signal of a different mode at the characteristic frequency and a second logic control signal of a different mode at the characteristic frequency; The first pulse excitation unit is used to generate pulse excitation signals of different modes under characteristic frequencies according to the first logic control signals of different modes under characteristic frequencies and the second logic control signals of different modes under characteristic frequencies.
2. The pulse excitation signal generator according to claim 1, characterized in that: The first waveform generator includes: an N-bit counter, a comparator, an odd-even separator, a first signal output unit and a second signal output unit; The N-bit counter is used to accumulate from 0 to N under the control of the waveform generating clock signal; The comparator is used to compare the size of the accumulated number of bits with the preset number of bits, and output a separation signal to the odd-even separator when the accumulated number of bits is smaller than the preset number of bits; The odd-even separator is used to separate the accumulated bits into odd and even bits and output odd bits and even bits; The first signal output unit is used to generate a first logic control signal according to the odd number of bits; The second signal output unit is used to generate a second logic control signal according to the even-numbered bit number.
3. The pulse excitation signal generator according to claim 1, characterized in that: The first pulse excitation unit includes: a first logic control switch and a second logic control switch; The control end of the first logic control switch receives the first logic control signal; the control end of the second logic control switch receives the second logic control signal; the first end of the first logic control switch is electrically connected to the positive high voltage source; the second end of the first logic control switch and the first end of the second logic control switch serve as the output ends of the pulse excitation unit to output the pulse excitation signal; the second end of the second logic control switch is electrically connected to the negative high voltage source.
4. The pulse excitation signal generator according to claim 1, characterized in that: The clock controller comprises: a pre-frequency division counter, a phase-frequency detector, a loop filter, a voltage-controlled oscillator and a post-frequency division counter; The pre-frequency division counter is used to divide the basic clock signal by N bits; The phase-frequency detector is used to detect the phase size of the basic clock signal after the frequency division process and the output reference frequency size of the basic clock signal; and is also used to detect the phase size of the feedback clock signal and the frequency size of the feedback clock signal; wherein the feedback clock signal is the clock signal output after the basic clock signal after the frequency division process passes through the phase-frequency detector, the loop filter and the voltage-controlled oscillator; The loop filter is used to output an offset elimination control signal to the voltage-controlled oscillator according to a phase difference between a phase size of the basic clock signal and a phase size of the feedback signal, and a frequency difference between an output reference frequency size of the basic clock signal and a frequency size of the feedback signal; The voltage-controlled oscillator is used to output a stable clock signal according to the offset elimination control signal; wherein the output frequency of the stable clock signal is the same as the output reference frequency of the basic clock signal after the frequency division process; The post-frequency division counter is used to perform M-bit frequency division processing on the output frequency of the stable clock signal.
5. The pulse excitation signal generator according to claim 1, characterized in that: Also includes: A plurality of second pulse excitation units; Each of the second pulse excitation units is used to generate pulse excitation signals of different modes at a specific frequency according to the first logic control signals of different modes at a specific frequency and the second logic control signals of different modes at a specific frequency.
6. The pulse excitation signal generator according to claim 5, characterized in that: The structure of the second pulse excitation unit is the same as that of the first pulse excitation unit.
7. The pulse excitation signal generator according to claim 1, characterized in that: Also includes: A plurality of second waveform generators and a plurality of third pulse excitation units; Each of the second waveform generators corresponds to each of the third pulse excitation units one by one; Each of the second waveform generators is used to convert the waveform generation clock signal at a specific frequency into a first logic control signal of a different mode at a specific frequency and a second logic control signal of a different mode at a specific frequency, and output them to the corresponding third pulse excitation unit; Each of the third pulse excitation units is used to generate a pulse excitation signal of different modes at a specific frequency according to the first logic control signal of different modes at a specific frequency output by the corresponding second waveform generator and the second logic control signal of different modes at a specific frequency.
8. The pulse excitation signal generator according to claim 7, characterized in that: The second waveform generator has the same structure as the first waveform generator; the third pulse excitation unit has the same structure as the first pulse excitation unit.
9. The pulse excitation signal generator according to claim 2, characterized in that: The N-bit counter is specifically used to generate a trigger signal when the waveform generates a clock signal, and accumulate from 0 to N under the control of the trigger signal.