Memory system, operating method thereof, and readable storage medium

Abstract

The embodiment of the invention provides a memory system and an operation method thereof. The memory system comprises at least one memory device and a memory controller coupled with the at least one memory device, the memory controller is configured to respond to a failure of a first read operation when a read operation is executed on a memory area in the memory device, and execute a part of or all of at least two read error processing flows.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a memory system and an operating method thereof, and a readable storage medium. Background Art

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems thereof. Summary of the invention

[0004] According to one aspect of an embodiment of the present disclosure, there is provided a memory system, including:

[0005] at least one memory device and a memory controller coupled to the at least one memory device;

[0006] The memory controller is configured to:

[0007] In response to a failure of an initial read operation when a read operation is performed on a storage area in the memory device, a part of or all of at least two read error handling processes are performed.

[0008] In some embodiments, the read error processing flow of the memory device includes a first type of read error processing flow and a second type of read error processing flow executed sequentially; the average processing time of the first type of read error processing flow is shorter than the average processing time of the second type of read error processing flow.

[0009] In some embodiments, in response to a failure of a first read operation after a storage area in the memory device is restored to an operating state, the first type of read error handling process is executed at least twice.

[0010] In some embodiments, the memory controller is configured to:

[0011] A preset time period is set between two adjacent first-type read error processing processes.

[0012] In some embodiments, the memory controller is configured to:

[0013] In response to the read operation still failing after executing the first type of read error handling flow at least twice, executing the second type of read error handling flow.

[0014] In some embodiments, the first type of read error handling process includes: a reread operation and a soft decoding operation;

[0015] The second type of read error processing flow includes: Redundant Array of Independent Disks RAID operation.

[0016] In some embodiments, the memory controller is configured to:

[0017] During each execution of the first type of read error handling process, in response to the re-read operation failing, a soft decoding operation is performed on the read data.

[0018] In some embodiments, the memory controller is configured to:

[0019] In response to the read operation still failing after executing the second type of read error handling process, a read failure message is issued.

[0020] In some embodiments, the first type of read error handling process includes: a reread operation;

[0021] The second type of read error processing flow includes: a soft decoding operation.

[0022] In some embodiments, the memory controller is configured to:

[0023] Acquire a first duration; the first duration being greater than the duration for the storage area in the memory device to recover to an operating state;

[0024] The number of executions of the first type of read error handling process is determined according to the first time length.

[0025] In some embodiments, the memory controller is configured to:

[0026] The first duration is determined according to the temperature of the memory device; the first duration is negatively correlated with the temperature of the memory device.

[0027] In some embodiments, the memory controller is configured to:

[0028] In response to a failure of a first read operation after the storage area in the memory device is restored to an operating state, a first type of read error processing flow is executed multiple times until a preset number of times is reached.

[0029] In some embodiments, before a read operation is performed on a storage area in the memory device, no operation is performed on the storage area in the memory device for a predetermined period of time; or

[0030] The first read operation when performing a read operation on the storage area in the memory device is the first read operation when performing a read operation on the storage area in the memory device after the memory system is powered on.

[0031] In some embodiments, the memory system includes: a universal flash storage UFS device or an embedded multimedia card eMMC device.

[0032] According to one aspect of an embodiment of the present disclosure, there is provided a method for operating a memory system, including:

[0033] In response to an access command, performing a read operation on a storage area in the memory device;

[0034] In response to a failure of an initial read operation when a read operation is performed on a storage area in the memory device, a part of or all of at least two read error handling processes are performed.

[0035] In some embodiments, the read error processing flow of the memory device includes a first type of read error processing flow and a second type of read error processing flow executed sequentially; the average processing time of the first type of read error processing flow is shorter than the average processing time of the second type of read error processing flow.

[0036] In some embodiments, the performing of at least two read error handling processes, part of the process or the whole process, includes:

[0037] In response to a failure of a first read operation after a storage area in the memory device is restored to an operating state, a first type of read error handling process is executed at least twice.

[0038] In some embodiments, the method further comprises:

[0039] A preset time period is set between two adjacent first-type read error processing processes.

[0040] In some embodiments, the method further comprises:

[0041] In response to the read operation still failing after executing the first type of read error handling flow at least twice, the second type of read error handling flow is executed.

[0042] In some embodiments, the first type of read error handling process includes: a reread operation and a soft decoding operation;

[0043] The second type of read error processing flow includes: Redundant Array of Independent Disks RAID operation.

[0044] In some embodiments, the method further comprises:

[0045] During each execution of the first type of read error handling process, in response to the re-read operation failing, a soft decoding operation is performed on the read data.

[0046] In some embodiments, the method further comprises:

[0047] In response to the read operation still failing after executing the second type of read error handling flow, a read failure message is issued.

[0048] In some embodiments, the first type of read error handling process includes: a reread operation;

[0049] The second type of read error processing flow includes: a soft decoding operation.

[0050] In some embodiments, the method further comprises:

[0051] Acquire a first duration; the first duration being greater than the duration for the storage area in the memory device to recover to an operating state;

[0052] The number of executions of the first type of read error handling process is determined according to the first time length.

[0053] In some embodiments, the method further comprises:

[0054] The first duration is determined according to the temperature of the memory device; the first duration is negatively correlated with the temperature of the memory device.

[0055] In some embodiments, the method further comprises:

[0056] In response to a failure of a first read operation after the storage area in the memory device is restored to an operating state, a first type of read error processing flow is executed multiple times until a preset number of times is reached.

[0057] In some embodiments, before a read operation is performed on a storage area in the memory device, no operation is performed on the storage area in the memory device for a predetermined period of time; or

[0058] The first read operation when performing a read operation on the storage area in the memory device is the first read operation when performing a read operation on the storage area in the memory device after the memory system is powered on.

[0059] According to one aspect of an embodiment of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and when the computer program is executed, the operating method is implemented.

[0060] An embodiment of the present disclosure provides a memory system, which includes at least one memory device and a memory controller coupled to the at least one memory device; the memory controller is configured to: in response to the failure of the first read operation after the storage area in the memory device is restored to an operating state, execute part of or all of at least two read error handling processes, without adding firmware or program steps to the original read operation process, and utilize the default read operation firmware or program of the original memory system to eliminate the situation where the first read error rate is high when the memory system is restored to an operating state, thereby improving the read efficiency of the memory system and facilitating the simplification of firmware or programs to reduce development costs and reduce the processing load of the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0062] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0063] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0064] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0065] Figure 3b is a schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0066] Figure 4 is a cross-sectional schematic diagram of a memory array including a NAND memory string according to an embodiment of the present disclosure;

[0067] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0068] Figure 6 A schematic diagram of a conventional read operation process according to an embodiment of the present disclosure;

[0069] Figure 7a Schematic diagram of a read error handling process according to an embodiment of the present disclosure Figure 1 ;

[0070] Figure 7b Schematic diagram 2 of a read error handling process according to an embodiment of the present disclosure;

[0071] Figure 7cSchematic diagram 3 of a read error handling process according to an embodiment of the present disclosure;

[0072] Figure 8 The flowchart of the operating method of the memory system according to one embodiment of the present disclosure is as follows Figure 1 ;

[0073] Fig. 9 FIG2 is a second flowchart of an operating method of a memory system according to an embodiment of the present disclosure.

[0074] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0075] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0076] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0077] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0078] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0079] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0080] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0081] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0082] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0083] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0084] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0085] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0086] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0087] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0088] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0089] Figure 3a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, every two rows of memory cell rows are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (Blocks in English), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (Fingers in English), and the upper selection gate isolation structure disposed in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two storage slices (Strings in English). Figure 3a The memory block shown in FIG. 1 includes 6 memory cells. In practical applications, the number of memory cells in a memory block is not limited thereto. The memory cells in a memory block coupled to a certain word line can be called a memory page (expressed in English as Page).

[0090] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0091] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as a three-dimensional NAND-type memory cell array for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0092] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0093] like Figure 3bAs shown in , each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and an upper select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0094] like Figure 3bAs shown in , the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in the selected memory block 304a, the source lines 314 coupled to the selected memory block 304a and the unselected memory blocks 304b in the same plane as the selected memory block 304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic data unit for programming operations. The size of a page 320 in bits can be related to the number of NAND memory strings 308 coupled by word lines 318 in one memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding page 320 and a gate line coupling the control gates. In combination with the previous Figure 3a A page 320 includes a plurality of memory cells 306, wherein the plurality of memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and the plurality of memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into a plurality of memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure. The memory cells in the memory slices sharing the same word line form a programmable (read / write) page.

[0095] Figure 4 1 shows a cross-sectional schematic diagram of an exemplary memory cell array 301 including NAND memory strings 308 according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 may determine the number of memory cells included in the memory cell array 301.

[0096] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0097] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0098] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0099] Return to reference Figure 3b, the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0100] The page buffer / sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512, and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0101] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0102] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel precharge stage, a channel boosting stage, a programming pulse stage, and a recovery stage. In the channel precharge stage, the voltage generator may generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boosting voltage, etc.; in the channel boosting stage, the channel boosting voltage may be applied to the selected word line; in the programming pulse stage, the target voltage for each programming may be applied to the selected word line. In the recovery stage, the voltage of both the unselected word line and the selected word line may be reduced to the corresponding voltage, such as Vcc, Vdd. In the recovery stage, the voltage may be reduced to the corresponding voltage by one or more step-by-step steps, such as first reducing the voltage to an intermediate voltage, and maintaining the intermediate voltage for a period of time, and then reducing the voltage to the corresponding voltage.

[0103] The control logic 512 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0104] In some specific application embodiments of the memory system, when the system 100 is running, the host 108 sends a command to the memory system 102 in response to the task requirements of the user, and obtains data from the memory system 102 or stores data in the memory system 102. When the host 108 processes the task requirements from the user, it needs to exchange data with the memory system 102. The memory controller 106, the memory device 104, and various interfaces in the memory system 102 are in a working state. At this time, it can be defined that the memory system 102 is in an operating state, or the storage area in the memory device 104 is in an operating state. The storage area of ​​the memory device 104 in this embodiment can be Figure 3a One, more or all of the storage blocks shown in; it may also include one, more or all of the storage slices in a storage block. The memory device 104 may include multiple Dies, and the storage area in the memory device 104 may include one, more or all of the Dies, and one Die includes multiple storage blocks. Die is a semiconductor structure including a storage cell array cut from a wafer according to a cutting path during the manufacturing process of the memory device 104, and multiple Dies are formed into a chip through hybrid bonding or other integration methods. The operating state may include any one of a programming operation, a read operation or an erase operation. The storage area in the memory device 104 is in an operating state, which may include a part of the storage area (part of the storage cell array) being in an operating state, or may include all the storage areas (all the storage cell arrays) being in an operating state.

[0105] In some embodiments, the memory controller 106 receives a command from the host 108 and controls the storage area in the memory device 104 to perform a programming operation, a reading operation, or an erasing operation, and the memory device 104 is in an operating state. In some embodiments, when no command from the host 108 is received, the memory controller 106 can control the memory device 104 to perform operations such as garbage collection, wear leveling, etc.

[0106] In some specific application embodiments of the memory system, when the storage area in the memory device 104 has not been operated for a period of time, that is, the storage area in the memory device 104 has been idle for a period of time without being programmed, read or erased, when the idle storage area needs to be read, the first read will have a high Fail Bit Count (FBC), and there will be many read errors. The FBC of subsequent reads will drop to a normal level. This phenomenon can be called temporary read errors (TRE). The occurrence of the TRE phenomenon will reduce the service quality of the memory system to a certain extent.

[0107] In some embodiments, when the storage area in the memory device 104 is idle for a period of time and is not operated, the memory device 104 may be in a powered-on state, but the corresponding operating voltage is not applied to the word line or the bit line. The memory device 104 may also be in a powered-off state (e.g., a shutdown state), and the TRE phenomenon will occur when it is restored to the operating state. Among them, the TRE phenomenon when the non-operating state at power-off is restored to the operating state after power-on is more serious than the TRE phenomenon when the non-operating state at power-on is restored to the operating state.

[0108] The reason why the NAND memory has TRE can be explained based on the physical structure of the memory cell. Figure 4 As shown, the NAND memory string 308 has a semiconductor channel, which may include polysilicon or other semiconductor materials. The difference in the occupancy rate of the grain boundary traps (GBT) of the semiconductor channel is one of the reasons for the large difference in FBC between the first read operation and the second read operation. Taking the polysilicon semiconductor channel as an example, when the memory cell in the NAND memory string 308 is programmed (written), due to the high voltage of the word line, the GBT of the polysilicon channel at the quasi-Fermi level is fully occupied. After the programming is completed, as the word line voltage gradually decreases from the programming voltage to 0V, the electrons in the GBTs of different energy levels will gradually migrate and leak. When the NAND memory string 308 changes from the operating state to the non-operating state without programming, reading, and erasing, the GBTs with leakage in the polysilicon channel will be more, resulting in a lower GBT occupancy rate. When the NAND memory string 308 is restored to the operating state, the first read operation may result in a higher read FBC due to the lower GBT occupancy rate. In some other embodiments, the charge capture / storage layer of the NAND storage string 308 may also reduce the GBT occupancy rate because the word line does not apply voltage, which may also cause the TRE phenomenon of the memory device 104. Exemplarily, some storage areas in the memory device 104 store cold data, which is not often programmed, read or erased. The storage area storing this part of cold data will be in an unaccessed state for a long time. When it is restored to the operating state, a more serious TRE phenomenon occurs, and the FDC read for the first time is higher.

[0109] In the second read operation after the first read operation, because the read voltage or pass voltage (Vpass) applied on the word line during the first read operation can be greater than 5V, the leaky GBT in the polysilicon channel is refilled, the occupancy rate of the GBT is high and close to the occupancy rate when it is just programmed, and the read FBC is small. It can be seen that when the GBT occupancy rate of the polysilicon channel is high, the read FBC will be small, the longer the processing time (duration) of the first read operation is, the longer the time for the word line to apply the voltage is, the more leaky GBTs are filled, and the less the read FBC is. The non-operating state here includes power-on and power-off. The TRE when the non-operating state of power-off is restored to the operating state will be more serious than the TRE when the non-operating state of power-on is restored to the operating state. The TRE at low temperature is more serious than the TRE at high temperature. The thicker the polysilicon channel film layer, the more serious the TRE. The more serious the TRE requires more first read processing time to eliminate.

[0110] In some example embodiments of the present disclosure, the TRE phenomenon can be eliminated or mitigated by optimizing the operating logic of the memory system 102 and the manufacturing process of the memory device 104, thereby reducing the time for the memory device 104 to recover from the non-operating state to the operating state during the regular read operation. For example, the TRE can be reduced by reducing the film thickness of the semiconductor channel; the uniformity of the film layer of the semiconductor channel can be improved to reduce the gap defects to reduce the TRE. For example, the first read operation can be defined as a pseudo-read operation, and the second read operation thereafter is used as a regular read operation process. The pseudo-read operation here can last for a period of time to eliminate the TRE phenomenon, such as 60ms or longer. The memory controller 106 determines that the memory device 104 has recovered to the regular read level by monitoring that the FBC during the pseudo-read is less than the preset value of the regular read, so that the memory system 102 is restored to the regular read operation.

[0111] The processing time of the pseudo-read operation can be determined by setting pseudo-read operations with different processing times for the memory device 104, testing the reading FBC to determine the time, and establishing a test model to use machine learning and big data analysis to determine the time to eliminate TRE under various working conditions. On this basis, the processing time can be appropriately increased to obtain a better reading effect. For example, at 25°C, the processing time of the pseudo-read operation of the memory device 104 to eliminate TRE is 60ms; at 55°C, the processing time of the pseudo-read operation of the memory device 104 to eliminate TRE is 20ms; at 85°C, the processing time of the pseudo-read operation of the memory device 104 to eliminate TRE is 10ms. The processing time is negatively correlated with the temperature. The longest processing time of the pseudo-read operation is determined based on the lowest operating temperature in the design standard of the memory device 104. When the memory device 104 is at other high temperatures, the TRE phenomenon can also be eliminated. Temperature compensation can also be performed based on the corresponding relationship between the processing time and temperature, and the processing time can be appropriately reduced based on the longest processing time at the lowest temperature to eliminate the TRE phenomenon under different working conditions.

[0112] Reference Figure 6 As shown, the conventional read operation process in this embodiment may include a default read operation (FW default read) set in the firmware, a reread operation (Read retry) when the default read operation fails, a soft decoding operation (Soft decode) when the reread operation fails, a RAID operation when the soft decoding fails, and a read operation stops after the RAID operation fails and the read fails due to the inability to correct the error, and the memory controller 106 sends a read failure (Readfail) signal to the host 108. The error correction operations such as the reread operation, soft decoding and RAID operation can be controlled by the error correction module (e.g., ECC module) in the memory controller 106 to perform the memory device 104, and the control command is sent by the memory controller 106 to the memory device 104 via the interface 516, and the memory device 104 feeds back the read information to the memory controller 106 via the interface 516. It should be pointed out that after any one of the reread operation, soft decoding and RAID operation is read successfully, the subsequent operation can be stopped.

[0113] In some exemplary embodiments, after the memory controller 106 sends the execution command, logical-physical address, and processing time of the pseudo read operation to the memory device 104, the memory device 104 does not read information from the storage unit and sends it to the memory controller 106 after executing the pseudo read operation, so as to save the bandwidth of the bus or interface 516. Therefore, the pseudo read operation is generally independent of Figure 6Based on this, setting a dummy read operation to eliminate the TRE phenomenon will introduce additional firmware or operating procedures, increase the complexity of the firmware or procedures of the memory controller 106 and the memory device 104, and reduce the efficiency of the read operation.

[0114] According to some aspects of the embodiments of the present disclosure, a memory system 102 and an operating method of the memory system 102 are provided. The memory system 102 includes: at least one memory device 104 and a memory controller 106 coupled to the at least one memory device 104; the memory controller 106 is configured to:

[0115] In response to a failure of an initial read operation when performing a read operation on a storage area in the memory device 104 , at least two partial or entire read error handling processes are executed.

[0116] In some embodiments, before performing a read operation on a storage area in the memory device 104, no operation is performed on the storage area in the memory device 104 for a predetermined time; wherein the operation may include a programming operation, a read operation, or an erase operation;

[0117] or

[0118] The first read operation when performing a read operation on the storage area in the memory device 104 is the first read operation when performing a read operation on the storage area in the memory device 104 after the memory system 102 is powered on.

[0119] In the embodiment of the present disclosure, the first read operation may be the first read operation after the powered-on memory device 104 is kept idle for a period of time (preset time), or the first read operation after the powered-off memory device 104 is powered on again, and may also be referred to as the first read operation after the storage area in the memory device 104 is restored to the operating state. The test method of the preset time may include: setting two read operations with different interval lengths, testing the FBC increase of the second read operation compared to the first read operation to establish a corresponding relationship with the interval length, the longer the interval length, the more serious the TRE phenomenon, and the more the FBC increases. When the preset time exceeds a certain value, it is necessary to execute part of the process or all of the processes in at least two read error handling processes to eliminate the TRE phenomenon.

[0120] According to some aspects of the embodiments of the present disclosure, the embodiments of the present disclosure provide a memory system 102 and an operating method of the memory system 102, wherein the memory system 102 includes: at least one memory device 104 and a memory controller 106 coupled to the at least one memory device 104; the memory controller 106 is configured to: in response to the failure of the first read operation after the storage area in the memory device 104 is restored to an operating state, execute part or all of at least two read error handling processes.

[0121] The memory controller 106 exchanges data with the host 108 through an interface (e.g., a PCIe interface, a SATA interface). The memory controller 106 receives a read command from the host 108 through an interface such as PCIe, controls the control logic in the memory device 104 to read the storage unit of the corresponding physical address in the storage unit array according to the logical-physical address implicit table, and sends the read information to the memory controller 106, which then sends the read information to the host 108. When the memory controller 106 controls the memory device 104 to perform a default read operation, the read operation can perform hard decoding, and if a read error occurs, an error correction operation, such as ECC error correction, will be triggered.

[0122] When the host 108 needs relevant data, it sends a read instruction to the memory controller 106. The memory controller 106 responds to the data read instruction of the host 108 and controls the memory device 104 to recover from the non-operating state to the operating state. At this time, the memory device 104 and the interfaces such as PCIe are powered on and in the rated working state. The memory controller 106 controls the memory device 104 to read the storage unit of the physical address corresponding to the corresponding logical address. Or the memory controller 106 can control the memory device 104 to perform garbage collection, wear leveling and other operations when there is no instruction from the host 108 based on the management needs or performance optimization of the memory system 102 itself. The memory controller 106 controls the memory device 104 to recover to the operating state.

[0123] The memory controller 106 controls the memory device 104 based on Figure 6 The conventional read operation flow shown first performs a first default read operation on the corresponding memory cell, and the read voltage is the default read voltage in the relevant read voltage comparison table. The read operation may succeed or fail to perform the first default read operation due to the TRE phenomenon. When the memory controller 106 determines that the first default read operation fails, the memory controller 106 controls the memory device 104 to perform part or all of the two read error handling processes. The read error handling process in the embodiment of the present disclosure may include Figure 6The execution order and logic of the error correction operations such as the reread operation, soft decoding, and independent disk redundant array RAID operation are also as shown. Figure 6 shown.

[0124] Specifically, refer to Figure 7a As shown, when the memory controller 106 determines that the first default read operation fails, two or more reread operations are performed, and the reread operations may apply hard decoding operations. A preset time interval may be set between two adjacent reread operations.

[0125] In some specific embodiments, the determination process of the reread voltage may include: the memory controller 106 (for example, the ECC module in the memory controller 106) obtains the corresponding voltage offset value by querying the corresponding reread table, and the voltage offset value may be a positive offset value or a negative offset value, and obtains the reread voltage by summing it with the default read voltage, and the memory controller 106 controls the memory device 104 to perform a reread operation on the storage unit of the corresponding physical address using the reread voltage. It should be noted that the memory controller 106 may adopt a polling method when querying the reread table, and a reread table may include multiple sub-tables, such as m sub-tables, where m is a natural number greater than 1. Each sub-table may include a voltage offset value of the corresponding storage state of the corresponding storage unit, and queries are performed from the first sub-table to the mth sub-table in sequence, and a voltage offset value is obtained by querying once, and then a reread voltage is obtained by summing. The memory device 104 uses the reread voltage for reading. Therefore, a re-read operation may have at most m sub-read operations, and this embodiment does not impose any limitation on this. The normal read operation flow can be restored as long as the total processing time is sufficient to eliminate the TRE phenomenon.

[0126] In some specific embodiments, the processing time of each reread operation can be the average processing time obtained by multiple tests of the memory device 104 before leaving the factory, and the total processing time of multiple reread operations (excluding the preset interval time) is greater than or equal to the processing time of the pseudo read in some embodiments, that is, greater than or equal to the minimum time to eliminate the TRE phenomenon at the current temperature. The total processing time can be the first time to eliminate the TRE phenomenon determined according to the temperature of the memory device 104, that is, the time when the memory device 104 is restored to the temperature where it can be executed. Figure 6 The duration of the operation state for a typical read operation flow is shown.

[0127] For example, at 25°C, the total processing time of multiple reread operations is greater than or equal to 60ms. The preset time range of the interval may include: 0 to 100ms, for example, 10ms; this preset time can be determined according to the GBT leakage rate of the semiconductor channel when the memory device 104 is in the operating state. During the preset time interval, the GBT of the semiconductor channel basically does not leak or leaks less, and the GBT occupancy rate basically does not decrease or decreases less so as not to cause a large increase in FBC. At this time, the default read voltage can still distinguish different storage states of the memory cell. Within this preset time interval, the memory controller 106 can determine whether the reread operation is read through, or whether the statistical FDC meets the preset conditions of the operating state and determines that the TRE phenomenon is eliminated; thereby determining whether to continue the subsequent reread operation, thereby saving operation time and improving the reading rate. When multiple reread operations fail, the TRE phenomenon at this time has been eliminated. If the read operation still fails, it can be determined that the read operation failure is not caused by the TRE phenomenon, and a soft decoding operation can be performed at this time.

[0128] In some embodiments, continue to refer to Figure 7a As shown, when a reread operation is performed once, that is, the read operation is successful, or the preset number of reread operations is not reached, that is, the total processing time of multiple reread operations does not reach the preset time (first time), the program can be exited. Figure 7a The read error handling process shown in the figure can be entered during the next read. Figure 6 In some other embodiments, regardless of whether the re-read operation is successful or not, multiple re-read operations must be performed to ensure that the TRE phenomenon is eliminated. If the last re-read operation fails, one or more re-read operations may be performed, or a soft decoding operation may be performed.

[0129] In some embodiments, reference Figure 7b As shown, with the reread operation and the soft decoding operation as a whole processing flow, the processing flow of sequentially executing the reread operation and the soft decoding operation can be defined as the first type of read error processing flow, and the parity check operation of the independent disk redundant array RAID can be defined as the second type of read error processing flow, and the average processing time of the first type of read error processing flow is less than the average processing time of the second type of read error processing flow. When the memory controller 106 determines that the first default read operation fails, the first type of read error processing flow is executed twice or multiple times, and the interval time can be set between adjacent first type of read error processing flows. In a first type of read error processing flow, there can also be a time interval between a reread operation and a soft decoding operation. When the first type of read error processing flow still fails to read multiple times, the TRE phenomenon at this time has been eliminated. If the read operation still fails, it can be determined that the read operation failure is not caused by the TRE phenomenon, and the independent disk redundant array RAID operation can be executed at this time.

[0130] In some embodiments, reference Figure 7c As shown, the reread operation, the soft decoding operation and the RAID operation will be performed in sequence, and the operation will be performed cyclically twice or more times, that is, all the processes in the entire read error handling process will be performed twice or more times. In some specific embodiments, the soft decoding operation can be understood as re-decoding the data by the decoding unit (such as the soft decoder) in the memory controller 106, and the re-read operation is performed according to the re-decoded data. The RAID operation can be understood as implementing the mirroring of the data through the secondary encoding, and reconstructing the stored data and its parity check data, wherein the re-encoding of the redundant array of the stored data is usually performed in the data buffer of the memory controller 106.

[0131] In some specific embodiments, the memory controller 106 may obtain the current temperature of the memory device 104 or the memory system 102 to determine the total processing time of the read error processing process. The lower the temperature, the more serious the TRE phenomenon of the memory device 104, and the longer the total processing time of the read error processing process needs to be continued. Figures 7a to 7c When the memory system 102 leaves the factory, Figure 6 The conventional read operation flow shown has been written into the execution firmware or program, and the processing time of each step has been fixed. For the same total processing time, Figure 7a The reread operation shown has the most cycles. Figure 7b The number of cycles for executing the first type of read error handling process is shown below. Figure 7c The number of cycles to execute all read error handling procedures is the minimum. Conversely, for different total processing times, the minimum total processing time can be selected. Figure 7a The processing flow shown in the figure can be selected according to the total processing time. Figure 7b The processing flow shown, the maximum total processing time can be selected Figure 7c The processing flow shown.

[0132] The present disclosure is based on Figure 6In the conventional read operation flow including the error correction operation shown, after the first default read fails, multiple partial processes or multiple full processes in the error correction operations such as reread operation, soft decoding and independent disk redundant array RAID operation are used to replace the pseudo read operation, and the total duration is greater than or equal to the duration of the pseudo read operation in the related technical solution (that is, the duration of eliminating TRE) to eliminate the TRE phenomenon when the storage area in the memory device 104 is restored to the operating state. The embodiment of the present disclosure eliminates the TRE phenomenon by using the default read operation firmware or program of the original memory system 102 without adding the original read operation flow firmware or program steps, which is conducive to the simplification of firmware or program to reduce development costs and reduce the processing load of the memory controller 106.

[0133] In some embodiments, reference Figure 7b As shown, the read error processing flow of the memory device 104 includes a first type of read error processing flow and a second type of read error processing flow executed sequentially; the average processing time of the first type of read error processing flow is shorter than the average processing time of the second type of read error processing flow.

[0134] In some embodiments, reference Figure 7b As shown, the first type of read error processing flow includes: reread operation and soft decoding operation; the second type of read error processing flow includes: independent disk redundant array RAID operation. Figure 7b In the operation flow diagram, the first type of read error processing flow is marked with a dotted box. In response to the failure of the first default read operation when the storage area in the memory device 104 is restored to the operating state, the memory controller 106 performs a reread operation and a soft decoding operation in sequence.

[0135] In some embodiments, reference Figure 7b As shown, the memory controller 106 is configured as follows:

[0136] In each execution of the first type of read error handling process, in response to a re-read operation failure, a soft decoding operation is performed on the read data. In some other embodiments, in response to a re-read operation success, the soft decoding operation is still performed until a preset plurality of first type of read error handling processes are completed, so as to ensure that there is enough total processing time to eliminate the TRE phenomenon.

[0137] In some embodiments, reference Figure 7b As shown, in response to the failure of the first read operation after the storage area in the memory device 104 is restored to the operating state, at least two first-type read error processing processes are executed.

[0138] In some embodiments, reference Figure 7b As shown, the memory controller 106 is configured as follows:

[0139] In response to the read operation still failing after executing the first type of read error handling flow at least twice, executing the second type of read error handling flow.

[0140] In this embodiment, when the first type of read error handling process fails to read after multiple times, the TRE phenomenon has been eliminated at this time. If the read operation still fails, it can be determined that the read operation failure is not caused by the TRE phenomenon. At this time, the independent disk redundant array RAID operation can be performed. Alternatively, when the first type of read error handling process still fails to read after multiple times, it is considered that the total processing time of the multiple first type of read error handling processes is not enough to eliminate the TRE phenomenon, and the operation time needs to be increased. In this case, an independent disk redundant array RAID operation with a longer processing time is performed to eliminate the TRE phenomenon. Regardless of which operation process passes the read operation, the operation can be exited. Figure 7b The error handling process shown in the figure, the next read operation enters Figure 6 Alternatively, regardless of whether the re-read operation is successful, the first type of read error handling process must be performed multiple times to ensure that the TRE phenomenon is eliminated.

[0141] In some embodiments, reference Figure 7b As shown, the memory controller 106 is configured as follows:

[0142] In response to the read operation still failing after executing the second type of read error handling process, a read failure message is issued.

[0143] After executing the reread operation, the soft decoding operation, and the RAID operation with a relatively long processing time, there is enough processing time to eliminate the TRE phenomenon. At this time, the read operation still fails, and it is considered that the error cannot be corrected by the ECC error correction mechanism of the memory controller 106. At this time, the data may be lost or damaged, and the memory controller 106 sends a read failure message (Read fail) to the host 108. The second read operation can be performed according to Figure 6 The conventional reading process shown is carried out.

[0144] In some embodiments, the memory controller 106 is configured to:

[0145] A preset time period is set between two adjacent first-type read error processing processes.

[0146] The first type of read error processing includes a single re-read operation, or a cycle of re-read operation and soft decoding operation. A preset time may be set between each first type of read error processing process, or a preset time may be set between each re-read operation and soft decoding operation. The preset time range of the interval may include: 0 to 100ms, for example, 10ms. This short interval will not cause a new TRE phenomenon. The memory controller 106 may determine whether the read operation is read through within the preset time interval, or determine whether the FDC meets the conventional preset conditions and determine that the TRE phenomenon is eliminated; thereby determining whether to continue the subsequent operation, thereby saving operation time and improving the reading rate.

[0147] In some embodiments, different from Figure 7b As shown, Figure 7a The first type of read error processing shown includes one operation, and the first type of read error processing flow includes: a reread operation;

[0148] The second type of read error handling process includes: soft decoding operation.

[0149] When multiple reread operations fail, a soft decoding operation is performed. After the soft decoding operation fails, a RAID operation is performed. After the RAID operation fails, the memory controller 106 sends a read failure message to the host 108 .

[0150] In some embodiments, reference Figure 7c As shown, the first type of read error handling may include a re-read operation. In some embodiments, the memory controller 106 is configured to:

[0151] Obtaining a first duration; the first duration is greater than the duration for the storage area in the memory device 104 to recover to an operating state;

[0152] The number of executions of the first type of read error handling process is determined according to the first duration.

[0153] In some embodiments, the memory controller 106 is configured to:

[0154] The first time period is determined according to the temperature of the memory device 104 ; the first time period is negatively correlated to the temperature of the memory device 104 .

[0155] In some embodiments, memory controller 106 is configured to:

[0156] In response to the failure of the first read operation after the storage area in the memory device 104 is restored to the operating state, the first type of read error processing flow is executed multiple times until a preset number of times is reached.

[0157] The first duration is the total processing duration of multiple first-type read error processing procedures, and the first duration does not include the preset interval duration between each operation. After executing multiple first-type read error processing procedures, the first-type read error procedure can be Figure 7a A single reread operation in Figure 7b The reread operation and the soft decoding operation are performed in sequence as shown. The average processing time of a single reread operation and a soft decoding operation of the same memory system 102 can be determined according to the firmware. The first time can be determined according to the test data of eliminating TRE of the memory device 104 corresponding to different temperatures, and then the number of executions of the first time is determined. When the first type of read error processing flow is executed, if the preset time is not reached, that is, the read is successful, the first type of read error processing flow can be exited, and the next read operation is performed according to Figure 6 Alternatively, regardless of whether the read operation is successful or not, the first type of read error handling process is performed multiple times until a preset number of times is reached to ensure that the TRE phenomenon is eliminated, and the next read operation is performed according to Figure 6 When the first type of read error handling process is executed for a preset number of times and the read still fails, the RAID operation is performed. If the read still fails, the memory controller 106 sends a read failure message to the host 108.

[0158] In some embodiments, the memory system 102 includes: a universal flash storage UFS device or an embedded multimedia card eMMC device.

[0159] According to some aspects of the embodiments of the present disclosure, Figure 8 A schematic flow chart of an operation method of a memory system 102 is provided, the operation method comprising:

[0160] In response to the access command, performing a read operation on the storage area in the memory device 104;

[0161] In response to a failure of an initial read operation when performing a read operation on a storage area in the memory device 104 , at least two partial or complete read error handling processes are performed.

[0162] In some embodiments, before performing a read operation on a storage area in the memory device 104, no operation is performed on the storage area in the memory device 104 for a predetermined time; wherein the operation may include a programming operation, a read operation, or an erase operation;

[0163] or

[0164] The first read operation when performing a read operation on the storage area in the memory device 104 is the first read operation when performing a read operation on the storage area in the memory device 104 after the memory system 102 is powered on.

[0165] According to some aspects of the embodiments of the present disclosure, Fig. 9 A schematic flow chart of an operation method of a memory system 102 is provided, the operation method comprising:

[0166] In response to the access command, restoring the storage area in the memory device 104 to an operational state;

[0167] In response to a failure of the first read operation after the storage area in the memory device 104 is restored to an operating state, at least two read error handling processes are performed in part or in whole.

[0168] The access command of the embodiment of the present disclosure can be sent by the host 108 to the memory controller 106 through an interface such as PCIe. In response to the access command, the memory controller 106 restores the storage area in the memory device 104 to an operating state. In response to the failure of the first read operation after the storage area in the memory device 104 is restored to an operating state, the memory controller 106 controls the memory device 104 to execute at least two partial or full processes in the read error handling process. Alternatively, based on the management needs of the memory system 102 itself or the command for performance optimization, the memory controller 106 can control the storage area in the memory device 104 to be restored to an operating state and perform operations such as garbage collection and wear leveling when there is no instruction from the host 108.

[0169] In some embodiments, the read error processing flow of the memory device 104 includes a first type of read error processing flow and a second type of read error processing flow executed sequentially; the average processing time of the first type of read error processing flow is shorter than the average processing time of the second type of read error processing flow.

[0170] In some embodiments, performing at least two read error handling processes in part or in whole includes:

[0171] Execute the first type of read error handling process at least twice.

[0172] In some embodiments, the operating method further includes:

[0173] A preset time period is set between two adjacent first-type read error processing processes.

[0174] In some embodiments, the operating method further includes:

[0175] In response to the read operation still failing after executing the first type of read error handling flow at least twice, the second type of read error handling flow is executed.

[0176] In some embodiments, the first type of read error handling process includes: a reread operation and a soft decoding operation;

[0177] The second type of read error handling process includes: Redundant Array of Independent Disks RAID operations.

[0178] In some embodiments, the operating method further includes:

[0179] During each execution of the first type of read error handling process, in response to a re-read operation failure, a soft decoding operation is performed on the read data.

[0180] In some embodiments, the operating method further includes:

[0181] In response to the read operation still failing after executing the second type of read error handling process, a read failure message is issued.

[0182] In some embodiments, the first type of read error handling process includes: a reread operation;

[0183] The second type of read error handling process includes: soft decoding operation.

[0184] In some embodiments, the operating method further includes:

[0185] Obtaining a first duration; the first duration is greater than the duration for the storage area in the memory device 104 to recover to an operating state;

[0186] The number of executions of the first type of read error handling process is determined according to the first duration.

[0187] In some embodiments, the operating method further includes:

[0188] The first time period is determined according to the temperature of the memory device 104 ; the first time period is negatively correlated to the temperature of the memory device 104 .

[0189] In some embodiments, the operating method further includes:

[0190] In response to the failure of the first read operation after the storage area in the memory device 104 is restored to the operating state, the first type of read error processing flow is executed multiple times until a preset number of times is reached.

[0191] According to some aspects of the embodiments of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and when the computer program is executed, the operation method of the above-mentioned embodiment is implemented. The readable storage medium may include a NAND memory, and the storage unit of the NAND memory may include a floating gate type storage unit of a floating gate transistor, or a charge capture type storage unit including a charge capture transistor.

[0192] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory system, characterized in that: include: at least one memory device and a memory controller coupled to the at least one memory device; The memory controller is configured to: In response to a failure of an initial read operation when a read operation is performed on a storage area in the memory device, a part of or all of at least two read error handling processes are performed.

2. The memory system according to claim 1, wherein: The read error processing flow of the memory device includes a first type of read error processing flow and a second type of read error processing flow that are executed sequentially; An average processing time of the first type of read error processing flow is shorter than an average processing time of the second type of read error processing flow.

3. The memory system according to claim 2, wherein: In response to a failure of a first read operation after a storage area in the memory device is restored to an operating state, a first type of read error handling process is executed at least twice.

4. The memory system according to claim 3, characterized in that: The memory controller is configured to: A preset time period is set between two adjacent first-type read error processing processes.

5. The memory system according to claim 3, characterized in that: The memory controller is configured to: In response to the read operation still failing after executing the first type of read error handling flow at least twice, executing the second type of read error handling flow.

6. The memory system according to claim 5, characterized in that: The first type of read error processing flow includes: a reread operation and a soft decoding operation; The second type of read error processing flow includes: Redundant Array of Independent Disks RAID operation.

7. The memory system according to claim 6, characterized in that: The memory controller is configured to: During each execution of the first type of read error handling process, in response to the re-read operation failing, a soft decoding operation is performed on the read data.

8. The memory system according to claim 6, wherein: The memory controller is configured to: In response to the read operation still failing after executing the second type of read error handling process, a read failure message is issued.

9. The memory system according to claim 5, characterized in that: The first type of read error processing process includes: a reread operation; The second type of read error processing flow includes: a soft decoding operation.

10. The memory system according to claim 3, wherein: The memory controller is configured to: Acquire a first duration; the first duration being greater than the duration for the storage area in the memory device to recover to an operating state; The number of executions of the first type of read error handling process is determined according to the first time length.

11. The memory system according to claim 10, characterized in that: The memory controller is configured to: The first duration is determined according to the temperature of the memory device; the first duration is negatively correlated with the temperature of the memory device.

12. The memory system according to claim 3, characterized in that: The memory controller is configured to: In response to a failure of a first read operation after the storage area in the memory device is restored to an operating state, a first type of read error processing flow is executed multiple times until a preset number of times is reached.

13. The memory system according to claim 1, wherein: Before performing a read operation on a storage area in the storage device, no operation is performed on the storage area in the storage device for a preset time; or The first read operation when performing a read operation on the storage area in the memory device is the first read operation when performing a read operation on the storage area in the memory device after the memory system is powered on.

14. The memory system according to any one of claims 1 to 13, characterized in that: The memory system includes: a universal flash storage UFS device or an embedded multimedia card eMMC device.

15. A method for operating a memory system, characterized in that: include: In response to an access command, performing a read operation on a storage area in the memory device; In response to a failure of an initial read operation when a read operation is performed on a storage area in the memory device, a part of or all of at least two read error handling processes are performed.

16. The operating method according to claim 15, characterized in that: The read error processing flow of the memory device includes a first type of read error processing flow and a second type of read error processing flow that are executed sequentially; An average processing time of the first type of read error processing flow is shorter than an average processing time of the second type of read error processing flow.

17. The operating method according to claim 16, characterized in that: The performing of at least two read error handling processes in part or in whole includes: In response to a failure of a first read operation after a storage area in the memory device is restored to an operating state, a first type of read error handling process is executed at least twice.

18. The operating method according to claim 17, characterized in that: The method further comprises: A preset time period is set between two adjacent first-type read error processing processes.

19. The operating method according to claim 17, characterized in that: The method further comprises: In response to the read operation still failing after executing the first type of read error handling flow at least twice, the second type of read error handling flow is executed.

20. The operating method according to claim 19, characterized in that: The first type of read error processing flow includes: a reread operation and a soft decoding operation; The second type of read error processing flow includes: Redundant Array of Independent Disks RAID operation.

21. The operating method according to claim 20, characterized in that: The method further comprises: During each execution of the first type of read error handling process, in response to the re-read operation failing, a soft decoding operation is performed on the read data.

22. The operating method according to claim 20, characterized in that: The method further comprises: In response to the read operation still failing after executing the second type of read error handling flow, a read failure message is issued.

23. The operating method according to claim 19, characterized in that: The first type of read error processing process includes: a reread operation; The second type of read error processing flow includes: a soft decoding operation.

24. The operating method according to claim 17, characterized in that: The method further comprises: Acquire a first duration; the first duration being greater than the duration for the storage area in the memory device to recover to an operating state; The number of executions of the first type of read error handling process is determined according to the first time length.

25. The operating method according to claim 24, characterized in that: The method further comprises: The first duration is determined according to the temperature of the memory device; the first duration is negatively correlated with the temperature of the memory device.

26. The operating method according to claim 17, characterized in that: The method further comprises: In response to a failure of a first read operation after the storage area in the memory device is restored to an operating state, a first type of read error processing flow is executed multiple times until a preset number of times is reached.

27. The operating method according to claim 15, characterized in that: Before performing a read operation on a storage area in the storage device, no operation is performed on the storage area in the storage device for a preset time; or The first read operation when performing a read operation on the storage area in the memory device is the first read operation when performing a read operation on the storage area in the memory device after the memory system is powered on.

28. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed, the operating method according to any one of claims 15 to 27 is implemented.

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