OTA-based application program upgrading method and device, equipment and medium

Abstract

The invention discloses an OTA-based application program upgrading method and device, equipment and a medium, and relates to the technical field of over-the-air downloading. An internal address area switching mechanism and an external address area switching mechanism are distinguished based on different first enable signal settings, the internal address area switching mechanism is an interaction module which does not need to pass through a bus matrix, and the switching efficiency is greatly improved especially for a scene with a relatively high response speed. Determining a target address area switching mode according to a second enable signal corresponding to the internal address switching mechanism; the application program is upgraded and stored according to the target address area switching mode without passing through the external logic of the bus matrix, so that more time is saved, and the upgrading efficiency of the application program is improved. Besides, the method has an internal address area switching mechanism and an external address area switching mechanism at the same time, corresponding upgrading modes can be found in various upgrading scenes, and the flexibility and diversity of application program upgrading are improved.

Description

Technical Field

[0001] The present invention relates to the field of over-the-air downloading technology, and in particular to an OTA-based application program upgrade method, device, equipment and medium. Background Art

[0002] Over-The-Air (OTA) is a wireless method that allows devices to receive and install updates over wireless networks without physical connections. Applications can be upgraded without affecting the current application, and the updated application will be executed at the next restart.

[0003] Conventional application upgrades switch the program address mapping to two groups of address areas through the first address area and the second address area, and confirm which address area the program upgrade is executed from through the non-volatile storage mark. The entire upgrade process starts with the central processing unit (CPU) sending out address addressing, and then performing address resolution through the interactive module of the bus matrix, so that the program can be read from the non-volatile memory. It takes a lot of time to reach the storage area through a large number of external logics of bus interaction, which cannot be achieved in some scenarios with faster response speeds, thereby reducing the efficiency of application upgrades and limiting the limitations of application upgrades.

[0004] Therefore, how to improve the efficiency of application program upgrades and the limitations of application program upgrades are issues that technical personnel in this field urgently need to address. Summary of the invention

[0005] The purpose of the present invention is to provide an OTA-based application upgrade method, device, equipment and medium to solve the problem of limitations of application upgrades in scenarios with high response speeds.

[0006] In order to solve the above technical problems, the present invention provides an OTA-based application program upgrade method, comprising:

[0007] Obtaining a first enable signal of an address region switching mechanism; wherein the first enable signal represents an internal address region switching mechanism and an external address region switching mechanism corresponding to the address region switching mechanism; the internal address region switching mechanism is an address region switching mechanism for performing address resolution in an internal logic manner between the CPU and the non-volatile memory; the internal logic manner is implemented between the CPU and the non-volatile memory without passing through a bus matrix;

[0008] When the first enable signal is an internal address area switching mechanism, a second enable signal corresponding to the internal address switching mechanism is obtained, and a target address area switching mode is determined according to the second enable signal; the application is upgraded and stored according to the target address area switching mode; wherein the target address area switching mode represents the area modes under the read and write operations corresponding to the application running area and the application update area respectively;

[0009] When the first enable signal is an external address area switching mechanism, space area allocation is performed in the non-volatile memory according to address configuration information corresponding to the application to upgrade the application.

[0010] On the one hand, the internal address area switching mechanism is determined by address resolution in an internal logic manner formed by the CPU accessing the non-volatile memory through the first port; wherein the first port does not need to pass through the bus matrix.

[0011] On the other hand, the target address area switching mode is a first internal address switching mode or a second internal address switching mode; wherein the non-volatile memory in the first internal address switching mode corresponds to a first operation area and a first update area; the first operation area stores address information of a read operation; the first update area stores address information of a write operation; the address information of the first operation area and the address information of the first update area form a mapping relationship;

[0012] The non-volatile memory in the second internal address switching mode corresponds to a second operating area and a second update area; the second operating area stores address information of a read operation; the second update area stores address information of a write operation; the address information of the second operating area forms a mapping relationship with the address information of the second update area; the address spaces corresponding to the first operating area, the second operating area, the first update area, and the second update area are the same.

[0013] On the other hand, if the target address area switching mode is the first internal address switching mode, upgrading and storing the application according to the target address area switching mode includes:

[0014] Running the application program in the first running area by means of a read operation;

[0015] When an application upgrade request is received, the application is upgraded and stored in the first update area according to the application upgrade request and a write operation mode.

[0016] On the other hand, upgrading and storing the application in the first update area according to the application upgrade request and the write operation mode includes:

[0017] When receiving an application upgrade request corresponding to OTA, the application is updated in the first update area corresponding to the non-volatile memory through a second port sent by other CPUs.

[0018] On the other hand, the non-volatile memory is located outside the CPU.

[0019] On the other hand, allocating a space area in the non-volatile memory according to the address configuration information corresponding to the application to upgrade the application includes:

[0020] Access request information for accessing the non-volatile memory through a second port sent by the CPU;

[0021] The control bus matrix performs address resolution on the access request information and the address configuration information to determine the address area of ​​the non-volatile memory corresponding to the application upgrade, so as to facilitate the update of the application.

[0022] In order to solve the above technical problems, the present invention also provides an OTA-based application program upgrade device, comprising:

[0023] An acquisition module is used to acquire a first enable signal of an address region switching mechanism; wherein the first enable signal represents an internal address region switching mechanism and an external address region switching mechanism corresponding to the address region switching mechanism; the internal address region switching mechanism is an address region switching mechanism for performing address resolution in an internal logic manner between the CPU and the non-volatile memory; the internal logic manner is implemented between the CPU and the non-volatile memory without passing through a bus matrix;

[0024] A first upgrade module, configured to obtain a second enable signal corresponding to the internal address switching mechanism when the first enable signal is an internal address region switching mechanism, and determine a target address region switching mode according to the second enable signal; and upgrade and store the application according to the target address region switching mode; wherein the target address region switching mode represents a region mode under read and write operations corresponding to an application running region and an application update region, respectively;

[0025] The second upgrade module is used to allocate space areas in the non-volatile memory according to the address configuration information corresponding to the application program to upgrade the application program when the first enable signal is an external address area switching mechanism.

[0026] In order to solve the above technical problems, the present invention also provides an OTA-based application program upgrade device, comprising:

[0027] Memory for storing computer programs;

[0028] A processor is used to implement the steps of the OTA-based application upgrade method as described above when executing the computer program.

[0029] In order to solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the OTA-based application upgrade method as described above are implemented.

[0030] The present invention provides an OTA-based application upgrade method, comprising: obtaining a first enable signal of an address region switching mechanism; wherein the first enable signal represents an internal address region switching mechanism and an external address region switching mechanism corresponding to the address region switching mechanism; the internal address region switching mechanism is an address region switching mechanism for performing address resolution in an internal logic manner between a CPU and a non-volatile memory; the internal logic manner is implemented between the CPU and the non-volatile memory without passing through a bus matrix; when the first enable signal is the internal address region switching mechanism, obtaining a second enable signal corresponding to the internal address switching mechanism, and determining a target address region switching mode according to the second enable signal; upgrading and storing the application according to the target address region switching mode; wherein the target address region switching mode represents the region modes under the read and write operations corresponding to the application running region and the application update region respectively; when the first enable signal is the external address region switching mechanism, performing space region allocation in the non-volatile memory according to the address configuration information corresponding to the application to upgrade the application. The present invention distinguishes between an internal address area switching mechanism and an external address area switching mechanism based on the different settings of the first enable signal. Corresponding to the internal address area switching mechanism, it is an interactive module that does not need to pass through the bus matrix. Especially for scenarios with a fast response speed, it does not pass through the external logic of the bus matrix, which saves a lot of time and improves the efficiency of application upgrades. In addition, it has both internal and external address area switching mechanisms, and can find corresponding upgrade methods in various upgrade scenarios, thereby improving the flexibility and diversity of application upgrades.

[0031] In addition, the present invention also provides an OTA-based application upgrade device, equipment and medium, which have the same beneficial effects as the above-mentioned OTA-based application upgrade method. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A flowchart of an OTA-based application upgrade method provided by an embodiment of the present invention;

[0034] Figure 2 A schematic diagram of access between a CPU and a non-volatile memory provided by an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of access to an external A / B SWAP-A mode provided by an embodiment of the present invention;

[0036] Figure 4 A schematic diagram of access to an external A / B SWAP-B mode provided by an embodiment of the present invention;

[0037] Figure 5 A schematic diagram of access to an internal A / B SWAP-A mode provided by an embodiment of the present invention;

[0038] Figure 6 A schematic diagram of access to an internal A / B SWAP-B mode provided by an embodiment of the present invention;

[0039] Figure 7 A flowchart of another OTA-based application upgrade method provided by an embodiment of the present invention;

[0040] Figure 8 A schematic diagram of a result corresponding to an A / B SWAP mechanism under an OTA function provided in an embodiment of the present invention;

[0041] Fig. 9 A structural diagram of an OTA-based application program upgrade device provided in an embodiment of the present invention;

[0042] Fig.10 A structural diagram of an OTA-based application upgrade device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] The core of the present invention is to provide an OTA-based application upgrade method, device, equipment and medium to solve the problem of limitations of application upgrades in scenarios with high response speeds.

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0046] Swap space (SWAP) is a virtual memory mechanism. When the system's physical memory is not enough to meet the needs of the currently running program, the system uses the pre-configured SWAP space on the hard disk to store inactive memory pages. OTA's AB space ensures that a running boot system can be retained during the OTA update by maintaining two systems. In the actual update process, there is currently only one way to access the storage address information of the non-volatile memory through the bus matrix, and the central processing unit (CPU) accesses the address to confirm access. When encountering a high response speed scenario, the access speed is slow due to the large number of interactions with external logic. The OTA-based application upgrade method provided by the present invention can solve the above technical problems.

[0047] Figure 1 A flowchart of an OTA-based application upgrade method provided in an embodiment of the present invention is shown in FIG. Figure 1 As shown, the method includes:

[0048] S11: Obtaining a first enabling signal of an address region switching mechanism;

[0049] The first enable signal represents an internal address region switching mechanism and an external address region switching mechanism corresponding to the address region switching mechanism; the internal address region switching mechanism is an address region switching mechanism for performing address resolution in an internal logic manner between the CPU and the non-volatile memory; the internal logic manner is implemented between the CPU and the non-volatile memory without passing through a bus matrix;

[0050] S12: when the first enable signal is an internal address region switching mechanism, obtaining a second enable signal corresponding to the internal address region switching mechanism, and determining a target address region switching mode according to the second enable signal; and upgrading and storing the application according to the target address region switching mode;

[0051] The target address area switching mode represents the area mode under the read and write operations corresponding to the application running area and the application updating area respectively;

[0052] S13: When the first enable signal is an external address region switching mechanism, a space region is allocated in the non-volatile memory according to address configuration information corresponding to the application to upgrade the application.

[0053] Specifically, the first enable signal of the address region switching mechanism is used to mark which address region switching mechanism is currently used, including an internal address region switching mechanism and an external address region switching mechanism. Figure 2 A schematic diagram of accessing a CPU and a non-volatile memory provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the above two address area switching mechanisms are included here. The CPU directly accesses the non-volatile memory as the internal address area switching mechanism, which mainly performs address resolution through internal logic without going through the bus matrix. The CPU accesses the non-volatile memory through the interactive module of the bus matrix as the external address area switching mechanism. Here, a large number of external logic methods are required to reach the storage area. Its external address area switching mechanism is also called external A / B SWAP mode. The application area and OTA update area of ​​the non-volatile storage will change. The CPU will go through the address resolution of the bus matrix, and the non-volatile storage area accessed will also change. Address resolution must be performed outside the NVM controller.

[0054] It should be noted that the positional relationship between the CPU and the non-volatile memory is not limited. The CPU may include a non-volatile memory, such as a static random access memory (SRAM), or the CPU may not include a non-volatile memory. This is not limited here.

[0055] In some embodiments, the non-volatile memory is external to the CPU.

[0056] It is understandable that in this embodiment, the data accessed by the non-volatile memory for the CPU is not lost, and the data is still not lost after power failure. The CPU will execute the instructions of the firmware or boot program, and its firmware or boot program will be stored in the non-volatile memory. Or download a new system image or patch to the non-volatile memory of the device. When the AB system is updated, the CPU will switch to the updated system partition after restarting, and the CPU will read the new system image, which is stored in the non-volatile memory.

[0057] The non-volatile memory provided in this embodiment is located outside the CPU and is used to ensure that data accessed by the CPU is not lost.

[0058] A bus matrix is ​​a hardware structure used in computer architecture to manage and control communications between multiple devices or processors. It is often used in embedded systems, high-performance computing systems, or multi-processor systems to achieve efficient data transmission and communication control. It allows multiple devices or processors to access the bus at the same time, dynamically allocates bandwidth according to the communication needs of the devices, and optimizes the overall performance of the system. It routes data between multiple devices to ensure that data can be correctly transmitted from one device to another (i.e., between the CPU and non-volatile memory).

[0059] The access between the CPU and the non-volatile memory mentioned in this embodiment can also be applied to other access scenarios and is not limited here. The internal logic method here is a logic method in which the accessed object is directly interacted with without going through a bus matrix, a bus interaction module, in the computer hardware design. The external logic method is that in the computer hardware logic, through a bus matrix, a bus interaction module, the storage area of ​​the non-volatile storage will change, and address resolution needs to be performed outside the non-volatile memory (NVM) controller.

[0060] In step S12, if the first enable signal is used to characterize the internal address area switching mechanism, it means that the internal address switching mode is adopted. On this basis, the internal address area switching mode is divided into two modes, one mode corresponds to first storing in the running area for reading operation and then writing in the area to be updated. The other mode corresponds to first writing in the area to be updated and then reading in the running area.

[0061] When the first enable signal in step S13 is used to represent the external address area switching mechanism, the space area inside the non-volatile memory is allocated according to the address configuration information corresponding to the application program to facilitate subsequent upgrade of the application program. The external address area switching mechanism in this embodiment corresponds to Figure 2 Access method through the bus matrix.

[0062] In some embodiments, allocating a space region in a non-volatile memory according to address configuration information corresponding to an application to upgrade the application includes:

[0063] access request information for accessing the non-volatile memory from the second port sent by the CPU;

[0064] The control bus matrix performs address resolution on the access request information and the address configuration information to determine the address area of ​​the non-volatile memory corresponding to the application upgrade, so as to facilitate the application update.

[0065] Specifically, the second port can be a data port or an access port for the non-volatile memory instruction corresponding to the CPU, and needs to pass through the bus matrix to confirm the address information of which group of non-volatile memory to access based on the CPU access address. The function of the bus matrix is ​​to parse the second port (P0) access issued by the CPU and confirm the non-volatile storage module number to be read. Table 1 is an address allocation table for the external A / B AWAP address area switching mechanism. As shown in Table 1, it is assumed that the start address and end address corresponding to each non-volatile storage in the external A / B SWAP mechanism, and from the application perspective, its NVM0 is the initial application area, NVM1 is the reserved update program area for the initial OTA mechanism, and NVM2 is the OTA irrelevant data area.

[0066] Table 1

[0067] NVM Number Starting address End address NVM0 32‘h0000_0000 32'h0001_FFFF NVM1 32‘h0002_0000 32'h0003_FFFF NVM2 32‘h0004_0000 32'h0005_FFFF

[0068] There are two corresponding modes in the external address area switching mechanism, namely, the external A / B SWAP-A mode and the external A / B SWAP-B mode. Figure 3 A schematic diagram of an external A / B SWAP-A mode access provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, CPU0 is responsible for applications, CPU1 is responsible for OTA updates, and CPU2 is responsible for data, corresponding to non-volatile storage 0, 1, and 2 respectively. Figure 4 A schematic diagram of an external A / B SWAP-B mode access provided by an embodiment of the present invention, such as Figure 4 As shown, CPU0 is responsible for applications, CPU1 is responsible for OTA updates, and CPU2 is responsible for data, corresponding to non-volatile storage 1, 0, and 2 respectively. Figure 3 and Figure 4 The corresponding embodiment is only one embodiment. There are still more CPUs and NVM storage areas. The NVM address of the external A / B SWAP mode is arbitrarily allocated and can be set according to actual conditions.

[0069] An OTA-based application upgrade method provided by an embodiment of the present invention includes: obtaining a first enable signal of an address region switching mechanism; wherein the first enable signal represents an internal address region switching mechanism and an external address region switching mechanism corresponding to the address region switching mechanism; the internal address region switching mechanism is an address region switching mechanism for performing address resolution in an internal logic manner between a CPU and a non-volatile memory; the internal logic manner is implemented between the CPU and the non-volatile memory without passing through a bus matrix; when the first enable signal is the internal address region switching mechanism, obtaining a second enable signal corresponding to the internal address switching mechanism, and determining a target address region switching mode according to the second enable signal; upgrading and storing the application according to the target address region switching mode; wherein the target address region switching mode represents the region modes under the read and write operations corresponding to the application running area and the application update area respectively; when the first enable signal is the external address region switching mechanism, performing spatial region allocation in the non-volatile memory according to the address configuration information corresponding to the application to upgrade the application. The present invention distinguishes between an internal address area switching mechanism and an external address area switching mechanism based on the different settings of the first enable signal. Corresponding to the internal address area switching mechanism, it is an interactive module that does not need to pass through the bus matrix. Especially for scenarios with a fast response speed, it does not pass through the external logic of the bus matrix, which saves a lot of time and improves the efficiency of application upgrades. In addition, it has both internal and external address area switching mechanisms, and can find corresponding upgrade methods in various upgrade scenarios, thereby improving the flexibility and diversity of application upgrades.

[0070] In some embodiments, the internal address region switching mechanism is determined by address resolution in an internal logic manner formed by the CPU accessing the non-volatile memory through the first port; wherein the first port does not need to pass through the bus matrix.

[0071] like Figure 2 As shown, the CPU accesses the non-volatile memory through the first port (P1 port), and the first port is a high-speed port. Addressing in this way does not need to go through the bus matrix, but directly accesses the non-volatile memory corresponding to the CPU to improve the upgrade access efficiency of the application.

[0072] It can be understood that the area accessible by the CPU through the first port is divided into AB areas. Table 2 is the address allocation table of the internal A / B AWAP address area switching mechanism. As shown in Table 2, after the system switches to the internal A / B AWAP address area switching mechanism, the address allocation table of Table 1 changes, and the corresponding storage space size remains unchanged.

[0073] Table 2

[0074] NVM Number Starting address End address NVM0 32‘h0000_0000 32'h0000_FFFF NVM1 32‘h0001_0000 32'h0001_FFFF NVM2 32‘h0002_0000 32'h0002_FFFF

[0075] It can be understood that the internal A / B AWAP address area switching mechanism includes two modes, namely, the internal A / B AWAP-A mode and the internal A / B AWAP-B mode. In some embodiments, the target address area switching mode is the first internal address switching mode or the second internal address switching mode; wherein the non-volatile memory in the first internal address switching mode correspondingly includes a first operating area and a first update area; the first operating area stores address information of a read operation; the first update area stores address information of a write operation; the address information of the first operating area and the address information of the first update area form a mapping relationship;

[0076] The non-volatile memory in the second internal address switching mode corresponds to a second operating area and a second update area; the second operating area stores address information for read operations; the second update area stores address information for write operations; the address information of the second operating area forms a mapping relationship with the address information of the second update area; the address spaces corresponding to the first operating area, the second operating area, the first update area, and the second update area are the same.

[0077] Figure 5 A schematic diagram of an internal A / B SWAP-A mode access provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, each CPU accesses the corresponding address mapping relationship between the area to be updated (first update area) and the current running area (first running area) through the first port (P1 port), which is a one-to-one correspondence. During a read operation, the CPU accesses the running area, and during a write operation, it accesses the area to be updated. Figure 6 A schematic diagram of an internal A / B SWAP-B mode access provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, relative to Figure 5 For example, after switching to the internal A / B SWAP-B mode, the physical areas of the current operating area and the area to be updated corresponding to the same non-volatile memory area are exchanged, and the write operation of the area to be updated (the second update area) is performed first, and then the read operation of the operating area (the second operating area) is performed.

[0078] The address spaces corresponding to the various areas (the first operating area, the second operating area, the first update area, and the second update area) are the same.

[0079] The division of the address range in the internal A / B SWAP mode provided in this embodiment ensures that in a scenario with a faster response speed, the external logic of the bus matrix is ​​not passed, which saves a lot of time and improves the efficiency of application program upgrade.

[0080] In some embodiments, if the target address area switching mode is the first internal address switching mode, upgrading and storing the application according to the target address area switching mode includes:

[0081] Running the application program in a read operation mode in the first running area;

[0082] When an application upgrade request is received, the application is upgraded and stored in the first update area according to the application upgrade request and the write operation mode.

[0083] Specifically, the application is run in the first running area by a read operation mode, and when an application upgrade request is received, the application is upgraded and stored in a first update area having the same area address as the first running area according to the request and a write operation mode.

[0084] After the application is updated, the power is turned on again, the area to be updated (the second update area) is used as the current running area, and the updated application is run in the second update area, thus completing a swap. Figure 6 The area allocation in .

[0085] In this embodiment, the read and write operations of the address range corresponding to the internal A / B SWAP mode are implemented to realize the subsequent application upgrade process and improve the application upgrade efficiency.

[0086] In some embodiments, upgrading and storing the application in the first update area according to the application upgrade request and the write operation mode includes:

[0087] When receiving an application upgrade request corresponding to OTA, the application is updated in the first update area corresponding to the non-volatile memory through the second port sent by other CPUs.

[0088] Specifically, in the above embodiments, the division of the address range of the non-volatile memory is considered to facilitate application access. Since it is difficult for the same CPU to perform two operations such as read and write operations at the same time, the corresponding subsequent OTA update operation is completed by other CPUs. Since the update operation does not need to be completed efficiently, the second port issued by other CPUs is used to update the first update area.

[0089] The other CPUs provided in this embodiment complete the actual OTA update operation, avoiding the same CPU from performing read and write operations at the same time, thereby improving the upgrade efficiency of the entire application.

[0090] Figure 7 A flowchart of another OTA-based application upgrade method provided by an embodiment of the present invention, such as Figure 7 As shown, including:

[0091] S21: Determine whether a system enable instruction is received; if so, proceed to step S22; if not, return to step S21;

[0092] S22: Determine whether the first enable signal is detected; if so, proceed to step S23; if not, proceed to step S24;

[0093] S24: No OTA mode update;

[0094] S23: Determine whether the first enable signal is an enable signal of the internal address region switching mechanism; if so, proceed to step S25; if not, proceed to step S26;

[0095] S26: Determine that it is an external address region switching mechanism, and allocate address space to the NVM according to the address configuration information;

[0096] S25: Obtain the second enable signal, and determine whether the second enable signal is the first internal address switching mode; if so, proceed to step S27; if not, proceed to step S28;

[0097] S27: Upgrading and storing the application according to the first internal address switching mode;

[0098] S28: Upgrading and storing the application program according to the second internal address switching mode;

[0099] S29: Execute the application program;

[0100] S30: Execute OTA update application;

[0101] S31: System reset.

[0102] After the system is enabled, the SWAP information will be read from the information area of ​​the non-volatile storage, including the internal / external SWAP KEY enable (only one can be effective at the same time) and the address allocation information of the external SWAP mode and the A / B mode selection of the internal SWAP mode. According to the SWAP type, the external SWAP allocates address space for non-volatile storage, and the internal SWAP distinguishes between A / B modes. When executing the program, an OTA update request may be received. After the update is completed, you can choose a time to reset the system, and then repeat the above process.

[0103] Figure 8 A schematic diagram of the result of an A / B SWAP mechanism corresponding to an OTA function provided in an embodiment of the present invention is shown as follows: Figure 8As shown in the figure, after the OTA function is completed, the internal SWAP mode consumes fewer clock cycles from the CPU sending a transmission request to the non-volatile storage P1 port receiving the transmission request than the external SWAP mode consumes from the CPU sending a transmission request to the non-volatile storage P0 port receiving the transmission request. It can be seen that the internal SWAP mode has significantly improved the application efficiency.

[0104] The above describes in detail various embodiments corresponding to the OTA-based application upgrade method. On this basis, the present invention also discloses an OTA-based application upgrade device corresponding to the above method. Fig. 9 The structure diagram of an OTA-based application upgrade device provided by an embodiment of the present invention. Fig. 9 As shown, the OTA-based application upgrade device includes:

[0105] The acquisition module 11 is used to acquire a first enable signal of the address region switching mechanism; wherein the first enable signal represents an internal address region switching mechanism and an external address region switching mechanism corresponding to the address region switching mechanism; the internal address region switching mechanism is an address region switching mechanism for performing address resolution in an internal logic manner between the CPU and the non-volatile memory; the internal logic manner is implemented between the CPU and the non-volatile memory without passing through a bus matrix;

[0106] The first upgrade module 12 is used to obtain a second enable signal corresponding to the internal address switching mechanism when the first enable signal is an internal address region switching mechanism, and determine a target address region switching mode according to the second enable signal; upgrade and store the application according to the target address region switching mode; wherein the target address region switching mode represents the region mode under the read and write operations corresponding to the application running region and the application update region respectively;

[0107] The second upgrade module 13 is used to allocate space areas in the non-volatile memory according to address configuration information corresponding to the application program to upgrade the application program when the first enable signal is an external address area switching mechanism.

[0108] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0109] For an introduction to an OTA-based application upgrade device provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above-mentioned OTA-based application upgrade method.

[0110] Fig.10 A structural diagram of an OTA-based application upgrade device provided in an embodiment of the present invention, such as Fig.10As shown, the device includes:

[0111] A memory 21, used for storing computer programs;

[0112] The processor 22 is used to implement the steps of the OTA-based application program upgrade method when executing the computer program.

[0113] The OTA-based application upgrade device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0114] Among them, the processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 22 can be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 22 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 22 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 22 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0115] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used to store the following computer program 211, wherein, after the computer program is loaded and executed by the processor 22, the relevant steps of the OTA-based application upgrade method disclosed in any of the aforementioned embodiments can be implemented. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 212 may include Windows, Unix, Linux, etc. Data 213 may include, but is not limited to, data involved in the OTA-based application upgrade method, etc.

[0116] In some embodiments, the OTA-based application upgrade device may also include a display screen 23 , an input / output interface 24 , a communication interface 25 , a power supply 26 , and a communication bus 27 .

[0117] Those skilled in the art can understand that Fig.10 The structure shown in the figure does not constitute a limitation on the OTA-based application upgrade device and may include more or fewer components than shown in the figure.

[0118] The processor 22 implements the OTA-based application upgrade method provided in any of the above embodiments by calling the instructions stored in the memory 21 .

[0119] For an introduction to an OTA-based application upgrade device provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above-mentioned OTA-based application upgrade method.

[0120] Furthermore, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by the processor 22, the steps of the above-mentioned OTA-based application upgrade method are implemented.

[0121] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0122] For an introduction to a computer-readable storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above OTA-based application upgrade method.

[0123] The above is a detailed introduction to an OTA-based application upgrade method, device, equipment and medium provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can refer to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

[0124] It should also be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. An OTA-based application upgrade method, characterized in that: include: Obtaining a first enable signal of an address region switching mechanism; wherein the first enable signal represents an internal address region switching mechanism and an external address region switching mechanism corresponding to the address region switching mechanism; the internal address region switching mechanism is an address region switching mechanism for performing address resolution in an internal logic manner between the CPU and the non-volatile memory; the internal logic manner is implemented between the CPU and the non-volatile memory without passing through a bus matrix; When the first enable signal is an internal address area switching mechanism, a second enable signal corresponding to the internal address switching mechanism is obtained, and a target address area switching mode is determined according to the second enable signal; the application is upgraded and stored according to the target address area switching mode; wherein the target address area switching mode represents the area modes under the read and write operations corresponding to the application running area and the application update area respectively; When the first enable signal is an external address area switching mechanism, space area allocation is performed in the non-volatile memory according to address configuration information corresponding to the application to upgrade the application.

2. The OTA-based application upgrade method according to claim 1, characterized in that: The internal address area switching mechanism is determined by address resolution in an internal logic manner formed by the CPU accessing the non-volatile memory through the first port; wherein the first port does not need to pass through the bus matrix.

3. The OTA-based application upgrade method according to claim 2, characterized in that: The target address area switching mode is a first internal address switching mode or a second internal address switching mode; wherein the non-volatile memory in the first internal address switching mode includes a first operation area and a first update area; the first operation area stores address information of a read operation; the first update area stores address information of a write operation; the address information of the first operation area and the address information of the first update area form a mapping relationship; The non-volatile memory in the second internal address switching mode corresponds to a second operating area and a second update area; the second operating area stores address information of a read operation; the second update area stores address information of a write operation; the address information of the second operating area forms a mapping relationship with the address information of the second update area; the address spaces corresponding to the first operating area, the second operating area, the first update area, and the second update area are the same.

4. The OTA-based application upgrade method according to claim 3, characterized in that: If the target address area switching mode is the first internal address switching mode, upgrading and storing the application according to the target address area switching mode includes: Running the application program in the first running area by means of a read operation; When an application upgrade request is received, the application is upgraded and stored in the first update area according to the application upgrade request and a write operation mode.

5. The OTA-based application upgrade method according to claim 4, characterized in that: The step of upgrading and storing the application in the first update area according to the application upgrade request and the write operation mode includes: When receiving an application upgrade request corresponding to OTA, the application is updated in the first update area corresponding to the non-volatile memory through a second port sent by other CPUs.

6. The OTA-based application upgrade method according to claim 1, characterized in that: The nonvolatile memory is located outside the CPU.

7. The OTA-based application upgrade method according to claim 1, characterized in that: Allocating a space area in the non-volatile memory according to address configuration information corresponding to the application to upgrade the application, including: Access request information for accessing the non-volatile memory through a second port sent by the CPU; The control bus matrix performs address resolution on the access request information and the address configuration information to determine the address area of ​​the non-volatile memory corresponding to the application upgrade, so as to facilitate the update of the application.

8. An OTA-based application upgrade device, characterized in that: include: An acquisition module is used to acquire a first enable signal of an address region switching mechanism; wherein the first enable signal represents an internal address region switching mechanism and an external address region switching mechanism corresponding to the address region switching mechanism; the internal address region switching mechanism is an address region switching mechanism for performing address resolution in an internal logic manner between the CPU and the non-volatile memory; the internal logic manner is implemented between the CPU and the non-volatile memory without passing through a bus matrix; A first upgrade module, configured to obtain a second enable signal corresponding to the internal address switching mechanism when the first enable signal is an internal address region switching mechanism, and determine a target address region switching mode according to the second enable signal; and upgrade and store the application according to the target address region switching mode; wherein the target address region switching mode represents a region mode under read and write operations corresponding to an application running region and an application update region, respectively; The second upgrade module is used to allocate space areas in the non-volatile memory according to the address configuration information corresponding to the application program to upgrade the application program when the first enable signal is an external address area switching mechanism.

9. An OTA-based application upgrade device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the OTA-based application upgrade method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the OTA-based application upgrade method according to any one of claims 1 to 7 are implemented.

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