Drive system

CN119226206APending Publication Date: 2024-12-313PEAK INC
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Patent Information

Application Number
CN202411389043.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-09-30
Publication Date
2024-12-31

AI Technical Summary

Technical Problem

In a serial interface transmitter with a half-rate architecture, when using an SST structure, the clock signal needs to directly control multiple drivers, resulting in complex clock path design, high power consumption, and susceptible to power noise.

Method used

Design a driving system to control the driver through control signals rather than clock signals, use matching units and switching units to perform exclusive or identical operations, generate full-rate data signals, reduce the design difficulty and power consumption of the clock path, and optimize Duty cycle and orthogonality of the clock signal.

Benefits of technology

The design of directly controlling the driver without a clock signal is realized, reducing the complexity and power consumption of the clock path, optimizing the deterministic jitter of the data signal, and improving the stability and efficiency of the system.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention discloses a driving system. The driving system comprises a driver and a controller, the driver comprises a matching unit with an output end, a first switch unit connected with the matching unit and a first reference voltage, and a second switch unit connected with the matching unit and a second reference voltage; the controller comprises a clock generation unit and a coding control unit, the clock generation unit is used for generating one or more groups of clock signals, and the coding control unit is used for coding input data based on the control of the corresponding clock signals to generate a group of control signals; and the first switch unit and the second switch unit are controlled through a control signal to generate a data signal at the output end. According to the driving system provided by the invention, a clock signal is not adopted as a direct control signal of the driver, and a full-rate data signal is obtained through an XOR or XNOR mode based on control of the control signal, so that the problem that a traditional driver with a half-rate SST structure needs a clock to control is solved.
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