Processing system, integrated circuit, device and method for data transfer

Abstract

The embodiment of the invention relates to a processing system, an integrated circuit, equipment and a method for data transmission. In accordance with various embodiments of the present disclosure, a processing system is provided. In some embodiments, a processing system includes a non-secure processing unit and an encryption co-processing unit. The encryption co-processing unit comprises a data interface and a hardware encryption engine. The data interface is configured to receive one or more control blocks and one or more data blocks from the non-secure processing unit. The hardware encryption engine is configured to process the one or more control blocks and the one or more data blocks received by the data interface in accordance with the encryption key. The data interface is configured to receive a first control block from the non-secure processing unit, latch the received first control block, receive a first data block from the non-secure processing unit, and transmit the latched first control block and the received first data block to the hardware encryption engine.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to secure data transfer and secure processing systems. Background Art

[0002] Applicants have identified many technical challenges and difficulties associated with secure processing of data, such as via encryption algorithms. Through applied effort, ingenuity, and innovation, Applicants have solved the problems associated with secure processing of data via encryption algorithms by developing solutions embodied in the present disclosure, which will be described in detail below. Summary of the invention

[0003] Various embodiments described herein relate to systems, integrated circuits, devices, and methods for data transfer for secure processing.

[0004] According to various embodiments of the present disclosure, a processing system is provided. In some embodiments, the processing system includes a non-secure processing unit and an encryption co-processing unit. The encryption co-processing unit includes a data interface and a hardware encryption engine. The data interface is configured to receive one or more control blocks and one or more data blocks from the non-secure processing unit. The hardware encryption engine is configured to process one or more control blocks and one or more data blocks received by the data interface according to an encryption key. The data interface is configured to receive a first control block from the non-secure processing unit, latch the received first control block, receive a first data block from the non-secure processing unit, and transmit the latched first control block and the received first data block to the hardware encryption engine.

[0005] In some embodiments, the data interface is configured to receive the second data block from the non-secure processing unit. If the second data block is received from the non-secure processing unit without a corresponding second control block, the data interface is configured to transmit the latched first control block and the received second data block to the hardware encryption engine.

[0006] In some embodiments, the data interface is configured to receive a second control block from a non-secure processing unit, latch the received second control block, receive a third data block from the non-secure processing unit, and transmit the latched second control block and the received third data block to a hardware encryption engine.

[0007] In some embodiments, the data interface is configured to receive a fourth data block from the non-secure processing unit. If the fourth data block is received from the non-secure processing unit without a corresponding third control block, the data interface is configured to transmit the latched second control block and the received fourth data block to the hardware encryption engine.

[0008] In some embodiments, the first control block includes a counter setting value corresponding to the number of data blocks to be received by the data interface from the non-secure processing unit in the absence of a corresponding control block, the data interface is configured to set a countdown counter to the counter setting value in the first control block, and the data interface is configured to decrement the countdown counter by one for each data block received from the non-secure processing unit in the absence of a corresponding control block.

[0009] In some embodiments, after each data block is received by the data interface from the non-secure processing unit without a corresponding control block, the data interface is configured to check the current value of the countdown counter. If the current value of the countdown counter is equal to zero, the data interface is configured to expect to receive a control block for the next data block received from the non-secure processing unit.

[0010] In some embodiments, the hardware cryptographic engine is configured to support Advanced Encryption Standard operations.

[0011] In some embodiments, each of the one or more control blocks contains 8 bytes of data, and each of the one or more data blocks contains 16 bytes of data.

[0012] According to various embodiments of the present disclosure, a processing system is provided. In some embodiments, the processing system includes a non-secure processing unit and an encryption co-processing unit. The encryption co-processing unit includes a data interface and a hardware encryption engine. The data interface is configured to receive a plurality of control blocks and a plurality of data blocks from the non-secure processing unit, at least some of the plurality of data blocks being received after corresponding corresponding control blocks in the plurality of control blocks. The hardware encryption engine is configured to process the plurality of control blocks and the plurality of data blocks received by the data interface according to an encryption key. The data interface is configured to latch each control block when each control block is received, overwriting any previously latched control block. Each time a data block is received, the data interface is configured to transmit the latched control block and the received data block to the hardware encryption engine.

[0013] According to various embodiments of the present disclosure, a method for receiving data to be processed by encryption is provided. In some embodiments, the method includes: receiving a first control block from a non-secure processing unit by a data interface of an encryption co-processing unit; latching the first control block received from the non-secure processing unit by the data interface; receiving a first data block from the non-secure processing unit by the data interface; and transmitting the locked first control block and the received first data block to a hardware encryption engine of the encryption co-processing unit by the data interface.

[0014] The above content of the invention is provided only for the purpose of summarizing some example embodiments, in order to provide a basic understanding of some aspects of the present disclosure. Therefore, it will be understood that the above embodiments are only examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It should also be understood that the scope of the present disclosure, in addition to covering the embodiments summarized here, also covers many potential embodiments, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The description of the exemplary embodiments may be read in conjunction with the accompanying drawings. It will be understood that for simplicity and clarity of illustration, the elements illustrated in the drawings are not necessarily drawn to scale unless otherwise noted. For example, the dimensions of some elements may be exaggerated relative to other elements unless otherwise noted. Embodiments incorporating the teachings of the present disclosure are illustrated and described with respect to the drawings presented herein, in which:

[0016] Figure 1 illustrates a block diagram of an example system for data transfer according to an example embodiment of the present disclosure;

[0017] Figure 2 illustrates a more detailed block diagram of a portion of an example system for data transfer according to an example embodiment of the present disclosure;

[0018] Figure 3 is an example flow chart illustrating an example method for transmission of data for secure processing according to an example embodiment of the present disclosure;

[0019] Figure 4 Pictured Figure 2 Example data flows within an example system for data transmission;

[0020] Figure 5 illustrates a more detailed block diagram of a portion of an example system for data transfer according to an alternative example embodiment of the present disclosure; and

[0021] Figure 6 is an example flow chart illustrating an example method for transmission of data for secure processing according to an alternative example embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Some embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. In fact, these disclosures may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure satisfies applicable legal requirements. Like reference numerals refer to like elements throughout.

[0023] As used herein, in the examples provided below, for explanation purposes, terms such as "front", "rear", "top" and the like are used to describe the relative positions of certain components or parts of components. In addition, it will be apparent to one of ordinary skill in the art from this disclosure that the terms "substantially" and "approximately" indicate that the referenced element or associated description is accurate within an applicable engineering tolerance.

[0024] As used herein, the term "comprising" means including but not limited to, and should be interpreted in the manner commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and consisting essentially of.

[0025] The phrases "in one embodiment," "according to one embodiment," etc. generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0026] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0027] If the specification states that a component or feature "may", "could", "might", "should", "will", "preferably", "likely", "usually", "optionally", "for example", "often", or "might" (or other such language) be included or have a property, the particular component or feature need not be included or have that property. Such a component or feature may optionally be included in some embodiments, or it may be excluded.

[0028] The secure communication and / or processing of data such as via encryption algorithms is becoming more and more common in many applications and systems. For example, the safety of automobiles is becoming more and more important, especially because it has been proven that hackers can remotely control vehicles. For this reason, the communication between the various processing systems of the vehicle (at least the processing systems that may have an impact on data security) is usually encrypted. Although such encryption ensures secure communication and data processing, the use of encryption adds new challenges in message processing delay and robustness (i.e., processing error handling). In some contexts, such processing systems are located at different locations of the vehicle and may include, for example, an engine control unit (ECU), a transmission control unit (TCU), an anti-lock braking system (ABS), a body control module (BCM), and / or a navigation and / or multimedia audio system.

[0029] In response to these emerging and steadily growing demands for security functions within the vehicle's processing system, one approach that has been used is to introduce a secure programmable element that is isolated from the rest of the microcontroller and is dedicated to processing and supervising security tasks. Typically, the secure element is a dedicated and preferably programmable hardware component (e.g., within a field programmable gate array (FPGA), digital signal processor (DSP), microcontroller, etc.) and is dedicated to processing and / or supervising security functions. With such an architecture, the isolated secure element acts as a server to the rest of the processing system, exposing cryptographic services that are activated upon request.

[0030] Although embodiments of the present disclosure will be described herein in terms of use with in-vehicle data transfer, embodiments of the present disclosure may be used for data transfer in any suitable system and / or environment.

[0031] Reference now Figure 1 , a block diagram of an example system for data transfer is illustrated according to an example embodiment of the present disclosure. In some embodiments, the example system includes at least one processing system 100, such as a microprocessor, programmed via software instructions. In some embodiments, the processing system 100 includes a secure element 105 and a non-secure element 125. As further described below, embodiments of the present invention relate to data transfer between a secure element 105 and a non-secure element 125 and data transfer within a secure element 105.

[0032] The safety element 105 is generally referred to as a hardware security module (HSM). In some embodiments, the safety element 105 includes a processing unit 110, such as an additional microprocessor or a dedicated hardware module programmed via software. In some embodiments, the safety element 105 also includes an encryption coprocessor 115. The encryption coprocessor 115 is a hardware engine dedicated to processing encryption services. In some embodiments, the encryption coprocessor 115 includes one or more digital encryption / cryptographic keys (unknown to non-safety element 125) that can be used, for example, to encrypt or decrypt data packets. In some embodiments, the safety element 105 is in an isolated environment to prevent access to the firmware (and therefore encryption keys) of the encryption coprocessor 115.

[0033] In some embodiments, the security element 105 is configured to use an encryption key with a symmetric encryption algorithm (e.g., Advanced Encryption Standard (AES)) or an asymmetric encryption algorithm to, for example, encrypt or decrypt data, such as by decrypting a signature field to verify the identity of the sender, calculate a hash function, etc. Symmetric key encryption is based on an algorithm run by two entities using the same key known to both entities. The AES encryption algorithm is defined by the National Institute of Standards and Technology (NIST). The AES encryption algorithm defines an exact mathematical algorithm that is applied to 16 bytes of input data and transforms the input data into an output. The AES encryption algorithm uses a secret key as an input parameter of the algorithm. The AES encryption algorithm is irreversible. That is, given an output, even if the algorithm is known, it is impossible to derive the input without knowing the secret key. A variation of the AES encryption algorithm, referred to as "AES Light," is described in commonly owned U.S. Patent Nos. 11,032,067, filed on June 28, 2018, and issued on June 8, 2021, and 11,057,194, filed on June 28, 2018, and issued on July 6, 2021, the contents of which are incorporated herein by reference in their entirety. Although embodiments of the present disclosure are described herein in terms of using the AES Light encryption algorithm, embodiments of the present disclosure may be used with any suitable encryption algorithm.

[0034] The architecture creates a separation between secure elements and non-secure elements. Cryptographic service processing and keys for cryptographic algorithms reside entirely within the secure domain.

[0035] In some embodiments, the processing system 100 includes one or more resources, such as: one or more memories, one or more communication interfaces, one or more analog-to-digital and / or digital-to-analog converters, one or more digital components, one or more analog components, and / or one or more mixed signal components. One or more memories may include, for example, but not limited to, volatile memory and / or non-volatile memory. One or more communication interfaces may include, for example, but not limited to, universal asynchronous receiver / transmitter (UART), serial peripheral interface bus (SPI), internal integrated circuit (I2C), controller area network (CAN) bus and / or Ethernet. One or more dedicated digital components may include, for example, but not limited to, hardware timers and / or counters. One or more analog components may include, for example, but not limited to, comparators, sensors, such as temperature sensors, etc. One or more mixed signal components may include, for example, but not limited to, pulse width modulation (PWM) drivers.

[0036] In some embodiments, each of these resources can be a local resource 130 accessible by (e.g., only by) a non-secure element 125, a shared resource 135 accessible by both a secure element 105 and a non-secure element 125, or a local resource 120 accessible by (e.g., only by) a secure element 105.

[0037] In some embodiments, processing system 100 includes a communication channel between secure element 105 and non-secure element 125 (via Figure 1 The communication channel is used to send encrypted service requests to the security element, such as encryption or decryption of data, which may come from message communications between different engine control units. For example, an engine control unit that detects a dangerous situation may send a message to another engine control unit asking it to activate the braking system. To avoid attacks on this communication, the exchanged data may be encrypted.

[0038] One method that has been used by the AES Light encryption algorithm is to transmit the data to be processed by the AES Light encryption algorithm in 16-byte blocks (referred to as AES blocks or data blocks). The data is processed by the AES Light encryption algorithm. According to the AESLight encryption algorithm, this type of data processing is called AES mode. Several modes within the AES algorithm are defined, such as: encryption, decryption, CMAC (Cipher-based Message Authentication Code) signature generation, CMAC signature verification, etc. The AES Light encryption algorithm can be operated via software, where the CPU transfers data to / from the AES Light encryption engine (described further below), or in hardware, where direct memory access (DMA) moves data into / out of the AES Light encryption engine.

[0039] According to the AES Light encryption algorithm, the data to be processed can be a stream of exactly 16 bytes or 16-byte data blocks. According to the AES Light encryption algorithm, before starting the encryption process, the encryption engine needs to be set up by passing specified control information. According to the AES Light encryption algorithm, such control information may include which kind of AES processing should be performed, which key should be used, how the data is sent (in the case where the AES Light encryption engine does not have an embedded DMA and an external DMA should be triggered), etc. According to the AES Light encryption algorithm, this setup information is transmitted via an 8-byte control block.

[0040] According to the AES Light encryption algorithm, after receiving the first control block, the AES Light encryption engine should be started, and if the data is a long stream of AES blocks, the AES Light encryption engine will mostly perform the same operation until all data is completely processed. According to the AES Light encryption algorithm, in addition to providing the AES Light encryption engine with a control block with setup information before the data is sent, the control block is also sent before the last data block to instruct the AESLight encryption engine to stop AES processing. According to the AES Light encryption algorithm, control blocks and data blocks are interleaved. That is, for each data block sent, there is a control block sent immediately before each data block (8-byte control block, 16-byte data block, 8-byte control block, 16-byte data block, 8-byte control block, 16-byte data block, etc., until the last data block is sent). According to the AES Light encryption algorithm, the AES Light encryption engine expects to receive such interleaved control blocks and data blocks.

[0041] However, as described above, if a long stream of AES blocks is transmitted, the AES Light encryption engine will essentially perform the same operation until all data is completely processed. Therefore, in many contexts, only the first control block and the last control block contain relevant content, and control blocks other than the first control block and the last control block are repeated.

[0042] Various embodiments of the present disclosure overcome the above technical challenges and difficulties and provide various technical improvements and advantages. Various embodiments of the present disclosure at least provide a mechanism for latching control block values ​​and reusing latched control block values ​​instead of transmitting control blocks before each data block.

[0043] Various embodiments of the present disclosure use an internal counter to indicate how many data blocks will be sent without a corresponding control block, and therefore how many times the latched value of a control block will be reused before a new control block is expected.

[0044] Various embodiments of the present disclosure use a write control signal and a match of a write transaction address with an address of a control register to trigger latching of a control register, and reuse the latched control block until a new control block has been latched again.

[0045] Various embodiments of the present disclosure enable the optional choice of using an internal counter to indicate how many data blocks will be sent without a corresponding control block, or using a write control signal and a match of a write transaction address with an address of a control register to trigger latching of a control register.

[0046] Various embodiments of the present disclosure enable innovative processing of data processing aimed at improving data transfer performance. By not transmitting a control block with each data block, various embodiments of the present disclosure enable the amount of data transmitted to be reduced by almost one third.

[0047] The AES Light encryption algorithm specifies the bit fields of the control block, that is, what each bit or combination of bits in the 8-byte control block indicates. For example, according to the AES Light encryption algorithm, some bits in the first control block specify which AES mode and which key are to be used. According to the current AES Light encryption algorithm, there are 10 unused bits in the control block. Various embodiments of the present disclosure use some or all of these unused bits in the control block to implement one or more features of embodiments of the present disclosure.

[0048] Reference now Figure 2 , according to an example embodiment of the present disclosure, illustrates a more detailed block diagram of a portion of an example system for data transmission. In some embodiments, Figure 2 The example system implementation uses an internal counter to indicate how many data blocks will be sent without a corresponding control block. Figure 2 A processing system 200, such as a microprocessor, is shown programmed via software instructions. In some embodiments, the processing system 200 includes a secure element and a non-secure element 225. Figure 2 In the example shown, the secure element includes a cryptographic coprocessor 215 and the cryptographic coprocessor 216 is omitted for simplicity. Figure 1 As further described below, embodiments of the present invention relate to data transfers between the cryptographic coprocessor 215 of the secure element and the non-secure element 225, as well as data transfers within the cryptographic coprocessor 215. As shown, the non-secure element 225 may include a CPU that transfers data to / from the cryptographic coprocessor 215 or a DMA that moves data to / from the cryptographic coprocessor 215. If DMA is used, the data transfer trigger procedure is as follows: Figure 2 As shown, the non-secure element 225 may utilize local resources (such as RAM 265 and / or non-volatile memory 270) to store / access control information and / or data.

[0049] In some embodiments, the encryption coprocessor 215 includes an AES Light encryption engine core 235, which implements the AES Light encryption algorithm, such as by using one or more keys stored in the key storage memory 240. In some embodiments, the AES Light encryption engine core implements the AES Light algorithm into the core logic, which is activated each time 16 data bytes are to be processed. In some embodiments, the way the input data is processed is determined by, for example, the AES mode as encryption, decryption, or signature calculation, etc. In some embodiments, the algorithm used to process the 16 data bytes is always the same regardless of the selected AES mode. In some embodiments, the implementation of the encryption engine has additional hardware features, such as a register interface for pushing data bytes and reading out results. In some embodiments, the implementation of the encryption engine has a component for notifying the encryption engine what to do, such as which AES mode, which secret key to use, etc. In some embodiments, as further described below, the component for notifying the encryption engine what to do is a control register.

[0050] In some embodiments, cryptographic coprocessor 215 includes data processing circuitry 245. In some embodiments, data processing circuitry 245 includes an AES register interface 250 that receives control blocks and data blocks from / sends control blocks and data blocks to / from non-secure element 225, such as Figure 2 In some embodiments, data processing circuitry 245 also includes a counter 255 (eg, a countdown counter) and a control block latch memory location 260 for latching a control block, as described herein.

[0051] Reference now Figure 3 , illustrates an example method 300 according to some embodiments of the present disclosure. Specifically, the example method 300 illustrates example steps / operations of transmitting data for secure processing according to some embodiments of the present disclosure. Figure 3 The example method of describes transferring data from a non-secure element 225 to a cryptographic coprocessor 215 , but embodiments of the present invention may also be used to transfer data from a cryptographic coprocessor 215 to a non-secure element 225 . Figure 3 The example method describes transferring data from the CPU as a non-secure element 225, rather than via DMA, but embodiments of the present invention may also be used to transfer data via DMA.

[0052] Figure 3 The example method 300 of FIG. 1 begins at step / operation 305. At step / operation 310, a controller in a security element (such as, but not limited to, the combination described above) Figure 2, the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) from a controller in a non-secure element (such as, but not limited to, the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) Figure 2 The CPU of the non-secure element 225 of the system 200 described above receives the control block. According to the AES Light encryption algorithm, the first control block includes setting information, such as, for example, which AES processing should be performed, which key should be used, how the data is sent, etc. In some embodiments, the first control block also includes a setting value for a timer (such as a countdown timer). In some embodiments, the setting value for the timer is equal to the number of data blocks that will be sent from the non-secure element in the absence of a corresponding control block. In some embodiments, the number of data blocks that will be sent in the absence of a corresponding control block is determined based on the number of data blocks that have been sent with the same control block as a rule. Therefore, in some embodiments, the number of data blocks that will be sent in the absence of a corresponding control block is equal to the total number of data blocks minus the last data block (according to the AES Light encryption algorithm, the last data block is preceded by the last control block, and the last control block indicates that the next data block is the last data block).

[0053] As described above, according to the current AES Light encryption algorithm, there are 10 unused bits in the control block. If all ten unused bits are used by embodiments of the present disclosure to specify counter setting values, the maximum counter setting value will be 1024 (i.e., 2^10). In some embodiments, some of the unused bits may be used for other features of embodiments of the present disclosure, in which case the maximum counter setting value will be less than 1024 (e.g., 512 (i.e., 2^9) if 9 of the unused bits are used to specify counter setting values, or 256 (i.e., 2^8) if 8 of the unused bits are used to specify counter setting values).

[0054] In some embodiments, if the number of data blocks to be sent without a corresponding control block is greater than the maximum counter setting value, which can be based on the number of unused bits used by embodiments of the present disclosure to specify the counter setting value, the data blocks to be sent without a corresponding control block can be divided into two or more groups, where the control block sent at the beginning of each group specifies the appropriate counter setting value for the group. For example, if the maximum counter setting value is 1024 and the number of data blocks to be sent without a corresponding control block is 1500, the data blocks can be sent in two groups. In such an example, there can be one group of 1000 data blocks and one group of 500 data blocks, where the control block in front of each group indicates the appropriate counter setting value for the group.

[0055] At step / operation 315, a controller in the security element (such as but not limited to the combination described above) Figure 2 , the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) will be a counter element (such as but not limited to the above combination Figure 2 The counter 255 of the described system 200 is set to the setting value specified in the control block received at step / operation 310. In some embodiments, the counter is a countdown counter.

[0056] In some embodiments, if the counter bit field is set to 0, this indicates that a control block will be sent with each data block. In some embodiments, this enables compatibility with the standard AES Light encryption algorithm.

[0057] At step / operation 320, a controller in a secure element (such as but not limited to the above for Figure 2 , the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) latches or stores the control block received at step / operation 310 at a memory location (such as, but not limited to, the above for Figure 2 The control block of the depicted system 200 latches the memory location 260).

[0058] At step / operation 325, a controller in the security element (such as but not limited to the above for Figure 2 , the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) from a controller in a non-secure element (such as but not limited to the above for Figure 2 A CPU of a non-secure element 225 of the described system 200 receives a data block.

[0059] At step / operation 330, a controller in a secure element (such as but not limited to the above for Figure 2 , the encryption coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) decrements the counter 255 in response to the data block received at step / operation 325.

[0060] At step / operation 335, a controller in the security element (such as but not limited to the above for Figure 2 , the encryption coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) transmits the latched control block and the data block received at step / operation 325 to the encryption engine (such as but not limited to the above for Figure 2 The AESLight encryption engine core 235 of the described system 200 is used to process according to the AES Light encryption algorithm.

[0061] At step / operation 340, a controller in a secure element (such as but not limited to the above for Figure 2 , the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) determines whether the value of the counter 255 is zero. If it is determined at step / operation 340 that the value of the counter 255 is not zero, the method 300 returns to step / operation 325, at which time the controller in the security element (such as but not limited to the above for Figure 2 , the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) receives another data block from the controller in the non-secure element. In some embodiments, steps / operations 325 to 340 will continue until it is determined at step / operation 340 that the value of the counter 255 is zero.

[0062] If it is determined at step / operation 340 that the value of counter 255 is zero, the method 300 proceeds to step / operation 345, where it is determined whether there are more data blocks to be transmitted (except the last data block). As described above, the number of data blocks to be sent without a corresponding control block can be greater than the maximum counter setting value, which can be based on the number of unused bits used by embodiments of the present disclosure to specify the counter setting value. In such a case, the data blocks to be sent without a corresponding control block can be divided into two or more groups, where the control block sent at the beginning of each group specifies the appropriate counter setting value for the group. Step / operation 345 takes into account such a situation, where there is a second (or third or fourth, etc.) group of data blocks to be sent without a corresponding control block. If it is determined at step / operation 345 that there are more data blocks to be transmitted (except the last data block), the method 300 returns to step / operation 310, in which a new control block with a new counter setting value is received. In some embodiments, steps / operations 310 through 345 will continue until it is determined at step / operation 345 that there are no more data blocks to be transmitted (other than the last data block), at which point method 300 proceeds to step / operation 350 .

[0063] At step / operation 350, a controller in a secure element (such as but not limited to the above with respect to Figure 2 , the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) from a controller in a non-secure element (such as but not limited to the above for Figure 2 The CPU of the non-secure element 225 of the described system 200 receives the last control block and the last data block.

[0064] At step / operation 355, a controller in the security element (such as but not limited to the above for Figure 2 , the encryption coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) transmits the last control block and the last data block received at step / operation 350 to the AES Light encryption engine core 235 for processing according to the AES Light encryption algorithm. Figure 3 The example method 300 ends at step / operation 360 .

[0065] Reference now Figure 4 , illustrating the example that can be Figure 3 The data example flow seen in the example method 300 of FIG. Figure 4 As shown, data stream 400 includes an initial control block 405, which contains setup information and a setting value ("N") for a timer as described above, the setting value for the timer being equal to the number of data blocks that will be sent without a corresponding control block. After initial control block 405 is sent, multiple data blocks 410a, 410b, 410c, etc. are sent without interleaved control blocks. After "N" data blocks have been sent without a corresponding preceding control block, a final control block 415 is sent, which indicates that the next data block is the last data block, and then a final data block 420 is sent.

[0066] Reference now Figure 5 , according to an example embodiment of the present disclosure, illustrates a more detailed block diagram of a portion of an example system for data transmission. In some embodiments, Figure 5 The example system implements the use of an internal write control signal to indicate that a new control block has been received, should be latched and should be reused until another new control block is received. Figure 5 A processing system 500, such as a microprocessor, is illustrated that is programmed via software instructions. In some embodiments, the processing system 500 includes a secure element and a non-secure element 525. Figure 5 In the example shown, the secure element includes a cryptographic coprocessor 515 and omits Figure 1 5. The embodiments of the present invention relate to data transfer between the cryptographic coprocessor 515 of the secure element and the non-secure element 525, as well as data transfer within the cryptographic coprocessor 515, as further described below. As shown, the non-secure element 525 may include a CPU for transferring data to / from the cryptographic coprocessor 515 or a DMA for moving data to / from the cryptographic coprocessor 515. If DMA is used, a data transfer trigger is sent, such as Figure 5 As shown, the non-secure element 525 can utilize local resources, such as RAM 565 and / or non-volatile memory 570, for storing / access control and / or data.

[0067] In some embodiments, the cryptographic coprocessor 515 includes an AES Light cryptographic engine core 535 that implements an AES Light cryptographic algorithm, such as by using one or more keys stored in a key storage memory 540 .

[0068] In some embodiments, cryptographic coprocessor 515 includes data processing circuitry 545. In some embodiments, data processing circuitry 545 includes an AES register interface 550 that receives control blocks and data blocks from / sends control blocks and data blocks to / from non-secure element 525, such as Figure 5 In some embodiments, data processing circuitry 545 also includes a control register write signal 555 and a control block latch memory location 560 for latching a control block as described herein.

[0069] Reference now Figure 6 , illustrates an example method 600 according to some embodiments of the present disclosure. Specifically, the example method 600 illustrates example steps / operations of transmitting data for secure processing according to some embodiments of the present disclosure. Figure 6 The example method of describes transferring data from a non-secure element 225 to a cryptographic coprocessor 215 , however embodiments of the present invention may also be used to transfer data from a cryptographic coprocessor 215 to a non-secure element 225 . Figure 6 The example method describes transferring data from the CPU as a non-secure element 225, rather than via DMA, however embodiments of the present invention may also be used to transfer data via DMA.

[0070] Figure 6 The example method 600 of 600 begins at step / operation 605. At step / operation 610, a controller in a security element (such as but not limited to the above-described Figure 2 , the encryption coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) determines whether the control block has been received, such as by determining the state of the control register write signal 555.

[0071] If it is determined at step / operation 605 that a control block has been received, the method 600 proceeds to step / operation 610. At step / operation 615, a controller in the security element (such as but not limited to the above for Figure 2 , the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) locks or stores the received control block at a memory location (such as, but not limited to, the above for Figure 2 The control block of the depicted system 200 latches the memory location 260).

[0072] If it is determined at step / operation 610 that the control block has not been received (because it has been previously received), the method 600 proceeds to step / operation 620. At step / operation 620, a controller in the security element (such as, but not limited to, the controller described above for Figure 2 , the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) from a controller in a non-secure element (such as but not limited to the above for Figure 2 A CPU of a non-secure element 225 of the described system 200 receives a data block.

[0073] At step / operation 625, a controller in the security element (such as but not limited to the above for Figure 2 , the cryptographic coprocessor 215 of the system 200 described in conjunction with the AES register interface 250) transmits the latched control block and the data block received at step / operation 620 to an encryption engine (such as but not limited to the above for Figure 2 The AES Light encryption engine core 235 of the described system 200 is used to perform processing according to the AES Light encryption algorithm.

[0074] At step / operation 630, it is determined whether there are more data blocks to be transmitted. If it is determined at step / operation 630 that there are more data blocks to be transmitted, method 600 returns to step / operation 610. In some embodiments, steps / operations 610 to 630 will continue until it is determined at step / operation 630 that there are no more data blocks to be transmitted, at which point method 600 proceeds to step / operation 635, at which point Figure 6 The example method 600 ends.

[0075] Note that each block of the flowchart and combinations of blocks in the flowchart may be implemented in various ways, such as hardware, firmware, circuitry, and / or other devices associated with the execution of software including one or more programming instructions. Figure 3 and Figure 6 One or more of the methods described in the method can be implemented by programming instructions, which can be stored by a non-transitory memory component of a device using an embodiment of the present disclosure and executed by one or more processing components in the device. These programming instructions can direct the processing component or other programmable device to operate in a specific manner so that the instructions stored in the non-transitory memory component produce an article, and the execution of the article implements the functions specified in the (multiple) flowchart blocks.

[0076] As described above and as will be understood based on the present disclosure, the embodiments of the present disclosure may be configured as methods, devices, etc. Therefore, embodiments may include various components, including complete hardware or any combination of software and hardware. In addition, embodiments may take the form of a computer program product on at least one non-transient computer-readable storage medium, and at least one non-transient computer-readable storage medium has a computer-readable program instruction (e.g., computer software) embodied in the storage medium. Similarly, embodiments may take the form of a computer program code stored on at least one non-transient computer-readable storage medium. Any suitable computer-readable storage medium may be used, including a non-transient hard disk, a CD-ROM, a flash memory, an optical storage device, or a magnetic storage device.

[0077] The example systems 100 , 200 , 500 may be implemented as part of an integrated circuit (IC) to perform, for example, one or more functions of a vehicle such as, but not limited to, engine control, transmission control, anti-lock braking, and the like.

[0078] The microprocessor 100, 200, 500 may include one or more processors, input / output circuit devices, data storage media, communication circuit devices, and / or other components configured to perform computing operations. In some embodiments, the data storage medium may be configured to store information, data, content, applications, instructions, etc., so that the microprocessor 100, 200, 500 can perform various functions. Therefore, in some embodiments, the microprocessor 100, 200, 500 may be referred to as functional logic. The microprocessor 100, 200, 500 may be embodied in a plurality of different ways, for example, in some embodiments, the microprocessor 100, 200, 500 may include one or more processing devices configured to be independently executed. Additionally or alternatively, in some embodiments, the microprocessor 100, 200, 500 may include one or more processors, which are configured in series via a bus to implement independent execution, pipeline and / or multithreading of instructions. The use of the terms "controller," "processor," and "processing circuitry" should be understood to include a single core processor, a multi-core processor, multiple processors within the microprocessor 100, 200, 500, and / or one or more remote or "cloud" processors external to the microprocessor 100, 200, 500.

[0079] In example embodiments, the microprocessor 100, 200, 500 may be configured to execute instructions stored in a data storage medium or instructions otherwise accessible to the processor. Alternatively or additionally, the microprocessor 100, 200, 500 is configured in some embodiments to execute hard-coded functions. Therefore, whether configured by hardware or software methods, or by a combination thereof, the microprocessor 100, 200, 500 represents an entity (e.g., physically embodied in a circuit device) that can perform operations according to an embodiment of the present disclosure while being configured accordingly. Alternatively or additionally, as another example in some example embodiments, when the microprocessor 100, 200, 500 is embodied as an executor of software instructions, when such instructions are executed, the instructions specifically configure the microprocessor 100, 200, 500 to execute the algorithm embodied in the specific operations described herein.

[0080] Although components are described with respect to functional limitations, it should be understood that specific implementations necessarily include the use of specific hardware. It should also be understood that certain components described herein may include similar or common hardware. For example, two sets of circuit devices may each utilize the same processor, network interface, storage medium, etc. to perform their associated functions, such that duplicate hardware is not required for each set of circuit devices.

[0081] Thus, use of the term "circuitry" herein with respect to components of an apparatus should be understood to include specific hardware configured to perform the functions associated with the specific circuitry described herein. The term "circuitry" should be broadly understood to include hardware, and in some embodiments, software for configuring the hardware. For example, in some embodiments, "circuitry" may include processing circuitry, storage media, network interfaces, input / output devices, etc.

[0082] Although Figure 1 , Figure 2 and Figure 5 The example block diagrams of FIG. 1 respectively illustrate example systems 100, 200, and 500 for data transmission for secure processing, but note that the scope of the present disclosure is not limited to Figure 1 , Figure 2 and Figure 5 Example system shown. In some embodiments, the example system for data transfer for secure processing may include one or more additional or alternative components.

[0083] in conclusion

[0084] Those skilled in the art will recognize many modifications and other embodiments of the disclosure set forth herein, and many modifications and other embodiments to which the disclosure relates have the benefit of the teachings presented in the above description and associated drawings. Although the drawings show only certain components of the apparatus and system described herein, it is understood that various other components may be used in conjunction with the system. Therefore, it should be understood that the disclosure is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, the steps in the above method do not necessarily occur in the order described in the drawings, and in some cases, one or more of the steps described may occur substantially simultaneously, or may involve additional steps. Although specific terms are used herein, they are used only in a general and descriptive sense and are not used for limiting purposes.

[0085] Although various embodiments according to the principles disclosed herein have been shown and described above, those skilled in the art may modify them without departing from the spirit and teachings of the present disclosure. The embodiments described herein are representative only and are not intended to be limiting. Many variations, combinations, and modifications are possible and within the scope of the present disclosure. Alternative embodiments resulting from combining, integrating, and / or omitting features of the embodiments are also within the scope of the present disclosure. Therefore, the scope of protection is not limited by the above description.

[0086] Additionally, section headings used herein are provided to be consistent with the recommendations under 37 CFR 1.77 or to otherwise provide organizational cues. These headings should not limit or characterize the disclosure(s) that may be issued from the disclosure as recited in any claim.

[0087] Although the present detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the described embodiments according to various modifications and improvements. For example, the appended claims may cover any form of integrated circuit that provides secure data transmission such as within a vehicle, and such as but not limited to an engine control unit (ECU), a transmission control unit (TCU), an anti-lock braking system (ABS), a body control module (BCM), and / or a navigation and / or multimedia audio system.

[0088] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that the claims be interpreted under 35 USC 112, section 6.

Claims

1. A processing system comprising: Non-secure processing unit; as well as An encryption co-processing unit, the encryption co-processing unit comprising: a data interface configured to receive one or more control blocks and one or more data blocks from the non-secure processing unit; and a hardware encryption engine configured to process the one or more control blocks and the one or more data blocks received by the data interface according to an encryption key; wherein the data interface is configured to receive a first control block from the non-secure processing unit; wherein the data interface is configured to latch the received first control block; wherein the data interface is configured to receive a first data block from the non-secure processing unit; and The data interface is configured to transmit the latched first control block and the received first data block to the hardware encryption engine.

2. The processing system of claim 1 , wherein the data interface is configured to receive a second data block from the non-secure processing unit; and in, If the second data block is received from the non-secure processing unit without a corresponding second control block, the data interface is configured to transmit the latched first control block and the received second data block to the hardware cryptographic engine.

3. The processing system of claim 2, wherein the data interface is configured to receive a second control block from the non-secure processing unit; wherein the data interface is configured to latch the received second control block; wherein the data interface is configured to receive a third data block from the non-secure processing unit; and The data interface is configured to transmit the latched second control block and the received third data block to the hardware encryption engine.

4. The processing system of claim 3, wherein the data interface is configured to receive a fourth data block from the non-secure processing unit; and in, If the fourth data block is received from the non-secure processing unit without a corresponding third control block, the data interface is configured to transmit the latched second control block and the received fourth data block to the hardware cryptographic engine.

5. The processing system of claim 1 , wherein the first control block includes a counter setting value corresponding to a number of data blocks to be received by the data interface from the non-secure processing unit in the absence of a corresponding control block; wherein the data interface is configured to set a countdown counter to the counter setting value in the first control block; and Wherein the data interface is configured to decrement the countdown counter by one for each data block received from the non-secure processing unit without a corresponding control block.

6. The processing system according to claim 5, wherein: After each data block is received by the data interface from the non-secure processing unit without a corresponding control block, the data interface is configured to check a current value of the countdown counter; and Wherein, if the current value of the countdown counter is equal to zero, the data interface is configured to anticipate receiving a control block for a next data block received from the non-secure processing unit.

7. The processing system of claim 1, wherein the hardware cryptographic engine is configured to support Advanced Encryption Standard operations.

8. The processing system of claim 1, wherein each of the one or more control blocks contains 8 bytes of data, and each of the one or more data blocks contains 16 bytes of data.

9. A processing system comprising: Non-secure processing unit; as well as An encryption co-processing unit, the encryption co-processing unit comprising: a data interface configured to receive a plurality of control blocks and a plurality of data blocks from the non-secure processing unit, at least some of the plurality of data blocks being received after corresponding respective ones of the plurality of control blocks; and a hardware encryption engine configured to process the plurality of control blocks and the plurality of data blocks received by the data interface according to an encryption key; wherein the data interface is configured to latch each control block as it is received, thereby overwriting any previously latched control block; and Each time a data block is received, the data interface is configured to transmit the latched control block and the received data block to the hardware encryption engine.

10. The processing system of claim 9, wherein at least a first control block of the plurality of control blocks includes a counter setting value corresponding to a number of data blocks to be received by the data interface from the non-secure processing unit in the absence of a corresponding control block; wherein the data interface is configured to set a countdown counter to the counter setting value in the first control block among the plurality of control blocks; and Wherein the data interface is configured to decrement the countdown counter by one for each data block received from the non-secure processing unit without a corresponding control block.

11. The processing system according to claim 10, wherein: After each data block is received by the data interface from the non-secure processing unit without a corresponding control block, the data interface is configured to check a current value of the countdown counter; and Wherein, if the current value of the countdown counter is equal to zero, the data interface is configured to anticipate receiving a control block for a next data block received from the non-secure processing unit.

12. The processing system of claim 9, wherein the hardware cryptographic engine is configured to support Advanced Encryption Standard operations.

13. The processing system of claim 9, wherein each of the plurality of control blocks contains 8 bytes of data, and each of the plurality of data blocks contains 16 bytes of data.

14. A method for receiving data to be encrypted, the method comprising: receiving a first control block from a non-secure processing unit via a data interface of the cryptographic co-processing unit; latching, by the data interface, the first control block received from the non-secure processing unit; receiving, by the data interface, a first data block from the non-secure processing unit; as well as The latched first control block and the received first data block are transmitted to the hardware encryption engine of the encryption co-processing unit through the data interface.

15. The method according to claim 14, further comprising: receiving, by the data interface, a second data block from the non-secure processing unit; as well as If the second data block is received from the non-secure processing unit without a corresponding second control block, the latched first control block and the received second data block are transmitted by the data interface to the hardware cryptographic engine of the cryptographic co-processing unit.

16. The method of claim 14, wherein the first control block includes a counter setting value corresponding to a number of data blocks to be received by the data interface from the non-secure processing unit in the absence of a corresponding control block; and The method further comprises: Setting the countdown counter to the counter setting value in the first control block by the data interface of the encryption co-processing unit; as well as The countdown counter is decremented by one by the data interface of the cryptographic co-processing unit for each data block received from the non-secure processing unit without a corresponding control block.

17. The method according to claim 16, further comprising: checking, by the data interface, a current value of the countdown counter after each data block is received by the data interface from the non-secure processing unit without a corresponding control block; Wherein, if the current value of the countdown counter is equal to zero, the data interface is configured to anticipate receiving a control block for a next data block received from the non-secure processing unit.

18. The method according to claim 14, further comprising: receiving, by the data interface, a second control block from the non-secure processing unit; locking the received second control block by the data interface of the encryption co-processing unit; receiving, by the data interface from the non-secure processing unit, a third data block from the non-secure processing unit; as well as The latched second control block and the received third data block are transmitted to the hardware encryption engine through the data interface.

19. The method according to claim 18, further comprising: receiving, by the data interface, a fourth data block from the non-secure processing unit; as well as If the fourth data block is received from the non-secure processing unit without a corresponding third control block, the locked second control block and the received fourth data block are transmitted by the data interface to the hardware encryption engine.

20. The method of claim 14, wherein the hardware cryptographic engine is configured to support Advanced Encryption Standard operations.

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