Method for realizing split verification of multi-core dsp secondary system based on FPGA

Abstract

The invention discloses a method for realizing split verification of a multi-core dsp secondary system based on an FPGA (Field Programmable Gate Array). The method comprises the following steps: S1, setting a multi-core dsp and a high-speed interconnection bus as a primary system; a plurality of command detection modules are additionally arranged at the tail end of a high-speed interconnection bus, and the command detection modules are used for replacing the function of a to-be-verified module; s2, the multi-core dsp issues a plurality of instructions and verifies the instructions to distinguish channels with problems and channels without problems; and S3, setting a to-be-verified module in the FPGA as a secondary system, setting a high-speed special bus, increasing the main frequency in the FPGA to the lowest frequency required by the secondary system, and performing communication verification by using the high-speed special bus to obtain a verification result. The whole system is divided into two stages of systems, so that when the multi-core dsp is transplanted, certain segmentation is performed on the use of configuration resources in the FPGA and the demand on a main frequency, the multi-core dsp can be transplanted by using one FPGA, the cost is reduced, and netlist segmentation is not required; and meanwhile, the requirement of the main frequency is ensured, and more verifiable interface types are available.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a method for realizing multi-core DSP secondary system split verification based on FPGA. Background Art

[0002] Multi-core DSP is an advanced technology that combines digital signal processing technology with multi-core processor architecture. Each DSP core can be connected to other necessary components of SOC through a high-speed interconnect bus. Figure 4 As shown, it is a schematic diagram of the structure of an existing multi-core DSP when transplanted to FPGA. The multi-core DSP can connect to the internal resources of FPGA such as SRAM and DDR through a high-speed interconnection bus, and can also connect to interfaces such as PCIE, SRIO and GMAC through a high-speed interconnection bus and a high-speed IO interconnection bus in sequence. It can also connect to interfaces such as UART, CAN, I2C and SPI through a high-speed interconnection bus and a low-speed IO interconnection bus in sequence.

[0003] When a multi-core dsp is transplanted to an FPGA, since the capacity of the FPGA is not enough to carry all the chips, logic reduction is required, such as reducing multiple dsp cores to two dsp cores or even one dsp core, removing the SRAM that occupies more storage resources, and removing the interfaces that are not currently verified. For example, if only GMAC is verified, GMAC is used to load the compiled software file to be verified, and the PCIE interface and SRIO interface can be removed first; at the same time, only the necessary parts for debugging are retained in the low-speed interface, and the others can be removed to form a minimum system that can be started. This minimum system generally includes the necessary parts for the chip to start and the parts to be verified, including at least one dsp core, a high-speed interconnect bus for communication between the hardware parts on the chip and the dsp core, DDR for instruction storage and movement, GMAC interface, UART interface for printing current verification status information and error information, and SPI interface for startup.

[0004] However, even in such a tailored system, the logic it contains is still far beyond the scope of an FPGA. To solve this problem, the usual method is to split the compiled netlist into several FPGAs for layout and routing, and complete the bit file generation.

[0005] However, there are at least three problems with this approach: 1) It is inconvenient to capture and observe signals in the netlist after segmentation. This is because after the netlist is segmented, the original logic is broken up and many additional netlist signals are generated, which causes the original signals to be broken up. The same bus data will be split into many signals, making it extremely inconvenient to capture waveforms. 2) Fewer types of interfaces can be verified, especially some interfaces that have minimum frequency requirements. This is because the clocks of various FPGAs are usually shared. When the crystal oscillator clock is supplied to multiple FPGAs at the same time, it will be forced to be divided by software during division. When verifying some special interfaces, the main clock after division cannot even meet the minimum frequency requirements, which makes verification difficult. 3) Using multiple FPGAs will increase the required costs, especially in scenarios with high performance requirements, the costs will increase dramatically. Summary of the invention

[0006] In view of the above three problems, the purpose of the present invention is to propose a method for implementing multi-core DSP two-level system split verification based on FPGA. By splitting the overall system into two-level systems, the use of resources in the FPGA and the demand for the main frequency are divided to a certain extent when the multi-core DSP is transplanted, so that one FPGA is sufficient to transplant the multi-core DSP, effectively reducing the cost and eliminating the need for netlist segmentation; at the same time, since the main frequency requirement is guaranteed, the types of verifiable interfaces are also effectively increased.

[0007] This is achieved through the following technical solutions: A method for implementing multi-core DSP secondary system split verification based on FPGA is used to transplant the multi-core DSP into an FPGA, the multi-core DSP includes multiple DSP cores and a high-speed interconnection bus, the FPGA includes at least a main frequency and a module to be verified, the multi-core DSP shares the main frequency in the FPGA, and the verification process is observed by a host computer. The method includes the following steps: S1, setting the multi-core DSP and the high-speed interconnection bus as a primary system; adding multiple command detection modules at the end of the high-speed interconnection bus, using the multiple command detection modules to replace the function of the module to be verified, and each command detection module is a parallel structure; S2, using step S1 The multi-core DSP in the system sends multiple instructions, verifies the multiple instructions through a high-speed interconnect bus and multiple command detection modules, distinguishes each path with problems and each path without problems and transmits them to the host computer; S3, after completing the verification in step S2, sets a high-speed dedicated bus and increases the main frequency in the FPGA to the minimum frequency required by the secondary system, takes the high-speed dedicated bus, the module to be verified and the multi-core DSP as the secondary system, and uses the high-speed dedicated bus to verify the communication between the multi-core DSP and the module to be verified, and obtains the verification result; wherein the high-speed dedicated bus is to remove the paths that are not related to the module to be verified in the high-speed interconnect bus.

[0008] By splitting the overall system into two levels, the first-level system occupies more resources but requires a lower main frequency, while the second-level system occupies fewer resources but has a higher main frequency. This allows the FPGA to effectively transplant the DSP core, reduce costs, and eliminate the need for netlist segmentation. It also ensures the main frequency of the module to be verified, allowing more types of interfaces to be verified.

[0009] Preferably, in step S1, each command detection module includes a command pre-storage module, a command receiving module, a detection comparison module and a result reporting module; wherein the command receiving module and the command pre-storage module are both buf buffers, the command receiving module is used to receive and parse the corresponding instructions during verification in step S2, the command pre-storage module is used to pre-store the parsing results of the command receiving module and transmit them to the detection comparison module; the detection comparison module is used to verify the detection results and determine whether the parsing results are correct; the result reporting module is used to report the judgment results of the detection comparison module to the host computer. The command detection module can effectively reduce the required main frequency and perform effective verification.

[0010] Preferably, the FPGA also includes multiple cores. In step S3, if the main frequency in the FPGA cannot be increased to the minimum frequency required by the secondary system, a dsp core is proxyed by a core of the FPGA, and the proxy core is connected to the module to be verified. Using the core of the FPGA to proxy the dsp core can reduce the resource usage required for the multi-core dsp during transplantation.

[0011] Preferably, when a core of FPGA is used to proxy a DSP core, the command detection module corresponding to the DSP core being proxied is used to connect the core used for proxy to verify whether there is a problem in the path. If there is a problem, it is reported to the host computer; if there is no problem, the core is connected to the module to be verified. Using the core of FPGA for proxy processing can further reduce the resources occupied by multi-core DSP and ensure the smooth progress of verification.

[0012] Preferably, the module to be verified is divided into multiple submodules, each submodule is set with a different priority, and in step S3, if the main frequency in the FPGA cannot be increased to the minimum frequency required by the secondary system, each submodule is subjected to communication verification in the order of priority. Setting the priority and performing communication verification in order can effectively reduce the resources used and the main frequency pressure during verification, making the transplantation process smoother and ensuring the main frequency requirements required by the verifiable interface type.

[0013] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention, by splitting the overall system into two-level systems, makes certain divisions in the use of FPGA resources and the demand for main frequency when porting multi-core DSPs, so that one FPGA is sufficient to port the multi-core DSPs, effectively reducing the cost without the need for netlist segmentation; at the same time, since the demand for main frequency is guaranteed, the types of verifiable interfaces are also effectively increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1It is a flow chart of a method for realizing multi-core DSP secondary system split verification based on FPGA; Figure 2 It is a structural schematic diagram of the connection between the primary system and the command detection module in a method for realizing multi-core DSP secondary system split verification based on FPGA; Figure 3 A schematic diagram of the structure of a secondary system in a method for realizing multi-core DSP secondary system split verification based on FPGA; Figure 4 This is a schematic diagram of the structure of an existing multi-core DSP when it is transplanted to FPGA. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0016] like Figure 1 As shown, it is a flow chart of a method for realizing multi-core dsp secondary system split verification based on FPGA, which is used to transplant the multi-core dsp into an FPGA. The verification process is observed by a host computer, which can be a computer or a single-chip microcomputer with display function. The multi-core dsp includes a high-speed interconnection bus and multiple parallel dsp cores. The high-speed interconnection bus is a high-speed transmission line. Each dsp core is connected to other resources and various interfaces in the FPGA through the high-speed interconnection bus. The FPGA includes a main frequency, configuration resources, various interfaces and multiple cores. The main frequency is the clock frequency. The multi-core dsp shares the main frequency, which means that it works under the drive of the same clock signal. Configuration resources include DDR, flash and SRAM, etc.; various interfaces include PCIE, SRIO, GMAC, UART, CAN, I2C and SPI interfaces; configuration resources and various interfaces can be divided into two categories when transplanting, one is the module to be verified that needs to be used during transplantation, and the other is the part that is not needed during transplantation. Even if the part that is not needed during transplantation is temporarily shielded or deleted, it will not affect the operation of the module to be verified.

[0017] The method specifically comprises the following steps: S1. Set up a multi-core DSP and a high-speed interconnect bus as a first-level system, add multiple command detection modules at the end of the high-speed interconnect bus, use multiple command detection modules to replace the function of the module to be verified, and each command detection module is a parallel structure. The high-speed interconnect bus of the first-level system is also connected to DDR and UART interfaces. DDR is used to store the instructions issued by each DSP core and the data generated during verification, and the UART interface is used to transmit the data generated by the first-level system during verification.

[0018] like Figure 2As shown, it is a structural diagram of the connection between the primary system and the command detection module in the method of realizing the split verification of the multi-core dsp secondary system based on FPGA. Each dsp core is parallel and does not affect each other. Each command detection module is also parallel and does not affect each other. The number of command detection modules cannot be less than the number of dsp cores. At least each dsp core must correspond to at least one command detection module to ensure that the verification path process can proceed smoothly.

[0019] Each dsp core can be the same or different. When there are many instructions or channels that need to be verified during the transplantation of individual dsp cores, the contents that need to be verified can be verified and tested by two or even more command detection modules to ensure the smooth progress of verification.

[0020] In this embodiment, in step S1, each command detection module includes a command pre-storage module, a command receiving module, a detection comparison module and a result reporting module connected in sequence. The command receiving module and the command pre-storage module are both buf buffers, and the buf buffer is a memory area that can be used to temporarily store the generated data. The command receiving module is used to receive the corresponding instructions for verification in step S2 and parse them to obtain the parsing results, and one instruction corresponds to one parsing result; the command pre-storage module is used to pre-store the parsing results of the command receiving module and transmit them to the detection comparison module; the detection comparison module is used to verify the detection results and determine whether the parsing results are correct; the result reporting module is used to report the judgment results of the detection comparison module to the host computer, so that the staff can observe. In any command detection module, one, two or even more instructions may be received. In the case of receiving more than one instruction, the command pre-storage module will wait for the parsing results of each instruction to be fully pre-stored, and then transmit them together to the detection comparison module to ensure the synchronization of verification.

[0021] For the first-level system, the essence is to verify whether each DSP core and the high-speed interconnect bus can accurately transmit the corresponding instructions sent by each DSP core to the corresponding position when the multi-core DSP is transplanted, without involving various actual interfaces. In this actual verification process, the high-speed interconnect bus will occupy more main frequency resources, but since there is no actual interface verification at this time, the minimum clock frequency requirements of various interfaces are effectively avoided.

[0022] S2. Use the multi-core DSP in step S1 to issue multiple instructions, verify the multiple instructions through a high-speed interconnect bus and multiple command detection modules, distinguish each path with problems and each path without problems and transmit them to the host computer, so that the staff can know the verification status and manually record and process each path with problems.

[0023] S3. After completing the verification in step S2, set up a high-speed dedicated bus and increase the main frequency in the FPGA to the minimum frequency required by the secondary system, such as Figure 3 As shown, it is a structural diagram of the secondary system in a method for realizing split verification of a multi-core DSP secondary system based on FPGA. The high-speed dedicated bus, the module to be verified and the multi-core DSP are used as the secondary system, and the communication verification between the multi-core DSP and the module to be verified is performed using the high-speed dedicated bus, which can effectively obtain the verification result. Among them, the high-speed dedicated bus is to remove the paths that are not related to the transplantation in the high-speed interconnect bus. The high-speed dedicated bus in the secondary system is also connected to the corresponding DDR and UART interfaces, and its functions are the same as those of the DDR and UART interfaces in the primary system.

[0024] In this embodiment, since FPGA often includes multiple cores, some cores may not be used during transplantation or there may be spare cores for handling faults. For these cores, in step S3, if the main frequency in the FPGA cannot be increased to the minimum frequency required by the secondary system, a dsp core can be surrogate with a core in the FPGA, and the core used for surrogate is connected to the module to be verified to verify whether the channel can transmit normally. In addition, without affecting the function of the FPGA, more cores can be used to correspond to the surrogate dsp core, thereby further reducing the main frequency pressure during transplantation. Using the core of the FPGA to surrogate the dsp core can reduce the resource usage required by the multi-core dsp during transplantation, especially the demand for the main frequency.

[0025] In this embodiment, when a core of an FPGA is used to proxy a DSP core, the command detection module corresponding to the DSP core being proxied is used to connect the core used for proxying to verify whether there is a problem in the path. If there is a problem, it is reported to the host computer in time for the staff to record it; if there is no problem, the core is connected to the module to be verified.

[0026] In this embodiment, the module to be verified can be divided into multiple sub-modules, and different priorities can be set for each sub-module. In step S3, if the main frequency in the FPGA cannot be increased to the minimum frequency required by the secondary system, each sub-module can be verified for communication in the order of priority, so that the main frequency and occupied resources of each sub-module during verification are less, so that the verification can proceed smoothly. For example, the module to be verified contains SRIO interface, UART interface and PCIE interface that need to be verified. The SRIO interface and PCEI interface, both of which are high-speed interfaces, can be taken as the first priority and verified first; then, the UART interface, which is a low-speed interface, is taken as the second level and then verified. Setting the priority to perform communication verification in order can effectively reduce the use of resources and main frequency pressure during verification, making the transplantation process smoother, and also ensuring the main frequency requirements required for the verifiable interface type.

[0027] In summary, the present invention splits the overall system into two-level systems, so that the use of FPGA resources and the demand for main frequency are divided to a certain extent when migrating multi-core DSPs, so that one FPGA is sufficient to migrate multi-core DSPs, effectively reducing costs and eliminating the need for netlist segmentation; at the same time, since the main frequency requirement is guaranteed, the types of verifiable interfaces are also effectively increased, which is significantly progressive.

[0028] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for implementing multi-core dsp secondary system split verification based on FPGA, which is used to transplant the multi-core dsp into an FPGA, the multi-core dsp includes multiple dsp cores and a high-speed interconnect bus, the FPGA includes at least a main frequency and a module to be verified, the multi-core dsp shares the main frequency in the FPGA, and the verification process is observed by a host computer, characterized in that: The method comprises the following steps: S1. Set a multi-core DSP and a high-speed interconnection bus as a primary system; add multiple command detection modules at the end of the high-speed interconnection bus, use multiple command detection modules to replace the function of the module to be verified, and each command detection module is a parallel structure; S2, using the multi-core DSP in step S1 to issue multiple instructions, verifying the multiple instructions through a high-speed interconnect bus and multiple command detection modules, distinguishing each path with problems and each path without problems and transmitting them to the host computer; S3. After completing the verification in step S2, set a high-speed dedicated bus and increase the main frequency in the FPGA to the minimum frequency required by the secondary system. Use the high-speed dedicated bus, the module to be verified and the multi-core DSP as the secondary system, and use the high-speed dedicated bus to verify the communication between the multi-core DSP and the module to be verified to obtain the verification result; wherein, the high-speed dedicated bus is to remove the paths that are not related to the module to be verified in the high-speed interconnect bus.

2. According to a method for realizing multi-core DSP secondary system split verification based on FPGA according to claim 1, it is characterized in that: In step S1, each command detection module includes a command pre-storage module, a command receiving module, a detection comparison module and a result reporting module; Among them, the command receiving module and the command pre-storage module are both buf buffers. The command receiving module is used to receive and parse the corresponding instructions during verification in step S2, and the command pre-storage module is used to pre-store the parsing results of the command receiving module and transmit them to the detection and comparison module; the detection and comparison module is used to verify the detection results and determine whether the parsing results are correct; the result reporting module is used to report the judgment results of the detection and comparison module to the host computer.

3. According to the method for realizing multi-core DSP secondary system split verification based on FPGA in claim 1, the FPGA also includes multiple cores, characterized in that: In step S3, if the main frequency in the FPGA cannot be increased to the minimum frequency required by the secondary system, a DSP core is proxyed with a core of the FPGA, and the proxy core is connected to the module to be verified.

4. The method for realizing multi-core DSP secondary system split verification based on FPGA according to claim 3 is characterized in that: When using an FPGA core to proxy a DSP core, the command detection module corresponding to the DSP core being proxied is used to connect to the proxy core to verify whether there is a problem in the path. If there is a problem, it is reported to the host computer; if there is no problem, the core is connected to the module to be verified.

5. The method for realizing multi-core DSP secondary system split verification based on FPGA according to claim 1 is characterized in that: The module to be verified is divided into multiple sub-modules, each sub-module is set with a different priority. In step S3, if the main frequency in the FPGA cannot be increased to the minimum frequency required by the secondary system, each sub-module is verified for communication in order of priority.

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