Chip power consumption calculation methods, computing devices and computer-readable storage media

Abstract

This application discloses a chip power consumption calculation method, computing device, and computer-readable storage medium, comprising: obtaining load information corresponding to the output port of at least one target device in the register-transfer-level netlist of the chip; creating a target intermediate-level netlist with balanced load corresponding to the output port based on the load information; expanding the register-transfer-level netlist based on the target intermediate-level netlist; and calculating the chip power consumption based on the expanded register-transfer-level netlist. Thus, by creating a corresponding target intermediate-level netlist with balanced load based on the load information corresponding to the device's output port, and expanding the register-transfer-level netlist based on the target intermediate-level netlist, and then calculating the chip power consumption based on the expanded register-transfer-level netlist, the power consumption of the chip can be calculated quickly and accurately. This ensures that the power consumption obtained before and after analog synthesis of the register-transfer-level circuit design is as consistent as possible, saving computing resources and improving chip design efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip power consumption calculation method, a computing device, and a computer-readable storage medium. Background Technology

[0002] In Register Transfer Level (RTL) circuit design, chip designers translate high-level functional descriptions into low-level hardware logic representations to describe the functionality and behavior of digital circuit systems. During this process, since RTL circuit design only describes functionality and behavior, including various logic units and registers, these devices need to be synchronized with clock signals to ensure they are driven at the correct times. Therefore, in RTL circuit design, clock ports and some register output ports may simultaneously drive a large number of devices. Driving too many devices from a single port can lead to timing errors, signal delays, increased power consumption, noise, and jitter.

[0003] During the analog synthesis phase, the synthesis tool generates a lower-level gate-level circuit representation based on the RTL description. In this process, the synthesis tool optimizes the circuit structure, merges logic units, and optimizes the clock network to reduce redundant logic and optimize clock distribution, thereby solving the problem of excessive port load.

[0004] However, the above approach can lead to differences in power consumption analysis results before and after simulation synthesis in RTL circuit design. This requires R&D personnel to spend more time and effort adjusting the chip design during the RTL design and simulation synthesis stages, thus wasting computing resources and reducing chip design efficiency. Summary of the Invention

[0005] The purpose of this application is to provide a chip power consumption calculation method, a computing device, and a computer-readable storage medium, so as to at least solve the problems in the related art.

[0006] To achieve the above objectives:

[0007] In a first aspect, embodiments of this application provide a chip power consumption calculation method, the method comprising:

[0008] Obtain the load information corresponding to the output port of at least one target device in the register transfer level netlist of the chip;

[0009] Based on the load information, create a target intermediate netlist with balanced load corresponding to the output port;

[0010] The register transfer level netlist is expanded according to the target intermediate level netlist;

[0011] The power consumption of the chip is calculated based on the expanded register-transfer-level netlist.

[0012] In one embodiment, creating a target intermediate-level netlist with balanced load corresponding to the output port includes:

[0013] Create the target intermediate-level netlist with a tree structure;

[0014] The target intermediate-level netlist includes at least one level of nodes in the tree structure, as well as the connection relationships between the nodes and the output port and the load.

[0015] In one embodiment, the load information includes the number of loads; the target intermediate-level netlist for creating the tree structure includes:

[0016] Get the number of loads that a single node connected to a load can connect to;

[0017] The number of nodes connected to the load in the intermediate-level netlist is determined based on the number of loads corresponding to the output port and the number of loads that a single node connected to the load can connect to.

[0018] In one embodiment, when the target intermediate-level netlist includes multi-level nodes, the step of creating the tree-structured target intermediate-level netlist further includes:

[0019] Get the number of next-level nodes that a single node in each level of nodes can connect to;

[0020] The number of nodes at each level in the target intermediate-level network table is determined based on the number of next-level nodes that a single node in each level of the target intermediate-level network table can connect to, and the number of next-level nodes in each level of the network table.

[0021] In one embodiment, before creating a target intermediate-level netlist with balanced load corresponding to the output port based on the load information, the method further includes:

[0022] Detect whether the number of loads corresponding to the output port is greater than or equal to a preset threshold.

[0023] If so, then the step of creating a target intermediate netlist with balanced load corresponding to the output port based on the load information is executed.

[0024] In one embodiment, obtaining the number of loads that a single node connected to a load can connect to includes:

[0025] In response to the received input information, determine the number of loads that the nodes connected to the load can connect to and / or the number of next-level nodes that a single node in each level can connect to.

[0026] In one embodiment, expanding the register transfer level netlist according to the target intermediate level netlist includes:

[0027] Replace the node in the register transfer level netlist where the output port is connected to the load with the target intermediate level netlist, such that the output port is connected to the first level node of the target intermediate level netlist and the load is connected to the last level node of the target intermediate level netlist.

[0028] In one embodiment, expanding the register transfer level netlist according to the target intermediate level netlist includes:

[0029] Add a first preset mark to the node in the register transfer level netlist where the output port is connected to the load. The first preset mark is used to indicate the first level node in the target intermediate level netlist where the output port is connected.

[0030] A second preset tag is added to the last-level node of the target intermediate-level netlist. The second preset tag is used to indicate the load connected to the last-level node. The target intermediate-level netlist is associated with the register transfer level netlist according to the first preset tag and the second preset tag.

[0031] In one embodiment, calculating the chip's power consumption based on the expanded register-transfer-level netlist includes:

[0032] Obtain the load capacitance of the target device and the load capacitance of each node in the target intermediate level netlist;

[0033] The power consumption of the target device is determined based on its load capacitance.

[0034] The power consumption of the target intermediate level netlist is determined based on the load capacitance of each node.

[0035] The power consumption of the chip is calculated based on the power consumption of the target device and the power consumption of the target intermediate level netlist.

[0036] In one embodiment, obtaining the load capacitance of the target device includes:

[0037] Obtain the capacitance of the network node connected to the first-level node of the target intermediate-level netlist at the output port of the target device, and the capacitance of the input port of the first-level node.

[0038] The sum of the capacitance of the network node and the capacitance of the input port of the first-level node is determined as the load capacitance of the target device.

[0039] Secondly, embodiments of this application provide a computing device, including: a processor and a memory storing a computer program, wherein when the processor runs the computer program, the chip power consumption calculation method described in the first aspect is implemented.

[0040] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the chip power consumption calculation method described in the first aspect.

[0041] The chip power consumption calculation method, computing device, and computer-readable storage medium provided in this application create a target intermediate-level netlist with balanced load corresponding to the output port through the load information of the device's output port, and expand the register-transfer-level netlist according to the target intermediate-level netlist. Then, the power consumption of the chip is calculated based on the expanded register-transfer-level netlist. This method can quickly and accurately calculate the power consumption of the chip, making the power consumption obtained before and after analog synthesis of the register-transfer-level circuit design as consistent as possible, saving computing resources and improving chip design efficiency. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating the chip power consumption calculation method provided in an embodiment of this application.

[0043] Figure 2 This is a schematic diagram of the structure of the RTL netlist in the embodiments of this application.

[0044] Figure 3 This is a schematic diagram of the structure of the expanded RTL netlist in the embodiments of this application.

[0045] Figure 4 This is a schematic diagram of the connections between devices in the embodiments of this application.

[0046] Figure 5 This is a schematic diagram of the chip power consumption calculation process in an embodiment of this application.

[0047] Figure 6 A schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0049] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0050] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, can be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0051] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0052] It should be noted that step designations such as S101 and S102 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S102 first and then S101, etc., but these should all be within the protection scope of this application.

[0053] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0054] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0055] See Figure 1 This application provides a chip power consumption calculation method, which can be executed by a chip power consumption calculation device provided in this application. The chip power consumption calculation device can be implemented in software and / or hardware, such as a computer, server, or other computing or electronic device. In this embodiment, the execution subject of the chip power consumption calculation method is an electronic device. The chip power consumption calculation method provided in this embodiment includes:

[0056] Step S101: Obtain the load information corresponding to the output port of at least one target device in the register transfer level netlist of the chip.

[0057] In this context, the register-transfer-level (RTL) netlist refers to the circuit design document written during the chip's circuit design phase. The target device refers to any component within the chip that affects its power consumption, including registers and the clock. Load information indicates the load connected to the output ports of the target device, and may include load type, capacitance, and quantity. Specifically, the load may be a register or other device at the next stage of the target device. In this embodiment, the register output port can be called the register output port, and the clock output port can be called the clock port. Furthermore, in this embodiment, the RTL netlist can be stored as a graph data structure to represent the designed circuit structure. In the graph data structure, nodes represent target devices and their ports, and edges represent the networks connecting the target devices. Figure 2 As shown, the target device A0 is connected to the loads A1, A2, ..., A9 through network node N0.

[0058] Step S102: Based on the load information, create a target intermediate netlist with balanced load corresponding to the output port.

[0059] Here, based on the load information corresponding to each output port of the target device, a target intermediate-level netlist with balanced load will be created for that output port. The target intermediate-level netlist can be a tree structure or any other structure capable of representing balanced load; no specific limitation is made here. Balanced load refers to a method of distributing the load as evenly as possible so that each node connected to the load or each level node in the target intermediate-level netlist has the same or similar data processing capabilities. Same or similar data processing capabilities include the same or similar data processing resources, data processing workload, and data processing time.

[0060] The chip design can include multiple target devices, and each target device can generate a corresponding target intermediate-level netlist.

[0061] In one embodiment, creating a target intermediate-level netlist with balanced load corresponding to the output port includes: creating a tree-structured target intermediate-level netlist; the intermediate-level netlist includes at least one level of nodes in the tree structure, and the connection relationships between nodes and output ports and loads. In one embodiment, the output port is connected to the first-level node of the target intermediate-level netlist, and the load is connected to the last-level node of the target intermediate-level netlist. In one embodiment, the first-level node and the last-level node of the target intermediate-level netlist can be nodes of the same level. The tree-structured target intermediate-level netlist may include only one level of nodes, generally called leaf nodes, or it may include multiple levels of nodes. When only one level of nodes is included, this level node can be considered the root node of the tree structure. When multiple levels of nodes are included, the tree-structured target intermediate-level netlist may include nodes at different levels, such as root nodes, branch nodes, and leaf nodes. The first-level node is the root node, and the last-level node is the leaf node. The root node is connected to the output port, and the leaf nodes are connected to the load. Branch nodes of different levels may exist between the root node and the leaf nodes.

[0062] In one embodiment, creating a target intermediate-level netlist with balanced load corresponding to the output port includes: creating a tree-structured target intermediate-level netlist; the target intermediate-level netlist includes a root node, at least one leaf node, and the connection relationships between the root node and the output port, the connection relationships between the leaf nodes and the load, and the connection relationships between the root node and the leaf nodes. The tree-structured target intermediate-level netlist includes only one root node, which connects to both the output port and all leaf nodes.

[0063] In one embodiment, creating a target intermediate-level netlist with balanced load corresponding to the output port includes: creating a tree-structured target intermediate-level netlist; the target intermediate-level netlist includes a root node, at least one branch node, and at least one leaf node, as well as the connection relationships between the root node and the output port, the connection relationships between the leaf nodes and the loads, and the connection relationships between the branch nodes and the root node and leaf nodes. In one embodiment, a tree-structured target intermediate-level netlist of the chip includes only one root node, which connects to both the output port and all branch nodes. In one embodiment, a leaf node has a connection relationship with only one branch node, but can have connections to multiple loads. Figure 3 As shown, both the clock tree and the buffer tree include a root node, branch nodes, and leaf nodes. The root node is connected to the register output port or the clock port, and the leaf nodes are connected to the load.

[0064] The tree structure is a data representation method for the target intermediate-level netlist, determined by its physical function. In chip design, a target device can correspond to a single target intermediate-level netlist. In this embodiment, the target device is a clock, and the target intermediate-level netlist corresponding to the clock port can be called a clock tree; if the target device is a register, the target intermediate-level netlist corresponding to the register output port can be called a buffer tree. It should be noted that each node in the tree structure corresponding to the target intermediate-level netlist can be implemented using a clock device, and different clock devices can be selected for nodes at different levels depending on their function.

[0065] In one embodiment, the load information includes the number of loads; creating the target intermediate-level netlist with a tree structure includes: obtaining the number of loads that a single node connected to a load can connect to; and determining the number of nodes connected to the loads in the target intermediate-level netlist based on the number of loads corresponding to the output ports and the number of loads that a single node connected to a load can connect to. The number of nodes connected to the loads is the total number of loads divided by the number of loads that a single node in that level can connect to. If the total number of loads is not an integer multiple of the number of nodes connected to the loads, the obtained value is incremented by 1 to determine the number of nodes connected to the loads.

[0066] In one embodiment, when the target intermediate-level netlist includes multiple levels of nodes, creating a tree-structured target intermediate-level netlist further includes: obtaining the number of next-level nodes that a single node in each level can connect to; and determining the number of nodes at each level in the target intermediate-level netlist based on the number of next-level nodes that a single node in each level can connect to and the number of next-level nodes at each level. The number of nodes at each level is the value obtained by dividing the total number of next-level nodes by the number of next-level nodes that a single node in that level can connect to. If the total number of next-level nodes is not an integer multiple of the number of next-level nodes that a single node in that level can connect to, then the obtained value is incremented by 1 and determined as the number of nodes at that level.

[0067] In one embodiment, when the target intermediate-level netlist includes a root node, at least one link node, and at least one leaf node, creating a tree-structured target intermediate-level netlist includes:

[0068] Obtain the number of loads that a single leaf node can connect to and the number of leaf nodes that a single support node can connect to;

[0069] The number of leaf nodes in the target intermediate-level netlist is determined based on the number of loads corresponding to the output ports and the number of loads that a single leaf node can connect to.

[0070] The number of support nodes in the target intermediate-level netlist is determined based on the number of leaf nodes in the target intermediate-level netlist and the number of leaf nodes that a single support node can connect to.

[0071] To balance the load connected to each leaf node as much as possible, after determining the number of loads that a single leaf node can connect to, the number of loads corresponding to the output port can be divided by the number of loads that a single leaf node can connect to, thus determining the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist. If the number of loads corresponding to the output port is an integer multiple of the number of loads that a single leaf node can connect to, the value obtained by dividing the number of loads corresponding to the output port by the number of loads that a single leaf node can connect to is used to determine the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist. If the number of loads corresponding to the output port is not an integer multiple of the number of loads that a single leaf node can connect to, the value obtained by dividing the number of loads corresponding to the output port by the number of loads that a single leaf node can connect to is incremented by 1, and this value is used to determine the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist. Of course, if the goal is to make the number of loads connected to each leaf node less than the number of loads that a single leaf node can connect to, the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist will be increased accordingly. For example, if a single leaf node can connect to 3 loads, and the output port corresponds to 12 loads, then the number of leaf nodes in the tree structure corresponding to the target intermediate level netlist is 4; while if the output port corresponds to 14 loads, then the number of leaf nodes in the tree structure corresponding to the target intermediate level netlist is 5, and so on.

[0072] Similarly, to ensure a balanced number of leaf nodes connected to each link node, after determining the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist, the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist can be divided by the number of leaf nodes that a single link node can connect to, thus determining the number of link nodes in the tree structure corresponding to the target intermediate-level netlist. If the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist is an integer multiple of the number of leaf nodes that a single link node can connect to, then the value obtained by dividing the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist by the number of leaf nodes that a single link node can connect to is used as the number of link nodes in the tree structure corresponding to the target intermediate-level netlist. If the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist is not an integer multiple of the number of leaf nodes that a single link node can connect to, then the value obtained by dividing the number of leaf nodes in the tree structure corresponding to the target intermediate-level netlist by the number of leaf nodes that a single link node can connect to is incremented by 1, and this value is used as the number of link nodes in the tree structure corresponding to the target intermediate-level netlist.

[0073] In this way, by quickly and accurately obtaining the number of leaf nodes and support nodes in the tree structure corresponding to the target intermediate level netlist, a target intermediate level netlist with balanced load corresponding to the output port can be created quickly and accurately, which improves the chip power consumption calculation speed and is easy to operate.

[0074] In one implementation, in response to received input information, the number of loads that a node connected to the load can connect to and / or the number of next-level nodes that a single node in each level can connect to are determined. The received input information can be preset or received from the user during the creation of the target intermediate-level netlist.

[0075] In one embodiment, when the target intermediate-level netlist includes a root node, at least one pole node, and at least one leaf node, obtaining the number of loads that a single leaf node can connect to and the number of leaf nodes that a single pole node can connect to includes determining the number of loads that a single leaf node can connect to and the number of leaf nodes that a single pole node can connect to in response to a received input operation.

[0076] Users can configure the number of loads that a single leaf node can connect to and the number of leaf nodes that a single support node can connect to via the settings interface provided by the electronic device. Upon receiving the input, the electronic device determines the number of loads and leaf nodes specified in the input as the number of loads that a single leaf node can connect to and the number of leaf nodes that a single support node can connect to, respectively. This allows users to independently set the parameters of the tree structure corresponding to the target intermediate-level netlist based on their needs, improving the flexibility of chip power consumption calculation.

[0077] In one embodiment, obtaining the number of loads that a single last-level node can connect to includes: obtaining the maximum value within a preset range of possible load counts that can be divided evenly by the number of loads corresponding to the output port, and determining the maximum value as the number of loads that a single last-level node can connect to. Here, the last-level node is a leaf node.

[0078] In one embodiment, obtaining the number of nodes that a single node can connect to in each level of nodes includes: obtaining the maximum value that is divisible by a target value within a preset range of values ​​for the number of nodes that a single node can connect to in each level of nodes, and determining the maximum value as the number of nodes that a single node in that level can connect to. Here, each level of node can be a support node, and the target value is obtained based on the quotient of the number of loads corresponding to the output port and the number of loads that a single last-level node can connect to.

[0079] In one embodiment, in order to minimize the complexity of the target intermediate-level netlist, the number of loads that a single leaf node can connect to and the number of leaf nodes that a single branch node can connect to can be maximized and balanced. Therefore, the maximum value within a preset range of the number of loads that a single leaf node can connect to that can be divided by the number of loads corresponding to the output port can be determined as the number of loads that a single leaf node can connect to. The maximum value within a preset range of the number of leaf nodes that a single branch node can connect to that can be divided by the target value can be determined as the number of leaf nodes that a single branch node can connect to. The target value is obtained based on the quotient of the number of loads corresponding to the output port and the number of loads that a single leaf node can connect to. For example, assuming the preset range of the number of loads that a single leaf node can connect to is [2, 5], and the preset range of the number of leaf nodes that a single support node can connect to is [2, 4], if the number of loads corresponding to the output port is 12, and the maximum value divisible by 12 in the range [2, 5] is 4, then the number of loads that a single leaf node can connect to is determined to be 4. Then, based on the determined number of loads that a single leaf node can connect to, the number of leaf nodes in the tree structure corresponding to the target intermediate level netlist can be determined to be 3. And the maximum value divisible by 3 in the range [2, 4] is 3, then the number of leaf nodes that a single support node can connect to is determined to be 3.

[0080] In one embodiment, before creating a target intermediate-level netlist with balanced load corresponding to the output port based on the load information, the method further includes:

[0081] Check if the number of loads corresponding to the output port is greater than a preset threshold.

[0082] If so, then execute the step of creating a target intermediate netlist with balanced load corresponding to the output port based on the load information.

[0083] The preset threshold number can be set according to actual needs, such as 3 or 5. It's understood that when the number of loads corresponding to the output ports is less than the preset threshold, it indicates a relatively small number of loads. In this case, creating a target intermediate-level netlist with balanced loads for the output ports might increase the calculation time for chip power consumption. Therefore, the step of creating a target intermediate-level netlist with balanced loads for the output ports based on the load information can be skipped. Conversely, when the number of loads corresponding to the output ports is greater than or equal to the preset threshold, it indicates a relatively large number of loads. In this case, a target intermediate-level netlist with balanced loads for the output ports needs to be created to calculate chip power consumption based on the target intermediate-level netlist. This ensures that the chip power consumption calculation result during the RTL design phase closely approximates the chip power consumption calculation result after analog synthesis. Thus, creating a target intermediate-level netlist with balanced loads for the output ports only when the number of loads corresponding to the output ports is greater than or equal to the preset threshold improves the chip power consumption calculation speed and further enhances chip design efficiency.

[0084] Step S103: Expand the register transfer level netlist according to the target intermediate level netlist.

[0085] Specifically, the register-transfer-level netlist is expanded based on the target intermediate-level netlist. This can be achieved by replacing the nodes in the register-transfer-level netlist that connect the output port to the load with the target intermediate-level netlist, or by adding the information from the target intermediate-level netlist to the register-transfer-level netlist. In other words, the target intermediate-level netlist is added to the register-transfer-level netlist, and the target intermediate-level netlist is additionally marked on the nodes in the register-transfer-level netlist that connect the output port to the load, thus obtaining the expanded register-transfer-level netlist.

[0086] In one embodiment, expanding the register-transfer level netlist according to the target intermediate level netlist includes: replacing nodes in the register-transfer level netlist where the output port is connected to the load with nodes in the target intermediate level netlist, such that the output port is connected to a first-level node in the target intermediate level netlist and the load is connected to a last-level node in the target intermediate level netlist. In one embodiment, the first-level node and the last-level node in the target intermediate level netlist can be nodes of the same level. For example, when the target intermediate level netlist only includes leaf nodes, replacing the nodes in the register-transfer level netlist where the output port is connected to the load with nodes in the target intermediate level netlist connects both the output port and the load to leaf nodes in the target intermediate level netlist. In one embodiment, the first-level node is the root node and the last-level node is the leaf node; that is, replacing the nodes in the register-transfer level netlist where the output port is connected to the load with nodes in the target intermediate level netlist connects the output port to the root node and the load to the leaf node.

[0087] In the register-transfer-level netlist, the nodes connecting the output ports to the load record the network nodes connected to the output ports, as well as the output ports and loads connected to those network nodes. By replacing the nodes in the data structure connecting the output ports to the loads in the register-transfer-level netlist with the target intermediate-level netlist, the output ports can be connected to the root nodes and the loads to the leaf nodes, thus expanding the register-transfer-level netlist. In this way, by replacing the nodes connecting the output ports to the loads in the register-transfer-level netlist with the target intermediate-level netlist, the power consumption of the chip can be calculated quickly and accurately.

[0088] The following example illustrates the process of replacing nodes in a register-transfer-level netlist with the target intermediate-level netlist:

[0089] like Figure 4 As shown, devices in a chip (referred to as Instances in the RTL netlist) connect to other devices through network nodes (referred to as Nets in the RTL netlist). Typically, each device has several output ports (interfaces that transmit signals) and several input ports (interfaces that receive signals). Output ports are connected to the input ports of other devices through network nodes. A Net connects only one device's output port and several other devices' input ports; that is, the output signal of one device is transmitted to the input ports of multiple devices through network nodes. The device providing the output port is usually called the driver of this Net, indicating that it drives the network. The devices connected to the Net that provide input ports are called receivers, indicating that they are the receivers of signals on this network. Therefore, in a register-transfer level netlist, the most basic data structures for recording netlist connections are Instances and Nets. Each Instance's data structure records which Net each of its ports (Input and Output) is connected to, while each Net records its connected Driver and Receiver.

[0090] Continue reading Figure 2 Assuming that in the original circuit, device A0 is connected to loads A1, A2, ..., A9 through network node N0, then in the register transfer level netlist, the output port of device A0 is connected to network node N0. The driver of network node N0 is device A0, and the receivers are loads A1, A2, ..., A9. Simultaneously, the input ports of loads A1, A2, ..., A9 are connected to network node N0. (Continue reading...) Figure 3The dashed box represents the generated clock tree / buffer tree, which includes a root node B0, a branch node B1, and three leaf nodes B2, B3, and B4. The network nodes connected from the input port of the root node to the output port of the leaf node are sequentially labeled N1, N2, N3, N4, N5, and N6. Specifically, the data structure connecting the output port to the load in the register transfer level netlist is replaced with the target intermediate level netlist. This means changing the connection of device A0's output port to network node N0 to device A0 being connected to network node N1, and changing the connection of the inputs of loads A1, A2, ..., A9 from network node N0 to network nodes N4, N5, and N6.

[0091] In one embodiment, expanding the register-transfer-level netlist according to the target intermediate-level netlist includes: adding a first preset tag to the node in the register-transfer-level netlist where the output port is connected to the load, the first preset tag indicating the first-level node of the target intermediate-level netlist connected to the output port; adding a second preset tag to the last-level node of the target intermediate-level netlist, the second preset tag indicating the load connected to the last-level node; associating the target intermediate-level netlist with the register-transfer-level netlist according to the first preset tag and the second preset tag, thereby realizing the expansion of the register-transfer-level netlist according to the target intermediate-level netlist.

[0092] Adding a first preset flag can be achieved by adding a variable to the node connected to the load at the output port of the register transfer level netlist, and using this variable as the first preset flag. Simultaneously, the loads connected to each last-level node can be added to the attributes of the last-level node to add a second preset flag to the last-level node of the target intermediate-level netlist.

[0093] In one embodiment, the first-level node is the root node, and the last-level node is the leaf node. The register-transfer-level netlist is expanded according to the target intermediate-level netlist, including: adding a first preset mark to the node in the register-transfer-level netlist where the output port is connected to the load. The first preset mark is used to indicate the root node of the target intermediate-level netlist where the output port is connected; adding a second preset mark to the leaf node of the target intermediate-level netlist. The second preset mark is used to indicate that the load connected to the leaf node associates the target intermediate-level netlist with the register-transfer-level netlist according to the first preset mark and the second preset mark.

[0094] In this approach, while preserving the existing connections in the register-transfer-level netlist, a first preset marker can be added directly to the nodes in the data structure connecting the output port and the load in the register-transfer-level netlist. This first preset marker indicates the node in the target intermediate-level netlist connected to the output port. A second preset marker is then added to the last-level node of the target intermediate-level netlist, indicating the load connected to that node. Based on these two preset markers, the target intermediate-level netlist is associated with the register-transfer-level netlist, thus allowing the target intermediate-level netlist to be added to the register-transfer-level netlist. Adding the first preset marker can be achieved by adding a variable to the node connecting the output port and the load in the register-transfer-level netlist and using this variable as the first preset marker. Simultaneously, the loads connected to each last-level node can be added to the attributes of the corresponding node to add the second preset marker to the last-level node of the target intermediate-level netlist. It is understandable that upon detecting the first preset flag, it can be known that the output port is configured with a target intermediate-level netlist. Based on the second preset flag added to the last-level node of this target intermediate-level netlist, the loads connected to each last-level node of the target intermediate-level netlist can be determined. Therefore, the connection relationship between the output port and the load can be subdivided based on this target intermediate-level netlist, facilitating the calculation of the chip's power consumption. In this way, the original connection relationship in the register transfer level netlist is preserved, while simultaneously reducing memory consumption and saving computational resources.

[0095] Continue reading Figure 2 and Figure 3 Taking the first-level node of the target intermediate-level netlist as the root node and the last-level node as the leaf node as an example, a first preset marker is added to the nodes in the register-transfer-level netlist where the output ports are connected to the loads, and a second preset marker is added to the leaf nodes of the target intermediate-level netlist. Specifically, on network node N0, device A0 is marked as connected to the root node B0 in the target intermediate-level netlist; on leaf node B2, leaf node B2 is marked as connected to loads A1, A2, and A3; on leaf node B3, leaf node B3 is marked as connected to the loads; and on leaf node B4, leaf node B4 is marked as connected to loads A7, A8, and A9. It should be noted that when the number of loads corresponding to the output ports of different devices is the same, the same target intermediate-level netlist can be used to expand the register-transfer-level netlist to reduce memory consumption.

[0096] Step S104: Calculate the chip's power consumption based on the expanded register transfer level netlist.

[0097] Since the expanded register transfer level netlist includes target intermediate level netlist information with balanced load corresponding to the output port of the target device, the power consumption of the chip can be calculated step by step in combination with the target intermediate level netlist when calculating the chip's power consumption, so as to avoid affecting the accuracy of power consumption calculation due to too many loads connected to the output port of the target device.

[0098] In one embodiment, the power consumption of the chip is calculated based on the extended register-transfer-level netlist, including:

[0099] Obtain the load capacitance of the target device and the load capacitance of each node in the target intermediate stage netlist;

[0100] Determine the power consumption of the target device based on its load capacitance.

[0101] Determine the power consumption of the target intermediate-level netlist based on the load capacitance of each node;

[0102] The power consumption of the chip is calculated based on the power consumption of the target device and the power consumption of the target intermediate level netlist.

[0103] The load capacitance of the target device refers to the sum of the capacitances connected to all output ports of the target device. The capacitance connected to each output port consists of two parts: one part is the capacitance of the network node itself connected to that output port, and the other part is the capacitance of the input port of the load connected to that network node. When the target intermediate-level netlist includes a root node, at least one branch node, and at least one leaf node, the load capacitance of each node in the target intermediate-level netlist includes the load capacitance of the root node, the load capacitance of the branch node, and the load capacitance of the leaf node in the target intermediate-level netlist. Furthermore, the method for obtaining the load capacitance of each node is the same as the method for obtaining the load capacitance of the target device. For example, see [link to relevant documentation]. Figure 3 The load capacitance of root node B0 is the sum of the capacitance of N2 and the capacitance of the input port of branch node B1. Optionally, determining the power consumption of a device or node based on its load capacitance is a prior art technique and will not be elaborated here. The power consumption of the target intermediate-level netlist is the sum of the power consumption of each node in the target intermediate-level netlist. The chip's power consumption can be obtained by superimposing the power consumption of each target device and the power consumption of the target intermediate-level netlist.

[0104] In one embodiment, obtaining the load capacitance of the target device includes: obtaining the capacitance of the network node connected to the output port of the target device and the first-level node of the target intermediate-level netlist, and the capacitance of the input port of the first-level node; and determining the sum of the capacitance of the network node and the capacitance of the input port of the first-level node as the load capacitance of the target device.

[0105] In this method, based on the target intermediate-level netlist with balanced load corresponding to the output port of the target device, it is only necessary to calculate the capacitance of the network node connected to the first-level node of the target intermediate-level netlist and the capacitance of the input port of the first-level node to determine the load capacitance of the target device. This reduces the computation time and enables fast and accurate calculation of the load capacitance of the target device.

[0106] In one embodiment, the first-level node of the target intermediate-level netlist is the root node, and obtaining the load capacitance of the target device includes:

[0107] Obtain the capacitance of the network node connecting the output port of the target device to the root node of the target intermediate-level netlist, and the capacitance of the input port of the root node.

[0108] The sum of the capacitance of the network nodes and the capacitance of the input port of the root node is determined as the load capacitance of the target device. The methods for obtaining the capacitance of the network nodes and the capacitance of the input port of the root node are existing technologies and will not be elaborated upon here. See further... Figure 2 Without considering the target intermediate-level netlist, the load capacitance of the target device A0 is the sum of the capacitance of network node N0 and the capacitance of the input ports of loads A1, A2, ..., A9. See further... Figure 3 Considering the target intermediate-level netlist, the load capacitance of target device A0 is the sum of the capacitance of network node N1 and the capacitance of the input port of root node B0. This allows for the rapid and accurate determination of the load capacitance of each device, further improving chip design efficiency.

[0109] In summary, the chip power consumption calculation method provided in the above embodiments creates a target intermediate-level netlist with balanced load corresponding to the output port by using the load information of the device's output port, and expands the register-transfer-level netlist according to the target intermediate-level netlist. Then, the chip power consumption is calculated based on the expanded register-transfer-level netlist. This method can quickly and accurately calculate the chip power consumption, making the power consumption obtained before and after analog synthesis of the register-transfer-level circuit design as consistent as possible, saving computing resources and improving chip design efficiency.

[0110] Based on the same inventive concept as the foregoing embodiments, the foregoing embodiments will be described in detail below through a specific example. In this example, the target devices are a register and a clock.

[0111] See Figure 5 The workflow of the chip power consumption calculation method provided in this embodiment mainly includes:

[0112] 1) After inputting the RTL netlist, analyze the load at the output of each register and the load at the clock.

[0113] 2) Create a clock tree for the clock port and a corresponding buffer tree for the output port.

[0114] 3) Insert the clock tree or buffer tree into the RTL netlist to obtain the expanded RTL netlist.

[0115] The expanded RTL netlist includes the connection relationships of each node in the clock tree or buffer tree, namely the connection relationship between the root node and the port of the clock tree or buffer tree, the connection relationship between the root node and the support node, and the connection relationship between the leaf node and the load.

[0116] 4) Calculate the chip's power consumption based on the expanded netlist.

[0117] 5) Output power consumption report.

[0118] Based on the same inventive concept as the foregoing embodiments, this embodiment of the invention provides a computing device, such as... Figure 6 As shown, the computing device includes: a processor 310 and a memory 311 storing computer programs; wherein, Figure 6 The processor 310 shown in the diagram does not indicate that there is only one processor 310, but only indicates the positional relationship of the processor 310 relative to other devices. In practical applications, there can be one or more processors 310; similarly, Figure 6 The memory 311 shown in the diagram has the same meaning, that is, it is only used to indicate the positional relationship of memory 311 relative to other devices. In practical applications, there can be one or more memories 311. When the processor 310 runs the computer program, it implements the chip power consumption calculation method applied to the above-mentioned computing device.

[0119] The computing device may also include at least one network interface 312. Various components in the electronic device are coupled together via a bus system 313. It is understood that the bus system 313 is used to implement communication between these components. In addition to a data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 6 The general designated all buses as Bus System 313.

[0120] The memory 311 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 311 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0121] The memory 311 in this embodiment of the invention is used to store various types of data to support the operation of the computing device. Examples of this data include: any computer programs used to operate on the computing device, such as operating systems and applications; contact data; phonebook data; messages; pictures; videos, etc. The operating system includes various system programs, such as the framework layer, core library layer, driver layer, etc., used to implement various basic services and handle hardware-based tasks. Applications can include various applications, such as media players, browsers, etc., used to implement various application services. Here, the program implementing the method of this embodiment of the invention can be included in the application.

[0122] Based on the same inventive concept as the foregoing embodiments, this embodiment also provides a computer-readable storage medium storing a computer program. The computer-readable storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it can also be various devices including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc. When the computer program stored in the computer-readable storage medium is executed by a processor, it implements the above-mentioned chip power consumption calculation method. For the specific steps implemented when the computer program is executed by the processor, please refer to [link to relevant documentation]. Figure 1 The description of the illustrated embodiments will not be repeated here.

[0123] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0124] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0125] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method of calculating chip power consumption, characterized by, The method comprises: Obtaining load information corresponding to an output port of at least one target device in a register transfer level netlist of a chip; the load information comprises a load quantity; According to the load information, creating a target intermediate level netlist with balanced loads corresponding to the output port; wherein the target intermediate level netlist is a tree structure, the target intermediate level netlist comprises at least one level of nodes of the tree structure, and a connection relationship between the nodes and the output port and the loads; the creation of the target intermediate level netlist comprises: obtaining a connectable load quantity of a single node connected with a load; determining a quantity of nodes connected with the loads in the target intermediate level netlist according to the load quantity corresponding to the output port and the connectable load quantity of the single node connected with the load; According to the target intermediate level netlist, expanding the register transfer level netlist; Based on the expanded register transfer level netlist, calculating power consumption of the chip.

2. The method of claim 1, wherein, When the target intermediate level netlist comprises multiple levels of nodes, creating the tree structure of the target intermediate level netlist further comprises: Obtaining a quantity of next level nodes connectable by a single node in each level of nodes; According to the quantity of next level nodes connectable by a single node in each level of nodes of the target intermediate level netlist and the quantity of next level nodes of each level of nodes, determining a quantity of each level of nodes in the target intermediate level netlist.

3. The method of claim 2, wherein, The obtaining of the connectable load quantity of the single node connected with the load comprises: In response to received input information, determining the connectable load quantity of the node connected with the load and / or the quantity of next level nodes connectable by a single node in each level of nodes.

4. The method of any one of claims 2-3, wherein, The expansion of the register transfer level netlist according to the target intermediate level netlist comprises: Replacing nodes connected with the output port and the loads in the register transfer level netlist with the target intermediate level netlist, so that the output port is connected to a first level node of the target intermediate level netlist and the loads are connected to a last level node of the target intermediate level netlist.

5. The method of any one of claims 2-3, wherein, The expansion of the register transfer level netlist according to the target intermediate level netlist comprises: Adding a first preset mark on the nodes connected with the output port and the loads in the register transfer level netlist, the first preset mark being used to indicate a first level node of the target intermediate level netlist to which the output port is connected; Adding a second preset mark on a last level node of the target intermediate level netlist, the second preset mark being used to indicate the loads connected to the last level node; According to the first preset mark and the second preset mark, associating the target intermediate level netlist to the register transfer level netlist.

6. The method of any one of claims 2-3, wherein, The calculation of the power consumption of the chip based on the expanded register transfer level netlist comprises: Obtaining load capacitances of the target device and load capacitances of each node in the target intermediate level netlist; According to the load capacitances of the target device, determining power consumption of the target device; According to the load capacitances of each node, determining power consumption of the target intermediate level netlist; calculating the power consumption of the chip based on the power consumption of the target device and the power consumption of the target intermediate stage netlist.

7. The method of claim 6, wherein, The obtaining the load capacitance of the target device comprises: obtaining the capacitance of a network node connected between an output port of the target device and a first stage node of the target intermediate stage netlist and the capacitance of an input port of the first stage node; determining the sum of the capacitance of the network node and the capacitance of the input port of the first stage node as the load capacitance of the target device.

8. A computing device, comprising: The computer program product comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the chip power consumption calculation method according to any one of claims 1 to 7 when executing the computer program. 9.A computer readable storage medium, storing a computer program, and the computer program is executed by a processor to implement the chip power consumption calculation method according to any one of claims 1 to 7.

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