Modeling method and device of hardcore module, equipment and storage medium

Abstract

The invention belongs to the technical field of integrated circuits, and discloses a modeling method, device and equipment for a hardcore module and a storage medium, and the modeling method comprises the steps: obtaining a to-be-modeled hardcore module; determining a target signal path mapped with a plurality of configuration scenes in the to-be-modeled hardcore module; for any configuration scene of the target signal path, determining a port of the to-be-modeled hardcore module corresponding to the configuration scene, the port including an input port and an output port; based on the corresponding relation between the configuration scenes and the ports, the ports of the to-be-modeled hardcore module are split, a modeled hardcore module is obtained, and in the modeled hardcore module, a signal path formed between a set of input ports and output ports is mapped with a unique configuration scene. According to the invention, the problem that the wiring theory of the chip is reachable and the actual connection is illegal in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a modeling method, device, equipment and storage medium for a hard core module. Background Art

[0002] In the field of integrated circuits, different chip architectures have different design rules, which requires a design rule check (DRC) for special resource modules during layout. The special circuit modules inside the chip refer to the circuit modules that are combined according to a fixed relative position relationship and port connection relationship to achieve a certain function.

[0003] However, at the current stage, when checking chips based on DRC, there are scenarios where the wiring in the chip is theoretically reachable, but the actual connection in the chip is illegal due to configuration point conflicts. Summary of the invention

[0004] The present invention provides a modeling method, device, equipment and storage medium of a hard core module, which are used to solve the problem in the prior art that the chip wiring is theoretically reachable but the actual connection is illegal.

[0005] In order to solve the above technical problems, in a first aspect, the present invention provides a modeling method for a hard core module, comprising:

[0006] Get the hard core module to be modeled;

[0007] Determine a target signal path in which a plurality of configuration scenarios are mapped in the hard core module to be modeled;

[0008] For any configuration scenario of the target signal path, determine the port of the hard core module to be modeled corresponding to the configuration scenario, wherein the port includes an input port and an output port;

[0009] Based on the correspondence between each of the configuration scenarios and the ports, the ports of the hard-core module to be modeled are split to obtain a modeled hard-core module, wherein in the modeled hard-core module, a signal path mapping formed between a group of the input ports and the output ports has a unique configuration scenario.

[0010] Optionally, for any configuration scenario of the target signal path, determining a port of the hard core module to be modeled corresponding to the configuration scenario includes:

[0011] Determining an output function mode and an input function mode corresponding to the target signal path;

[0012] Determine the output port corresponding to any of the output function modes;

[0013] The input port corresponding to any of the input function modes is determined, wherein any configuration scenario corresponds to a unique input function mode and output function mode.

[0014] Optionally, the determining an input port corresponding to any of the input function modes includes:

[0015] Receive hard core module parameters input by the user;

[0016] Determining an input function mode corresponding to the hard core module parameters;

[0017] For each input function mode, an input port corresponding to the input function mode is determined.

[0018] Optionally, after splitting the ports of the hard core module to be modeled based on the correspondence between each of the configuration scenarios and the ports to obtain the modeled hard core module, the method further includes:

[0019] Traversing the circuit connections of the chip, and collecting the circuit connections of the modeled hard core modules in the chip;

[0020] Based on the circuit connection of the modeled hard core module, updating and establishing the connection design rules of the chip;

[0021] Traversing the user design netlist of the chip, collecting the hard core modules that meet the connection design rules and the available positions of the hard core modules on the chip;

[0022] The hard core module is placed on the available position corresponding to the chip.

[0023] Optionally, placing the hard core module at the available position corresponding to the chip includes:

[0024] Establishing a search tree consisting of the hard core modules on the chip by a branch and bound search method, wherein each node of the search tree corresponds to an available position of the hard core module on the chip, and the connection relationship between the nodes corresponds to the connection relationship between the hard core modules;

[0025] Search the search tree from top to bottom. If the downward search node is a legal solution, search downward. If the downward search node is an illegal solution, backtrack upward.

[0026] After searching all nodes of the search tree, an optimal solution search tree is obtained;

[0027] Corresponding to the structure of the optimal solution search tree, each of the hard core modules is placed at the available position corresponding to the chip.

[0028] In a second aspect, the present invention provides a modeling device for a hard core module, comprising:

[0029] An acquisition module is used to acquire a hard core module to be modeled;

[0030] A first determination module is used to determine a target signal path in the hard core module to be modeled that is mapped with multiple configuration scenarios;

[0031] A second determination module, configured to determine, for any configuration scenario of the target signal path, a port of the hard core module to be modeled corresponding to the configuration scenario, wherein the port includes an input port and an output port;

[0032] A splitting module is used to split the ports of the hard-core module to be modeled based on the corresponding relationship between each configuration scenario and the port to obtain a modeled hard-core module, wherein in the modeled hard-core module, a signal path mapping formed between a group of input ports and output ports has a unique configuration scenario.

[0033] In a third aspect, the present invention provides a modeling device for a hard core module, including a memory and a processor, wherein:

[0034] The memory is used to store computer programs;

[0035] The processor is used to read the program in the memory and execute the steps of the modeling method of the hard core module provided in the first aspect above.

[0036] In a fourth aspect, the present invention provides a computer-readable storage medium having a readable computer program stored thereon, which, when executed by a processor, implements the steps of the modeling method of the hard-core module provided in the first aspect above.

[0037] Compared with the prior art, the modeling method of a hard core module provided by the present invention has the following beneficial effects:

[0038] The present invention splits each port of the hard-core module in the chip based on the configuration scenario to obtain a modeled hard-core module, so that the signal path mapping formed between each port of the modeled hard-core module has a unique configuration scenario, and on this basis, wiring is performed based on the modeled hard-core module. Since the connection (signal path) between each configuration point only corresponds to a unique configuration scenario, the configuration scenarios finally realized by each configuration point will not be crossed and are independent of each other, so there will be no scenario of illegal actual connection in the chip caused by configuration point conflict. In summary, the technical solution of the present invention can solve the problem in the prior art that the chip has a scenario where the wiring theory can reach an illegal actual connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only part of the embodiments of the present invention, rather than all of the embodiments. For ordinary technicians in this field, without paying creative work, other drawings obtained based on these drawings all fall within the scope of protection of the present invention.

[0040] Figure 1 is a flow chart of a modeling method of a hard core module provided by an embodiment of the present invention;

[0041] Figure 2 is a flow chart of another hard core module modeling method provided by an embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of a hard core module provided by an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of a search tree of a hard core module provided by an embodiment of the present invention;

[0044] Figure 5 is a structural diagram of a modeling device for a hard core module provided by an embodiment of the present invention;

[0045] Figure 6 is a structural schematic diagram of a modeling device for a hard core module provided by an embodiment of the present invention;

[0046] Figure 7 It is a structural schematic diagram of a computer-readable storage medium provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0048] In order to make the description of the disclosed content more detailed and complete, the following is an illustrative description of the implementation mode and specific examples of the present invention; however, this is not the only form of implementing or applying the specific embodiments of the present invention. The implementation mode covers the features of multiple specific embodiments and the method steps and their sequence for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equal functions and step sequences. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0050] In addition, in the description of the embodiments of the present invention, "multiple" means two or more than two, and other quantifiers are similar and should be understood. The preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In addition, the embodiments of the present invention and the features therein may be combined with each other without conflict.

[0051] like Figure 1 FIG. 1 is a flow chart of a modeling method for a hard core module provided by an embodiment of the present invention, comprising the following steps:

[0052] Step S101, obtaining a hard core module to be modeled.

[0053] It should be noted that the hard core module to be modeled in this step may be a hard core module with configuration point conflicts.

[0054] Step S102: determining a target signal path to which multiple configuration scenarios are mapped in the hard core module to be modeled.

[0055] It should be noted that in the hard core module to be modeled, there may be a situation where a certain signal path can realize multiple configuration scenarios. In this case, it can be determined that the signal path mapping has multiple configuration scenarios.

[0056] As a specific example, for example, the hard core module to be modeled is a multiplexer. Since the multiplexer is used to select one of multiple input signals for output, the signal path formed between the output port and the input port of the multiplexer will naturally form multiple configuration scenarios.

[0057] Step S103: for any configuration scenario of the target signal path, determine the port of the hard core module to be modeled corresponding to the configuration scenario.

[0058] The ports include input ports and output ports.

[0059] It can be understood that in this step, the ports of the hard-core module to be modeled corresponding to the configuration scenario can realize the above configuration scenario when the first signal is output from the first input port to the first output port. At this time, the ports of the hard-core module to be modeled corresponding to the above configuration scenario can be considered to be the first input port and the first output port.

[0060] Step S104 , based on the correspondence between each of the configuration scenarios and the ports, split the ports of the hard core module to be modeled to obtain a modeled hard core module.

[0061] Wherein, in the modeled hard core module, a signal path mapping formed between a group of the input ports and the output ports has a unique configuration scenario.

[0062] It can be understood that in this step, when splitting the hard-core module to be modeled, the input ports corresponding to the same configuration scenario are split together, the output ports corresponding to the same configuration scenario are split together, and the split input ports are used as an input port of the hard-core module after modeling, and the split output ports are used as output ports of the hard-core module after modeling. Naturally, the signal path mapping formed between any input port and output port of the hard-core module after modeling has a unique configuration scenario.

[0063] It should be noted that the input port corresponding to the same configuration scenario can be one or more, and the output port corresponding to the same configuration scenario can be one or more. The specific number can be determined based on the specific functions implemented in the configuration scenario during application, and is not limited in detail here.

[0064] The embodiment of the present invention splits each port of the hard-core module in the chip based on the configuration scenario to obtain a modeled hard-core module, so that the signal path mapping formed between the ports of the modeled hard-core module has a unique configuration scenario. On this basis, wiring is performed based on the modeled hard-core module. Since the connection (signal path) between its configuration points only corresponds to a unique configuration scenario, the configuration scenarios finally realized by each configuration point will not be crossed and are independent of each other. Therefore, there will be no scenario in which the actual connection in the chip is illegal due to configuration point conflicts. In summary, the technical solution of the embodiment of the present invention can solve the scenario in the prior art where the chip has wiring theory that can reach the actual connection but is illegal.

[0065] In an optional implementation, after step S104, the mode of each hard core module may be verified to check whether the bit stream can select a correct configuration scenario according to the used ports and signal paths.

[0066] In an optional implementation, Figure 2 As shown, step S103 includes:

[0067] Step S1031, determining the output function mode and the input function mode corresponding to the target signal path;

[0068] Step S1032, determining the output port corresponding to any of the output function modes;

[0069] Step S1033, determining the input port corresponding to any of the input function modes.

[0070] Among them, any configuration scenario corresponds to a unique input function mode and output function mode.

[0071] It can be understood that the configuration scenario corresponding to the signal path is jointly determined by the output function mode and the input function mode, and the input function mode is implemented by the input port, and the output function mode is implemented by the output port.

[0072] It should be noted that the input function mode may correspond to multiple input ports or one input port; the output function mode may correspond to multiple output ports or one output port.

[0073] Furthermore, when splitting the input port and the output port, the input port corresponding to any input function mode can be split together as an input port of the hard core module after modeling, and the output port corresponding to any output function mode can be split together as an output port of the hard core module after modeling;

[0074] It can be understood that through this implementation method, the input function mode and output function corresponding to the signal path are determined, and then the input port corresponding to the input function mode and the output port corresponding to the output function mode are determined. The output port and input port corresponding to any configuration scenario can be found. When further splitting based on the determined input port and output port, it can naturally be determined that the signal path between the input port and the output port corresponds to a unique configuration scenario.

[0075] In an optional implementation manner, determining the input port corresponding to any one of the input function modes includes:

[0076] Receive hard core module parameters input by the user;

[0077] Determining an input function mode corresponding to the hard core module parameters;

[0078] For each input function mode, an input port corresponding to the input function mode is determined.

[0079] In this implementation, it can be understood that the input function mode that the user wants to implement can be determined through the hard-core module parameters input by the user. Any function mode requires a corresponding input port to implement. Naturally, for each input function mode, the input port corresponding to the input function mode can be determined, and then the input port can be split.

[0080] It can be understood that in this implementation, the user experience can be improved by defining the functional mode that the user wants to input, and after determining the input functional mode corresponding to the hard-core module parameters through the hard-core module parameters input by the user, the input port corresponding to any input functional mode can naturally be determined.

[0081] In an optional implementation, after splitting the ports of the hard core to be modeled based on the correspondence between each of the configuration scenarios and the ports to obtain the modeled hard core module, the method further includes:

[0082] Traversing the circuit connections of the chip, and collecting the circuit connections of the modeled hard core modules in the chip;

[0083] Based on the circuit connection of the modeled hard core module, updating and establishing the connection design rules of the chip;

[0084] Traversing the user design netlist of the chip, collecting the hard core modules that meet the connection design rules and the available positions of the hard core modules on the chip;

[0085] The hard core module is placed on the available position corresponding to the chip.

[0086] It is understandable that after modeling the hard core module to be modeled, the port layout of the hard core module has changed. In order to check the connection of subsequent hard core modules, the connection design rules of the chip need to be updated. Therefore, it is necessary to collect the circuit connections of the modeled hard core module and update the connection design rules of the chip.

[0087] It should be noted that the user design netlist refers to a data file that describes the internal connection relationship of the circuit generated by the designer after completing the logic design in the integrated circuit design process. This netlist file lists in detail all the components in the design (such as logic gates, storage cells, etc.) and the connections between them.

[0088] Therefore, it can be understood that the solution of this implementation can obtain the available position and the number of available positions of the hard core module, and then the hard core module can be placed in the available position of the chip.

[0089] As a specific example, Figure 3 The figure shows a schematic diagram of a hard core module provided by an embodiment of the present invention, wherein each circle represents a hard core module, the lines between the circles represent the connection relationship between the hard core modules, and the characters A, B, C, D, E and F inside each circle represent the name of the hard core module, wherein the numeric characters such as 1 and 2 represent the number of available positions of the hard core module on the chip, for example, F2 means that the hard core module F has two available positions on the chip.

[0090] In an optional implementation manner, placing the hard core module at the available position corresponding to the chip includes:

[0091] Establishing a search tree consisting of the hard core modules on the chip by a branch and bound search method, wherein each node of the search tree corresponds to an available position of the hard core module on the chip, and the connection relationship between the nodes corresponds to the connection relationship between the hard core modules;

[0092] Search the search tree from top to bottom. If the downward search node is a legal solution, search downward. If the downward search node is an illegal solution, backtrack upward.

[0093] After searching all nodes of the search tree, an optimal solution search tree is obtained;

[0094] Corresponding to the structure of the optimal solution search tree, each of the hard core modules is placed at the available position corresponding to the chip.

[0095] It should be noted that in this implementation, the arrangement of nodes in the search tree from top to bottom is set based on the flow direction of the signal, that is, when the signal is input into each hard-core module, its flow direction is from the hard-core module at the top of the search tree to the hard-core module at the bottom of the search tree. It is naturally understandable that each level in the search tree represents a hard-core module. When the node of the previous level is connected to multiple nodes of the next level, it means that the hard-core module of the next level has multiple available positions. If it is connected to a node of the next level, it means that the hard-core module of the next level has one available position.

[0096] It should be noted that a search node being a legal solution means that the available position of the hard core module corresponding to the node complies with the design rules, and a search node being an illegal solution means that the available position of the hard core module corresponding to the node does not comply with the design rules.

[0097] It should be noted that when the downward search node is an illegal solution, backtracking upward can be called the pruning operation of branch and bound search. The pruned nodes are not included in the final optimal solution search tree. In this way, after searching all the nodes of the search tree, all illegal nodes in the search tree can be pruned. In this way, the nodes in the final optimal solution search tree are the real available positions of each hard-core module.

[0098] As a specific example, Figure 4 The structure diagram of the search tree of a hard core module provided by an embodiment of the present invention is shown. The structure diagram is based on Figure 3The connection relationship of each hard core module and the number of available positions in the chip are established, where A0 is the available position of the A hard core module in the chip, and similarly B0 and C0 are the available positions of the B hard core module and the C hard core module in the chip. D0, E0 and F0 are the first available positions of the D hard core module, the E hard core module and the F hard core module in the chip respectively, and D1, E1 and F1 are the second available positions of the D hard core module, the E hard core module and the F hard core module in the chip respectively.

[0099] It can be understood that in this implementation, the branch and bound search method for hard core module layout optimization has the following significant advantages: 1. Global optimal solution: This method can systematically explore the solution space and has the potential to find the global optimal layout that satisfies all given constraints, that is, the best layout configuration achieved after considering multiple factors such as area, wiring length, and power consumption. 2. Efficient computing resource utilization: The pruning strategy avoids invalid search paths and reduces unnecessary calculations, so that a better solution can be found within a limited computing time, improving design efficiency. 3. Constraint satisfaction: During the search process, the design rules and the constraints of interdependence between modules can be strictly followed, ensuring the feasibility of the layout and reducing the need for later design modifications. 4. Flexibility and scalability: The branch and bound search framework allows the bound function and branch strategy to be adjusted according to different design requirements, and is easy to adapt to integrated circuit design projects of different scales and complexities. 5. Intuitive visualization: The constructed search tree structure provides designers with an intuitive way to understand the process and results of layout optimization, which is convenient for analyzing and adjusting layout strategies. In summary, this method can effectively manage design time and resources while ensuring design quality.

[0100] Based on the above-mentioned modeling method of the hard core module, the embodiment of the present invention provides a modeling device of the hard core module, such as Figure 5 As shown, the present invention provides a modeling device for a hard core module, comprising:

[0101] An acquisition module 510 is used to acquire a hard core module to be modeled;

[0102] A first determination module 520 is used to determine a target signal path in the hard core module to be modeled that is mapped with multiple configuration scenarios;

[0103] A second determination module 530 is used to determine, for any configuration scenario of the target signal path, a port of the hard core module to be modeled corresponding to the configuration scenario, wherein the port includes an input port and an output port;

[0104] The splitting module 540 is used to split the ports of the hard-core module to be modeled based on the corresponding relationship between each configuration scenario and the port to obtain the modeled hard-core module, wherein in the modeled hard-core module, a signal path mapping formed between a group of input ports and output ports has a unique configuration scenario.

[0105] For other details about how each module in the modeling device of the hard-core module implements the above-mentioned technical solution, please refer to the description of the modeling method of the hard-core module provided in the above-mentioned invention embodiment, which will not be repeated here.

[0106] Based on the modeling method of the above hard core modules, such as Figure 6 As shown, an embodiment of the present invention further provides a structural schematic diagram of a modeling device for a hard core module, the modeling device includes a processor 61 and a memory 62 coupled to the processor 61. The memory 62 stores a computer program, and when the computer program is executed by the processor 61, the processor 61 executes the steps of the modeling method for the hard core module in the above embodiment.

[0107] For other details about how the processor 61 in the modeling device of the hard core module implements the above technical solution, please refer to the description of the modeling method of the hard core module provided in the above invention embodiment, which will not be repeated here.

[0108] Among them, the processor 61 can also be called a CPU (Central Processing Unit), and the processor 61 may be an integrated circuit chip with signal processing capabilities; the processor 61 can also be a general-purpose processor, DSP (Digital Signal Process), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, among which the general-purpose processor can be a microprocessor or the processor 61 can also be any conventional processor, etc.

[0109] like Figure 7As shown, the embodiment of the present invention also provides a schematic diagram of the structure of a computer-readable storage medium, on which a readable computer program 71 is stored; wherein the computer program 71 can be stored in the above storage medium in the form of a software product, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, magnetic disk or optical disk, ROM (Read-Only Memory), RAM (Random Access Memory) and other media that can store program codes, or terminal devices such as computers, servers, mobile phones, and tablets.

[0110] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0111] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0112] In addition, each functional module in each embodiment of the present invention may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may be stored in a computer-readable storage medium.

[0113] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0114] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium), or a semiconductor medium (e.g., an SSD (solid state disk, solid state hard disk)).

[0115] The technical solution provided by the present invention is introduced in detail above. The present invention applies specific examples to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

[0116] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, optical storage, etc.) containing computer-usable program code.

[0117] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0118] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0119] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0120] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A modeling method for a hard core module, characterized in that: include: Get the hard core module to be modeled; Determine a target signal path in which a plurality of configuration scenarios are mapped in the hard core module to be modeled; For any configuration scenario of the target signal path, determine the port of the hard core module to be modeled corresponding to the configuration scenario, wherein the port includes an input port and an output port; Based on the correspondence between each of the configuration scenarios and the ports, the ports of the hard-core module to be modeled are split to obtain a modeled hard-core module, wherein in the modeled hard-core module, a signal path mapping formed between a group of the input ports and the output ports has a unique configuration scenario.

2. The modeling method of the hard core module according to claim 1, characterized in that: The step of determining, for any configuration scenario of the target signal path, a port of the hard core module to be modeled corresponding to the configuration scenario, includes: Determining an output function mode and an input function mode corresponding to the target signal path; Determine the output port corresponding to any of the output function modes; The input port corresponding to any of the input function modes is determined, wherein any configuration scenario corresponds to a unique input function mode and output function mode.

3. The modeling method of the hard core module according to claim 2, characterized in that: The determining the input port corresponding to any one of the input function modes comprises: Receive hard core module parameters input by the user; Determining an input function mode corresponding to the hard core module parameters; For each input function mode, an input port corresponding to the input function mode is determined.

4. The modeling method of the hard core module according to claim 1, characterized in that: After splitting the ports of the hard core module to be modeled based on the correspondence between each of the configuration scenarios and the ports to obtain the modeled hard core module, the method further includes: Traversing the circuit connections of the chip, and collecting the circuit connections of the modeled hard core modules in the chip; Based on the circuit connection of the modeled hard core module, updating and establishing the connection design rules of the chip; Traversing the user design netlist of the chip, collecting the hard core modules that meet the connection design rules and the available positions of the hard core modules on the chip; The hard core module is placed on the available position corresponding to the chip.

5. The modeling method of the hard core module according to claim 4, characterized in that: Placing the hard core module at the available position corresponding to the chip includes: Establishing a search tree consisting of the hard core modules on the chip by a branch and bound search method, wherein each node of the search tree corresponds to an available position of the hard core module on the chip, and the connection relationship between the nodes corresponds to the connection relationship between the hard core modules; Search the search tree from top to bottom, searching downward when the downward search node is a legal solution, and backtracking upward when the downward search node is an illegal solution; After searching all nodes of the search tree, an optimal solution search tree is obtained; Corresponding to the structure of the optimal solution search tree, each of the hard core modules is placed at the available position corresponding to the chip.

6. A modeling device for a hard core module, characterized in that: include: An acquisition module is used to acquire a hard core module to be modeled; A first determination module is used to determine a target signal path in the hard core module to be modeled that is mapped with multiple configuration scenarios; A second determination module, configured to determine, for any configuration scenario of the target signal path, a port of the hard core module to be modeled corresponding to the configuration scenario, wherein the port includes an input port and an output port; A splitting module is used to split the ports of the hard-core module to be modeled based on the corresponding relationship between each configuration scenario and the port to obtain a modeled hard-core module, wherein in the modeled hard-core module, a signal path mapping formed between a group of input ports and output ports has a unique configuration scenario.

7. The modeling device of the hard core module according to claim 6, characterized in that: The second determining module is further used for: Determining an output function mode and an input function mode corresponding to the target signal path; Determine the output port corresponding to any of the output function modes; The input port corresponding to any of the input function modes is determined, wherein any configuration scenario corresponds to a unique input function mode and output function mode.

8. The modeling device of the hard core module according to claim 7, characterized in that: The second determining module is further used for: Receive hard core module parameters input by the user; Determining an input function mode corresponding to the hard core module parameters; For each input function mode, an input port corresponding to the input function mode is determined.

9. A modeling device for a hard core module, characterized in that: comprising a memory and a processor, wherein: The memory is used to store computer programs; The processor is used to read the computer program in the memory and execute the steps of any hard core module modeling method according to claims 1-5.

10. A computer-readable storage medium, characterized in that: A readable computer program is stored thereon, and when the program is executed by a processor, the steps of the modeling method of any hard core module as claimed in claims 1-5 are implemented.

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