Thermoelectric coupling simulation method for early design stage of integrated circuit

Abstract

The invention discloses a thermoelectric coupling simulation method for an early design stage of an integrated circuit, and relates to the technical field of integrated circuit analysis. Comprising the following steps: carrying out unit characterization on all standard units in a process library at different temperatures, and obtaining a lib file; the power consumption of the circuit is synthesized and analyzed under the lib files, and a circuit temperature-module power consumption table is established; at the initial temperature, inputting the power consumption of each module of the circuit into a thermal simulation tool HotSpot for thermoelectric coupling simulation to obtain the initial simulation temperature of each module; looking up the table according to the last simulation temperature in the table to obtain the power consumption of each module, and performing simulation again to obtain the current simulation temperature; iterating the steps and calculating a difference value of simulation temperatures obtained by two adjacent times of simulation; and redesigning the circuit, the layout of each module and the boundary condition of chip packaging according to whether iterative convergence is carried out or not and the temperature difference. The method is used for obtaining reliable chip temperature distribution, layout optimization and the like in early circuit design.

Description

Technical Field

[0001] The invention belongs to the technical field of early design analysis of integrated circuits, and in particular relates to a thermoelectric coupling simulation method for the early design stage of integrated circuits. Background Art

[0002] As semiconductor process nodes shrink, power density increases. The rapid growth of power consumption poses a challenge to the temperature of the entire system. Managing the heat generated by the system has become an important issue in circuit design. The rising heat in such systems can result in expensive packaging and cooling costs, and significantly reduce the performance, service life, and reliability of computing systems. Therefore, thermal analysis is a necessary procedure in chip design. Traditional thermal analysis relies on multi-physics simulation tools based on the finite element method (FEM) (such as COMSOL and ANSYS). However, such commercial simulation tools have high computational costs and long solution times. These limitations make commercial simulation tools unsuitable for evaluating early circuit designs (i.e., RTL-level circuits), circuit design schemes, and numerous operating scenarios. Therefore, fast and accurate thermal analysis is essential for chip design and thermal optimization.

[0003] Static or leakage power consumption is the power consumed when the circuit is not running any load. The main source of leakage power consumption is subthreshold leakage current, which occurs when a small amount of current flows. When the gate-source voltage Vgs in the MOS device is lower than the threshold voltage Vth, the subthreshold leakage current increases exponentially with the increase of temperature. In large-scale circuits with high operating temperatures, in order to obtain a more accurate operating temperature, the impact of leakage power consumption cannot be ignored. When studying thermal-aware and power-aware simulation technologies, because the increase in circuit temperature leads to an increase in leakage power consumption, and the increase in power consumption leads to an increase in circuit temperature, it is necessary to solve this temperature and leakage power consumption feedback loop to ensure that they are truly effective in chip-level or system-level design. Some work has explored the problem of leakage power consumption in thermal simulation, mainly using thermal simulation methods with linear or piecewise linear leakage power consumption models and thermal simulation methods with leakage power consumption awareness based on Green's function. In addition, there are methods that describe the relationship between leakage power consumption and temperature as an empirical formula to complete temperature power consumption feedback. However, these methods do not accurately consider the impact of different processes and circuit functions on the power consumption and operating temperature of the entire circuit, which is an urgent problem to be solved in circuit thermal simulation. Summary of the invention

[0004] In view of the above, the present invention provides a thermoelectric coupling simulation method for the early design stage of integrated circuits, which is used to obtain reliable chip temperature distribution and layout optimization in early circuit design.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention discloses a thermoelectric coupling simulation method for an early design stage of an integrated circuit, comprising the following steps:

[0007] 1) Perform unit characterization on all standard units in the process library at different temperatures, and the unit characterization results at one temperature constitute a lib file;

[0008] 2) Perform logic synthesis and power consumption analysis on the RTL-level netlist corresponding to the chip to be simulated for thermoelectric coupling and the lib file at each temperature, obtain the power consumption of each module of the RTL-level netlist at each temperature, and establish a temperature-module power consumption table;

[0009] 3) Perform thermoelectric coupling simulation on the power consumption of each module successively; in the first simulation, an initial temperature is arbitrarily selected, and the power consumption of each module at this temperature in the temperature-module power consumption table is input into the thermal simulation tool HotSpot for simulation to obtain the initial simulation temperature of each module;

[0010] In the next simulation, the power consumption of each module corresponding to the last simulation temperature is found in the temperature-module power consumption table, and the power consumption is input into the thermal simulation tool HotSpot for simulation to obtain the current simulation temperature of each module, and the difference between the simulation temperatures obtained from two adjacent thermal simulations is calculated;

[0011] When the difference in the simulated temperature is less than a preset standard value, the thermoelectric coupling simulation operation is terminated, the simulated temperature of each module during the last simulation is obtained, and the layout planning of each module in the chip is optimized according to the obtained simulated temperature.

[0012] Furthermore, in the step 2), before performing logic synthesis and power consumption analysis, the lib file is first converted into a db file using the LibraryCompiler tool.

[0013] Furthermore, in step 2), the logic synthesis and power consumption analysis are implemented by Design Compiler; when using Design Compiler for logic synthesis and power consumption analysis, the input of Design Compiler also includes timing constraints, and the timing constraints include clock period, clock offset, clock delay, input delay and output delay.

[0014] Furthermore, in step 2), the initial temperature is 25°C.

[0015] Furthermore, in the step 3), if the last simulation temperature falls between two adjacent temperature values ​​in the table, linear interpolation is used to obtain the power consumption value of each module at the simulation temperature.

[0016] Furthermore, in step 3), when the temperature difference between two adjacent simulations increases continuously in successive thermoelectric coupling simulations and leads to thermal runaway, the RTL level circuit design and the boundary conditions of the chip package are modified.

[0017] In a second aspect, the present invention discloses a thermoelectric coupling simulation system for implementing the method, comprising:

[0018] The lib file acquisition module is used to perform unit characterization on all standard units in the process library at different temperatures. The unit characterization results at one temperature constitute a lib file;

[0019] The temperature-module power consumption table acquisition module is used to perform logic synthesis and power consumption analysis on the RTL-level netlist corresponding to the chip to be subjected to thermoelectric coupling simulation and the lib file at each temperature, obtain the power consumption of each module of the RTL-level netlist at each temperature, and establish the temperature-module power consumption table;

[0020] Thermoelectric coupling simulation module, which is used to perform thermoelectric coupling simulation on the power consumption of each module successively; during the first simulation, an initial temperature is selected, and the power consumption of each module at this temperature in the temperature-module power consumption table is input into the thermal simulation tool HotSpot for thermal simulation to obtain the initial simulation temperature of each module;

[0021] In the next simulation, the power consumption of each module corresponding to the last simulation temperature is found in the temperature-module power consumption table, and the power consumption is input into the thermal simulation tool HotSpot for simulation to obtain the current simulation temperature of each module, and the difference between the simulation temperatures obtained in two adjacent simulations is calculated;

[0022] The optimization module is used to compare the difference of the simulation temperature with the preset standard value. When the difference of the simulation temperature is less than the preset standard value, the thermal simulation operation is terminated, the simulation temperature of each module during the last thermal simulation is obtained, and the layout planning of each module in the chip is optimized according to the obtained simulation temperature; when the temperature difference between two adjacent simulations increases continuously in successive thermoelectric coupling simulations and causes thermal runaway, the RTL-level circuit design is modified and the boundary conditions of the chip package are modified.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The present invention adopts technical methods such as standard unit characterization, circuit logic synthesis and power consumption analysis, and proposes a chip-level thermoelectric coupling simulation method from the power consumption analysis of each module of the RTL-level code circuit to the feedback of the manufacturing process, leakage power consumption and temperature. The method overcomes the defects of the simulation method in the existing thermoelectric coupling technology, which does not consider the leakage power consumption or considers the leakage power consumption but does not consider the manufacturing process, thereby obtaining a thermal simulation method with smaller error than the method of using the empirical formula to process the leakage power consumption of the open source thermal simulation tool HotSpot (based on the commercial thermal simulation tool icepak); based on the difference in simulation temperature obtained from two adjacent thermal simulations, the layout planning of each module in the chip is optimized, and finally the optimal module layout planning is obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the framework of the detailed thermal simulation method of the entire invention;

[0026] Figure 2 It is a schematic diagram of the change of power consumption of a pulsating array circuit as the temperature increases;

[0027] Figure 3 This is a schematic diagram of chip layering during thermal simulation. DETAILED DESCRIPTION

[0028] The present invention is further described and illustrated below in conjunction with specific embodiments. The embodiments are merely exemplary of the present disclosure and do not define the scope of limitation. The technical features of each embodiment of the present invention may be combined accordingly without conflicting with each other.

[0029] The present invention provides a thermoelectric coupling simulation method for an early design stage of an integrated circuit, the method comprising the following steps:

[0030] 1) Use the Cadence Liberate tool to characterize all standard cells in the process library at different temperatures, perform a complete characterization process for each temperature, and finally obtain the lib files at these temperatures;

[0031] 2) Perform logic synthesis and power consumption analysis on the RTL (Register Transfer Level) netlist to be analyzed and the lib file at each temperature to obtain the power consumption of each module of the RTL netlist at each temperature; at this time, establish a temperature-module power consumption table corresponding to block0 power, block1 power, ... blocknpower from T0, T1 ... Tm; one variable of the table is temperature, and the other variable is the module in the circuit, and the table content is the different power consumption of each module at different temperatures;

[0032] The logic synthesis is the process of converting a digital circuit design described in a high-level abstract form such as a hardware description language (HDL) into a gate-level netlist, which is a form of representing a circuit structure using logic gates (such as AND gates, OR gates, NOT gates, etc.) and their connection relationships; the power consumption analysis refers to obtaining the dynamic power consumption and leakage power consumption consumed by an electronic device or circuit during operation;

[0033] 3) The table lookup process is based on a thermal simulation method of a compact thermal model HotSpot. The input of the thermal simulation method of the compact thermal model HotSpot includes the power consumption of each module, the layout of all modules, and the characteristics of the packaging materials. In the first iteration, the power consumption of each module at 25°C is read and used as the input of the thermal simulation method of the compact thermal model HotSpot. The temperature of all modules or the temperature distribution map of the entire chip is obtained after the first thermal simulation process is completed.

[0034] At the beginning of the second iteration, the previous temperature result is used to look up the table in the created table. The table result is the power consumption of each module at the previous simulation temperature. The power consumption obtained from the table lookup is used as the input of the thermal simulation, and the temperature of each module or the temperature distribution diagram of the entire chip is obtained by simulation; and the temperature difference of the simulation temperature obtained from two adjacent thermal simulations is calculated;

[0035] The thermal simulation is repeated and iterated. If the temperature difference is less than the preset standard value, the temperature is considered to have converged and the thermal simulation operation is terminated. The simulation temperature of each module during the last thermal simulation is obtained, and the layout plan of each module is optimized according to the obtained module simulation temperature. When the temperature difference between two adjacent simulations increases continuously in successive thermoelectric coupling simulations, resulting in thermal runaway, the RTL-level circuit design and the boundary conditions of the chip package are modified. Among them, optimizing the layout plan of each module includes separating two or more adjacent modules with higher temperatures and preventing them from continuing to be close together. Modifying the RTL-level circuit and modifying the boundary condition design of the chip package is to avoid thermal runaway.

[0036] After application, the present invention considers the influence of leakage power consumption on chip temperature according to actual conditions, and creates a table related to power consumption and temperature. The table can be used for thermal simulation of the present invention on the HotSpot architecture, and can also be used for the commercial software ANSYS icepak to modify the power consumption of the heat source to temperature-dependent power consumption, and fill the table relationship into its power consumption setting to complete the thermal simulation of the commercial tool considering leakage power consumption.

[0037] The power consumption input by the thermal simulation method includes dynamic power consumption and leakage power consumption. The main source of leakage power consumption is subthreshold leakage current, which occurs when a small amount of current flows. When the gate-source voltage Vgs in the MOS device is lower than the threshold voltage Vth, the leakage current is affected by temperature. The subthreshold leakage current increases exponentially with the increase of temperature, as shown in the formula:

[0038]

[0039] Among them, I subthreshold is the subthreshold leakage current; A s is a process-related constant; V th is the threshold voltage; L and W are the effective device channel length and width; V GS is the gate-source voltage; n is the subthreshold swing coefficient of the transistor; V DS is the drain-source voltage; v T is the thermal voltage k is the Boltzmann constant, T is the temperature in Kelvin, and q is the charge of the electron.

[0040] In large-scale circuits with high operating temperatures, the impact of leakage power consumption cannot be ignored in order to obtain a more accurate operating temperature. When studying thermal-aware and power-aware simulation technologies, because the increase in circuit temperature leads to an increase in leakage power consumption, and the increase in power consumption leads to an increase in circuit temperature, this temperature and leakage power consumption feedback loop needs to be solved to ensure that they are truly effective in chip-level or system-level designs.

[0041] In order to create an accurate power consumption model related to temperature fluctuations, the present invention uses the Cadence Liberate tool to use SPICE (Simulation Program with Integrated Circuit Emphasis, a simulation program focusing on integrated circuits) to characterize standard cells, which include AND-OR gates, multipliers, etc. The purpose of standard cell characterization is to create a set of high-quality standard cell libraries to accurately and efficiently simulate the behavior of standard cells in actual circuits. These model sets are used for different purposes by a variety of different digital design tools. The cell characterization output uses an industry standard format (such as Synopsys Liberty (.lib) format), and the lib file includes information such as timing and power consumption of standard cells under different inputs.

[0042] Table 1 Schematic diagram of input files required for Liberate characterization

[0043]

[0044]

[0045] As shown in Table 1, in the MODELS folder, the file with the extension .scs contains the device model with the process corner. In the NETLIST folder, netlists contains the layout netlist in SPICE format. In the TEMPLATE folder, the template.tcl file contains all the input signal conversion times and output capacitance loads, pin lists, cell names, cell definitions (including delay templates, power templates, and constraint templates). Standard cell definitions can be obtained from existing lib files in the process library. The userdata.lib file contains all standard cell areas and pins. In the char.tcl file, all environmental variables such as voltage and temperature are included; sub-standard cell settings include NMOS, PMOS, and diode configurations to accurately reflect the transistor configuration of the process being characterized; next, write the NLDM, CCS, or ECSM model in the .lib file, and name the lib file according to the PVT (process, voltage, temperature) conditions and the different models used.

[0046] See also Figure 1 As shown, it is a framework diagram of the thermal simulation method in the entire invention.

[0047] At the beginning of the cell characterization, each standard cell is characterized at different temperatures. In the setup.tcl script, a specific embodiment of the present invention defines temperature conditions from 25°C to 125°C, with a temperature gradient of 5°C, and a total of 21 different temperature settings. This range covers the operating temperature range of the chip under non-special circumstances. For each temperature, the complete characterization process is performed, and other input information remains unchanged, corresponding to the TSMC 28nm process library. It is worth noting that under the same input conditions, the leakage power consumption of the same standard cell will increase with increasing temperature.

[0048] Logic synthesis and power analysis are important components of the circuit design process. The input of logic synthesis includes not only RTL code and constraint files (such as SDC that defines clock and timing constraints), but also a process-related db format standard cell target library. The db file is converted from the lib file using the Library Compiler tool (that is, before performing logic synthesis and power analysis, the lib file is first converted to a db file using the Library Compiler tool). The synthesis tool uses the information in the db file to select appropriate standard cells to implement the design to meet performance requirements while optimizing costs. In order to prevent the logic synthesis tool from performing different optimizations on the RTL-level netlist under different temperature conditions, resulting in changes in the final mapping netlist, a specific embodiment of the present invention uniformly uses the gate-level netlist synthesized at 25°C (that is, the mapping netlist output at 25°C) as the input for power analysis over the entire temperature range. Subsequently, power analysis is performed using lib files corresponding to different temperatures, and the total power consumption of the RTL-level circuit corresponding to each file at a specific temperature is output. This ensures that power analysis at different temperatures is performed on the same mapping netlist, thereby improving the reliability of the experimental results.

[0049] After logic synthesis, the mapped gate-level netlist, the characterized and converted db file, and the timing constraints (including clock cycle, clock offset, clock delay, input delay, output delay, etc.) are input into Design Compiler, which can also be used for early design power consumption analysis. The present invention estimates power consumption by defining the switching rate of the node through vectorless power consumption analysis. Then, "report power" is used to obtain the dynamic power consumption and leakage power consumption of the RTL circuit under a specific process and temperature. This process of outputting power consumption requires repeated reading of the lib files of T0, T1, ...Tm, and finally obtaining the block0 power, block1 power, ...blockn power at the temperature of T0, T1, ...Tm, and establishing a temperature-module power consumption table for a specific process and circuit.

[0050] After the table is created, the thermal simulation process begins by looking up the table to consider the iterative feedback of temperature and power consumption. The table lookup process is based on a thermal simulation method based on a compact thermal model called HotSpot. The input of the thermal simulation includes the power consumption of each module, the layout planning of all modules (i.e., the position of each module in the circuit, the length and width of each module), and the packaging material characteristics (i.e., the thermal conductivity of the material, the length, width and thickness of the material, the temperature of the external environment, and the boundary conditions of the chip package, including the thermal resistance between the outermost heat sink fins of the chip and the air).

[0051] See also Figure 3As shown in FIG. 1 , it is a schematic diagram of the layered structure of the chip during the thermal simulation process in the entire invention. The present invention only uses the upward heat dissipation path in the thermal simulation, so the circuit packaging boundary condition only considers the thermal resistance of the topmost heat dissipation fin in contact with the air, and does not consider the thermal resistance of the printed circuit board (PCB) in contact with the air when dissipating heat downward.

[0052] In the first iteration, a specific embodiment of the present invention reads the power consumption of each module at 25°C in the table, completes the first thermal simulation process, and obtains the temperature of all modules. Starting from the second iteration, the previous temperature results will be used to find the power consumption of each module at this temperature from the created table, and the power consumption obtained from the table is thermally simulated to obtain the temperature of each module. The above is the simulation process of the block model. In the grid model, it is first necessary to complete the mapping from the chip temperature distribution map obtained by simulation to the module temperature, look up the table to obtain the power consumption of each module at this temperature, and then input it into the thermal simulation tool to solve the chip temperature distribution map, and map it to the block temperature again. Iterate in this way until the power consumption and temperature converge. In this process, since the temperature variable in the table is a discrete variable with an interval of 5°C, when the simulation temperature falls between the temperature variables in the table, linear interpolation will be used between adjacent temperatures to obtain a more accurate power consumption value. Within every 5°C range, the temperature power consumption curve can be considered linear.

[0053] The whole process is repeated until the temperature difference between two iterations meets the convergence criterion (i.e., the temperature difference is less than a preset standard value, and in a specific embodiment of the present invention, the preset standard value is 0.1°C). Another situation is that the iteration causes the temperature difference to increase continuously, thus leading to thermal runaway. In this case, it is necessary to reconsider the boundary conditions of RTL-level circuit design, module layout planning, and circuit packaging.

[0054] If the table building process starts from 25°C to 125°C with an interval of 5°C, it will involve reading the mapped netlist, adding timing constraints and outputting power consumption 21 times. Since the research focus of the present invention is the impact of leakage power consumption and temperature feedback on the final temperature, a larger circuit scale accompanied by a higher operating temperature can better highlight the effectiveness of our method and make the simulation temperature closer to the actual operating temperature. Therefore, the present invention requires a larger circuit scale to verify the proposed method. Unfortunately, a larger circuit scale will lead to an increase in the synthesis time and the time to read the netlist, and power consumption analysis at 21 temperatures is particularly time-consuming. Therefore, the present invention proposes a method to simplify this process. The present invention is aimed at building tables for small-scale circuits because their synthesis time or the time to read the mapped netlist is shorter, which is convenient for analyzing the results. Based on the power consumption temperature curve of the small-scale circuit, the present invention observed consistent results.

[0055] See also Figure 2As shown, it is a change in the power consumption of a pulsating array circuit with increasing temperature. As the temperature increases, the dynamic power consumption maintains a slow linear growth, while the leakage power consumption increases exponentially. This observation is almost consistent with the theoretical expectations mentioned above. Therefore, in order to reduce the table building time, a specific embodiment of the present invention only uses lib files at 25°C and 125°C for synthesis and power consumption analysis. From the curve, the present invention reads the power consumption value at every 5°C interval, establishes a complete table, and completes the power consumption analysis at two temperatures, which can greatly reduce the table building time and improve the efficiency of the thermal simulation method of power consumption temperature feedback.

[0056] In this embodiment, a thermoelectric coupling simulation system for implementing the method is also provided, including:

[0057] The lib file acquisition module is used to perform unit characterization on all standard units in the process library at different temperatures. The unit characterization results at one temperature constitute a lib file;

[0058] The temperature-module power consumption table acquisition module is used to perform logic synthesis and power consumption analysis on the RTL-level netlist corresponding to the chip to be thermally simulated and the lib file at each temperature, obtain the power consumption of each module of the RTL-level netlist at each temperature, and establish the temperature-module power consumption table;

[0059] Thermoelectric coupling simulation module, which is used to input the power consumption of each module at an initial temperature in the table into the thermal simulation tool HotSpot for thermal simulation to obtain the initial simulation temperature of each module;

[0060] And find the power consumption of each module corresponding to the last simulation temperature in the table, and input the power consumption corresponding to all the modules found into the thermal simulation tool HotSpot for thermal simulation, obtain the current simulation temperature of each module, and calculate the difference between the simulation temperatures obtained by two adjacent thermal simulations; among which, the last simulation temperature during the second thermal simulation is the initial simulation temperature;

[0061] The optimization module is used to compare the difference of the simulated temperature with the preset standard value. When the difference of the simulated temperature is less than the preset standard value, the thermal simulation operation is terminated, the simulated temperature of each module during the last thermal simulation is obtained, and the layout planning of each module in the chip is optimized according to the obtained simulated temperature; if the temperature difference continues to increase and leads to thermal runaway, the RTL-level circuit design is modified and the boundary conditions of the chip package are modified.

[0062] For the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment, and the implementation methods of the remaining modules will not be repeated here. The system embodiment described above is only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of the present invention. Ordinary technicians in this field can understand and implement it without paying creative work.

[0063] The embodiments of the system of the present invention can be applied to any device with data processing capabilities, and the device with data processing capabilities can be a device or apparatus such as a computer. The system embodiments can be implemented by software, or by hardware or a combination of software and hardware. Taking software implementation as an example, as a device in a logical sense, the corresponding computer program instructions in the non-volatile memory are read into the memory by the processor of any device with data processing capabilities and run.

[0064] Obviously, the above-described embodiments and drawings are only some examples of the present application. For those of ordinary skill in the art, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that, although the work done in this development process may be complicated and lengthy, for those of ordinary skill in the art, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application. Without departing from the concept of the present application, several variations and improvements can also be made, which all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A thermoelectric coupling simulation method for the early design stage of integrated circuits, characterized in that: The following steps are involved: 1) Perform unit characterization on all standard units in the process library at different temperatures, and the unit characterization results at one temperature constitute a lib file; 2) Perform logic synthesis and power consumption analysis on the RTL-level netlist corresponding to the chip to be simulated for thermoelectric coupling and the lib file at each temperature, obtain the power consumption of each module of the RTL-level netlist at each temperature, and establish a temperature-module power consumption table; 3) Perform thermoelectric coupling simulation on the power consumption of each module successively; in the first simulation, select an initial temperature, input the power consumption of each module at this temperature in the temperature-module power consumption table into the thermal simulation tool HotSpot for simulation, and obtain the initial simulation temperature of each module; In the next simulation, the power consumption of each module corresponding to the last simulation temperature is found in the temperature-module power consumption table, and the power consumption is input into the thermal simulation tool HotSpot for simulation to obtain the current simulation temperature of each module, and the difference between the simulation temperatures obtained from two adjacent thermal simulations is calculated; When the difference in the simulated temperature is less than a preset standard value, the thermoelectric coupling simulation operation is terminated, the simulated temperature of each module during the last simulation is obtained, and the layout planning of each module in the chip is optimized according to the obtained simulated temperature.

2. The method according to claim 1, characterized in that In step 1), the Cadence Liberate tool is used to perform cell characterization on all standard cells in the process library at different temperatures.

3. The method according to claim 1, characterized in that In step 1), the lib file includes timing and power consumption information of the standard unit under different input states.

4. The method according to claim 1, characterized in that: In the step 2), before performing logic synthesis and power consumption analysis, the library compiler tool is used to convert the lib file into a db file.

5. The method according to claim 1, characterized in that In step 2), the logic synthesis and power consumption analysis are implemented by Design Compiler; when using Design Compiler for logic synthesis and power consumption analysis, the input of Design Compiler also includes timing constraints, and the timing constraints include clock period, clock offset, clock delay, input delay and output delay.

6. The method according to claim 1, characterized in that In step 3), the initial temperature is 25°C.

7. The method according to claim 1, characterized in that In the step 3), if the last simulation temperature falls between two adjacent temperature values ​​in the table, linear interpolation is used to obtain the power consumption value of each module at the simulation temperature.

8. The method according to claim 1, characterized in that In step 3), when the temperature difference between two adjacent simulations increases continuously in successive thermoelectric coupling simulations and leads to thermal runaway, the RTL level circuit design and the boundary conditions of the chip package are modified.

9. The method according to claim 8, characterized in that The boundary conditions of the chip package include the thermal resistance between the outermost heat dissipation fins of the chip and the air.

10. A thermoelectric coupling simulation system for implementing the method of claim 8, characterized in that: include: The lib file acquisition module is used to perform unit characterization on all standard units in the process library at different temperatures. The unit characterization results at one temperature constitute a lib file; The temperature-module power consumption table acquisition module is used to perform logic synthesis and power consumption analysis on the RTL-level netlist corresponding to the chip to be subjected to thermoelectric coupling simulation and the lib file at each temperature, obtain the power consumption of each module of the RTL-level netlist at each temperature, and establish the temperature-module power consumption table; Thermoelectric coupling simulation module, which is used to perform thermoelectric coupling simulation on the power consumption of each module successively; during the first simulation, an initial temperature is selected, and the power consumption of each module at this temperature in the temperature-module power consumption table is input into the thermal simulation tool HotSpot for thermal simulation to obtain the initial simulation temperature of each module; In the next simulation, the power consumption of each module corresponding to the last simulation temperature is found in the temperature-module power consumption table, and the power consumption is input into the thermal simulation tool HotSpot for simulation to obtain the current simulation temperature of each module, and the difference between the simulation temperatures obtained in two adjacent simulations is calculated; The optimization module is used to compare the difference of the simulation temperature with the preset standard value. When the difference of the simulation temperature is less than the preset standard value, the thermal simulation operation is terminated, the simulation temperature of each module during the last thermal simulation is obtained, and the layout planning of each module in the chip is optimized according to the obtained simulation temperature; when the temperature difference between two adjacent simulations increases continuously in successive thermoelectric coupling simulations and causes thermal runaway, the RTL-level circuit design is modified and the boundary conditions of the chip package are modified.

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