Array substrate, driving method of pixel circuit, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a driving method of a pixel circuit, a display panel and a display device, relates to the technical field of display, and is used for improving the PWM dimming precision of the display panel. The array substrate comprises a substrate and a plurality of pixel circuits arranged on the substrate. The pixel circuit includes a first light emission control transistor and a second light emission control transistor. The array substrate further comprises a first light-emitting control signal line and a second light-emitting control signal line. The first light emission control signal line is electrically connected to a gate of the first light emission control transistor. The second light emission control signal line is electrically connected to the gate of the second light emission control transistor. The array substrate further comprises a plurality of conducting layers, the first light-emitting control signal line and the second light-emitting control signal line are electrically insulated and located on different conducting layers, and orthographic projections of the first light-emitting control signal line and the second light-emitting control signal line on the substrate do not coincide. The array substrate is used for preparing the display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method for a pixel circuit, a display panel, and a display device. Background Art

[0002] With the development of display technology, display devices such as mobile phones, televisions and computers are increasingly used in people's lives. Display devices include pixel circuits and light-emitting devices. The pixel circuit controls the driving current flowing through the light-emitting device, thereby driving the light-emitting device to display different grayscales, thereby realizing image display. Among them, the luminous efficiency of the light-emitting device will decrease with the decrease of the current density under low current density conditions. In order to improve the luminous efficiency of the light-emitting device, the pixel circuit introduces a pulse width modulation (English: Pulse Width Modulation; PWM for short) dimming method to adjust the brightness of the light-emitting device. PWM dimming controls the light-emitting time of the light-emitting device, adjusts the light-emitting brightness of the light-emitting device, changes the overall brightness of the display screen, and makes the overall brightness of the display screen more stable. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide an array substrate, a driving method for a pixel circuit, a display panel and a display device, so as to improve the PWM dimming accuracy of the display panel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, an array substrate is provided. The array substrate includes a substrate and a plurality of pixel circuits arranged on the substrate, wherein the plurality of pixel circuits are arranged in a plurality of rows and columns. The pixel circuit includes a first light-emitting control transistor and a second light-emitting control transistor. The array substrate also includes a first light-emitting control signal line and a second light-emitting control signal line. The first light-emitting control signal line is electrically connected to the gate of the first light-emitting control transistor. The second light-emitting control signal line is electrically connected to the gate of the second light-emitting control transistor. The array substrate also includes a plurality of conductive layers, wherein the first light-emitting control signal line and the second light-emitting control signal line are electrically insulated, the first light-emitting control signal line and the second light-emitting control signal line are located in different conductive layers, and the orthographic projections of the first light-emitting control signal line and the second light-emitting control signal line on the substrate do not overlap.

[0006] The array substrate provided by the embodiment of the present disclosure is such that the first light-emitting control transistor and the second light-emitting control transistor are independently controlled by the first light-emitting control signal line and the second light-emitting control signal line, respectively, and the control method of the first light-emitting control transistor and the second light-emitting control transistor is more flexible, which is conducive to improving the dimming accuracy of the pixel circuit. For example, the first light-emitting control signal line and the second light-emitting control signal line transmit two different PWM signals respectively, and the signal start and end times of the two PWM signals are different (with a certain phase difference). The duration of the overlap of the working levels of the two PWM signals transmitted by the first light-emitting control signal line and the second light-emitting control signal line can be any value, which is conducive to improving the accuracy of PWM dimming. Moreover, the first light-emitting control signal line and the second light-emitting control signal line are located in different conductive layers, which is conducive to reducing the interval between the first light-emitting control signal line and the second light-emitting control signal line, which is conducive to reducing the space occupied by the pixel circuit and improving the pixel density of the display panel. The orthographic projections of the first light-emitting control signal line and the second light-emitting control signal line on the substrate do not overlap, which can avoid the formation of parasitic capacitance between the first light-emitting control signal line and the second light-emitting control signal line, which is conducive to reducing the risk of signal interference between the first light-emitting control signal line and the second light-emitting control signal line.

[0007] In some embodiments, the plurality of conductive layers include a first gate conductive layer and a first source-drain conductive layer. The first gate conductive layer includes a first gate pattern and the second light-emitting control signal line. The first gate pattern forms a gate of the first light-emitting control transistor. The first source-drain conductive layer is disposed on a side of the first gate conductive layer away from the substrate, and includes the first light-emitting control signal line. The orthographic projection of the first light-emitting control signal line on the substrate partially overlaps with the orthographic projection of the first gate pattern on the substrate, and the first light-emitting control signal line is electrically connected to the first gate pattern.

[0008] In some embodiments, the pixel circuit further includes a driving transistor. The array substrate further includes a semiconductor layer, which is disposed between the substrate and the first gate conductive layer. The semiconductor layer includes a first channel region of the first light-emitting control transistor, a second channel region of the second light-emitting control transistor, a third channel region of the driving transistor, a first connection region, and a second connection region. The first connection region and the second connection region are respectively located on opposite sides of the third channel region, and the first connection region is respectively connected to the third channel region and the second channel region, and the second connection region is respectively connected to the third channel region and the first channel region. The orthographic projection of the first gate pattern on the substrate partially overlaps with the orthographic projection of the first channel region on the substrate, and does not overlap with the orthographic projection of the first connection region on the substrate. The orthographic projection of the second light-emitting control signal line on the substrate partially overlaps with the orthographic projection of the second channel region on the substrate.

[0009] In some embodiments, the pixel circuit further includes a first reset transistor. The semiconductor layer further includes a third connection region and a fourth channel region of the first reset transistor. The first gate conductive layer further includes a fourth gate pattern, and the orthographic projection of the fourth gate pattern on the substrate at least partially overlaps with the orthographic projection of the fourth channel region on the substrate. The first source-drain conductive layer further includes a first enable signal line and a first adapter block, the orthographic projection of the first enable signal line on the substrate partially overlaps with the orthographic projection of the fourth gate pattern on the substrate, and the first enable signal line is electrically connected to the fourth gate pattern. The first adapter block is electrically connected to the third connection region and the gate of the driving transistor. The array substrate further includes a second gate conductive layer, the second gate conductive layer is disposed between the first gate conductive layer and the first source-drain conductive layer, and includes a first initialization voltage signal line, and the first initialization voltage signal line is electrically connected to the first electrode of the first reset transistor.

[0010] In some embodiments, the pixel circuit further includes a compensation transistor. The semiconductor layer further includes a fifth channel region of the compensation transistor, one side of the fifth channel region is connected to the first connection region, and the other side is connected to the third connection region. The first gate conductive layer further includes a fifth gate pattern, and the orthographic projection of the fifth gate pattern on the substrate covers the orthographic projection of the fifth channel region on the substrate. The first source-drain conductive layer further includes a second enable signal line, the orthographic projection of the second enable signal line on the substrate partially overlaps with the orthographic projection of the fifth gate pattern on the substrate, and the second enable signal line is electrically connected to the fifth gate pattern.

[0011] In some embodiments, the compensation transistor is a dual-gate transistor, and the fifth channel region includes a first sub-region and a second sub-region that are spaced apart. The semiconductor layer further includes a fourth connection region, and the fourth connection region is located between the first sub-region and the second sub-region, and is connected to the first sub-region and the second sub-region. The second gate conductive layer further includes a first shielding portion, and the orthographic projection of the first shielding portion on the substrate at least partially overlaps with the orthographic projection of the fourth connection region on the substrate.

[0012] In some embodiments, the second gate conductive layer further includes a second shielding portion, and the orthographic projections of the second shielding portion, the third connection region, and the second enable signal line on the substrate at least partially overlap.

[0013] In some embodiments, the pixel circuit further includes a data write transistor. The semiconductor layer further includes a sixth channel region of the data write transistor, and along the first direction, the fifth channel region and the sixth channel region are staggered, and the sixth channel region is connected to the second connection region. The first direction is the column direction in which the multiple pixel circuits are arranged. The first gate conductive layer further includes a sixth gate pattern, and the orthographic projection of the sixth gate pattern on the substrate partially overlaps with the orthographic projection of the sixth channel region on the substrate. The first source and drain conductive layer further includes a first scan signal line, and the orthographic projection of the first scan signal line on the substrate partially overlaps with the orthographic projection of the sixth gate pattern on the substrate, and the first scan signal line is electrically connected to the sixth gate pattern.

[0014] In some embodiments, the pixel circuit further includes a second reset transistor. The semiconductor layer further includes a seventh channel region of the second reset transistor. The first gate conductive layer further includes a seventh gate pattern, and the orthographic projection of the seventh gate pattern on the substrate partially overlaps with the orthographic projection of the seventh channel region on the substrate. The second gate conductive layer further includes a second initialization voltage signal line, and the second initialization voltage signal line is electrically connected to the first electrode of the second reset transistor. The first source-drain conductive layer further includes a second scan signal line, and the orthographic projection of the second scan signal line on the substrate partially overlaps with the orthographic projection of the seventh gate pattern on the substrate, and the second scan signal line is electrically connected to the seventh gate pattern.

[0015] In some embodiments, the array substrate further includes a light shielding layer disposed between the substrate and the semiconductor layer, and an orthographic projection of the light shielding layer on the substrate at least partially overlaps with an orthographic projection of the pixel circuit on the substrate.

[0016] In some embodiments, the array substrate has a display area and a peripheral area surrounding the display area. The array substrate includes a plurality of first initialization voltage signal lines, a plurality of second initialization voltage signal lines, and a second voltage signal bus. A row of pixel circuits is electrically connected to a first initialization voltage signal line and a second initialization voltage signal line; the second voltage signal bus is arranged in the peripheral area and at least partially surrounds the display area. The array substrate also includes a second source-drain conductive layer. The second source-drain conductive layer is arranged on a side of the first source-drain conductive layer away from the substrate, and includes a plurality of first connection lines, a plurality of second connection lines, and a plurality of third connection lines extending along a first direction. Each first connection line is electrically connected to the plurality of first initialization voltage signal lines, each second connection line is electrically connected to the plurality of second initialization voltage signal lines, and each third connection line extends to the peripheral area and is electrically connected to the second voltage signal bus.

[0017] On the other hand, a control method for a pixel circuit is also provided. The pixel circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. The gate of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, the first electrode is electrically connected to a first voltage signal line, and the second electrode is electrically connected to the first electrode of the driving transistor. The gate of the second light-emitting control transistor is electrically connected to a second light-emitting control signal line, the first electrode is electrically connected to a second electrode of the driving transistor, and the second electrode is electrically connected to a light-emitting device. The first light-emitting control signal line is configured to transmit a first pulse width modulation signal, and the second light-emitting control signal line is configured to transmit a second pulse width modulation signal.

[0018] A display cycle includes a light-emitting stage. The driving method includes: in the light-emitting stage, the first pulse width modulation signal has a first working level period, the second pulse width modulation signal has a second working level period, the first working level period is different from the second working level period, and the first working level period partially overlaps with the second working level period.

[0019] In some embodiments, the amplitude, frequency and duty cycle of the first pulse width modulation signal are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal. The start and end time of the first working level period lags behind the start and end time of the second working level period.

[0020] In some embodiments, the pixel circuit further includes a first reset transistor, a second reset transistor, a data write transistor and a compensation transistor. The gate of the first reset transistor is electrically connected to the first enable signal line, the first electrode is electrically connected to the first initialization voltage signal line, and the second electrode is electrically connected to the gate of the driving transistor. The gate of the second reset transistor is electrically connected to the second scan signal line, the first electrode is electrically connected to the second initialization voltage signal line, and the second electrode is electrically connected to the second electrode of the second light-emitting control transistor. The gate of the data write transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first electrode of the driving transistor. The gate of the compensation transistor is electrically connected to the second enable signal line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the gate of the driving transistor.

[0021] A display cycle also includes a blank phase, in which at least one of the first light-emitting control transistor and the second light-emitting control transistor is turned off. The blank phase includes a first initialization phase, a second initialization phase and a data writing phase. The driving method also includes: in the first initialization phase, the first reset transistor is turned on under the control of the first enable signal from the first enable signal line, and the first initialization voltage signal from the first initialization voltage signal line is transmitted to the gate of the driving transistor. In the second initialization phase, the first reset transistor remains turned on, the compensation transistor is turned on under the control of the second enable signal from the second enable signal line, and the first initialization voltage signal is transmitted to the second electrode of the driving transistor. In the data writing phase, the compensation transistor remains turned on, the data writing transistor is turned on under the control of the first scan signal from the first scan signal line, and the data signal from the data line is transmitted to the first electrode of the driving transistor.

[0022] In some embodiments, the blank phase also includes a bias phase after the data writing phase. The driving method also includes: in the bias phase, the first light-emitting control transistor is turned off, the second light-emitting control transistor is turned on, and the second reset transistor is turned on under the control of the second scanning signal of the second scanning signal line, and the second initialization voltage signal from the second initialization voltage signal terminal is transmitted to the second electrode of the second light-emitting control transistor and the first electrode of the driving transistor in sequence.

[0023] In some embodiments, during the second initialization phase and the data writing phase, the second reset transistor is turned on under the control of a second scan signal from the second scan signal line, and transmits a second initialization voltage signal from a second initialization voltage signal line to the second electrode of the second light emitting control transistor.

[0024] In some embodiments, the first working level period is within the second working level period, and the start and end times of the first working level period are respectively separated from the start and end times of the second working level period. Alternatively, the second working level period is within the first working level period, and the start and end times of the first working level period are respectively separated from the start and end times of the second working level period.

[0025] In some embodiments, the amplitude, frequency and duty cycle of the first pulse width modulation signal are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal. The start and end time of the first working level period are respectively ahead of the start and end time of the second working level period.

[0026] In another aspect, a display panel is provided, comprising a plurality of light emitting devices and an array substrate as described in any one of the above embodiments, wherein the plurality of light emitting devices are arranged on the array substrate, and each light emitting device is electrically connected to a pixel circuit.

[0027] In another aspect, a display device is provided, comprising a driving circuit board and the above-mentioned display panel, wherein the driving circuit board is electrically connected to the display panel and configured to transmit a control signal to the display panel.

[0028] The driving method of the pixel circuit, the display panel and the display device provided by the embodiments of the present disclosure can achieve the same beneficial effects as those achieved by the above-mentioned array substrate, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1 is a structural diagram of a display device according to some embodiments;

[0031] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0032] Figure 3 is a cross-sectional structural diagram of a display panel according to some embodiments;

[0033] Figure 4 is a structural diagram of a pixel circuit according to some embodiments;

[0034] Figure 5 It is a PWM signal diagram in the prior art;

[0035] Figure 6 is a structural diagram of an array substrate according to some embodiments;

[0036] Figure 7 is another structural diagram of an array substrate according to some embodiments;

[0037] Figure 8 is a control timing diagram of a first light emitting control signal line and a second light emitting control signal line according to some embodiments;

[0038] Fig. 9is another structural diagram of a pixel circuit according to some embodiments;

[0039] Fig.10 is a structural diagram of a semiconductor layer according to some embodiments;

[0040] Fig.11 A diagram showing a stacked structure of a semiconductor layer and a light shielding layer according to some embodiments;

[0041] Fig.12 is a diagram of a stacked structure of a semiconductor layer and a first gate conductive layer according to some embodiments;

[0042] Fig.13 A diagram showing a stacked structure from a semiconductor layer to a second gate conductive layer according to some embodiments;

[0043] Fig.14 A diagram of a stacked structure from a semiconductor layer to a first source-drain conductive layer according to some embodiments;

[0044] Fig.15 A diagram of a stacked structure from a semiconductor layer to a second source-drain conductive layer according to some embodiments;

[0045] Fig.16A is a schematic diagram of an array substrate according to some embodiments;

[0046] Fig. 16B is a structural diagram of an array substrate according to some embodiments;

[0047] Fig.17 is another structural diagram of a pixel circuit according to some embodiments;

[0048] Fig.18 is another structural diagram of a pixel circuit according to some embodiments;

[0049] Fig.19 is another control timing diagram of the first light emitting control signal line and the second light emitting control signal line according to some embodiments;

[0050] Fig. 20 is a connection relationship diagram of a first light emitting control signal line, a second light emitting control signal line and a first shift register according to some embodiments;

[0051] Fig.21 is a connection relationship diagram of the first enable signal line and the second enable signal line and the second shift register;

[0052] Fig. 22 is a control timing diagram of a pixel circuit according to some embodiments;

[0053] Fig.23 is another control timing diagram of a pixel circuit according to some embodiments;

[0054] Fig.24 is another control timing diagram of a pixel circuit according to some embodiments;

[0055] Fig.25 is another control timing diagram of a pixel circuit according to some embodiments;

[0056] Fig.26 is another control timing diagram of a pixel circuit according to some embodiments;

[0057] Fig. 27 is another control timing diagram of a pixel circuit according to some embodiments. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0059] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0060] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0061] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0062] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0063] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0064] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0065] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0066] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0067] See also Figure 1 Some embodiments of the present disclosure provide a display device 1000, which may be any device that displays anything, whether in motion (eg, video) or fixed (eg, still image), and whether text or images.

[0068] For example, the display device 1000 can be any product or component with display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle display, a flight display, etc. Figure 1 As shown, the display device 1000 may be a mobile phone.

[0069] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an organic light-emitting diode (OLED) display device, a quantum dot electroluminescent display device (QLED) or a mini / micro light-emitting diode (MLED). From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device or a foldable display device. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular. Some embodiments of the present disclosure are schematically described below by taking a rectangular and planar organic light-emitting diode display device as an example, but the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered as long as the same technical concept is applied.

[0070] In some embodiments, see Figure 2 , the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may include, for example, a timing controller (Timing Controller; TCON for short), a power management chip DC / DC, and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 may also include other circuit structures, which are not listed here one by one. The driving circuit board 1200 is electrically connected to the display panel 1100 and is configured to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to display an image. The above-mentioned control signal may include, for example, a clock signal, a power supply voltage signal, and a data signal, which are not listed here one by one.

[0071] In addition, the display device 1000 may further include an under-screen camera and an under-screen fingerprint recognition sensor, etc., so that the display device 1000 can realize a variety of different functions such as taking pictures, recording videos, fingerprint recognition or face recognition, which are not specifically limited here.

[0072] See also Figure 2 The display panel 1100 has a display area AA and a peripheral area BB, wherein the peripheral area BB is at least located on one side of the display area AA. For example, the peripheral area BB is arranged around the display area AA. The display area AA is an area on the display panel 1100 for displaying images, and the display area AA is provided with a plurality of sub-pixels P, which are the smallest light-emitting units on the display panel 1100 and are used to display images.

[0073] Among them, multiple sub-pixels P can emit light of the same color, such as white light or blue light. Based on this, the display panel also includes a color filter layer arranged on the display side, that is, the display panel adopts a COE (full name in English: CF onEncapsulation; Chinese name: color filter layer on encapsulation film) structure. Alternatively, multiple sub-pixels P can emit light of different colors. For example, multiple sub-pixels P include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light. Exemplarily, multiple sub-pixels P can be divided into multiple pixel units, each pixel unit including a red sub-pixel, a blue sub-pixel, and one (or two) green sub-pixels.

[0074] See also Figure 3 , the display panel 1100 includes an array substrate 100, a plurality of light-emitting devices 200 and an encapsulation layer 300 which are stacked. Of course, the display panel 1100 may also include a functional stack arranged on the side of the encapsulation layer 300 away from the array substrate 100. The functional stack may be, for example, one or more of a touch function layer, an anti-reflection layer, a hardening layer, a color film layer (the display panel adopts a COE structure) and an anti-fingerprint layer, so that the display panel 1100 can achieve corresponding functions. The embodiments of the present disclosure do not specifically limit the types and quantities of the above-mentioned functional stacks.

[0075] Continue reading Figure 3 , the array substrate 100 may include a substrate 11, a semiconductor layer Poly disposed on the substrate 11, and a plurality of conductive layers 12 disposed on a side of the semiconductor layer Poly away from the substrate 11. In some embodiments, Figure 3As shown, the multiple conductive layers 12 include a first gate conductive layer Gate1, a second gate conductive layer Gate2, a first source-drain conductive layer SD1, and a second source-drain conductive layer SD2, which are sequentially arranged along a direction Z away from the substrate 11. The array substrate 100 also includes an insulating layer located between any two adjacent conductive layers mentioned above. Exemplarily, the array substrate also includes a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ILD, a first planarization layer PLN1, and a second planarization layer PLN2. Of course, the array substrate 100 may also include other conductive layers or insulating layers, which are not listed here one by one.

[0076] Continue reading Figure 3 The light emitting device 200 may include, for example, a stacked anode 201, a light emitting functional layer 202, and a cathode layer 203. The display panel 1100 may further include a pixel defining layer PDL, which is disposed on a side of the anode 201 away from the array substrate 100 and includes a plurality of openings, and each light emitting device 200 is located in an opening area.

[0077] The encapsulation layer 300 is configured to reduce the risk of water vapor and oxygen in the external environment entering the light emitting device 200, thereby increasing the service life of the display panel 1100. The encapsulation layer 300 may be an encapsulation film or an encapsulation substrate. Figure 3 As shown, the encapsulation layer 300 may be an encapsulation film. In this case, the encapsulation layer 300 may include a first inorganic encapsulation layer 301 , an organic encapsulation layer 302 , and a second inorganic encapsulation layer 303 which are sequentially stacked.

[0078] like Figure 2 As shown, the array substrate 100 has a display area AA and a peripheral area BB, and the peripheral area BB is arranged around the display area AA. The display area AA of the array substrate 100 is the same area as the display area AA of the display panel 1100, and the peripheral area BB of the array substrate 100 is the same area as the peripheral area BB of the display panel 1100.

[0079] The array substrate 100 includes a plurality of pixel circuits 110, which are disposed in the display area AA and arranged in a plurality of rows and columns in the display area AA. The plurality of rows of pixel circuits 110 are arranged along a first direction Y, and each row includes a plurality of pixel circuits 110 arranged along a second direction X. The plurality of columns of pixel circuits 110 are arranged along the second direction X, and each column includes a plurality of pixel circuits 110 arranged along the first direction Y. In other words, the first direction Y is the column direction in which the plurality of pixel circuits 110 are arranged, and the second direction X is the row direction in which the plurality of pixel circuits 110 are arranged. The first direction Y and the second direction X intersect each other, and illustratively, the first direction Y and the second direction X are perpendicular to each other.

[0080] Among them, the pixel circuit 110 includes a plurality of thin film transistors (Thin Film Transistor; abbreviated as: TFT) and at least one capacitor Cst. Exemplarily, the pixel circuit 110 can be a "7T1C" circuit or an "8T1C" circuit, etc., wherein "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to the capacitor Cst, and the number before "C" refers to the number of capacitors Cst. In the following embodiments of the present disclosure, the pixel circuit 110 is a "7T1C" circuit as an example for schematic description, but the embodiments of the present disclosure are not limited to this, and any other pixel circuit 110 can also be considered as long as the same technical concept is applied.

[0081] The thin film transistor can be a P-type transistor or an N-type transistor. The P-type transistor is turned on under the action of a low level and is turned off under the action of a high level; the N-type transistor is turned on under the action of a high level and is turned off under the action of a low level. In the embodiments disclosed herein, P-type transistors are used as examples for explanation. The first electrode of each thin film transistor used in the pixel circuit is one of the source and the drain of the thin film transistor, and the second electrode is the other of the source and the drain of the thin film transistor. Exemplarily, the first electrode of the thin film transistor is the source, and the second electrode is the drain.

[0082] In some embodiments, Figure 4 As shown, the plurality of thin film transistors may include a driving transistor T3, a first light emission control transistor T1, and a second light emission control transistor T2. A first electrode of the first light emission control transistor T1 is electrically connected to a first voltage signal line VDD, and a second electrode is electrically connected to a first electrode of the driving transistor T3. A first electrode of the second light emission control transistor T2 is electrically connected to a second electrode of the driving transistor T3, and a second electrode is electrically connected to the light emitting device 200. In the light emission phase of a display frame, when the first light emission control transistor T1 and the second light emission control transistor T2 are turned on at the same time, the driving current generated by the driving transistor T3 may flow to the light emitting device 200, and drive the light emitting device 200 to emit light.

[0083] In the related art, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 of the same pixel circuit are electrically connected to the same light-emitting control signal line, so that the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on or off at the same time. When the pixel circuit adopts PWM dimming, PWM dimming adjusts the duration of the light-emitting device by adjusting the duration of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 being turned on during the light-emitting phase, thereby adjusting the duration of the light-emitting device to emit light, thereby achieving the purpose of adjusting the light-emitting brightness of the light-emitting device. Figure 5As shown, in the PWM signal, the duration of a working level K is usually an even multiple of the horizontal scanning time (1H), and 1H can usually be 2μs to 20μs. Limited by the duration of a working level K, the accuracy of PWM dimming is low. It can be understood that the working level refers to the voltage that turns on the first light-emitting control transistor T1 and the second light-emitting control transistor T2. When the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are P-type transistors, the working level is a low-level voltage.

[0084] To solve the above technical problems, see Figure 6 and Figure 7 The array substrate 100 provided by the embodiment of the present disclosure includes a first light emission control transistor T1 and a second light emission control transistor T2. The array substrate 100 also includes a first light emission control signal line EM1 and a second light emission control signal line EM2. Figure 7 It is a stacked structure diagram of the semiconductor layer Poly, the first gate conductive layer Gate1 and the first source and drain conductive layer SD1 of the array substrate.

[0085] The first light-emitting control signal line EM1 is electrically connected to the gate of the first light-emitting control transistor T1, the second light-emitting control signal line EM2 is electrically connected to the second light-emitting control transistor T2, and the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are electrically insulated. In this way, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are independently controlled by the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2, respectively, and the control method of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 is more flexible, which is conducive to improving the PWM dimming accuracy of the pixel circuit 110.

[0086] For example, Figure 8 As shown, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are respectively used to transmit two different PWM signals, and the start and end times of the two PWM signals are different (with a certain limit difference). Figure 8 As shown, the low level duration W of the two PWM signals transmitted by the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 is equal, and the low level opening time can differ by any value ΔK. Based on this, the low level overlap duration of the two PWM signals can be any value, which is conducive to improving the accuracy of PWM dimming. The specific control method of the pixel circuit 110 is described below. The signal start and end time of the signal refers to the time when the signal starts and the time when it is cut off (ended).

[0087] The first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are located in different conductive layers 12, which is beneficial to reducing the interval between the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 along the first direction Y, which is beneficial to reducing the space occupied by the pixel circuit 110 and improving the pixel density (Pixels Per Inch; abbreviated as: PPI) of the display panel 1100. The orthographic projections of the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 on the substrate 11 do not overlap, which can avoid the formation of parasitic capacitance between the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2, which is beneficial to reducing the risk of signal interference between the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2.

[0088] Of course, in some other embodiments, without considering the space occupied by the pixel circuit 110, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 may also be located in the same conductive layer. In this way, it is sufficient to ensure that there is a sufficient interval between the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 to avoid interference between the signals transmitted therebetween.

[0089] In some embodiments, see Fig. 9 The pixel circuit 110 further includes a driving transistor T3, a first reset transistor T4, a compensation transistor T5, a data writing transistor T6, a second reset transistor T7 and a capacitor Cst.

[0090] like Fig. 9 As shown, the gate of the first reset transistor T4 is electrically connected to the first enable signal line Scan-1, the first electrode is electrically connected to the first initialization voltage signal line Vinit1, and the second electrode is electrically connected to the gate of the driving transistor T3. The gate of the compensation transistor T5 is electrically connected to the second enable signal line Scan2, the first electrode is electrically connected to the second electrode of the driving transistor T3, and the second electrode is electrically connected to the gate of the driving transistor T3. The gate of the data writing transistor T6 is electrically connected to the first scanning signal line GL1, the first electrode is electrically connected to the data line DL, and the second electrode is electrically connected to the first electrode of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second scanning signal line GL2, the first electrode is electrically connected to the second initialization voltage signal line Vinit2, and the second electrode is electrically connected to the second electrode (the anode of the light emitting device 200) of the second light emitting control transistor T2. One electrode plate of the capacitor Cst is electrically connected to the first voltage signal line VDD, and the other electrode plate is electrically connected to the gate of the driving transistor T3.

[0091] Compared with the scan signal (such as the first scan signal transmitted by the first scan signal line and the second scan signal transmitted by the second scan signal line), the pulse width of the enable signal (such as the first enable signal transmitted by the first enable signal line Scan-1 and the second enable signal transmitted by the second enable signal line Scan2) is wider, and the first reset transistor T4 and the compensation transistor T5 are controlled by the enable signal, which is conducive to fully writing the signal into the corresponding node and more conducive to the timing adjustment of the pixel circuit 110. Exemplarily, the pulse width of the first enable signal transmitted by the first enable signal line Scan-1 is longer, which is conducive to fully writing the first initialization voltage signal from the first initial voltage signal line Vinit1 into the gate of the driving transistor T3.

[0092] In some embodiments, the second enable signal line Scan2 is insulated from the first scan signal line GL1, and the two are configured to transmit different voltage signals. In this way, the data write transistor T6 and the compensation transistor T5 are controlled by different signal lines, and the control timing of the data write transistor T6 and the compensation transistor T5 is more flexible, which is beneficial to improving the control accuracy of the pixel circuit 110 (see below).

[0093] like Fig.10 As shown, the semiconductor layer Poly includes a plurality of semiconductor patterns 20, each semiconductor pattern 20 is used to form a pixel circuit 110, or in other words, the pixel circuit 110 includes a semiconductor pattern 20. It should be noted that, Fig.10 In the embodiment, the semiconductor layer Poly adopts different filling shapes to distinguish different regions of the semiconductor pattern 20, and the semiconductor pattern 20 is a continuous overall structure.

[0094] See also Fig.10 and Fig.11 The semiconductor pattern 20 may include a first channel region 21 of a first light emission control transistor T1, a second channel region 22 of a second light emission control transistor T2, a third channel region 23 of a driving transistor T3, a fourth channel region 24 of a first reset transistor T4, a fifth channel region 25 of a compensation transistor T5, a sixth channel region 26 of a data write transistor T6, a seventh channel region 27 of a second reset transistor T7, a first connection region 28, a second connection region 29, a third connection region 210, a fourth connection region 211 and a fifth connection region 212.

[0095] The first channel region 21 is used to form a channel structure of the first light emission control transistor T1, and the second channel region 22 is used to form a channel structure of the second light emission control transistor T2. The first channel region 21 and the second channel region 22 are staggered along the first direction Y. In other words, the first channel region 21 and the second channel region 22 are spaced apart in the first direction Y, which is beneficial to the wiring arrangement of the first light emission control signal line EM1 and the second light emission control signal line EM2.

[0096] The first connection region 28 and the second connection region 29 are respectively located at opposite sides of the third channel region 23 (along the second direction X). The first connection region 28 is connected to the third channel region 23 and the second channel region 22, so that the first electrode of the second light emission control transistor T2 is electrically connected to the second electrode of the driving transistor T3. The first connection region 28 can form the second electrode of the driving transistor T3 and the first electrode of the second light emission control transistor T2. Fig.10 As shown, the first connection region 28 is also electrically connected to the fifth channel region 25 of the compensation transistor T5 and forms a first electrode of the compensation transistor T5.

[0097] Along the first direction Y, the fourth channel region 24 and the fifth channel region 25 are staggered, and the fifth channel region 25 and the sixth channel region 26 are staggered, so that the first enable signal line Scan1, the second enable signal line Scan2 and the first scanning signal line GL1 are arranged at intervals along the first direction Y, which is beneficial to the spatial arrangement of the first enable signal line Scan1, the second enable signal line Scan2 and the first scanning signal line GL1.

[0098] The second connection region 29 is connected to the third channel region 23 and the first channel region 21, so that the second electrode of the first light emission control transistor T1 is electrically connected to the first electrode of the driving transistor T3. In other words, the second connection region 29 can form the first electrode of the driving transistor T3 and the second electrode of the first light emission control transistor T1. Fig.10 As shown, the second connection region 29 is also electrically connected to the sixth channel region 26 of the data writing transistor T6 and forms the second electrode of the data writing transistor T6.

[0099] The fourth channel region 24 of the first reset transistor T4 and the fifth channel region 25 of the compensation transistor T5 are connected via the third connection region 210, and the third connection region 210 electrically connects the second electrode of the first reset transistor T4 and the second electrode of the compensation transistor T5. In other words, the third connection region 210 forms the second electrode of the first reset transistor T4 and the second electrode of the compensation transistor T5.

[0100] The second channel region 22 of the second light emission control transistor T2 and the seventh channel region 27 of the second reset transistor T7 are connected via the fifth connection region 212, and the fifth connection region 212 electrically connects the second electrode of the second light emission control transistor T2 and the second electrode of the second reset transistor T7. In other words, the fifth connection region 212 forms the second electrode of the second light emission control transistor T2 and the second reset transistor T7.

[0101] In some embodiments, continue to refer to Fig.10 and Fig.11, the compensation transistor T5 can be a dual-gate transistor, which is beneficial to reduce the leakage current of the compensation transistor T5, thereby improving the gate voltage holding capability of the driving transistor T3. The fifth channel region 25 includes a first sub-region 251 and a second sub-region 252 that are spaced apart. The fourth connection region 211 is located between the first sub-region 251 and the second sub-region 252, and is used to connect the first sub-region 251 and the second sub-region 252.

[0102] The semiconductor pattern 20 may further include a sixth connection region 213, a seventh connection region 214, an eighth connection region 215 and a ninth connection region 216. The sixth connection region 213 is located on a side of the seventh channel region 27 away from the fifth connection region 212 and is connected to the seventh channel region 27 to form a first electrode of the second reset transistor T7 and is configured to be electrically connected to a second initialization voltage signal line (not shown).

[0103] The seventh connection area 214 is located on a side of the first channel area 21 away from the second connection area 29, and is connected to the first channel area 21; the seventh connection area 214 is used to form the first electrode of the first light-emitting control transistor T1, and is electrically connected to the first voltage signal line (not shown in the figure). The eighth connection area 215 is located on a side of the fourth channel area 24 away from the third connection area 210, and is connected to the fourth channel area 24. The eighth connection area 215 is used to form the first electrode of the first reset transistor T4, and is electrically connected to the first initialization voltage signal line (not shown in the figure). The ninth connection area 216 is located on a side of the sixth channel area 26 away from the second connection area 29, and is connected to the sixth channel area 26. The ninth connection area 216 is used to form the first electrode of the data writing transistor T6, and is electrically connected to the data line (not shown in the figure).

[0104] In some embodiments, continue to refer to Fig.10 , the first reset transistor T4 can be a dual-gate transistor, which is beneficial to reduce the leakage current of the first reset transistor T4, thereby improving the gate voltage holding capability of the driving transistor T3. The fourth channel region 24 includes a third sub-region 241 and a fourth sub-region 242 that are spaced apart. The semiconductor layer Poly also includes a tenth connection region 217, which is located between the third sub-region 241 and the fourth sub-region 242 and is used to connect the third sub-region 241 and the fourth sub-region 242.

[0105] In some embodiments, see Fig.12 The array substrate 100 further includes a light shielding layer BSM. The light shielding layer BSM is disposed between the substrate 11 and the pixel circuit 110, and the orthographic projection of the light shielding layer BSM on the substrate 11 at least partially overlaps with the orthographic projection of the pixel circuit 110 on the substrate.

[0106] Exemplarily, the light shielding layer BSM is disposed between the substrate 11 and the semiconductor layer Poly, and the orthographic projection of the light shielding layer BSM on the substrate 11 partially overlaps with the orthographic projection of the semiconductor layer Poly on the substrate 11. Fig.12 As shown, the orthographic projections of the third channel region 23 , the fourth channel region 24 and the fifth channel region 25 in the semiconductor pattern 20 on the substrate 11 are located within the range of the orthographic projection of the light shielding layer BSM on the substrate 11 .

[0107] In some embodiments, see Fig.11 The first gate conductive layer Gate1 is disposed on a side of the semiconductor layer Poly away from the substrate 11 , and includes a first gate pattern 31 , a second light emitting control signal line EM2 , a third gate pattern 33 , a fourth gate pattern 34 , a fifth gate pattern 35 , a sixth gate pattern 36 and a seventh gate pattern 37 .

[0108] See also Fig.10 and Fig.11 , the orthographic projection of the first gate pattern 31 on the substrate 11 partially overlaps with the orthographic projection of the first channel region 21 on the substrate 11. Exemplarily, the orthographic projection of the first gate pattern 31 on the substrate 11 covers the orthographic projection of the first channel region 21 on the substrate 11, and is used to form the gate of the first light emission control transistor T1. Moreover, the orthographic projection of the first gate pattern 31 on the substrate 11 does not overlap with the orthographic projection of the first connection region 28 on the substrate 11, so that a transistor can be avoided from being formed between the first gate pattern 31 and the first connection region 28.

[0109] The orthographic projection of the second light-emitting control signal line EM2 on the substrate 11 partially overlaps with the orthographic projection of the second channel region 22 on the substrate 11. Exemplarily, the second light-emitting control signal line EM2 includes a second gate pattern 221, the orthographic projection of the second gate pattern 221 on the substrate 11 overlaps with the orthographic projection of the second channel region 22 on the substrate 11, and the second gate pattern 221 is used to form the gate of the second light-emitting control transistor T2. That is, the second light-emitting control signal line EM2 is used to transmit the second pulse width modulation signal on the one hand, and is also used to form the gate of the second light-emitting control transistor T2 on the other hand.

[0110] See also Fig.10 and Fig.11, the orthographic projection of the third gate pattern 33 on the substrate 11 covers the orthographic projection of the third channel region 23 on the substrate 11, and is used to form the gate of the driving transistor T3. Of course, the third gate pattern 33 is also used to form an electrode plate of the capacitor Cst. The orthographic projection of the fourth gate pattern 34 on the substrate 11 partially overlaps with the orthographic projection of the fourth channel region 24 on the substrate 11, and is used to form the gate of the first reset transistor T4. Exemplarily, the orthographic projection of the fourth gate pattern 34 on the substrate 11 covers the orthographic projection of the fourth channel region 24 on the substrate 11. The orthographic projection of the fifth gate pattern 35 on the substrate 11 partially overlaps with the orthographic projection of the fifth channel region 25 on the substrate 11, and is used to form the gate of the compensation transistor T5. Exemplarily, the orthographic projection of the fifth gate pattern 35 on the substrate 11 covers the orthographic projection of the fifth channel region 25 on the substrate 11. The orthographic projection of the sixth gate pattern 36 on the substrate 11 partially overlaps with the orthographic projection of the sixth channel region 26 on the substrate 11, and is used to form the gate of the data writing transistor T6. Exemplarily, the orthographic projection of the sixth gate pattern 36 on the substrate 11 covers the orthographic projection of the sixth channel region 26 on the substrate 11. The orthographic projection of the seventh gate pattern 37 on the substrate 11 partially overlaps with the orthographic projection of the seventh channel region 27 on the substrate 11, and is used to form the gate of the second reset transistor T7. Exemplarily, the orthographic projection of the seventh gate pattern 37 on the substrate 11 covers the orthographic projection of the seventh channel region 27 on the substrate 11.

[0111] For example, Fig.11 As shown, along the first direction Y, the first gate pattern 31, the second light-emitting control signal line EM2, the gate pattern 32, the third gate pattern 33, the fourth gate pattern 34, the fifth gate pattern 35, the sixth gate pattern 36 and the seventh gate pattern 37 included in the same pixel circuit 110 are staggered, so that the gate of the first light-emitting control transistor T1, the gate of the second light-emitting control transistor T2, the gate of the driving transistor T3, the gate of the first reset transistor T4, the gate of the compensation transistor T5, the gate of the data writing transistor T6 and the gate of the second reset transistor T7 can be connected to different signal lines respectively, which can improve the control accuracy of the pixel circuit 110, and the above-mentioned different signal lines are arranged along the first direction Y to reduce the risk of signal interference between adjacent signal lines.

[0112] In some embodiments, Fig.13 As shown, the second gate conductive layer Gate2 is disposed on a side of the first gate conductive layer Gate1 away from the substrate 11, and may include a first initialization voltage signal line Vinit1, a second initialization signal line Vinit2, a first shielding portion 41, a second shielding portion 42, and a capacitor electrode 43. The first shielding portion 41, the second shielding portion 42, and the capacitor electrode 43 are interconnected to form a whole.

[0113] See also Fig.13 The orthographic projection of the capacitor electrode 43 on the substrate 11 partially overlaps with the orthographic projection of the third gate pattern 33 on the substrate 11 to form another electrode of the storage capacitor Cst.

[0114] See also Fig.14 The first source-drain conductive layer SD1 is arranged on the side of the second gate conductive layer Gate2 away from the substrate 11, and includes a first light-emitting control signal line EM1, a first enable signal line Scan1, a second enable signal line Scan2, a first scan signal line GL1, a second scan signal line GL2, a first voltage signal line VDD, a first transfer block 51, a second transfer block 52, a third transfer block 53, a fourth transfer block 54 and a fifth transfer block 55.

[0115] See also Fig.13 and Fig.14 , the orthographic projection of the first light-emitting control signal line EM1 on the substrate 11 partially overlaps with the orthographic projection of the first gate pattern 31 on the substrate 11, and the first light-emitting control signal line EM1 is electrically connected to the first gate pattern 31. In the process of preparing the array substrate 100, it is necessary to use the first gate conductive layer Gate1 as a mask layer to perform doping treatment on the semiconductor layer Poly. The first light-emitting control signal line EM1 and the first gate pattern 31 are located in different conductive layers 12, and the first light-emitting control signal line EM1 is arranged in the first source-drain conductive layer SD1, which can avoid the first light-emitting control signal line EM1 from blocking the semiconductor layer Poly during the doping process of the semiconductor layer Poly. Moreover, it is beneficial to increase the interval between the first light-emitting control signal line EM1 and the semiconductor pattern 20, reduce the parasitic capacitance formed between the first light-emitting control signal line EM1 and the semiconductor pattern 20, and further reduce the influence of the signal transmitted by the first light-emitting control signal line EM1 on the semiconductor pattern 20.

[0116] The orthographic projection of the first enable signal line Scan1 on the substrate 11 partially overlaps with the orthographic projection of the fourth gate pattern 34 on the substrate 11, and the first enable signal line Scan1 is electrically connected to the fourth gate pattern 34. The orthographic projection of the first enable signal line Scan1 on the substrate 11 also partially overlaps with the orthographic projection of the semiconductor layer Poly on the substrate 11. The first enable signal line Scan1 and the fourth gate pattern 34 are arranged on different conductive layers 12, and the first enable signal line Scan1 is arranged on the first source-drain conductive layer SD1, which can avoid the first enable signal line Scan1 from blocking the semiconductor layer Poly during the doping process of the semiconductor layer Poly. Moreover, it is beneficial to increase the interval between the first enable signal line Scan1 and the semiconductor pattern 20, reduce the parasitic capacitance formed between the first enable signal line Scan1 and the semiconductor pattern 20, and further reduce the influence of the signal transmitted by the first enable signal line Scan1 on the semiconductor pattern 20.

[0117] The orthographic projection of the second enable signal line Scan2 on the substrate 11 partially overlaps with the orthographic projection of the fifth gate pattern 35 on the substrate 11, and the second enable signal line Scan2 is electrically connected to the fifth gate pattern 35. The orthographic projection of the first scan signal line GL1 on the substrate 11 partially overlaps with the orthographic projection of the sixth gate pattern 36 on the substrate 11, and the first scan signal line GL1 is electrically connected to the sixth gate pattern 36. The orthographic projection of the second scan signal line GL2 on the substrate 11 partially overlaps with the orthographic projection of the seventh gate pattern 37 on the substrate 11, and the second scan signal line GL2 is electrically connected to the seventh gate pattern 37. For similar reasons to the first light-emitting control signal line EM1 and the first enable signal line Scan1, the second enable signal line Scan2, the first scan signal line GL1, and the second scan signal line GL2 are arranged in the first source-drain conductive layer SD1, so that the second enable signal line Scan2, the first scan signal line GL1, and the second scan signal line GL2 can avoid shielding the semiconductor layer Poly during the doping process of the semiconductor layer Poly. Moreover, it is helpful to reduce the parasitic capacitance formed between the second enable signal line Scan2, the first scan signal line GL1, the second scan signal line GL2 and the semiconductor pattern 20 respectively, thereby reducing the influence of the signals transmitted by the second enable signal line Scan2, the first scan signal line GL1 and the second scan signal line GL2 on the semiconductor pattern 20.

[0118] The orthographic projection of the first adapter block 51 on the substrate 11 overlaps with the orthographic projections of the third connection area 210 and the third gate pattern 33 on the substrate 11, and the two ends of the first adapter block 51 are electrically connected to the third connection area 210 and the third gate pattern 33, respectively, so that the second electrode of the first reset transistor T4 and the second electrode of the compensation transistor T5 are electrically connected to the gate of the driving transistor T3.

[0119] See also Fig.13 and Fig.14 The orthographic projection of the second adapter block 52 on the substrate 11 overlaps with the orthographic projection of the first initialization voltage signal line Vinit1 and the eighth connection area (the first electrode of the first reset transistor T4) on the substrate 11, and the second adapter block 52 is electrically connected to the first initialization voltage signal line Vinit1 and the eighth connection area, respectively, so that the first initialization voltage signal line Vinit1 is electrically connected to the first electrode of the first reset transistor T4.

[0120] The orthographic projection of the third adapter block 53 on the substrate 11 overlaps with the orthographic projection of the second initialization voltage signal line Vinit1 and the sixth connection area (the first electrode of the second reset transistor T7) on the substrate 11, and the third adapter block 53 is electrically connected to the second initialization voltage signal line Vinit2 and the sixth connection area, so that the second initialization voltage signal line Vinit2 is electrically connected to the first electrode of the second reset transistor T7.

[0121] The orthographic projection of the fourth adapter block 54 on the substrate 11 partially overlaps with the orthographic projection of the fifth connection area on the substrate 11, and the fourth adapter block 54 is electrically connected to the fifth connection area 212, so that the fourth adapter block 54 is electrically connected to the second electrode of the second light-emitting control transistor T2 and the second electrode of the second reset transistor T7, and the fourth adapter block 54 is also used to be electrically connected to the light-emitting device.

[0122] The orthographic projection of the fifth adapter block 55 on the substrate 11 partially overlaps with the orthographic projection of the ninth connection area 216 on the substrate 11, and the fifth adapter block 55 is electrically connected to the ninth connection area 216, and the fifth adapter block 55 is electrically connected to the first electrode of the data writing transistor T6. The fifth adapter block 55 is also used to be electrically connected to the data line.

[0123] See also Fig.13 and Fig.14 , the orthographic projection of the first shielding portion 41 on the substrate 11 at least partially overlaps with the orthographic projection of the fourth connection area 211 on the substrate 11. Exemplarily, the orthographic projection of the first shielding portion 41 on the substrate 11 covers the orthographic projection of the fourth connection area 211 on the substrate 11. The first shielding portion 41 is used to shield the upper signal line (the signal line on the side of the second gate conductive layer Gate2 away from the substrate 11) from signal interference to the fourth connection area 211.

[0124] The orthographic projection of the second shielding portion 42 on the substrate 11 partially overlaps with the orthographic projection of the third connection area 210 on the substrate 11. For example, the orthographic projection of the second shielding portion 42 on the substrate 11 covers the orthographic projection of the third connection area 210 on the substrate 11. The orthographic projection of the second shielding portion 42 on the substrate 11 also partially overlaps with the orthographic projection of the first scan signal line GL1 and the second enable signal line Scan2 on the substrate 11. The second shielding portion 42 can reduce the signal interference of the first scan signal line GL1 and the second enable signal line Scan2 on the third connection area 210. In some embodiments, refer to Fig.15 , Fig.16A and Fig. 16B , the array substrate 100 further includes a second source-drain conductive layer SD2. The second source-drain conductive layer SD2 is disposed on a side of the first source-drain conductive layer SD1 away from the substrate 11, and includes a plurality of data lines DL extending along the first direction Y, a plurality of first voltage signal connection lines VDD', a plurality of first connection lines 61, a plurality of second connection lines 62, and a plurality of third connection lines 63. Among them, Fig.16A It is a simplified view of the array substrate, used to more clearly show the connection relationship between the multiple first connection lines 61, the multiple second connection lines 62, the multiple third connection lines 63 and the first initialization voltage signal line Vinit1, the multiple second initialization voltage signal lines Vinit2 and the second voltage signal bus VSS. Fig. 16B This is a structural diagram of the area where nine adjacent pixel circuits in a row are located in the array substrate.

[0125] Each of the plurality of data lines DL is electrically connected to a column of pixel circuits 110. Each of the plurality of first voltage signal connection lines VDD' is electrically connected to the plurality of first voltage signal lines VDD on the first source-drain conductive layer SD1, so as to connect the plurality of first voltage signal lines VDD into a mesh structure, thereby reducing the resistance of the plurality of first voltage signal lines VDD. For example, Fig.15 As shown, a plurality of data lines DL and a plurality of first voltage signal connection lines VDD′ are alternately arranged along the second direction X.

[0126] like Fig.16A and Fig. 16B As shown, the multiple columns of pixel circuits 110 can be divided into multiple groups, each group includes multiple columns of pixel circuits 110, and the multiple pixel circuits 110 located in the same row in a group correspond to the multiple sub-pixels of a pixel unit. For example, a pixel unit includes a red sub-pixel, a blue sub-pixel, and a green sub-pixel. A group includes three columns of pixel circuits 110, and the three pixel circuits located in the same row in a group correspond to the red sub-pixel, the blue sub-pixel, and the green sub-pixel of a pixel unit.

[0127] The first connection line 61, the second connection line 62, and the third connection line 63 are respectively arranged between two adjacent groups of pixel circuits 110, and only one of the first connection line 61, the second connection line 62, and the third connection line 63 is arranged between each two adjacent groups of pixel circuits 110. In the embodiment of the present disclosure, there is no specific limitation on the arrangement order and arrangement density of the first connection line 61, the second connection line 62, and the third connection line 63. Exemplarily, the first connection line 61, the second connection line 62, and the third connection line 63 are periodically arranged along the second direction.

[0128] Each first connection line 61 is electrically connected to a plurality of first initialization voltage signal lines Vinit1, and is used to connect the plurality of first initialization voltage signal lines Vinit1 into a mesh structure to reduce the resistance of the plurality of first initialization voltage signal lines Vinit1. Each second connection line 62 is electrically connected to a plurality of second initialization voltage signal lines Vinit2, and is used to connect the plurality of second initialization voltage signal lines Vinit2 into a mesh structure to reduce the resistance of the plurality of second initialization voltage signal lines Vinit2.

[0129] The peripheral area BB also includes a second voltage signal bus VSS, which is used to electrically connect to the cathode layer. Both ends of each third connection line 63 extend to the peripheral area BB and are electrically connected to the second voltage signal bus VSS. The third connection line 63 is connected in parallel with the cathode layer, which is beneficial to reducing the resistance on the cathode layer.

[0130] For example, Fig.15 As shown, the plurality of second adapter blocks 52 include a second target adapter block 52A, the orthographic projection of the second target adapter block 52A on the substrate partially overlaps with the orthographic projection of the first connection line 61 on the substrate, and the second target adapter block 52A is electrically connected to the first connection line 61. As described above, the second adapter block 52 is also electrically connected to the first initialization voltage signal line Vinit1 and the first electrode (the eighth connection area) of the first reset transistor. Based on this, the second target adapter block 52A can electrically connect the first connection line 61 to the first initialization voltage signal line Vinit1, so that the first connection line 61 is connected to the first initialization voltage signal line Vinit1 to form a mesh structure. It can be understood that the specific structure of the pixel circuit 110 can also adopt other pixel circuits. For example, Fig.17 As shown, the pixel circuit 110 may further include a reset transistor T8, the gate of the reset transistor T8 is electrically connected to the second scanning signal line GL2, the first electrode is electrically connected to the reference voltage signal line Vref, and the second electrode is electrically connected to the first electrode of the driving transistor T3. Fig.18 As shown, the second electrode of the first reset transistor T5 may also be electrically connected to the second electrode of the driving transistor T3. The embodiments of the present disclosure do not limit the specific structure of the pixel circuit 110, as long as the same technical concept is applied.

[0131] In some embodiments, the second source-drain conductive layer SD2 further includes a plurality of seventh adapter blocks 64, and the seventh adapter blocks 64 are used to connect the pixel circuit 110 and the light-emitting device 200. Fig.15 As shown, the shapes of the plurality of seventh adapter blocks 64 may be different to connect the light emitting devices 200 at different positions. The orthographic projection of the seventh adapter block 64 on the substrate 11 partially overlaps with the orthographic projection of the fourth adapter block 54 on the substrate 11, and the seventh adapter block 64 is electrically connected to the fourth adapter block 54, and further electrically connected to the drain of the second light emitting control transistor T2 of the pixel circuit. The seventh adapter block 64 is also used to be electrically connected to the anode of the light emitting device, and further electrically connect the light emitting device to the pixel circuit.

[0132] See also Fig.19 Some embodiments of the present disclosure further provide a method for driving a pixel circuit 110, which can be used to drive the pixel circuit 110 described in any of the above embodiments. Fig. 9 The pixel circuit 110 shown in the figure is described as an example, and can also be applied to other pixel circuits (such as Fig.17 and Fig.18 The pixel circuit shown in the figure) can be modified by applying the same technical idea.

[0133] The first light emitting control signal line EM1 is configured to transmit a first pulse width modulation signal PWM1, and the second light emitting control signal line EM2 is configured to transmit a second pulse width modulation signal PWM2.

[0134] A display cycle includes a blank phase B and a light-emitting phase D. Fig.19 As shown, the driving method includes:

[0135] In the light-emitting stage D, the first pulse width modulation signal PWM1 has a first working level period K1, and the second pulse width modulation signal PWM2 has a second working level period K2. The first working level period K1 refers to a period in the first pulse width modulation signal PWM1 for driving the first light-emitting control transistor T1 to turn on, and the second working level period K2 refers to a period in the second pulse width modulation signal PWM2 for driving the second light-emitting control transistor T2 to turn on.

[0136] The first working level period K1 is different from the second working level period K2. For example, the start time (start-up time) of the first working level period K1 is different from the start time of the second working level period K2, and / or the end time (end time) of the first working level period K1 is different from the end time of the second working level period K2. In this way, the control flexibility of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 can be increased, which is beneficial to improving the PWM dimming accuracy of the pixel circuit 110.

[0137] The first working level period K1 partially overlaps with the second working level period K2. When the first working level period K1 overlaps with the second working level period K2, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on at the same time, and the driving current generated by the driving transistor T3 can be transmitted to the light-emitting device 200 to drive the light-emitting device to emit light. In the embodiment of the present disclosure, the length of time that the first working level period K1 and the second working level period K2 overlap with each other can be controlled by controlling the start and end time of the first working level period K1 and the second working level period K2, thereby improving the dimming accuracy of the pixel circuit 110.

[0138] In some embodiments, the portion where the first working level period K1 and the second working level period K2 overlap is the light-emitting period K3, the duration of the first working level period K1 is longer than the duration of the light-emitting period K3, and the duration of the second working level period K2 is longer than the duration of the light-emitting period K3. In this way, the minimum light-emitting duration of each light-emitting stage in PWM dimming can be shortened, thereby reducing the total light-emitting duration of the light-emitting device in a display cycle, which is beneficial to improving the dimming accuracy of the pixel circuit 110.

[0139] In some embodiments, see Fig.19 The amplitude (high and low level voltage values), frequency and duty cycle of the first pulse width modulation signal PWM1 are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal PWM2. This helps to reduce the control difficulty of the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2.

[0140] The array substrate further includes a shift register located in the peripheral area BB, and the shift register includes a plurality of cascaded shift register circuits. The first light emitting control signal line EM1 and the second light emitting control signal line EM2 can be electrically connected to the same shift register or to different shift registers.

[0141] Exemplarily, when the amplitude, frequency and duty cycle of the first pulse width modulation signal PWM1 are different from at least one of the amplitude, frequency and duty cycle of the second pulse width modulation signal PWM2, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are electrically connected to two different shift registers respectively.

[0142] Exemplarily, when the amplitude, frequency and duty cycle of the first pulse width modulation signal PWM1 are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal PWM2, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 can be electrically connected to the same shift register or to different shift registers.

[0143] like Fig. 20 As shown, in the embodiment of the present disclosure, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are electrically connected to the same shift register as an example for description, which is conducive to simplifying the circuit structure of the array substrate 100, reducing the width of the peripheral area BB, and further realizing a narrow frame of the display panel 1100. In the case where the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are electrically connected to the same shift register (EM-GOA), the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 electrically connected to the same row of pixel circuits 110 are electrically connected to shift register circuits of different stages, respectively.

[0144] Exemplarily, each row of pixel circuits 110 is electrically connected to a first reflection control signal line EM1 and a second reflection control signal line EM2. The array substrate 100 includes a first shift register 400, which includes a plurality of first shift register circuits EM-GOA cascaded in sequence.

[0145] In the case where the start and end time of the first working level period K1 are respectively delayed (latter) than the start and end time of the second working level period K2, as Fig. 20 As shown, the first light emitting control signal line EM1 electrically connected to the N-th row pixel circuit 110 is electrically connected to the N-th stage first shift register circuit EM-GOA-N. The second light emitting control signal line EM2 electrically connected to the N-th row pixel circuit is electrically connected to the (N+M)-th stage first shift register circuit EM-GOA-(N+M).

[0146] Alternatively, when the start and end time of the first working level period K1 are respectively ahead of (behind) the start and end time of the second working level period K2, the second light emitting control signal line EM2 electrically connected to the pixel circuit of the Nth row is electrically connected to the first shift register circuit EM-GOA-N of the Nth stage. The first light emitting control signal line EM1 electrically connected to the pixel circuit of the Nth row is electrically connected to the first shift register circuit EM-GOA-(N+M) of the (N+M)th stage (not shown in the figure).

[0147] Among them, the amplitude, frequency and duty cycle of the PWM signals output by the Nth level first shift register circuit EM-GOA-N and the (N+M)th level first shift register circuit EM-GOA-(N+M) are correspondingly equal, and the start and end time difference is MH (M line scanning time).

[0148] In some embodiments, M≤4. Exemplarily, M can be 1, 2, 3 or 4, so that, on the one hand, it is helpful to reduce the number of first shift register circuits EM-GOA and reduce the space of the peripheral area BB occupied by the first shift register 400. On the other hand, the interval between the second light-emitting control signal line EM2 and the (N+M)-th level first shift register circuit EM-GOA-(N+M) along the first direction Y can be reduced, which is helpful to reduce the connection difficulty between the second light-emitting control signal line EM2 and the (N+M)-th level first shift register circuit EM-GOA-(N+M). It can be understood that the value of M in the embodiments of the present disclosure is not limited to this, and any other reasonable value can also be considered, as long as the same technical ideas are applied and the driving timing requirements of the pixel circuit are met.

[0149] In some embodiments, the first enable signal line Scan1 and the second enable signal line Scan2 may be electrically connected to the same shift register, or to different shift registers.

[0150] Exemplarily, the first enable signal line Scan1 and the second enable signal line Scan2 are electrically connected to different shift registers, so that the timing of the first enable signal line Scan1 and the second enable signal line Scan2 can be better adjusted, which is beneficial to improving the control accuracy of the pixel circuit.

[0151] For example, Fig.21As shown, the first enable signal line Scan1 and the second enable signal line Scan2 are electrically connected to the same shift register. In this way, it is helpful to simplify the circuit structure of the array substrate, reduce the width of the peripheral area BB, and thus achieve a narrow frame of the display panel. In the case where the first enable signal line Scan1 and the second enable signal line Scan2 are electrically connected to the same shift register, the first enable signal line Scan1 and the second enable signal line Scan2 electrically connected to the same row of pixel circuits 110 are electrically connected to shift register circuits of different stages respectively.

[0152] like Fig.21 As shown, in the embodiment of the present disclosure, description is given by taking the example that the first enable signal line Scan1 and the second enable signal line Scan2 are electrically connected to the same shift register.

[0153] Exemplarily, each row of pixel circuits 110 is connected to a first enable signal line Scan1 and a second enable signal line Scan2. The array substrate 100 includes a second shift register 500, and the second shift register 500 includes a plurality of second shift register circuits Scan-GOA that are cascaded in sequence.

[0154] like Fig.21 As shown, the first enable signal line Scan1 electrically connected to the Nth row pixel circuit 110 is electrically connected to the (NQ)th stage second shift register circuit Scan-GOA-(N-2). The second enable signal line Scan2 electrically connected to the Nth row pixel circuit 110 is electrically connected to the Nth stage second shift register circuit Scan-GOA-N.

[0155] Alternatively, the first enable signal line Scan1 electrically connected to the pixel circuit of the Nth row is electrically connected to the second shift register circuit Scan-GOA-N of the Nth stage. The second enable signal line Scan2 electrically connected to the pixel circuit 110 of the Nth row is electrically connected to the second shift register circuit Scan-GOA-(N+Q) of the (N+Q)th stage.

[0156] Among them, the waveforms of the enable signals output by the Nth-stage second shift register circuit Scan-GOA-N and the (N+Q)th-stage second shift register circuit Scan-GOA-(N+Q) are the same and have a certain phase difference.

[0157] In some embodiments, 3≤Q≤9. Exemplarily, Q can be 3, 4, 5, 6, 7, 8 or 9. On the one hand, it is beneficial to reduce the number of second shift register circuits Scan-GOA and reduce the space of the peripheral area BB occupied by the second shift register 500. On the other hand, the interval between the second enable signal line Scan2 and the (N+Q)th level second shift register circuit Scan-GOA-(N+Q) along the first direction Y can be reduced, which is beneficial to reduce the connection difficulty between the second enable signal line Scan2 and the (N+Q)th level second shift register circuit Scan-GOA-(N+Q). It can be understood that the value of Q in the embodiments of the present disclosure is not limited to this, and any other reasonable value can also be considered, as long as the same technical ideas are applied and the driving timing requirements of the pixel circuit are met.

[0158] In some embodiments, see Fig. 22 In the blank phase B, at least one of the first light emission control transistor T1 and the second light emission control transistor T2 is turned off (not conducting), and the light emitting device 200 does not emit light.

[0159] Exemplarily, the start and end time of the first working level period K1 is delayed (latter) than the start and end time of the second working level period K2. The blank phase B includes a first sub-segment B11, a second sub-segment B12 and a third sub-segment B13.

[0160] In the first sub-segment B11, the first pulse width modulation signal PWM1 transmitted by the first light-emitting control signal line EM1 is at the working level (low level), and the second pulse width modulation signal transmitted by the second light-emitting control signal line EM2 is at the cut-off level (high level). At this time, the first light-emitting control transistor T1 is turned on, and the second light-emitting control transistor T2 is turned off. In the second sub-segment B12, the first pulse width modulation signal PWM1 transmitted by the first light-emitting control signal line EM1 and the second pulse width modulation signal PWM2 transmitted by the second light-emitting control signal line EM2 are both at the cut-off level, and the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are both turned off. In the third sub-segment B13, the first pulse width modulation signal PWM1 transmitted by the first light-emitting control signal line EM1 is at the cut-off level, and the second pulse width modulation signal is at the working level. At this time, the first light-emitting control transistor T1 is turned off, and the second light-emitting control transistor T2 is turned on.

[0161] In some embodiments, Fig.21 As shown, the blank phase B includes a first initialization phase B21, a second initialization phase B22 and a data writing phase B23. The driving method further includes:

[0162] In the first initialization stage B21, the first light emission control transistor T1 is turned on for at least part of the time period, and the second light emission control transistor T2 is turned off. The first reset transistor T4 is turned on under the control of the first enable signal from the first enable signal line Scan1, and transmits the first initialization voltage signal from the first initialization voltage signal line Vinit1 to the gate of the driving transistor T3, so as to perform voltage initialization on the gate of the driving transistor T3.

[0163] In the second initialization stage B22, the first reset transistor T4 remains turned on, and the compensation transistor T5 is turned on under the control of the second enable signal from the second enable signal line Scan2, and the first initialization voltage signal from the gate of the driving transistor T3 is transmitted to the second electrode of the driving transistor T3 to perform voltage initialization on the second electrode of the driving transistor T3.

[0164] In the data writing stage B23, the first reset transistor T4 is turned off, the compensation transistor T5 remains turned on, and the data writing transistor T5 is turned on under the control of the first scanning signal from the first scanning signal line GL1, and the data signal from the data line DL is transmitted to the first electrode of the driving transistor T3. The data signal is sequentially transmitted through the driving transistor T3 and the compensation transistor T5 to transmit the compensated data signal (Vdata+Vth) to the gate of the driving transistor T3.

[0165] The first initialization stage B21 is partially located in the first sub-segment B11 and partially located in the second sub-segment B12. The second initialization stage B22 is located in the second sub-segment B12 to prevent the first initialization voltage signal from being transmitted to the anode of the light-emitting device 200 and to prevent signal interference to the anode of the light-emitting device 200. The data writing stage B23 is located in the second sub-segment B12, that is, in the data writing stage B23, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 remain turned off, so that the first voltage signal line VDD and the light-emitting device 200 can be prevented from interfering with the written data signal.

[0166] In the first initialization stage B21, the gate of the driving transistor T3 is initialized to the Vinit1 voltage, and the first light-emitting control transistor T1 is turned on for at least part of the time period, the first electrode of the driving transistor T3 is the VDD voltage, and a large voltage difference (Vinit1-VDD) is formed between the gate and the source of the driving transistor T3, and the voltage difference (Vinit1-VDD) is greater than the voltage difference between the gate and the source of the driving transistor T3 in the light-emitting stage D of the previous display cycle. In this way, in the first initialization stage B21 of each frame, the bias state of the driving transistor T3 is the same, and is (Vinit1-VDD).

[0167] In the second initialization stage B22, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned off at the same time, and the first reset transistor T4 and the compensation transistor T5 are turned on, and the voltage of the first initialization signal line Vinit1 is transmitted to the gate and the second electrode (drain) of the driving transistor T3. At this time, the first electrode of the driving transistor T3 has a higher voltage (the first voltage VDD maintained in the first initialization stage B21), and the first electrode of the driving transistor T3 acts as a source to leak to the second electrode of the driving transistor T3, and finally remains at Vinit1-Vth. In each display cycle, and before the data writing stage B23, the voltages of the gate, the first electrode and the second electrode of the driving transistor T3 are independent of the voltage of the previous display cycle, which can avoid the problem of brightness difference when grayscale switching, thereby improving the problem of afterimage on the display panel. In addition, by increasing the duration of the first initialization stage B21 and the second initialization stage B22, the first initialization voltage Vinit1 can be more fully written into the gate of the driving transistor T3 and the second electrode of the driving transistor T3, and the first electrode voltage of the driving transistor T3 can be fully changed to Vinit1-Vth, thereby enhancing the effect of improving the afterimage.

[0168] It should be noted that the driving transistor T3 is in the grayscale A screen for a long time, and the Vgs voltage of the driving transistor T3 is in the gate voltage -VDD of the A grayscale for a long time. The driving transistor T3 is in the grayscale C screen for a long time, and the Vgs voltage of the driving transistor T3 is in the gate voltage -VDD of the C grayscale for a long time. The degree of characteristic deviation of the driving transistor under the above-mentioned A and C grayscales is different. When switching from A grayscale and C grayscale to B grayscale respectively, the driving transistor T3 is re-shifted by the new Vgs voltage. In this process, the brightness of grayscale B gradually changes and tends to be stable. The industry usually uses the brightness contrast of the two switching screens, grayscale A switching to grayscale B and grayscale C switching to grayscale B, to characterize the image quality, which is the afterimage referred to above.

[0169] In some embodiments, Fig. 22 As shown, in the second initialization stage B22 and the data writing stage B23, the second reset transistor T7 is turned on under the control of the second scanning signal from the second scanning signal line GL2, and the second initialization voltage signal from the second initialization voltage signal line Vinit2 is transmitted to the second electrode of the second light-emitting control transistor T2, that is, the second initialization voltage signal is transmitted to the anode of the light-emitting device 200, so as to initialize the anode of the light-emitting device.

[0170] In some embodiments, Fig.23 and Fig.24 As shown, the blank phase B may further include a bias phase B24 located after the data writing phase B23.

[0171] In the bias phase B24, the first light-emitting control signal line EM1 transmits a cut-off level signal, and the first light-emitting control transistor T1 is cut off. The second light-emitting control signal line EM2 transmits a working level signal, and the second light-emitting control transistor T2 is turned on. The second reset transistor T7 is turned on under the control of the second scanning signal of the second scanning signal line GL2, and transmits the second initialization voltage signal from the second initialization voltage signal terminal Vinit2 to the second electrode of the second light-emitting control transistor T2 and the first electrode of the second light-emitting control transistor T2 (the second electrode of the driving transistor) in sequence.

[0172] In the bias phase B24, the first light-emitting control transistor T1, the first reset transistor T4, the compensation transistor T5 and the data writing transistor T6 are turned off, and the second reset transistor T7 and the second light-emitting control transistor T2 are turned on at the same time, and the voltage of the anode of the light-emitting device and the second electrode of the driving transistor T3 are reset by the voltage of the second initialization voltage signal line Vinit2, and the voltage of the second electrode of the driving transistor T3 is not affected by the previously written data signal. In the case where the light-emitting phase D includes multiple working level periods (or the case where the PWM signal adopts multi-pulse dimming), before the first light-emitting control transistor T1 is turned on each time, the voltage of the second electrode of the driving transistor T3 is the same and is not affected by the written data signal, which can avoid flickering of the light-emitting device.

[0173] It should be noted that in the data writing stage B23, the second pole of the driving transistor T3 will write the compensated data signal, and the compensated data signal of each display cycle may be different. In this way, if the voltage of the second pole of the driving transistor T3 is not reset, and the residual voltage of the second pole of the driving transistor T3 will affect the size of the driving current in the light-emitting stage D, and the residual voltage of the second pole of the driving transistor T3 in each display cycle may have different effects on the driving current, therefore, it may cause visual stroboscopic, which is the flicker mentioned above. The driving method of the pixel circuit provided in the present application resets the voltage of the second pole of the driving transistor T3 in the bias stage B24, thereby reducing or even avoiding the residual voltage of the driving transistor T3, thereby reducing the risk of flickering in the light-emitting device.

[0174] In some other embodiments, some driving methods of pixel driving circuits are also provided. Fig.25 , the first working level period K1 can be located within the second working level period K2, and the start and end times of the first working level period K1 are spaced from the start and end times of the second working level period K2. Fig.26, the second working level period K2 is located within the first working level period K1, and the start and end times of the first working level period K1 are spaced from the start and end times of the second working level period K2. Fig. 27 , the amplitude, frequency and duty cycle of the first pulse width modulation signal PWM1 are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal PWM2. And the start and end time of the first working level period K1 are respectively ahead of the start and end time of the second working level period K2. The embodiments of the present disclosure will not be described in detail.

[0175] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: It includes a substrate and a plurality of pixel circuits disposed on the substrate, wherein the plurality of pixel circuits are arranged in a plurality of rows and columns; The pixel circuit includes a first light emission control transistor and a second light emission control transistor; The array substrate further includes: a first light emission control signal line electrically connected to the gate of the first light emission control transistor; a second light emission control signal line electrically connected to the gate of the second light emission control transistor; The array substrate also includes multiple conductive layers, the first light-emitting control signal line and the second light-emitting control signal line are electrically insulated, the first light-emitting control signal line and the second light-emitting control signal line are located in different conductive layers, and the orthographic projections of the first light-emitting control signal line and the second light-emitting control signal line on the substrate do not overlap.

2. The array substrate according to claim 1, characterized in that: The plurality of conductive layers include: A first gate conductive layer, comprising a first gate pattern and the second light emission control signal line; the first gate pattern forms a gate of the first light emission control transistor; A first source-drain conductive layer is arranged on a side of the first gate conductive layer away from the substrate, and includes the first light-emitting control signal line. The orthographic projection of the first light-emitting control signal line on the substrate partially overlaps with the orthographic projection of the first gate pattern on the substrate, and the first light-emitting control signal line is electrically connected to the first gate pattern.

3. The array substrate according to claim 2, characterized in that: The pixel circuit also includes a driving transistor; The array substrate further includes a semiconductor layer, which is disposed between the substrate and the first gate conductive layer; the semiconductor layer includes a first channel region of the first light emission control transistor, a second channel region of the second light emission control transistor, a third channel region of the driving transistor, a first connection region and a second connection region; the first connection region and the second connection region are respectively located on two opposite sides of the third channel region, and the first connection region is respectively connected to the third channel region and the second channel region, and the second connection region is respectively connected to the third channel region and the first channel region; Among them, the orthographic projection of the first gate pattern on the substrate partially overlaps with the orthographic projection of the first channel region on the substrate, and does not overlap with the orthographic projection of the first connection region on the substrate; the orthographic projection of the second light-emitting control signal line on the substrate partially overlaps with the orthographic projection of the second channel region on the substrate.

4. The array substrate according to claim 3, characterized in that: The pixel circuit further includes a first reset transistor; The semiconductor layer further includes a third connection region and a fourth channel region of the first reset transistor; The first gate conductive layer further includes a fourth gate pattern, and an orthographic projection of the fourth gate pattern on the substrate partially overlaps with an orthographic projection of the fourth channel region on the substrate; The first source-drain conductive layer further includes a first enable signal line and a first transfer block; The orthographic projection of the first enable signal line on the substrate overlaps with the orthographic projection of the fourth gate pattern on the substrate, and the first enable signal line is electrically connected to the fourth gate pattern; the first adapter block is electrically connected to the third connection area and the gate of the driving transistor; The array substrate further includes a second gate conductive layer, which is disposed between the first gate conductive layer and the first source-drain conductive layer and includes a first initialization voltage signal line, which is electrically connected to a first electrode of the first reset transistor.

5. The array substrate according to claim 4, characterized in that: The pixel circuit further includes a compensation transistor; The semiconductor layer further includes a fifth channel region of the compensation transistor, one side of the fifth channel region is connected to the first connection region, and the other side of the fifth channel region is connected to the third connection region; The first gate conductive layer further includes a fifth gate pattern, and an orthographic projection of the fifth gate pattern on the substrate partially overlaps with an orthographic projection of the fifth channel region on the substrate; The first source-drain conductive layer further includes a second enable signal line, an orthographic projection of the second enable signal line on the substrate partially overlaps with an orthographic projection of the fifth gate pattern on the substrate, and the second enable signal line is electrically connected to the fifth gate pattern.

6. The array substrate according to claim 5, characterized in that: The compensation transistor is a dual-gate transistor, and the fifth channel region includes a first sub-region and a second sub-region which are spaced apart from each other; The semiconductor layer further includes a fourth connection region, wherein the fourth connection region is located between the first sub-region and the second sub-region and is connected to the first sub-region and the second sub-region; The second gate conductive layer further includes a first blocking portion, and an orthographic projection of the first blocking portion on the substrate at least partially overlaps with an orthographic projection of the fourth connection region on the substrate.

7. The array substrate according to claim 4, characterized in that: The second gate conductive layer further includes a second shielding portion, and the orthographic projections of the second shielding portion, the third connection region, and the second enable signal line on the substrate at least partially overlap.

8. The array substrate according to any one of claims 4 to 7, characterized in that: The pixel circuit also includes a data writing transistor; The semiconductor layer further includes a sixth channel region of the data writing transistor, and along a first direction, the fifth channel region and the sixth channel region are staggered, and the sixth channel region is connected to the second connection region; the first direction is a column direction in which the plurality of pixel circuits are arranged; The first gate conductive layer further includes a sixth gate pattern, and an orthographic projection of the sixth gate pattern on the substrate partially overlaps with an orthographic projection of the sixth channel region on the substrate; The first source-drain conductive layer further includes a first scan signal line, an orthographic projection of the first scan signal line on the substrate partially overlaps with an orthographic projection of the sixth gate pattern on the substrate, and the first scan signal line is electrically connected to the sixth gate pattern.

9. The array substrate according to any one of claims 3 to 7, characterized in that: The pixel circuit further includes a second reset transistor; The semiconductor layer further includes a seventh channel region of the second reset transistor; The first gate conductive layer further includes a seventh gate pattern, and an orthographic projection of the seventh gate pattern on the substrate partially overlaps with an orthographic projection of the seventh channel region on the substrate; The second gate conductive layer further comprises a second initialization voltage signal line, and the second initialization voltage signal line is electrically connected to the first electrode of the second reset transistor; The first source-drain conductive layer further includes a second scan signal line, an orthographic projection of the second scan signal line on the substrate partially overlaps with an orthographic projection of the seventh gate pattern on the substrate, and the second scan signal line is electrically connected to the seventh gate pattern.

10. The array substrate according to any one of claims 3 to 7, characterized in that: The array substrate further includes: A light shielding layer is disposed between the substrate and the semiconductor layer, and an orthographic projection of the light shielding layer on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer on the substrate.

11. The array substrate according to any one of claims 1 to 7, characterized in that: The array substrate comprises a display area and a peripheral area surrounding the display area; The array substrate comprises a plurality of first initialization voltage signal lines, a plurality of second initialization voltage signal lines and a second voltage signal bus; a row of pixel circuits is electrically connected to a first initialization voltage signal line and a second initialization voltage signal line, and the second voltage signal bus is arranged in the peripheral area and at least partially surrounds the display area; The array substrate also includes a second source-drain conductive layer, which is arranged on a side of the first source-drain conductive layer away from the substrate, and includes a plurality of first connecting lines, a plurality of second connecting lines and a plurality of third connecting lines extending along a first direction; each first connecting line is electrically connected to the plurality of first initialization voltage signal lines, each second connecting line is electrically connected to the plurality of second initialization voltage signal lines, and each third connecting line extends to the peripheral area and is electrically connected to the second voltage signal bus.

12. A method for driving a pixel circuit, characterized in that: The pixel circuit includes a driving transistor, a first light-emitting control transistor and a second light-emitting control transistor; a gate of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, a first electrode is electrically connected to a first voltage signal line, and a second electrode is electrically connected to a first electrode of the driving transistor; a gate of the second light-emitting control transistor is electrically connected to a second light-emitting control signal line, a first electrode is electrically connected to a second electrode of the driving transistor, and a second electrode is electrically connected to a light-emitting device; wherein the first light-emitting control signal line is configured to transmit a first pulse width modulation signal, and the second light-emitting control signal line is configured to transmit a second pulse width modulation signal; A display cycle includes a light-emitting phase, and the driving method includes: In the light emitting stage, the first pulse width modulation signal has a first working level period, and the second pulse width modulation signal has a second working level period. The first working level period is different from the second working level period, and the first working level period partially overlaps with the second working level period.

13. The driving method according to claim 12, characterized in that: The amplitude, frequency and duty cycle of the first pulse width modulation signal are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal; The start and end times of the first working level period are both later than the start and end times of the second working level period.

14. The driving method according to claim 13, characterized in that: The pixel circuit further includes a first reset transistor, a second reset transistor, a data write transistor and a compensation transistor; the gate of the first reset transistor is electrically connected to the first enable signal line, the first electrode is electrically connected to the first initialization voltage signal line, and the second electrode is electrically connected to the gate of the driving transistor; the gate of the second reset transistor is electrically connected to the second scanning signal line, the first electrode is electrically connected to the second initialization voltage signal line, and the second electrode is electrically connected to the second electrode of the second light emitting control transistor; the gate of the data write transistor is electrically connected to the first scanning signal line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the first electrode of the driving transistor; the gate of the compensation transistor is electrically connected to the second enable signal line, the first electrode is electrically connected to the second electrode of the driving transistor, and the second electrode is electrically connected to the gate of the driving transistor; A display cycle further includes a blank period, during which at least one of the first light emission control transistor and the second light emission control transistor is turned off; The blank phase includes a first initialization phase, a second initialization phase and a data writing phase; The driving method further includes: In the first initialization stage, the first reset transistor is turned on under the control of the first enable signal from the first enable signal line, and transmits the first initialization voltage signal from the first initialization voltage signal line to the gate of the driving transistor; In the second initialization stage, the first reset transistor remains turned on, and the compensation transistor is turned on under the control of the second enable signal from the second enable signal line, and transmits the first initialization voltage signal to the second electrode of the driving transistor; In the data writing phase, the compensation transistor remains turned on, and the data writing transistor is turned on under the control of the first scanning signal from the first scanning signal line to transmit the data signal from the data line to the first electrode of the driving transistor.

15. The driving method according to claim 14, characterized in that: The blank phase also includes a bias phase after the data writing phase; the driving method also includes: In the bias stage, the first light-emitting control transistor is turned off, the second light-emitting control transistor is turned on, and the second reset transistor is turned on under the control of the second scanning signal of the second scanning signal line, and the second initialization voltage signal from the second initialization voltage signal end is transmitted to the second electrode of the second light-emitting control transistor and the first electrode of the driving transistor in sequence.

16. The driving method according to claim 14 or 15, characterized in that: In the second initialization phase and the data writing phase, the second reset transistor is turned on under the control of the second scan signal from the second scan signal line, and transmits the second initialization voltage signal from the second initialization voltage signal line to the second electrode of the second light emitting control transistor.

17. The driving method according to claim 12, characterized in that: The first working level period is within the second working level period, and the start and end times of the first working level period are spaced apart from the start and end times of the second working level period; Alternatively, the second working level period is located within the first working level period, and the start and end times of the first working level period are spaced apart from the start and end times of the second working level period.

18. The driving method according to claim 12, characterized in that: The amplitude, frequency and duty cycle of the first pulse width modulation signal are respectively the same as the amplitude, frequency and duty cycle of the second pulse width modulation signal; The start and end times of the first working level period are respectively ahead of the start and end times of the second working level period.

19. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 11; A plurality of light emitting devices are arranged on the array substrate, and each light emitting device is electrically connected to a pixel circuit.

20. A display device, characterized in that: include: The display panel according to claim 19, The driving circuit board is electrically connected to the display panel and is configured to transmit a control signal to the display panel.

Images