latches, memory, sequential circuits and chips

Abstract

This application discloses a latch, a memory, a timing circuit, and a chip, belonging to the field of storage technology. The latch includes a latching circuit and a blocking circuit. The latching circuit has a first output terminal, a second output terminal, a first power supply terminal, and a second power supply terminal. The high level of the output signal at the first output terminal is provided by the first power supply terminal, and the high level of the output signal at the second output terminal is provided by the second power supply terminal. The blocking circuit blocks the connection between the first power supply terminal and the power supply after the output signal at the first output terminal changes from high to low, and blocks the connection between the second power supply terminal and the power supply after the output signal at the second output terminal changes from high to low. Using this application can reduce the power consumption of the latch.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a latch, memory, timing circuit and chip. Background Technology

[0002] A latch is a memory cell circuit that is sensitive to pulse signals. It can change its storage state under the action of a specific pulse signal and maintain the changed storage state until the next specific pulse signal is applied. Summary of the Invention

[0003] This application provides a latch, a memory, a timing circuit, and a chip, which can reduce the power consumption of the latch. The technical solution is as follows:

[0004] In a first aspect, a latch is provided, the latch including a latching circuit and a blocking circuit, wherein the latching circuit has a first output terminal, a second output terminal, a first power supply terminal and a second power supply terminal, the high level of the output signal of the first output terminal is provided by the first power supply terminal, and the high level of the output signal of the second output terminal is provided by the second power supply terminal.

[0005] The blocking circuit is used to: block the connection between the first power supply terminal and the power supply after the output signal at the first output terminal changes from a high level to a low level; and block the connection between the second power supply terminal and the power supply after the output signal at the second output terminal changes from a high level to a low level.

[0006] Optionally, the latching circuit has a first input terminal and a second input terminal, and the blocking circuit includes a first switching circuit and a second switching circuit;

[0007] The first switching circuit is connected to the first power supply terminal, the first input terminal, the power supply, and the clock signal source, respectively; the second switching circuit is connected to the second power supply terminal, the second input terminal, the power supply, and the clock signal source, respectively.

[0008] The first switching circuit is used to: block the connection between the first power supply terminal and the power supply after the input signal of the first input terminal and the clock signal source drives the output signal of the first output terminal to a low level;

[0009] The second switching circuit is used to: block the connection between the second power supply terminal and the power supply after the input signal of the second input terminal and the clock signal source drives the output signal of the second output terminal to a low level.

[0010] Optionally, the first switching circuit includes a first transistor and a second transistor;

[0011] The gate of the first transistor is connected to the first input terminal, and the gate of the second transistor is connected to the clock signal source;

[0012] The first and second terminals of the first transistor are respectively connected to the first power supply terminal and the power supply, and the first and second terminals of the second transistor are respectively connected to the first power supply terminal and the power supply.

[0013] Optionally, the second switching circuit includes a third transistor and a fourth transistor;

[0014] The gate of the third transistor is connected to the second input terminal, and the gate of the fourth transistor is connected to the clock signal source.

[0015] The first and second terminals of the third transistor are connected to the second power supply terminal and the power supply, respectively, and the first and second terminals of the fourth transistor are connected to the second power supply terminal and the power supply, respectively.

[0016] Optionally, the latching circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0017] The gate of the fifth transistor is connected to the first input terminal, the first terminal of the fifth transistor is connected to the first output terminal, and the second terminal of the fifth transistor is connected to the first terminal of the seventh transistor.

[0018] The gate of the sixth transistor is connected to the second input terminal, the first terminal of the sixth transistor is connected to the second output terminal, and the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor.

[0019] The gate of the seventh transistor is connected to a clock signal source, and the second terminal of the seventh transistor is grounded.

[0020] Optionally, the latching circuit further includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

[0021] The first terminal of the eighth transistor is connected to the first power supply terminal, the second terminal of the eighth transistor is connected to the first output terminal, and the gate of the eighth transistor is connected to the second output terminal.

[0022] The first terminal of the ninth transistor is connected to the second power supply terminal, the second terminal of the ninth transistor is connected to the second output terminal, and the gate of the ninth transistor is connected to the first output terminal.

[0023] The first terminal of the tenth transistor is connected to the first output terminal, the second terminal of the tenth transistor is grounded, and the gate of the tenth transistor is connected to the second output terminal.

[0024] The first terminal of the eleventh transistor is connected to the second output terminal, the second terminal of the eleventh transistor is grounded, and the gate of the eleventh transistor is connected to the first output terminal.

[0025] Optionally, the types of the first transistor, the second transistor, the third transistor, and the fourth transistor are different from the type of the seventh transistor, wherein the types include P-type MOS transistors or N-type MOS transistors.

[0026] Secondly, a latch is provided, the latch including a latching circuit and a blocking circuit, wherein the latching circuit has a third output terminal, a fourth output terminal, a first ground terminal and a second ground terminal, the third output terminal is grounded through the first ground terminal and the fourth output terminal is grounded through the second ground terminal;

[0027] The blocking circuit is used to: block the first grounding terminal from grounding after the output signal at the third output terminal changes from low level to high level; and block the second grounding terminal from grounding after the output signal at the fourth output terminal changes from low level to high level.

[0028] Optionally, the latching circuit has a third input terminal and a fourth input terminal, and the blocking circuit includes a third switching circuit and a fourth switching circuit;

[0029] The third switching circuit is connected to the first ground terminal, the third input terminal and the clock signal source respectively, and the fourth switching circuit is connected to the second ground terminal, the fourth input terminal and the clock signal source respectively;

[0030] The third switching circuit is used to: block the first grounding terminal from grounding after the input signals of the third input terminal and the clock signal source drive the output signal of the third output terminal to a high level;

[0031] The fourth switching circuit is used to: block the second grounding terminal from grounding after the input signals of the fourth input terminal and the clock signal source drive the output signal of the fourth output terminal to a high level.

[0032] Optionally, the third switching circuit includes a twelfth transistor and a thirteenth transistor;

[0033] The gate of the twelfth transistor is connected to the third input terminal, and the gate of the thirteenth transistor is connected to the clock signal source.

[0034] The first terminal of the twelfth transistor is connected to the first ground terminal, and the second terminal of the twelfth transistor is grounded. The first terminal of the thirteenth transistor is connected to the first ground terminal, and the second terminal of the thirteenth transistor is grounded.

[0035] Optionally, the fourth switching circuit includes a fourteenth transistor and a fifteenth transistor;

[0036] The gate of the fourteenth transistor is connected to the fourth input terminal, and the gate of the fifteenth transistor is connected to the clock signal source.

[0037] The first terminal of the fourteenth transistor is connected to the second ground terminal, and the second terminal of the fourteenth transistor is grounded. The first terminal of the fifteenth transistor is connected to the second ground terminal, and the second terminal of the fifteenth transistor is grounded.

[0038] Optionally, the latching circuit includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor;

[0039] The gate of the sixteenth transistor is connected to the third input terminal, the first terminal of the sixteenth transistor is connected to the second terminal of the eighteenth transistor, and the second terminal of the sixteenth transistor is connected to the third output terminal.

[0040] The gate of the seventeenth transistor is connected to the fourth input terminal, the first terminal of the seventeenth transistor is connected to the second terminal of the eighteenth transistor, and the second terminal of the seventeenth transistor is connected to the fourth output terminal.

[0041] The gate of the eighteenth transistor is connected to a clock signal source, and the first terminal of the eighteenth transistor is grounded.

[0042] Optionally, the latching circuit further includes a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor;

[0043] The first terminal of the nineteenth transistor is connected to the power supply, the second terminal of the nineteenth transistor is connected to the third output terminal, and the gate of the nineteenth transistor is connected to the fourth output terminal.

[0044] The first terminal of the twentieth transistor is connected to the power supply, the second terminal of the twentieth transistor is connected to the fourth output terminal, and the gate of the twentieth transistor is connected to the third output terminal.

[0045] The first terminal of the 21st transistor is connected to the third output terminal, the second terminal of the 21st transistor is connected to the first ground terminal, and the gate of the 21st transistor is connected to the fourth output terminal.

[0046] The first terminal of the twelfth transistor is connected to the fourth output terminal, the second terminal of the twelfth transistor is connected to the second ground terminal, and the gate of the twelfth transistor is connected to the third output terminal.

[0047] Optionally, the twelfth, thirteenth, fourteenth, and fifteenth transistors are of a different type than the eighteenth transistor, wherein the type includes a P-type MOS transistor or an N-type MOS transistor.

[0048] Thirdly, a memory is provided, the memory including peripheral circuitry, the peripheral circuitry including at least one latch as described in the first and / or second aspects above.

[0049] Fourthly, a timing circuit is provided, the timing circuit including at least one latch as described in the first and / or second aspects above.

[0050] Fifthly, a chip is provided that includes at least one latch as described in the first and / or second aspects above.

[0051] The beneficial effects of the technical solutions provided in this application are:

[0052] The embodiments provided in this application add a blocking circuit to the latch. After the output signal at the first output terminal of the latch circuit changes from high to low, the blocking circuit can block the conduction between the first power supply terminal and the power supply. Because the first power supply terminal is blocked, even if the transistor in the latch circuit that is in series with the first power supply terminal is not turned off in time, no shoot-through current will flow through the corresponding transistor, thus reducing the power consumption of the latch circuit. Similarly, after the output signal at the second output terminal changes from high to low, the blocking circuit can block the conduction between the second power supply terminal and the power supply. Because the second power supply terminal is blocked, even if the transistor in the latch circuit that is in series with the second power supply terminal is not turned off in time, no shoot-through current will flow through the corresponding transistor, thus reducing the power consumption of the latch circuit. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of an exemplary latch circuit provided in an embodiment of this application;

[0055] Figure 2 This is a schematic diagram of an exemplary latch circuit provided in an embodiment of this application;

[0056] Figure 3 This is a circuit diagram of a latch provided in an embodiment of this application;

[0057] Figure 4 This is a circuit diagram of a latch provided in an embodiment of this application;

[0058] Figure 5 This is a circuit diagram of a latch provided in an embodiment of this application;

[0059] Figure 6 This is a circuit diagram of a latch provided in an embodiment of this application;

[0060] Figure 7 This is a circuit diagram of a latch provided in an embodiment of this application;

[0061] Figure 8 This is a circuit diagram of a latch provided in an embodiment of this application;

[0062] Figure 9 This is a schematic diagram of a timing circuit provided in an embodiment of this application;

[0063] Figure 10 This is a schematic diagram of a timing circuit provided in an embodiment of this application;

[0064] Figure 11 This is a schematic diagram of a timing circuit provided in an embodiment of this application;

[0065] Figure 12 This is a schematic diagram of a timing circuit provided in an embodiment of this application;

[0066] Figure 13 This is a schematic diagram of a memory including peripheral circuitry provided in an embodiment of this application;

[0067] Figure 14 This is a schematic diagram of a memory including a memory cell array and peripheral circuitry provided in an embodiment of this application;

[0068] Figure 15 This is a schematic diagram of a system with a memory provided in an embodiment of this application;

[0069] Figure 16 This is an illustration of a memory card with a memory provided in an embodiment of this application;

[0070] Figure 17 This is a schematic diagram of a solid-state driver with a memory device provided in an embodiment of this application.

[0071] Illustration

[0072] 1. Latch circuit; 11. First output terminal; 12. Second output terminal; 13. First power supply terminal; 14. Second power supply terminal; 15. First input terminal; 16. Second input terminal; 17. Fifth transistor; 18. Sixth transistor; 19. Seventh transistor; 110. Eighth transistor; 111. Ninth transistor; 112. Tenth transistor; 113. Eleventh transistor;

[0073] 2. Blocking circuit; 21. First switching circuit; 22. Second switching circuit; 211. First transistor; 212. Second transistor; 221. Third transistor; 222. Fourth transistor;

[0074] 3. Latch circuit; 31. Third output terminal; 32. Fourth output terminal; 33. First ground terminal; 34. Second ground terminal; 35. Third input terminal; 36. Fourth input terminal; 37. Sixteenth transistor; 38. Seventeenth transistor; 39. Eighteenth transistor; 310. Nineteenth transistor; 311. Twentieth transistor; 312. Twenty-first transistor; 313. Twenty-second transistor;

[0075] 4. Blocking circuit; 41. Third switching circuit; 42. Fourth switching circuit; 411. Twelfth transistor; 412. Thirteenth transistor; 421. Fourteenth transistor; 422. Fifteenth transistor;

[0076] 51. First latch; 52. Second latch. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0078] Figure 1 This is a schematic diagram of an exemplary latching circuit provided in an embodiment of this application. For example... Figure 1As shown, the latch circuit includes two P-type MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistors) MP0 and MP1, and five N-type MOS transistors MN0, MN1, MN2, MN3, and MN_CLK. The gates of MN2 and MN3 are the input terminals D and Dn of the latch circuit, respectively. The first terminals of MP0, MN0, and MN2, and the gates of MP1 and MN1 are connected to the output terminal Qn of the latch circuit. The first terminals of MN1, MN3, and MP1, and the gates of MP0 and MN0 are connected to the output terminal Q of the latch circuit. The second terminals of MP0 and MP1 are connected to VDD (power supply), and the second terminals of MN0 and MN1 are grounded. The second terminals of MN2 and MN3 are connected to the first terminal of MN_CLK, the second terminal of MN_CLK is grounded, and the gate of MN_CLK is connected to CLK (clock). In the embodiments of this application, the first pole and the second pole refer to the source or the drain. When the first pole of a MOS transistor is the source, its corresponding second pole is the drain, and when the first pole of a MOS transistor is the drain, its corresponding second pole is the source.

[0079] exist Figure 1 In the latch circuit shown, D and Dn are input terminals with opposite input signals, and Q and Qn are output terminals with opposite output signals. These output signals represent the states to be stored; for example, the first stored state is Q = 1, Qn = 0; and the second stored state is Q = 0, Qn = 1. Here, "1" represents a high level, and "0" represents a low level. When CLK is high, MN_CLK is on; when CLK is low, MN_CLK is off. When CLK is on, changing the input signals of D and Dn can change the output signals of Q and Qn.

[0080] Specifically, when CLK=1, D=1, Dn=0: Q=1, Qn=0. MN_CLK, MN2, MP1, and MN0 are on. When CLK=1, D=0, Dn=1: Q=0, Qn=1. MN_CLK, MN3, MP0, and MN1 are on.

[0081] exist Figure 1In the latch circuit shown, after switching from a storage state of Q=1, Qn=0 to a storage state of Q=0, Qn=1, MP1 will not immediately turn off, but MN3 will immediately turn on. This creates a brief continuity between VDD and ground, resulting in a large through-current flowing through MP1 and MN3, thus increasing the power consumption of the latch circuit. Similarly, after switching from a storage state of Q=0, Qn=1 to a storage state of Q=1, Qn=0, MP0 will not immediately turn off, but MN2 will immediately turn on. This also creates a brief continuity between VDD and ground, resulting in a large through-current flowing through MP0 and MN2, further increasing the power consumption of the latch circuit.

[0082] Figure 2 This is a schematic diagram of an exemplary latching circuit provided in an embodiment of this application. For example... Figure 2 As shown, the latch circuit includes two N-type MOSFETs, MN0 and MN1, and five P-type MOSFETs, MP0, MP1, MP2, MP3, and MP_CLK. The gates of MP2 and MP3 are the input terminals D and Dn of the latch circuit, respectively. The first terminals of MN0, MP0, and MP2, and the gates of MP1 and MN1 are connected to the output terminal Qn of the latch circuit. The first terminals of MP1, MP3, and MN1, and the gates of MP0 and MN0 are connected to the output terminal Q of the latch circuit. The second terminals of MP0 and MP1 are connected to VDD, and the second terminals of MN0 and MN1 are grounded. The second terminals of MP2 and MP3 are connected to the first terminal of MP_CLK, the second terminal of MP_CLK is connected to VDD, and the gate of MP_CLK is connected to CLK.

[0083] exist Figure 2 In the latch circuit shown, D and Dn are input terminals with opposite input signals, and Q and Qn are output terminals with opposite output signals. These output signals represent the states to be stored; for example, the first stored state is Q = 1, Qn = 0; and the second stored state is Q = 0, Qn = 1. Here, "1" represents a high level, and "0" represents a low level. When CLK is high, MN_CLK is on; when CLK is low, MN_CLK is off. When CLK is on, changing the input signals of D and Dn can change the output signals of Q and Qn.

[0084] Specifically, when CLK=0, D=1, and Dn=0: Q=1 and Qn=0. MP_CLK, MP3, MP1, and MN0 are on. When CLK=0, D=0, and Dn=1: Q=0 and Qn=1. MP_CLK, MP2, MP0, and MN1 are on.

[0085] exist Figure 2In the latch circuit shown, after switching from a storage state of Q=1, Qn=0 to a storage state of Q=0, Qn=1, MN0 will not immediately turn off, but MP2 will immediately turn on. This creates a brief continuity between VDD and ground, resulting in a large direct current flowing through MP2 and MN0, thus increasing the power consumption of the latch circuit. Similarly, after switching from a storage state of Q=0, Qn=1 to a storage state of Q=1, Qn=0, MN1 will not immediately turn off, but MP3 will immediately turn on. This also creates a brief continuity between VDD and ground, resulting in a large direct current flowing through MN1 and MP3, further increasing the power consumption of the latch circuit.

[0086] From the above Figure 1 and Figure 2 As can be seen from the content, when the latch changes its storage state, some of the internal transistors fail to change their conduction state in time, which causes the power supply to be directly grounded through the transistors, resulting in a through current flowing through the transistors, which in turn increases the power consumption of the latch.

[0087] Figure 3 This is a circuit diagram of a latch provided in an embodiment of this application. Figure 3 As shown, the latch includes a latching circuit 1 and a blocking circuit 2. The latching circuit 1 has a first output terminal 11, a second output terminal 12, a first power supply terminal 13, and a second power supply terminal 14. The high level of the output signal at the first output terminal 11 is provided by the first power supply terminal 13, and the high level of the output signal at the second output terminal 12 is provided by the second power supply terminal 14. Both the first power supply terminal 13 and the second power supply terminal 14 in the latching circuit 1 are connected to the power supply through the blocking circuit 2.

[0088] in, Figure 3 The latch circuit 1 shown can be any latch circuit with dual outputs, such as the one described above. Figure 1 The latch circuit shown is an example of a latch circuit 1. The high and low levels output by the first output terminal 11 and the second output terminal 12 in latch circuit 1 are opposite; that is, when the first output terminal 11 outputs a high level, the second output terminal 12 outputs a low level, and vice versa. In one example, the high level output by the first output terminal 11 and the low level output by the second output terminal 12 can form the first storage state of latch circuit 1, such as "10", and the low level output by the first output terminal 11 and the high level output by the second output terminal 12 can form the second storage state of latch circuit 1, such as "01".

[0089] Figure 3The blocking circuit 2 shown is used to block the connection between the first power supply terminal 13 and the power supply after the output signal of the first output terminal 11 changes from high level to low level (which is also the time when the output signal of the second output terminal 12 changes from low level to high level), and to connect the second power supply terminal 14 to the power supply. Thus, after the storage state of the latch circuit 1 changes, even if the transistor connected in series with the first power supply terminal 13 in the latch circuit 1 fails to switch to the off state in time, no DC current will flow through the corresponding transistor because the first power supply terminal 13 is disconnected from the power supply, thereby reducing the power consumption of the latch circuit 1.

[0090] Figure 3 The blocking circuit 2 shown is also used to block the connection between the second power supply terminal 14 and the power supply after the output signal of the second output terminal 12 changes from high level to low level (which is also the output signal of the first output terminal 11 changes from low level to high level), and to connect the first power supply terminal 13 and the power supply. Thus, when the storage state of the latch circuit 1 switches, even if the transistor connected in series with the second power supply terminal 14 in the latch circuit 1 fails to switch to the off state in time, no DC current will flow through the corresponding transistor due to the disconnection of the second power supply terminal 14 from the power supply, thereby reducing the power consumption of the latch circuit 1.

[0091] Figure 4 This is a circuit diagram of a latch provided in an embodiment of this application. Figure 4 As shown, the latch circuit 1 has a first input terminal 15 and a second input terminal 16. The first input terminal 15 and the second input terminal 16 of the latch circuit 1 can be the control terminals of the latch circuit 1. By controlling the input signals of the first input terminal 15 and the second input terminal 16, the switching of the stored state in the latch circuit 1 can be controlled.

[0092] In one example, the high and low levels of the input signals at the first input terminal 15 and the second input terminal 16 can be reversed. For instance, when the first input terminal 15 is high and the second input terminal 16 is low, the latch circuit 1 is in a first storage state. When the first input terminal 15 switches to a low level and the second input terminal 16 switches to a high level, the latch circuit 1 can switch from the first storage state to the second storage state. Additionally, the latch circuit 1 can also be connected to a clock signal source (…). Figure 4 (As shown in the diagram), the signal input from the clock signal source can control whether the signals input to the first input terminal 15 and the second input terminal 16 are valid. For example, only when the signal input from the clock signal source is high can the signals input to the first input terminal 15 and the second input terminal 16 control the switching of the storage state in the latch circuit 1.

[0093] See also Figure 4 The blocking circuit 2 may include a first switching circuit 21 and a second switching circuit 22.

[0094] The first switching circuit 21 is connected to the first power supply terminal 13, the first input terminal 15, the power supply, and the clock signal source. The first input terminal 15 and the clock signal source can be the control terminals of the first switching circuit 21. The signals input to the first input terminal 15 and the clock signal source can control the conduction state between the power supply and the first power supply terminal 13. Specifically, the first switching circuit 21 is used to block the conduction between the first power supply terminal 13 and the power supply after the input signals from the first input terminal 15 and the clock signal source drive the output signal of the first output terminal 11 to a low level.

[0095] Based on the above Figure 4 As described in the introduction, the first input terminal 15 of the latch circuit 1 and the output signal of the clock signal source can drive the storage state switching of the latch circuit 1. Therefore, the first input terminal 15 and the output signal of the clock signal source can be used as the input signal of the first switching circuit 21. When the output signal of the first input terminal 15 and the clock signal source is used to drive the output signal of the first output terminal 11 of the latch circuit 1 to a low level, the first input terminal 15 and the output signal of the clock signal source are input to the first switching circuit 21, which can block the first power supply terminal 13 from the power supply.

[0096] For example, when the first input terminal 15 and the clock signal source switch to a high level, the output signal of the first output terminal 11 of the latch circuit 1 can be driven to a low level, and the switch between the first power supply terminal 13 and the power supply in the first switching circuit 21 can be opened. Since the high level of the first output terminal 11 is provided by the first power supply terminal 13, when the output of the first output terminal 11 is low, blocking the conduction between the first power supply terminal 13 and the power supply allows the first output terminal 11 to directly output a low level without affecting the storage state of the latch circuit 1. Furthermore, since the conduction between the first power supply terminal 13 and the power supply is blocked, the transistor connected in series with the first power supply terminal 13 and grounded in the latch circuit 1 will not have DC current flowing through it even if it is not disconnected in time, thus reducing the power consumption of the latch circuit 1.

[0097] In one example, the first switching circuit 21 can block the first power supply terminal 13 from being connected to the power supply only when the output signal of the first output terminal 11 of the latch circuit 1 is switched to a low level by the signals from the first input terminal 15 and the clock signal source. When the output signal of the first input terminal 15 or the clock signal source changes, the first switching circuit 21 can restore the connection between the first power supply terminal 13 and the power supply to ensure the normal operation of the latch circuit 1.

[0098] See also Figure 4The second switching circuit 22 is connected to the second power supply terminal 14, the second input terminal 16 of the latch circuit 1, the power supply, and the clock signal source. The second input terminal 16 and the clock signal source can be the control terminals of the second switching circuit 22, and the signals input to the second input terminal 16 and the clock signal source can control the conduction state between the power supply and the second power supply terminal 14. Specifically, the second switching circuit 22 is used to block the conduction between the second power supply terminal 14 and the power supply after the input signals from the second input terminal 16 and the clock signal source drive the output signal of the second output terminal 12 to a low level.

[0099] Based on the above Figure 4 As described in the introduction, the second input terminal 16 of the latch circuit 1 and the output signal of the clock signal source can drive the storage state switching of the latch circuit 1. Therefore, the second input terminal 16 and the output signal of the clock signal source can be used as the input signal of the second switching circuit 22. When the output signal of the second input terminal 16 and the clock signal source is used to drive the output signal of the second output terminal 12 of the latch circuit 1 to a low level, the second input terminal 16 and the output signal of the clock signal source are input to the second switching circuit 22, which can block the second power supply terminal 14 from the power supply.

[0100] For example, when the second input terminal 16 and the clock signal source switch to a high level, the output signal of the second output terminal 12 of the latch circuit 1 can be driven to a low level, and the switch between the second power supply terminal 14 and the power supply in the second switching circuit 22 can be opened. Since the high level of the second output terminal 12 is provided by the second power supply terminal 14, when the output of the second output terminal 12 is low, blocking the conduction between the second power supply terminal 14 and the power supply allows the second output terminal 12 to directly output a low level without affecting the stored state of the latch circuit 1. Furthermore, since the conduction between the second power supply terminal 14 and the power supply is blocked, the transistor connected in series with the second power supply terminal 14 and grounded in the latch circuit 1 will not have DC current flowing through it even if it is not turned off in time, thus reducing the power consumption of the latch circuit 1.

[0101] In one example, the second switching circuit 22 can block the connection between the second power supply terminal 14 and the power supply only when the output signal of the second output terminal 12 of the latch circuit 1 is switched to a low level by the signals from the second input terminal 16 and the clock signal source. When the output signal of the second input terminal 16 or the clock signal source changes, the second switching circuit 22 can restore the connection between the second power supply terminal 14 and the power supply to ensure the normal operation of the latch circuit 1.

[0102] Figure 5 This is a circuit diagram of a latch provided in an embodiment of this application. Figure 5As shown, the first switching circuit 21 includes a first transistor 211 and a second transistor 212. The gate of the first transistor 211 is connected to the first input terminal 15, and the gate of the second transistor 212 is connected to a clock signal source. The first and second terminals of the first transistor 211 are connected to the first power supply terminal 13 and a power source, respectively, and the first and second terminals of the second transistor 212 are also connected to the first power supply terminal 13 and a power source, respectively.

[0103] In implementation, the types of the first transistor 211 and the second transistor 212 can be set according to the input signals of the first input terminal 15 and the clock signal source driving the first output terminal 11 when the output signal of the first input terminal 15 and the clock signal source driving the first output terminal 11 is low, so that when the output signal of the first input terminal 15 and the clock signal source driving the first output terminal 11 is low, both the first transistor 211 and the second transistor 212 are in an off state. This type can be a P-type MOSFET or an N-type MOSFET. For example, when the output signal of the first input terminal 15 and the clock signal source driving the first output terminal 11 is low, both the first input terminal 15 and the clock signal source are high, then both the first transistor 211 and the second transistor 212 can be P-type MOSFETs.

[0104] See also Figure 5 The second switching circuit 22 includes a third transistor 221 and a fourth transistor 222. The gate of the third transistor 221 is connected to the second input terminal 16, and the gate of the fourth transistor 222 is connected to a clock signal source. The first and second terminals of the third transistor 221 are connected to the second power supply terminal 14 and the power supply, respectively, and the first and second terminals of the fourth transistor 222 are connected to the second power supply terminal 14 and the power supply, respectively.

[0105] In implementation, the types of the third transistor 221 and the fourth transistor 222 can be set according to the input signals of the first input terminal 15 and the clock signal source driving the first output terminal 11 when the output signal of the first input terminal 15 and the clock signal source driving the first output terminal 11 is low, so that the third transistor 221 and the fourth transistor 222 are both in the off state when the output signal of the first input terminal 15 and the clock signal source driving the first output terminal 11 is low. This type can be a P-type MOSFET or an N-type MOSFET. For example, when the output signal of the first input terminal 15 and the clock signal source driving the first output terminal 11 is low, both the first input terminal 15 and the clock signal source are at a high level, then both the first transistor 211 and the second transistor 212 can be P-type MOSFETs.

[0106] In one possible implementation, the latch circuit 1 includes a fifth transistor 17, a sixth transistor 18, and a seventh transistor 19. For example... Figure 5As shown, the gate of the fifth transistor 17 is connected to the first input terminal 15, the first terminal of the fifth transistor 17 is connected to the first output terminal 11, and the second terminal of the fifth transistor 17 is connected to the first terminal of the seventh transistor 19. The gate of the sixth transistor 18 is connected to the second input terminal 16, the first terminal of the sixth transistor 18 is connected to the second output terminal 12, and the second terminal of the sixth transistor 18 is connected to the first terminal of the seventh transistor 19. The gate of the seventh transistor 19 is connected to a clock signal source, and the second terminal of the seventh transistor 19 is grounded.

[0107] See also Figure 5 The latch circuit 1 further includes an eighth transistor 110, a ninth transistor 111, a tenth transistor 112, and an eleventh transistor 113. The first terminal of the eighth transistor 110 is connected to the first power supply terminal 13, the second terminal of the eighth transistor 110 is connected to the first output terminal 11, and the gate of the eighth transistor 110 is connected to the second output terminal 12. The first terminal of the ninth transistor 111 is connected to the second power supply terminal 14, the second terminal of the ninth transistor 111 is connected to the second output terminal 12, and the gate of the ninth transistor 111 is connected to the first output terminal 11. The first terminal of the tenth transistor 112 is connected to the first output terminal 11, the second terminal of the tenth transistor 112 is grounded, and the gate of the eleventh transistor 113 is connected to the first output terminal 11.

[0108] Among them, the fifth transistor 17, the sixth transistor 18, the seventh transistor 19, the tenth transistor 112, and the eleventh transistor 113 can be of the same type, such as N-type MOSFETs. The eighth transistor 110 and the ninth transistor 111 can be of the same type, but different from the fifth transistor 17, such as P-type MOSFETs. The first transistor 211, the second transistor 212, the third transistor 221, and the fourth transistor 222 can be of the same type, but different from the seventh transistor 19, such as P-type MOSFETs.

[0109] Taking the fifth transistor 17 as an N-type MOSFET as an example, when the first input terminal 15 is high, the second input terminal 16 is low, and CLK outputs a high level, the fifth transistor 17, the seventh transistor 19, the ninth transistor 111, and the tenth transistor 112 in latch circuit 1 are turned on, and only the third transistor 221 in the second switching circuit 2 is turned on in blocking circuit 2. The first output terminal 11 outputs a low level, and the second output terminal 12 outputs a high level. When the first input terminal 15 switches to a low level, the second input terminal 16 switches to a high level, and CLK outputs a high level, the sixth transistor 18, the seventh transistor 19, the eighth transistor 110, and the eleventh transistor 113 in latch circuit 1 are turned on, and only the first transistor 211 in the first switching circuit 21 is turned on in blocking circuit 2. The first output terminal 11 outputs a high level, and the second output terminal 12 outputs a low level. In this circuit, the high level at the second input terminal 16 acts on the gate of the sixth transistor 18, turning it on. However, due to circuit control delay, the high level output from the first output terminal 11 acts on the gate of the ninth transistor 111, blocking its conduction, which is later than the turn-on of the sixth transistor 18. Therefore, after the latch circuit 1 switches the storage state, there is a momentary conduction between the ninth transistor 111 and the sixth transistor 18 and the ground terminal. However, the high level of the clock signal source and the high level of the second input terminal 16 block the third transistor 221 and the fourth transistor 222 in the second switching circuit 22 for the same amount of time as the high level of the second input terminal 16 turns on the sixth transistor 18. Therefore, even if the ninth transistor 111 fails to turn off in time, the second switching circuit 22 can still block the connection between the second power supply terminal 14 and the power supply, preventing current from flowing between the ninth transistor 111 and the sixth transistor 18 and the ground terminal. This reduces the power consumption of the latch circuit 1. Furthermore, the situation is similar for the fifth transistor 17 being a P-type MOS transistor as described above, and will not be repeated in this embodiment.

[0110] Figure 6 This is a circuit diagram of a latch provided in an embodiment of this application. Figure 6 As shown, the latch includes a latching circuit 3 and a blocking circuit 4. The latching circuit 3 has a third output terminal 31, a fourth output terminal 32, a first ground terminal 33, and a second ground terminal 34. The third output terminal 31 is grounded through the first ground terminal 33, and the fourth output terminal 32 is grounded through the second ground terminal 34. Both the first ground terminal 33 and the second ground terminal 34 in the latching circuit 3 are grounded through the blocking circuit 4.

[0111] in, Figure 6 The latch circuit 3 shown can be any latch circuit with dual outputs, such as the one described above. Figure 2The latch circuit shown is an example of a latch circuit 3. In latch circuit 3, the third output terminal 31 and the fourth output terminal 32 output signals are opposite; that is, when the third output terminal 31 outputs a high level, the fourth output terminal 32 outputs a low level, and vice versa. In one example, the high level output by the third output terminal 31 and the low level output by the fourth output terminal 32 can form the first storage state of latch circuit 3, such as "10", and the low level output by the third output terminal 31 and the high level output by the fourth output terminal 32 can form the second storage state of latch circuit 1, such as "01".

[0112] Figure 6 The blocking circuit 4 shown is used to block the grounding of the first ground terminal 33 and ground the second ground terminal 34 after the output signal of the third output terminal 31 changes from low to high (which is also the time when the output signal of the fourth output terminal 32 changes from high to low). Thus, after the storage state of the latch circuit 3 changes, even if the transistor connected in series with the first ground terminal 33 in the latch circuit 1 fails to switch to the off state in time, no DC current will flow through the corresponding transistor because the first ground terminal 33 is not grounded, thereby reducing the power consumption of the latch circuit 3.

[0113] Figure 6 The blocking circuit 4 shown is also used to block the grounding of the second grounding terminal 34 and ground the first grounding terminal 33 after the output signal of the fourth output terminal 32 changes from low level to high level (which is also the output signal of the third output terminal 31 changes from high level to low level). In this way, after the storage state of the latch circuit 3 is switched, even if the transistor connected in series with the second grounding terminal 34 in the latch circuit 3 fails to switch to the off state in time, no DC current will flow through the corresponding transistor because the second grounding terminal 34 is not grounded, thus reducing the power consumption of the latch circuit 3.

[0114] Figure 7 This is a circuit diagram of a latch provided in an embodiment of this application. Figure 7 As shown, the latch circuit 3 has a third input terminal 35 and a fourth input terminal 36. The third input terminal 35 and the fourth input terminal 36 of the latch circuit 3 can be the control terminals of the latch circuit 3. By controlling the input signals of the third input terminal 35 and the fourth input terminal 36, the switching of the storage state in the latch circuit 3 can be controlled.

[0115] In one example, the input signals to the third input terminal 35 and the fourth input terminal 36 can be opposite. For example, when the third input terminal 35 is high and the fourth input terminal 36 is low, the latch circuit 3 is in the first storage state. When the third input terminal 35 switches to a low level and the fourth input terminal 36 switches to a high level, the latch circuit 3 can switch from the first storage state to the second storage state. Additionally, the latch circuit 3 can also be connected to a clock signal source (…). Figure 7 (As shown in the diagram), the signal input from the clock signal source can control whether the signals input to the third input terminal 35 and the fourth input terminal 36 are valid. For example, only when the signal input from the clock signal source is high can the signals input to the third input terminal 35 and the fourth input terminal 36 control the switching of the storage state in the latch circuit 3.

[0116] See also Figure 7 The blocking circuit 4 may include a third switching circuit 41 and a fourth switching circuit 42.

[0117] The third switching circuit 41 is connected to the first ground terminal 33, the third input terminal 35, the clock signal source, and GND (ground point). The third input terminal 35 and the clock signal source can be the control terminals of the third switching circuit 41. The signals input to the third input terminal 35 and the clock signal source can control the conduction state between the first ground terminal 33 and GND. Specifically, the third switching circuit 41 is used to block the conduction between the first ground terminal 33 and GND after the input signals from the third input terminal 35 and the clock signal source drive the output signal of the third output terminal 31 to a high level, that is, to block the first ground terminal 33 from being grounded.

[0118] Based on the above Figure 7 As described in the introduction, the third input terminal 35 of the latch circuit 3 and the output signal of the clock signal source can drive the storage state switching of the latch circuit 3. Therefore, the third input terminal 35 and the output signal of the clock signal source can be used as the input signal of the third switching circuit 41. When the output signal of the third input terminal 35 and the clock signal source is used to drive the output signal of the third output terminal 31 of the latch circuit 3 to a high level, the third input terminal 35 and the output signal of the clock signal source, after being input to the third switching circuit 41, can block the grounding of the first ground terminal 33.

[0119] For example, when the third input terminal 35 and the clock signal source switch to a high level, the output signal of the third output terminal 31 of the latch circuit 3 can be driven to a high level, and the switch between the first ground terminal 33 and GND in the third switching circuit 41 can be opened. Since the output of the third input terminal 35 of the latch circuit 3 is high, even if the first ground terminal 33 is blocked from grounding, it will not affect the storage state of the latch circuit 3. Furthermore, since the first ground terminal 33 is blocked from grounding, the transistor connected in series between the first ground terminal 33 and the power supply in the latch circuit 3 will not have DC current flowing through it even if it is not turned off in time, thus reducing the power consumption of the latch circuit 3.

[0120] In one example, the third switching circuit 41 can block the first ground terminal 33 from grounding only when the output signal of the third input terminal 35 and the clock signal source output signal drives the output signal of the third input terminal 35 of the latch circuit 3 to switch to a high level. When the output signal of the third input terminal 35 or the clock signal source changes, the third switching circuit 41 can restore the first ground terminal 33 to grounding to ensure the normal operation of the latch circuit 3.

[0121] See also Figure 7 The fourth switching circuit 42 is connected to the second ground terminal 34, the fourth input terminal 36, the clock signal source, and GND. The fourth input terminal 36 and the clock signal source can be the control terminals of the fourth switching circuit 42, and the signals input to the fourth input terminal 36 and the clock signal source can control the conduction state between the second ground terminal 34 and GND. Specifically, the fourth switching circuit 42 is used to block the grounding of the second ground terminal 34 after the input signals from the fourth input terminal 36 and the clock signal source drive the output signal of the fourth output terminal 32 to a high level.

[0122] Based on the above Figure 7 As described in the introduction, the fourth input terminal 36 of the latch circuit 3 and the output signal of the clock signal source can drive the storage state switching of the latch circuit 3. Therefore, the fourth input terminal 36 and the output signal of the clock signal source can be used as the input signal of the fourth switching circuit 42. When the output signal of the fourth input terminal 36 and the clock signal source is used to drive the output signal of the fourth output terminal 32 of the latch circuit 3 to a high level, the fourth input terminal 36 and the output signal of the clock signal source, after being input to the fourth switching circuit 42, can block the grounding of the second ground terminal 34.

[0123] For example, when the fourth input terminal 36 and the clock signal source switch to a high level, the output signal of the fourth output terminal 32 of the latch circuit 3 can be driven to a high level, and the switch between the second ground terminal 34 and GND in the third switching circuit 41 can be opened. Since the output of the fourth input terminal 36 of the latch circuit 3 is high, even if the second ground terminal 34 is blocked from grounding, it will not affect the storage state of the latch circuit 3. Furthermore, since the second ground terminal 34 is blocked from grounding, the transistor connected in series between the second ground terminal 34 and the power supply in the latch circuit 3 will not have DC current flowing through it even if it is not turned off in time, thus reducing the power consumption of the latch circuit 3.

[0124] In one example, the fourth switching circuit 42 can block the second ground terminal 34 from grounding only when the output signal of the fourth input terminal 36 and the clock signal source output signal drives the output signal of the fourth input terminal 36 of the latch circuit 3 to switch to a high level. When the output signal of the fourth input terminal 36 or the clock signal source changes, the fourth switching circuit 42 can restore the first ground terminal 33 to ground to ensure the normal operation of the latch circuit 3.

[0125] Figure 8 This is a circuit diagram of a latch provided in an embodiment of this application. Figure 8 As shown, the third switching circuit 41 includes a twelfth transistor 411 and a thirteenth transistor 412. The gate of the twelfth transistor 411 is connected to the third input terminal 35, and the gate of the thirteenth transistor 412 is connected to a clock signal source. The first terminal of the twelfth transistor 411 is connected to the first ground terminal 33, and the second terminal of the twelfth transistor 411 is grounded. The first terminal of the thirteenth transistor 412 is connected to the first ground terminal 33, and the second terminal of the thirteenth transistor 412 is grounded.

[0126] In implementation, the types of the twelfth transistor 411 and the thirteenth transistor 412 can be set according to the input signals of the third input terminal 35 and the clock signal source driving the third output terminal 33 when the output signal of the third input terminal 35 and the clock signal source driving the third output terminal 33 is at a high level. This ensures that when the output signal of the third input terminal 35 and the clock signal source driving the third output terminal 33 is at a high level, both the twelfth transistor 411 and the thirteenth transistor 412 are in an off state. This type can be a P-type MOSFET or an N-type MOSFET. For example, when the output signal of the third input terminal 35 and the clock signal source driving the third output terminal 33 is at a high level, both the third input terminal 35 and the clock signal source are at a low level, then both the twelfth transistor 411 and the thirteenth transistor 412 can be N-type MOSFETs.

[0127] See also Figure 8 In one possible implementation, the fourth switching circuit 42 includes a fourteenth transistor 421 and a fifteenth transistor 422. The gate of the fourteenth transistor 421 is connected to the fourth input terminal 36, and the gate of the fifteenth transistor 422 is connected to a clock signal source. The first terminal of the fourteenth transistor 421 is connected to the second ground terminal 34, and the second terminal of the fourteenth transistor 421 is grounded. The first terminal of the fifteenth transistor 422 is connected to the second ground terminal 34, and the second terminal of the fifteenth transistor 422 is grounded.

[0128] In implementation, the types of the fourteenth transistor 421 and the fifteenth transistor 422 can be set according to the input signals of the fourth input terminal 36 and the clock signal source driving the fourth output terminal 34 when the output signal of the fourth input terminal 36 and the clock signal source driving the fourth output terminal 34 is at a high level. This ensures that both the fourteenth transistor 421 and the fifteenth transistor 422 are in a turned-off state when the output signal of the fourth input terminal 36 and the clock signal source driving the fourth output terminal 34 is at a high level. The transistor type can be either a P-type MOSFET or an N-type MOSFET. For example, when the output signal of the fourth input terminal 36 and the clock signal source driving the fourth output terminal 34 is at a high level, both the fourth input terminal 36 and the clock signal source are at a low level, in which case both the fourteenth transistor 421 and the fifteenth transistor 422 can be N-type MOSFETs.

[0129] In one possible implementation, the latch circuit 3 includes a sixteenth transistor 37, a seventeenth transistor 38, and an eighteenth transistor 39. For example... Figure 8 As shown, the gate of the sixteenth transistor 37 is connected to the third input terminal 35, the first terminal of the sixteenth transistor 37 is connected to the second terminal of the eighteenth transistor 39, and the second terminal of the sixteenth transistor 37 is connected to the third output terminal 31. The gate of the seventeenth transistor 38 is connected to the fourth input terminal 36, the first terminal of the seventeenth transistor 38 is connected to the second terminal of the eighteenth transistor 39, and the second terminal of the seventeenth transistor 38 is connected to the fourth output terminal 32. The gate of the eighteenth transistor 39 is connected to a clock signal source, and the first terminal of the eighteenth transistor 39 is grounded.

[0130] See also Figure 8 The latch circuit 3 also includes a nineteenth transistor 310, a twentieth transistor 311, a twenty-first transistor 312, and a twenty-second transistor 313. The first terminal of the nineteenth transistor 310 is connected to the power supply, the second terminal of the nineteenth transistor 310 is connected to the third output terminal 31, and the gate of the nineteenth transistor 310 is connected to the fourth output terminal 32. The first terminal of the twentieth transistor 311 is connected to the power supply, the second terminal of the twentieth transistor 311 is connected to the fourth output terminal 32, and the gate of the twentieth transistor 311 is connected to the third output terminal 31. The first terminal of the twenty-first transistor 312 is connected to the third output terminal 31, the second terminal of the twenty-first transistor 312 is connected to the first ground terminal 33, and the gate of the twenty-first transistor 312 is connected to the fourth output terminal 42. The first terminal of the twenty-second transistor 313 is connected to the fourth output terminal 32, the second terminal of the twenty-second transistor 313 is connected to the second ground terminal 34, and the gate of the twenty-second transistor 313 is connected to the third output terminal 31.

[0131] Among them, the sixteenth transistor 37, the seventeenth transistor 38, the eighteenth transistor 39, the nineteenth transistor 310, and the twentieth transistor 311 can be of the same type, such as P-type MOSFETs. The twenty-first transistor 312 and the twenty-second transistor 313 can be of the same type, but different from the sixteenth transistor 37, such as N-type MOSFETs. The twelfth transistor 411, the thirteenth transistor 412, the fourteenth transistor 421, and the fifteenth transistor 422 can be of the same type, but different from the eighteenth transistor 39, such as N-type MOSFETs.

[0132] Taking the sixteenth transistor 37 as a P-type MOSFET as an example, when the third input terminal 35 is low, the fourth input terminal 36 is high, and CLK outputs a low level, the sixteenth transistor 37, the eighteenth transistor 39, the nineteenth transistor 310, and the twenty-second transistor 313 in the latch circuit 3 are turned on, and only the fourteenth transistor 421 in the third switching circuit 4 is turned on in the blocking circuit 4. The third output terminal 31 outputs a high level, and the fourth output terminal 32 outputs a low level. When the third input terminal 35 switches to a high level, the fourth input terminal 36 switches to a low level, and CLK outputs a low level, the seventeenth transistor 38, the twentieth transistor 311, and the twenty-first transistor 312 in the latch circuit 3 are turned on, and only the twelfth transistor 411 in the fourth switching circuit 42 is turned on in the blocking circuit 4. The third output terminal 31 outputs a low level, and the fourth output terminal 32 outputs a high level. In this circuit, a low-level signal at the fourth input terminal 36 turns on the gate of the seventeenth transistor 38. However, due to circuit control delay, a low-level signal at the third output terminal 31 turns on the gate of the twenty-second transistor 313, blocking its conduction, which is later than the turn-on of the seventeenth transistor 38. Therefore, after the latch circuit 3 switches storage states, there is a momentary conduction between the seventeenth transistor 38, the twenty-second transistor 313, and the ground terminal. However, the time it takes for the low-level signal source and the low-level signal at the fourth input terminal 36 to block the fourteenth transistor 421 and the fifteenth transistor 422 in the fourth switching circuit 42 is the same as the time it takes for the high-level signal at the fourth input terminal 36 to turn on the seventeenth transistor 38. Therefore, even if the twenty-second transistor 313 fails to turn off in time, the fourth switching circuit 42 can still block the second ground terminal 34 from grounding, preventing current from flowing between the seventeenth transistor 38, the twenty-second transistor 313, and the ground terminal, thus reducing the power consumption of the latch circuit 3. In addition, the sixteenth transistor 37 is an N-type MOS transistor, which is similar to the case where the sixteenth transistor 37 is a P-type MOS transistor as described above, and will not be described again in this embodiment.

[0133] Figures 9 to 12 These are schematic diagrams of exemplary timing circuits provided in the embodiments of this application.

[0134] in, Figures 9 to 12 The sequential circuit shown consists of two latches: a first latch 51 and a second latch 52, as follows: Figures 9-12 As shown, the input terminals D and Dn of the first latch 51 are the input terminals of the sequential circuit, and the input signals are opposite. The output terminals Q and Qn of the first latch 51 are connected to the input terminals D and Dn of the second latch 52. The clock signal sources (CLK) connected to the first latch 51 and the second latch 52 are opposite; that is, when the clock signal source connected to the first latch 51 is high, the clock signal source connected to the second latch 52 is low, and vice versa. The output terminal Q or Qn of the second latch 52 is the output terminal of the sequential circuit.

[0135] in, Figures 9 to 12 In the above embodiments, latch_n can be... Figures 3 to 5 The latch shown, latch_p, can be one of the latches described in the above embodiments. Figures 6 to 8 The latch shown is an example. In this application, latch_n or latch_p can be used to form a sequential circuit. For example... Figure 9 The sequential circuit shown can have both the first latch 51 and the second latch 52 as latch_n. Figure 10 The sequential circuit shown can also have both the first latch 51 and the second latch 52 as latch_p. For example... Figure 11 The sequential circuit shown can have a first latch 51 as latch_n and a second latch 52 as latch_p. For example... Figure 12 The sequential circuit shown can have a first latch 51 (latch_p) and a second latch 52 (latch_n). Since the latches provided in this embodiment have lower power consumption than conventional latches, the sequential circuit constructed from the latches provided in this application also has lower power consumption than conventional sequential circuits.

[0136] This application also provides a memory, which can be a memory with peripheral circuitry. Since the latch provided in this application has lower power consumption than a conventional latch, the memory using the latch provided in this application also has lower power consumption than a conventional memory.

[0137] Figure 13 This is a schematic circuit diagram of an exemplary memory 1300 provided in an embodiment of this application. The memory 1300 may include a memory cell array device 1301 and peripheral circuitry 1302 coupled to the memory cell array device 1301. The peripheral circuitry 1302 is configured with at least one such... Figures 3 to 8 The latch 1302a shown, and the memory cell array device 1301, can be a NAND flash memory cell array, wherein the memory cells 1306 are provided in the form of an array of NAND memory strings 1308, each NAND memory string 1308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 1308 includes a plurality of memory cells 1306 that are series-coupled and vertically stacked. Each memory cell 1306 can hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 1306. Each memory cell 1306 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0138] In some implementations, each memory cell 1306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 1306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal memory values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal memory values ​​to the cell. A fourth nominal memory value can be used for the erase state.

[0139] like Figure 13As shown, each NAND flash memory string 1308 may include a source select gate (SSG) 1310 at its source end and a drain select gate (DSG) 1312 at its drain end. SSG 1310 and DSG 1312 can be configured to activate a selected NAND flash memory string 1308 (column of the array) during read and program processing. In some embodiments, the sources of NAND flash memory strings 1308 in the same block 1304 are coupled via the same source line (SL) 1314 (e.g., common SL). In other words, according to some embodiments, all NAND flash memory strings 1308 in the same block 1304 have an array common source (ACS). According to some embodiments, the DSG 1312 of each NAND flash memory string 1308 is coupled to a corresponding bit line 1316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 1308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 1312) or a deselection voltage (e.g., 0V) to the corresponding DSG 1312 via one or more DSG lines 1313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 1310) or a deselection voltage (e.g., 0V) to the corresponding SSG 1310 via one or more SSG lines 1315.

[0140] like Figure 13As shown, the NAND storage string 1308 can be organized into multiple blocks 1304, each of which can have a common source line 1314 (e.g., coupled to ground). In some implementations, each block 1304 is the basic data unit for an erase operation, i.e., all memory cells 1306 on the same block 1304 are erased simultaneously. To erase memory cells 1306 in a selected block 1304a, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 1314 of the selected block 1304a and the unselected block 1304b on the same plane as the selected block 1304a. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 1306 of adjacent NAND memory strings 1308 can be coupled via word lines 1318, which select which row of memory cells 1306 is affected by read and program processing. In some embodiments, each word line 1318 is coupled to a page 1320 of memory cells 1306, which is the basic data unit used for programming processing. The size of a page 1320, in bits, can be related to the number of NAND memory strings 1308 coupled by word lines 1318 in a block 1304. Each word line 1318 may include multiple control gates (gate electrodes) at each memory cell 1306 in the corresponding page 1320 and gate lines coupling the control gates.

[0141] Continue to refer to Figure 13 Peripheral circuitry 1302 can be coupled to memory cell array 1301 via bit line 1316, word line 1318, source line 1314, SSG line 1315, and DSG line 1313. Peripheral circuitry 1302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 1301 by applying voltage and / or current signals to each target memory cell 1306 and sensing voltage and / or current signals from each target memory cell 1306 via bit line 1316, word line 1318, source line 1314, SSG line 1315, and DSG line 1313. Peripheral circuitry 1302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 14 Some exemplary peripheral circuits are shown. Peripheral circuit 1302 includes a page buffer / sensing amplifier 1404, a column decoder / bit line driver 1406, a row decoder / word line driver 1408, a voltage generator 1410, a control logic unit 1412, a register 1414, an interface 1416, and a data bus 1418. Figure 14 The peripheral circuit shown may include at least one of the above examples. Figures 3 to 8The latch shown may also include at least one of the above-mentioned latches. Figures 9 to 12 The peripheral circuit shown. It should be understood that in some examples, it may also include... Figure 14 Additional peripheral circuitry not shown.

[0142] Page buffer / sensor amplifier 1404 can be configured to read data from and program (write) data to memory cell array 1301 according to control signals from control logic unit 1412. In one example, page buffer / sensor amplifier 1304 can store a page of programming data (write data) to be programmed into a page 1320 of memory cell array 1301. In another example, page buffer / sensor amplifier 1404 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 1306 coupled to selected word line 1318. In yet another example, page buffer / sensor amplifier 1404 can also sense a low-power signal from bit line 1316 representing a data bit stored in memory cell 1306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 1406 can be configured to be controlled by control logic unit 1412 and select one or more NAND memory strings 1308 by applying a bit line voltage generated from voltage generator 1410.

[0143] The row decoder / word line driver 1408 can be configured to be controlled by control logic unit 1412 and to select / deselect block 1304 of memory cell array 1301 and select / deselect word line 1318 of block 1304. The row decoder / word line driver 1408 can also be configured to drive word line 1318 using word line voltages generated from voltage generator 1410. In some embodiments, the row decoder / word line driver 1408 can also select / deselect and drive SSG line 1315 and DSG line 1313. As described in detail below, the row decoder / word line driver 1408 is configured to perform an erase operation on memory cell 1406 coupled to one or more selected word lines 1418. Voltage generator 1410 can be configured to be controlled by control logic unit 1412 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 1301.

[0144] Control logic unit 1412 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 1414 can be coupled to control logic unit 1412 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 1416 can be coupled to control logic unit 1412 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 1412, and to buffer status information received from control logic unit 1412 and relay it to the host. Interface 1416 can also be coupled to column decoder / bitline driver 1406 via data bus 1418 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 1301.

[0145] Figure 15 A block diagram of an exemplary system 1500 having memory according to some aspects of this disclosure is shown. System 1500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 15 As shown, the system 1500 may include a host 1508 and a storage system 1502, the storage system 1502 having one or more memories 1504 and a memory controller 1506. The host 1508 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 1508 may be configured to send data to or receive data from the memory 1504.

[0146] Memory 1504 can be any memory disclosed in this application. For example, it can be one of the above-mentioned... Figure 14 The memory 1300 shown. The memory 1504 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from the drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0147] According to some embodiments, a memory controller 1506 is coupled to a memory 1504 and a host 1508 and is configured to control the memory 1504. The memory controller 1506 can manage data stored in the memory 1504 and communicate with the host 1508. In some embodiments, the memory controller 1506 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1506 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which serve as data storage for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise storage arrays. The memory controller 1506 can be configured to control the operation of the memory 1504, such as read, erase, and program processing. The memory controller 1506 can also be configured to manage various functions relating to data stored or to be stored in the memory 1504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1506 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 1504. The memory controller 1506 can also perform any other suitable function, such as formatting the memory 1504. The memory controller 1506 can communicate with external devices (e.g., host 1508) according to specific communication protocols. For example, the memory controller 1506 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0148] The memory controller 1506 and one or more memories 1504 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 1502 can be implemented and packaged into different types of end electronic products. Figure 16In one example shown, the memory controller 1506 and a single memory 1504 can be integrated into a memory card 1602. The memory card 1602 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1602 can also include a connection between the memory card 1602 and a host computer (e.g., Figure 15 The host 1508 is coupled to the memory card connector 1604. In such a... Figure 17 In another example shown, the memory controller 1506 and multiple memories 1504 can be integrated into the SSD 306. The SSD 1706 may also include components for connecting the SSD 1706 to a host computer (e.g., Figure 15 The SSD connector 1708 is coupled to the host 1508. In some embodiments, the storage capacity and / or operating speed of the SSD 1706 is greater than the storage capacity and / or operating speed of the memory card 1602.

[0149] This application also provides a chip that may include processing circuitry, such as, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), or a microprocessor (MP). The latches used in the chip's processing circuitry may be those described in the above embodiments. Figures 3 to 8 Any of the latches shown. Since the latches provided in this application have lower power consumption than conventional latches, chips using the latches provided in this application also have lower power consumption than conventional chips.

[0150] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0151] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A latch, characterized in that, The latch includes a latching circuit (1) and a blocking circuit (2). The latching circuit (1) has a first output terminal (11), a second output terminal (12), a first power supply terminal (13), and a second power supply terminal (14). The high level in the output signal of the first output terminal (11) is provided by the first power supply terminal (13), and the high level in the output signal of the second output terminal (12) is provided by the second power supply terminal (14). The blocking circuit (2) is used for: After the output signal at the first output terminal (11) changes from high level to low level, the connection between the first power supply terminal (13) and the power supply is blocked. After the output signal at the second output terminal (12) changes from high level to low level, the connection between the second power supply terminal (14) and the power supply is blocked.

2. The latch according to claim 1, characterized in that, The latching circuit (1) has a first input terminal (15) and a second input terminal (16), and the blocking circuit (2) includes a first switching circuit (21) and a second switching circuit (22). The first switching circuit (21) is connected to the first power supply terminal (13), the first input terminal (15), the power supply and the clock signal source respectively, and the second switching circuit (22) is connected to the second power supply terminal (14), the second input terminal (16), the power supply and the clock signal source respectively; The first switching circuit (21) is used to: block the connection between the first power supply terminal (13) and the power supply after the input signal of the first input terminal (15) and the clock signal source drives the output signal of the first output terminal (11) to a low level; The second switching circuit (22) is used to: block the connection between the second power supply terminal (14) and the power supply after the input signal of the second input terminal (16) and the clock signal source drives the output signal of the second output terminal (12) to a low level.

3. The latch according to claim 2, characterized in that, The first switching circuit (21) includes a first transistor (211) and a second transistor (212); The gate of the first transistor (211) is connected to the first input terminal (15), and the gate of the second transistor (212) is connected to the clock signal source; The first and second terminals of the first transistor (211) are connected to the first power supply terminal (13) and the power supply, respectively, and the first and second terminals of the second transistor (212) are connected to the first power supply terminal (13) and the power supply, respectively.

4. The latch according to claim 3, characterized in that, The second switching circuit (22) includes a third transistor (221) and a fourth transistor (222); The gate of the third transistor (221) is connected to the second input terminal (16), and the gate of the fourth transistor (222) is connected to the clock signal source; The first and second terminals of the third transistor (221) are connected to the second power supply terminal (14) and the power supply, respectively, and the first and second terminals of the fourth transistor (222) are connected to the second power supply terminal (14) and the power supply, respectively.

5. The latch according to claim 4, characterized in that, The latching circuit (1) includes a fifth transistor (17), a sixth transistor (18), and a seventh transistor (19). The gate of the fifth transistor (17) is connected to the first input terminal (15), the first terminal of the fifth transistor (17) is connected to the first output terminal (11), and the second terminal of the fifth transistor (17) is connected to the first terminal of the seventh transistor (19). The gate of the sixth transistor (18) is connected to the second input terminal (16), the first terminal of the sixth transistor (18) is connected to the second output terminal (12), and the second terminal of the sixth transistor (18) is connected to the first terminal of the seventh transistor (19). The gate of the seventh transistor (19) is connected to a clock signal source, and the second terminal of the seventh transistor (19) is grounded.

6. The latch according to claim 5, characterized in that, The latch circuit (1) also includes an eighth transistor (110), a ninth transistor (111), a tenth transistor (112), and an eleventh transistor (113). The first terminal of the eighth transistor (110) is connected to the first power supply terminal (13), the second terminal of the eighth transistor (110) is connected to the first output terminal (11), and the gate of the eighth transistor (110) is connected to the second output terminal (12). The first terminal of the ninth transistor (111) is connected to the second power supply terminal (14), the second terminal of the ninth transistor (111) is connected to the second output terminal (12), and the gate of the ninth transistor (111) is connected to the first output terminal (11). The first terminal of the tenth transistor (112) is connected to the first output terminal (11), the second terminal of the tenth transistor (112) is grounded, and the gate of the tenth transistor (112) is connected to the second output terminal (12). The first terminal of the eleventh transistor (113) is connected to the second output terminal (12), the second terminal of the eleventh transistor (113) is grounded, and the gate of the eleventh transistor (113) is connected to the first output terminal (11).

7. The latch according to claim 5, characterized in that, The types of the first transistor (211), the second transistor (212), the third transistor (221), and the fourth transistor (222) are different from the type of the seventh transistor (19), wherein the type includes a P-type MOS transistor or an N-type MOS transistor.

8. A latch, characterized in that, The latch includes a latching circuit (3) and a blocking circuit (4). The latching circuit (3) has a third output terminal (31), a fourth output terminal (32), a first ground terminal (33), and a second ground terminal (34). The third output terminal (31) is grounded through the first ground terminal (33), and the fourth output terminal (32) is grounded through the second ground terminal (34). The blocking circuit (4) is used for: After the output signal at the third output terminal (31) changes from low level to high level, the grounding of the first ground terminal (33) is blocked. After the output signal at the fourth output terminal (32) changes from low level to high level, the grounding of the second ground terminal (34) is blocked.

9. The latch according to claim 8, characterized in that, The latching circuit (3) has a third input terminal (35) and a fourth input terminal (36), and the blocking circuit (4) includes a third switching circuit (41) and a fourth switching circuit (42). The third switch circuit (41) is connected to the first ground terminal (33), the third input terminal (35) and the clock signal source respectively, and the fourth switch circuit (42) is connected to the second ground terminal (34), the fourth input terminal (36) and the clock signal source respectively; The third switching circuit (41) is used to: block the first ground terminal (33) from grounding after the input signal of the third input terminal (35) and the clock signal source drives the output signal of the third output terminal (31) to a high level; The fourth switching circuit (42) is used to block the second grounding terminal (34) from grounding after the input signal of the fourth input terminal (36) and the clock signal source drives the output signal of the fourth output terminal (32) to a high level.

10. The latch according to claim 9, characterized in that, The third switching circuit (41) includes a twelfth transistor (411) and a thirteenth transistor (412). The gate of the twelfth transistor (411) is connected to the third input terminal (35), and the gate of the thirteenth transistor (412) is connected to the clock signal source; The first terminal of the twelfth transistor (411) is connected to the first ground terminal (33), and the second terminal of the twelfth transistor (411) is grounded. The first terminal of the thirteenth transistor (412) is connected to the first ground terminal (33), and the second terminal of the thirteenth transistor (412) is grounded.

11. The latch according to claim 10, characterized in that, The fourth switching circuit (42) includes a fourteenth transistor (421) and a fifteenth transistor (422); The gate of the fourteenth transistor (421) is connected to the fourth input terminal (36), and the gate of the fifteenth transistor (422) is connected to the clock signal source; The first terminal of the fourteenth transistor (421) is connected to the second ground terminal (34), and the second terminal of the fourteenth transistor (421) is grounded. The first terminal of the fifteenth transistor (422) is connected to the second ground terminal (34), and the second terminal of the fifteenth transistor (422) is grounded.

12. The latch according to claim 11, characterized in that, The latching circuit (3) includes a sixteenth transistor (37), a seventeenth transistor (38), and an eighteenth transistor (39); The gate of the sixteenth transistor (37) is connected to the third input terminal (35), the first terminal of the sixteenth transistor (37) is connected to the second terminal of the eighteenth transistor (39), and the second terminal of the sixteenth transistor (37) is connected to the third output terminal (31). The gate of the seventeenth transistor (38) is connected to the fourth input terminal (36), the first terminal of the seventeenth transistor (38) is connected to the second terminal of the eighteenth transistor (39), and the second terminal of the seventeenth transistor (38) is connected to the fourth output terminal (32). The gate of the eighteenth transistor (39) is connected to a clock signal source, and the first terminal of the eighteenth transistor (39) is grounded.

13. The latch according to claim 12, characterized in that, The latching circuit (3) also includes a nineteenth transistor (310), a twentieth transistor (311), a twenty-first transistor (312), and a twenty-second transistor (313). The first terminal of the nineteenth transistor (310) is connected to the power supply, the second terminal of the nineteenth transistor (310) is connected to the third output terminal (31), and the gate of the nineteenth transistor (310) is connected to the fourth output terminal (32). The first terminal of the twentieth transistor (311) is connected to the power supply, the second terminal of the twentieth transistor (311) is connected to the fourth output terminal (32), and the gate of the twentieth transistor (311) is connected to the third output terminal (31). The first terminal of the 21st transistor (312) is connected to the third output terminal (31), the second terminal of the 21st transistor (312) is connected to the first ground terminal (33), and the gate of the 21st transistor (312) is connected to the fourth output terminal (42). The first terminal of the twelfth transistor (313) is connected to the fourth output terminal (32), the second terminal of the twelfth transistor (313) is connected to the second ground terminal (34), and the gate of the twelfth transistor (313) is connected to the third output terminal (31).

14. The latch according to claim 12, characterized in that, The types of the twelfth transistor (411), the thirteenth transistor (412), the fourteenth transistor (421), and the fifteenth transistor (422) are different from the type of the eighteenth transistor (39), wherein the type includes a P-type MOS transistor or an N-type MOS transistor.

15. A memory, characterized in that, The memory includes peripheral circuitry, which includes at least one latch as described in any one of claims 1 to 14.

16. A sequential circuit, characterized in that, The timing circuit includes at least one latch as described in any one of claims 1 to 14.

Images