Dual-port storage and calculation integrated circuit, chip and electronic equipment

Abstract

The embodiment of the invention discloses a dual-port storage and calculation integrated circuit, a chip and electronic equipment, and the dual-port storage and calculation integrated circuit comprises two storage unit arrays, a calculation unit array and a control unit. The control unit selects a write data storage unit array and a calculation storage unit array from the two storage unit arrays according to the write address information and the calculation address information, and the write data storage unit array receives weight data and stores the weight data into a target write data storage unit; the calculation storage unit array sends the weight data stored in the target calculation storage unit to the corresponding target calculation unit; and the target calculation unit receives the to-be-calculated data and calculates the to-be-calculated data and the received weight data to obtain a calculation result. According to the embodiment of the invention, when the weight data is written into one part of the storage units in the storage and calculation array, the stored weight data is extracted from the other part of the storage units and is calculated with the input to-be-calculated data, so that the calculation efficiency is greatly improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a dual-port storage-computing integrated circuit, chip and electronic device. Background Art

[0002] Computing-in-Memory (CIM) refers to the technology of combining computing with storage and directly embedding algorithms inside the memory. Simply put, it is to operate the data input into the neural network with the weight parameters pre-stored in the memory unit to realize the weighted accumulation of the input data, which is the convolution operation. The convolution operation is the core component unit of the deep learning algorithm and accounts for more than 90% of the operations in most current artificial intelligence (AI) chips. This means that through the new architecture of computing-in-memory, 90% or even more of the operations can be completed and output directly by the memory.

[0003] The integration of storage and computing solves the long-standing problems of "storage wall" and "power consumption wall", completely eliminates memory access delays, and greatly reduces data transfer power consumption, resulting in ultra-high computing power and energy efficiency. It is an architecture that is more suitable for AI computing than the von Neumann architecture.

[0004] The common storage-computing-in-memory is generally a single-port computing-computing-in-memory (SP-CIM), that is, one port is provided to access the memory. This architecture provides a clock and a set of address signal lines. When writing is enabled and calculation is disabled, CIM enters write mode, and controls the order of writing weight data and determines the address of writing weight data through the clock and the above set of address signal lines, so as to perform regular write operations; when calculation is enabled and writing is disabled, CIM enters calculation mode, and controls the order of calculation and determines the address of weight data involved in the calculation through the clock and the above set of address signal lines, and controls the order of data input into the neural network through the clock, so that the data input into the neural network is calculated with the weight data pre-stored in the CIM and the result is output.

[0005] In the calculation of neural networks, data processing is mainly performed in the form of a matrix rather than a single row or column. Each write operation can only write one row of weight data, which means that before the calculation, at least Y write operations are required to ensure that the storage cell array in the CIM is filled with weight data, where Y is the total number of rows in the storage cell array.

[0006] However, SP-CIM has only one port and cannot support simultaneous writing and computing operations. Writing a large amount of data to SP-CIM takes a long time, and the long writing time will interrupt the computing process. Therefore, SP-CIM cannot maintain peak computing power for a long time, which in turn affects the final computing efficiency. Summary of the invention

[0007] An embodiment of the present disclosure provides a dual-port storage and computing integrated circuit, which includes: two storage cell arrays, a computing cell array and a control unit; the control unit is used to: receive input write address information and computing address information; according to the write address information, select a write data storage cell array to which weight data is to be written from the two storage cell arrays, and determine a target write data storage cell from the write data storage cell array; according to the computing address information, select a computing storage cell array to participate in the calculation from the two storage cell arrays, and determine a target computing storage cell from the computing storage cell array; the write data storage cell array is used to: receive input weight data and store the weight data in a target write data storage cell; the computing storage cell array is used to: send the weight data stored in the target computing storage cell to the corresponding target computing cell in the computing cell array; the target computing unit is used to: receive input data to be calculated, and calculate the data to be calculated and the weight data stored in the target computing storage cell to obtain a calculation result and output the calculation result.

[0008] In some embodiments, the control unit is further used to: receive an input write clock signal, and sequentially determine a target write data storage unit from the write data storage unit array based on the write clock signal and write address information; receive an input computing clock signal, and sequentially determine a target computing storage unit from the computing storage unit array based on the computing clock signal and computing address information.

[0009] In some embodiments, the control unit is further used to: receive a write enable signal, and control the write data storage unit array to enable the write weight data function according to the write enable signal; receive a calculation enable signal, and control the calculation unit array to enable the calculation function according to the calculation enable signal.

[0010] In some embodiments, the control unit is further used to: in response to receiving a read data mode selection signal and read address information, select a read data storage cell array for reading weight data from two storage cell arrays according to the read address information, and determine a target read data storage cell from the read data storage cell array; the read data storage cell array is used to: output the weight data stored in the target read data storage cell.

[0011] In some embodiments, the control unit is further used to: in response to receiving a read data mode selection signal and read address information, control the computing unit array to enable a read data function; use the computing storage unit array as a read data storage unit array, and determine a target read data storage unit from the read data storage unit array based on the read address information; the read data storage unit array is further used to: send the weight data stored in the target read data storage unit to the corresponding target computing unit in the computing unit array; the target computing unit is used to: output the received weight data.

[0012] In some embodiments, the target calculation unit includes a multiplier for performing multiplication calculation on the data to be calculated and the weight data stored in the target calculation storage unit to obtain a calculation result and output the calculation result.

[0013] In some embodiments, the circuit also includes two word line arrays, each word line array in the two word line arrays corresponds to one storage cell array in the two storage cell arrays; the control unit is further used to: determine the write data word line array from the two word line arrays according to the write address information, and determine the target word line for writing weight data from the write data word line array; determine the storage cell corresponding to the target word line in the write data storage cell array as the target write data storage cell; the write data storage cell array is used to: use the word line of the weight data to be written to store the received weight data in the target write data storage cell.

[0014] In some embodiments, the circuit also includes an addition tree and a shift accumulator; the addition tree is used to accumulate the calculation results corresponding to the same weight output by the computing unit array to obtain a first accumulation result; the shift accumulator is used to shift and accumulate each first accumulation result to obtain a second accumulation result.

[0015] According to another aspect of an embodiment of the present disclosure, a chip is provided, which includes the above-mentioned dual-port storage-computing integrated circuit.

[0016] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, the electronic device comprising the above chip.

[0017] The dual-port storage-computation integrated circuit, chip and electronic device provided by the above embodiments of the present disclosure realizes data writing operation and data calculation operation on the two storage cell arrays respectively and simultaneously by setting two storage cell arrays and calculation cell arrays. Compared with the existing single-port storage-computation integrated memory, while writing weight data to a part of the storage cells in the storage-computation integrated memory, the stored weight data can be extracted from another part of the storage cells to perform calculations with the input data to be calculated, so that writing weight data and using weight data for calculation are independent and do not interfere with each other, and the calculation efficiency is greatly improved. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications.

[0018] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps;

[0020] Figure 1 is a structural diagram of a dual-port storage-computation integrated circuit provided by an exemplary embodiment of the present disclosure;

[0021] Figure 2A is an exemplary timing diagram for writing weight data based on a write clock signal provided by an exemplary embodiment of the present disclosure;

[0022] Figure 2B is an exemplary timing diagram of performing calculation based on a calculation clock signal provided by an exemplary embodiment of the present disclosure;

[0023] Figure 3 is an exemplary structural diagram of a computing unit provided by an exemplary embodiment of the present disclosure;

[0024] Figure 4 is an exemplary timing diagram for reading weight data based on a computing clock signal provided by an exemplary embodiment of the present disclosure;

[0025] Figure 5 It is another structural schematic diagram of a dual-port storage-computation-in-one circuit provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0027] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0028] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0029] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0030] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0031] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0032] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0033] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0034] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0035] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0036] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0037] Application Overview

[0038] In order to solve the problem of computing efficiency bottleneck in the current single-port storage and computing integrated memory, an embodiment of the present disclosure provides a dual-port storage and computing integrated circuit, which includes two storage cell arrays and a computing unit array. While one of the two storage cell arrays is writing data, the other storage cell array and the computing unit array are calculating data. Therefore, compared with the existing single-port storage and computing integrated memory, the circuit provided by the embodiment of the present disclosure can write weight data to a part of the storage cells in the storage and computing array, while extracting the stored weight data from another part of the storage cells to perform calculations on the input data to be calculated, thereby achieving the writing and calculation of weight data independently and without interfering with each other. The circuit has a longer peak computing power retention time, higher effective computing power, more flexible design space and a wider range of applications.

[0039] Exemplary Structure

[0040] Figure 1 1 is a schematic diagram of a dual-port storage-computation integrated circuit provided by an exemplary embodiment of the present disclosure. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

[0041] like Figure 1 As shown, the circuit includes: two storage unit arrays, a calculation unit array and a control unit 101.

[0042] The storage cells included in each of the two storage cell arrays are usually used to store a single bit included in the input multi-bit weight data, and the single bit is the weight data described below. For ease of description, the two storage cell arrays are represented as a first storage cell array and a second storage cell array. Figure 1 As shown, 102 is a storage and computing array composed of two storage cell arrays and a computing cell array, wherein the storage cells marked as Cell_MUX0 constitute the first storage cell array, and the storage cells marked as Cell_MUX1 constitute the second storage cell array. Each computing cell in the above computing cell array may correspond to two storage cells, which belong to the first storage cell array and the second storage cell array respectively.

[0043] Optionally, the arrangement of the two storage unit arrays and the computing unit array can be set arbitrarily. For example, in order to reduce the distance that data is transmitted within the circuit, the arrangement can be as follows: Figure 1In the arrangement shown, the corresponding two storage units (Cell_MUX0 and Cell_MUX1) and the computing unit are arranged in one area, that is, two storage units and one computing unit form a dual-port storage and computing module. Figure 1 As shown, the array formed by multiple dual-port storage and computing modules includes Y rows and X columns.

[0044] The control unit 101 may be a control circuit disposed outside the two storage unit arrays and computing unit arrays. The control unit 101 may receive externally input write address information, computing address information, and other information for controlling the read and write computing operations of the dual-port storage and computing circuit.

[0045] Optionally, the information for controlling the read and write computing operations of the dual-port storage-computation integrated circuit can be input from a system circuit disposed outside the circuit, and the system circuit can be disposed in the same space (e.g., inside the same chip) as the dual-port storage-computation integrated circuit, or in a different space (e.g., in another chip). As an example, the dual-port storage-computation integrated circuit and the system circuit can both be disposed in a SOC (System on Chip) chip.

[0046] In this embodiment, the control unit 101 is used to:

[0047] Receive input write address information and calculated address information. The write address information and calculated address information may be address information input from outside the circuit, and the address information may include information indicating the memory cell array to which the memory cell to be selected belongs. For example, if the lowest bit of the address information is 0, it indicates that the selected memory cell belongs to the first memory array, and if the lowest bit of the address information is 1, it indicates that the selected memory cell belongs to the second memory array.

[0048] like Figure 1 As shown, WADR is the write address information, CIMADR is the calculation address information, WD0-WD Y-1 The weight data to be written to each row.

[0049] The control unit 101 selects a write data storage cell array into which weight data is to be written from the two storage cell arrays according to the write address information, and determines a target write data storage cell from the write data storage cell array.

[0050] The control unit 101 selects a calculation storage cell array participating in the calculation from the two storage cell arrays according to the calculation address information, and determines a target calculation storage cell from the calculation storage cell arrays.

[0051] Specifically, the number of write address information may be one or more, that is, each write operation may operate on one or more groups of storage cells in the write data storage cell array. For example, one write address information corresponds to Figure 1 A row in the first storage cell array shown, that is, each write operation can write weight data to a row of target write data storage cells. Similarly, the number of calculation address information can also be one or more, that is, each calculation operation can operate on one or more groups of storage cells in the calculation storage cell array. For example, one calculation address information corresponds to Figure 1 A row in the second storage cell array is shown, that is, each calculation operation can be performed on a row of target calculation storage cells.

[0052] In this embodiment, the write data storage unit array is used to receive input weight data and store the weight data in a target write data storage unit.

[0053] Specifically, each storage cell array of the present embodiment may include a weight data input port. When a storage cell array is selected as a write data storage cell array, the data input port it contains may receive input weight data and store the weight data in the corresponding target write data storage unit according to the write address information.

[0054] Each row of the storage cell array can simultaneously input multi-bit weight data, and each bit of the multi-bit weight data is stored in a corresponding storage cell. Figure 1 WD0 shown includes WD 0,0 -WD 0,X-1 , W.D. Y-1 Including WD Y-1,0 -WD Y-1,X-1 WD 0,0 -WD 0,X-1 is divided into L groups, each group includes K single bits, and K single bits constitute a multi-bit weight data. Similarly, WD Y-1,0 -WD Y-1,X-1 It is divided into L groups, each group includes K single bits, and K single bits constitute a multi-bit weight data. For example, X is 32, and one row can store 4 8-bit weight data.

[0055] In this embodiment, the calculation storage unit array is used to send the weight data stored in the target calculation storage unit to the corresponding target calculation unit in the calculation unit array.

[0056] Specifically, after a target calculation storage unit is selected from the calculation storage unit array based on the above-mentioned calculation address information, the line between the target storage unit and the corresponding target calculation unit can be turned on, thereby sending the weight data stored in the target calculation storage unit to the target calculation unit.

[0057] like Figure 1 As shown, storage unit 1021 and storage unit 1022 correspond to one computing unit. If storage unit 1022 is a target computing storage unit, then its corresponding computing unit 1023 is a target computing unit.

[0058] In this embodiment, the target calculation unit is used to: receive input data to be calculated, calculate the data to be calculated and the weight data stored in the target calculation storage unit, obtain the calculation result and output the calculation result.

[0059] Specifically, the computing unit array of this embodiment may include a data input port to be calculated, and the target computing unit may receive the data to be calculated inputted from the data input port, and perform calculation with the received weight data. The above-mentioned data to be calculated may be data in the neural network to be used for calculation with the weight data, for example, it may be text data, image data, audio data, video data, etc. Usually, the data to be calculated is single-bit data, for example, the data to be calculated may be a bit included in the multi-bit feature data in the neural network.

[0060] like Figure 1 As shown, NN0–NN Y-1 The computing unit 1023 calculates the input data NN to be calculated. Y-1 The weight data output by the storage unit 1022 is calculated and the calculation result is output. It should be noted that NN0-NN Y-1 The data are respectively input into the computing units included in the corresponding rows of the computing unit array, that is, all computing units included in each row can perform calculations with the corresponding data to be calculated, or part of the computing units included in each row can perform calculations with the corresponding data to be calculated through controlled switch elements. For example, Figure 1 The other computing units in the same row as computing unit 1023 can all process the NN input therein. Y-1 and weight data for calculation.

[0061] exist Figure 1 In the calculation, the data to be calculated in each row includes NN0-NN Y-1 , the data to be calculated is single-bit data, for example, it can be a single-bit included in the multi-bit feature data to be calculated in the neural network. Since the data to be calculated in each row of input can usually be a single-bit included in a multi-bit data (for example, N-bit data), the single-bit included in the multi-bit data is expressed as NN0-NN N-1 During calculation, multiple groups of data to be calculated are calculated in sequence based on the calculation clock. For example, in the first calculation clock cycle, NN0-NN of the first multi-bit data is calculated. N-1The corresponding rows are input respectively, and each calculation unit included in the corresponding row calculates the input data to be calculated and the stored weight data; in the second calculation clock cycle, NN0-NN of the second multi-bit data is calculated. N-1 The corresponding rows are input respectively, and the calculation units included in the corresponding rows calculate the input data to be calculated and the stored weight data. This process is repeated until the calculation of multiple multi-bit data is completed.

[0062] It should be noted that the number of bits N of the input multi-bit data and the number of rows Y of the memory cell array may be the same or different. For the convenience of description in the drawings, the number of bits N and Y of the multi-bit data shown in 1 are the same, that is, the data to be calculated input in each calculation cycle includes NN0-NN Y-1 . In order to make the memory cell array more versatile, the number of rows Y of the memory cell array is usually set to a larger value, and the number of bits N of the input multi-bit data is less than Y. Therefore, one or more multi-bit data can be input in one calculation cycle. For example, when N is 8 and Y is 16, one multi-bit data can be input in one calculation cycle, that is, NN0-NN7 are input to 8 rows respectively, or 2 multi-bit data can be input in one calculation cycle, that is, NN0-NN7 of the first multi-bit data are input to the first 8 rows respectively, and NN0-NN7 of the second multi-bit data are input to the second 8 rows respectively.

[0063] The computing function implemented by the computing unit in the computing unit array can be set according to the application scenario of the dual-port storage-computation integrated circuit. For example, the computing unit can be a multiplier, a NOR gate, etc. Generally, when the dual-port storage-computation integrated circuit provided in this embodiment is used for the operation of a neural network, the calculation result output by the computing unit is the product of the data to be calculated and the weight data.

[0064] The circuit provided by the above-mentioned embodiment of the present disclosure realizes data writing operation and data calculation operation on two storage cell arrays at the same time by setting two storage cell arrays and calculation cell arrays. Compared with the existing single-port storage-computation integrated memory, while writing weight data to a part of the storage cells in the storage-computation integrated memory, the stored weight data can be extracted from another part of the storage cells to perform calculations with the input data to be calculated, so that writing weight data and using weight data for calculation are independent and do not interfere with each other, and the calculation efficiency is greatly improved. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications.

[0065] In some optional implementations, the target calculation unit includes a multiplier for performing multiplication calculation on the data to be calculated and the weight data stored in the target calculation storage unit to obtain a calculation result and output the calculation result.

[0066] This embodiment does not limit the implementation method of the multiplier. For example, the multiplication calculation can be implemented by an AND gate, or by a combination of a NOT gate and a NOR gate. By setting the computing unit as a multiplier, the circuit can be applied to processes such as convolution operations of a neural network, which helps to improve the computing efficiency of the neural network accelerator.

[0067] In some optional implementations, the control unit 101 is further configured to:

[0068] Receive an input write clock signal, and sequentially determine a target write data storage unit from the write data storage unit array according to the write clock signal and the write address information. Receive an input calculation clock signal, and sequentially determine a target calculation storage unit from the calculation storage unit array according to the calculation clock signal and the calculation address information.

[0069] like Figure 1 As shown in Figure 1, CLK_W is the write clock signal, and CLK_CIM is the calculation clock signal. Figure 2A As shown, it shows an exemplary timing diagram of writing data into the write data storage unit array based on the write clock signal. Wherein, CLK_W is the write clock signal, WADR is the write address information, WD is the written data, T su is the signal establishment time, T hd It is known from the figure that in each write cycle, the control unit 101 selects the corresponding target write data storage unit according to the write address information, and the target write data storage unit receives and stores the input weight data.

[0070] like Figure 2B As shown, it shows an exemplary timing diagram for obtaining weight data from the calculation storage unit array for calculation based on the calculation clock signal. Among them, CLK_CIM is the calculation clock signal, CIMADR is the calculation address information, NN is the input data to be calculated, T su is the signal establishment time, T hd is the signal holding time, T delay is the delay time. As can be seen from the figure, in each calculation cycle, the control unit 101 selects the corresponding target calculation storage unit according to the calculation address information, and the target calculation storage unit sends the stored weight data to the corresponding target calculation unit. The target calculation unit calculates the input data to be calculated and the weight data, and the calculation result is shown in the SUM in the figure. SUM0, SUM1, and SUM2 in the figure represent the calculation results obtained in each calculation cycle.

[0071] It should be noted that Figure 2A and Figure 2B The diamond grid part in the timing diagram in represents the negligible signal, that is, the valid signal must meet the signal setup time and signal hold time. Figure 2A and Figure 2B The timing shown is schematic. In a write cycle, a write operation can be performed on one or more storage units. In a calculation cycle, weight data can also be extracted from one or more storage units and calculated with the input data to be calculated.

[0072] This embodiment generates a write clock signal and a calculation clock signal, and can perform write operations and calculation operations on the write data storage cell array and the calculation storage cell array respectively according to different timings. The write operation and the calculation operation can be independent of each other, and can be synchronous or asynchronous, and the length of the cycle can be the same or different, thereby realizing flexible setting of the writing and calculation speeds, improving the flexibility of circuit application, and expanding the application scope of the dual-port storage and calculation integrated circuit.

[0073] In some optional implementations, the control unit 101 is further configured to:

[0074] A write enable signal is received, and a write data storage unit array is controlled to start a function of writing weight data according to the write enable signal.

[0075] A computing enable signal is received, and a computing unit array is controlled to start a computing function according to the computing enable signal.

[0076] like Figure 1 As shown, W_E is a write enable signal and CIM_E is a calculation enable signal.

[0077] like Figure 2A As shown, when W_E is at a high level, the write function of the write storage cell array is enabled, and the write storage cell array writes the input weight data into the target write data storage cell corresponding to the write address information WADR. When W_E is at a low level, data is prohibited from being written into the write storage cell array.

[0078] like Figure 2B As shown, when CIM_E is at a high level, the calculation function of the calculation unit array is enabled. The target calculation unit in the calculation unit array receives the input data to be calculated and receives the weight data in the corresponding target calculation storage unit, and calculates the data to be calculated and the weight data.

[0079] This embodiment can flexibly control the write function and the calculation function of the two storage cell arrays by receiving the write enable signal and the calculation enable signal, which helps to avoid errors in the function execution of the two storage cell arrays and improves the accuracy of the in-memory calculation.

[0080] In some optional implementations, the control unit 101 is further configured to:

[0081] In response to receiving a read data mode selection signal and read address information, a read data storage cell array for reading weight data is selected from two storage cell arrays according to the read address information, and a target read data storage cell is determined from the read data storage cell array.

[0082] The read data storage unit array is used to: output the weight data stored in the target read data storage unit.

[0083] Specifically, the process of determining the calculation storage unit array and using the calculation unit array to perform calculation in the above embodiment can be performed in the calculation mode. When receiving the read data mode selection signal, the circuit can enter the read data mode.

[0084] In the read data mode, one or two storage cell arrays can be determined as the read data storage cell arrays according to the read address information. For example, each storage cell array may include a data output port, which is connected to each storage cell through a switch. When the control unit 101 receives the read data mode selection signal and the read address information, the data output port can be connected to the target read data storage cell, thereby outputting the weight data in the target read data storage cell.

[0085] This embodiment realizes reading the stored weight data from any one of the two storage cell arrays by receiving a read data mode selection signal, thereby expanding the function of the dual-port storage and computing circuit.

[0086] In some optional implementations, the control unit 101 is further configured to:

[0087] In response to receiving a read data mode selection signal and read address information, the calculation unit array is controlled to start the read data function; the calculation storage unit array is used as a read data storage unit array, and a target read data storage unit is determined from the read data storage unit array according to the read address information.

[0088] Specifically, the computing unit array in this embodiment can be expanded to include two functions: computing mode and data reading mode. The above-mentioned data reading mode selection signal is used to switch the computing unit array from computing mode to data reading mode. Figure 3 As shown, for a computing unit 301, the computing unit can receive a mode selection signal BIST_MODE. When BIST_MODE is 1 (or 0), the computing unit enters a computing mode. When BIST_MODE is 0 (or 1), the computing unit enters a data reading mode.

[0089] The read data storage unit array is further used to:

[0090] The weight data stored in the target read data storage unit is sent to the corresponding target computing unit in the computing unit array.

[0091] The target calculation unit is used to: output the received weight data.

[0092] like Figure 3 As shown, the calculation unit 301 may include a logic control subunit 3011 and a calculation subunit 3012. In the calculation mode (for example, BIST_MODE is 1), the logic control subunit 3011 may store the weight data WD output by the target calculation storage unit corresponding to the calculation unit 301. j and the data to be calculated NN j Input calculation subunit 3012, calculation subunit 3012 calculates WD j and NN j For example, when the calculation subunit 3012 performs the multiplication calculation function, the calculation result is Q=WD j *NN j .

[0093] In the read data mode (for example, BIST_MODE is 0), the target calculation storage unit is used as the target read data storage unit, and the logic control subunit 3011 can store the weight data WD stored in the target read data storage unit. j Direct output, i.e. Q = WD j .

[0094] like Figure 4 As shown, it shows an exemplary timing diagram of reading weight data from the read data storage unit array based on the calculation clock signal. Since the data reading function is performed by the calculation unit array, Figure 4 CLK_CIM, CIMADR and Figure 2B CLK_CIM and CIMADR are the same. In the read data mode, CIMADR is the read address information. Each calculation cycle is a read data cycle. In each read data cycle, the calculation unit array outputs the corresponding weight data Q according to the read address information.

[0095] It should be noted that Figure 3 The circuit results shown are only schematic, and the structures of the above-mentioned logic control subunit 3011 and the calculation subunit 3012 can be set arbitrarily. For example, the logic control subunit 3011 and the calculation subunit 3012 can be set to Figure 3 In the discrete structure shown, the logic control subunit 3011 and the calculation subunit 3012 can also be set in the same logic circuit. As long as the switching between the calculation mode and the data reading mode can be realized, it is within the scope of the present embodiment.

[0096] This embodiment realizes setting the computing units in the computing unit array to have two functions: data calculation and data reading, without setting up a separate weight data output channel, thereby improving the integration of the dual-port storage and computing circuit, helping to reduce the area of ​​the circuit, shortening the data transmission length, and reducing the power consumption of the circuit.

[0097] In some optional implementations, the circuit further includes two word line arrays, and each word line array in the two word line arrays corresponds to one of the two memory cell arrays. Figure 5 As shown, marked as WWL0[0]-WWL Y-1 The word line [0] corresponds to the first memory cell array (i.e., the memory cell array composed of Cell_MUX0), marked as WWL0[1]-WWL Y-1 The word line of [1] corresponds to the second memory cell array (ie, the memory cell array formed by Cell_MUX1).

[0098] The control unit 101 is further configured to:

[0099] According to the write address information, a write data word line array is determined from the two word line arrays, and a target word line for writing weight data is determined from the write data word line array; and a storage cell corresponding to the target word line in the write data storage cell array is determined as a target write data storage cell.

[0100] Write data storage unit array is used to:

[0101] The received weight data is stored in the target write data storage unit using the word line to which the weight data is to be written.

[0102] like Figure 5 As shown, each row of the array composed of dual-port storage and computing circuits corresponds to two word lines, WWL i [0] and WWL i [1], where i is the row number. i [0] corresponds to the first storage cell Cell_MUX0 in row i, WWL i [1] corresponds to the second storage unit Cell_MUX1 in row i. Figure 5 As shown, if the write address information corresponds to Cell_MUX0 of the i-th row of the array, the first storage cell array is a write data storage cell array, WWL0[0]-WWL Y-1 [0] is the write data word line array, WWL of the i-th row i [0] is the target word line, Cell_MUX0 in the i-th row is the target write data storage unit, and the control unit 101 can connect Cell_MUX0 in the i-th row to WWL i[0] is turned on, so that Cell_MUX0 in the i-th row can receive and save the corresponding input weight data.

[0103] This embodiment realizes the selection of any memory cell array in the two memory cell arrays by setting two word lines in each row of the dual-port storage and computing circuit, which helps to efficiently write weight data to any memory cell array and improves the efficiency of data storage and in-memory calculations of the dual-port storage and computing module array.

[0104] In some optional implementations, such as Figure 5 As shown, the circuit further includes an addition tree 103 and a shift accumulator 104 .

[0105] The addition tree 103 is used to accumulate the calculation results corresponding to the same weight output by the calculation unit array to obtain a first accumulation result. Figure 5 As shown, at the end of a round of calculation of the calculation unit array, the addition tree 103 accumulates the calculation results output by the calculation units of each column of the array to obtain the first accumulation result corresponding to each column (such as s0-s1 in the figure). X-1 ). It should be noted that s0-s X-1 are the results of multiplying and adding Y single-bit weight data and the data to be calculated, that is, s0-s X-1 are all multi-bit data. For example, if the number of rows Y is 32, then s0-s X-1 It is the result of multiplication and addition of 32 pairs of single-bit data, and the number of bits can be 6.

[0106] The shift accumulator 104 is used to perform shift accumulation on each first accumulation result to obtain a second accumulation result (SUM0-SUM L-1 ). Generally, when the shift accumulator 104 performs a shift-accumulate operation, it targets s0-s X-1 For example, if the number of columns X involved in the operation is 32, and each row stores 4 (i.e. L is 4) 8-bit weight data, then s0-s X-1 It can be divided into 4 groups, and each group of data performs shift accumulation respectively, and the obtained SUM contains 4 second accumulation results, and each second accumulation result is the result of multiplying and adding Y 8-bit weight data and Y data to be calculated.

[0107] Optionally, since a neural network usually performs multiplication and addition calculations on a one-to-one correspondence of multiple multi-bit input data (such as feature data) and multiple multi-bit weight data, each time the Y single-bit data to be calculated (i.e., NN0–NN Y-1) and multiple single-bit weight data for multiplication and accumulation, the second accumulated results obtained each time can be shifted and accumulated multiple times to obtain the multiplication and addition results of multiple multi-bit input data and multiple multi-bit weight data. For example, the SUM0 obtained by multiple calculations is shifted and accumulated one by one to obtain the multiplication and addition results of the Y multi-bit weight data included in the 0th group and the Y multi-bit input data input.

[0108] This embodiment realizes the calculation and shift accumulation of multiple multi-bit data to be calculated and multiple multi-bit weight data by setting an addition tree and a shift accumulator. Therefore, when the dual-port storage and computing module array is applied to the neural network computing scenario, the neural network calculation and the weight data are written to the dual-port storage and computing circuit at the same time, which improves the efficiency of the neural network calculation.

[0109] The embodiment of the present disclosure further provides a chip, on which a dual-port storage-computing integrated circuit is integrated. The technical details of the dual-port storage-computing integrated circuit are as follows: Figure 1-Figure 5 As shown in the relevant description, no further description is given here.

[0110] The embodiments of the present disclosure also provide an electronic device, which includes the chip described in the above embodiments. In addition, the electronic device may also include an input device, an output device, and necessary memory, etc. Among them, the input device may include such as a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting weight data, feature data, etc. The output device may include such as a display, a printer, and a communication network and its connected remote output device, etc., for outputting calculation results, etc. The memory is used to store the data input by the above input device, and the data generated during the operation of the dual-port storage and calculation integrated circuit. The memory may include volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0111] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0112] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other.

[0113] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0114] The circuits of the present disclosure may be implemented in many ways. For example, the circuits of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the functions of the circuits of the present disclosure. Thus, the present disclosure also covers recording media storing programs for executing the functions of the circuits of the present disclosure.

[0115] It should also be noted that in the circuit of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as an equivalent solution of the present disclosure.

[0116] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0117] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A dual-port storage and computing integrated circuit, comprising: two storage unit arrays, a computing unit array and a control unit; The control unit is used to: receive input write address information and calculate address information; According to the write address information, from the two storage cell arrays, a write data storage cell array to be written with weight data is selected, and a target write data storage cell is determined from the write data storage cell array; According to the calculation address information, a calculation storage cell array participating in the calculation is selected from the two storage cell arrays, and a target calculation storage cell is determined from the calculation storage cell arrays; The write data storage unit array is used to: receive input weight data and store the weight data in the target write data storage unit; The calculation storage unit array is used to: send the weight data stored in the target calculation storage unit to the corresponding target calculation unit in the calculation unit array; The target calculation unit is used to receive input data to be calculated, calculate the data to be calculated and the weight data stored in the target calculation storage unit, obtain a calculation result, and output the calculation result.

2. The circuit according to claim 1, wherein The control unit is further configured to: receiving an input write clock signal, and sequentially determining a target write data storage unit from the write data storage unit array according to the write clock signal and the write address information; An input computing clock signal is received, and a target computing storage unit is sequentially determined from the computing storage unit array according to the computing clock signal and the computing address information.

3. The circuit according to claim 1, wherein: The control unit is further configured to: Receive a write enable signal, and control the write data storage unit array to enable a function of writing weight data according to the write enable signal; A computing enable signal is received, and the computing unit array is controlled to start a computing function according to the computing enable signal.

4. The circuit according to claim 1, wherein: The control unit is further configured to: In response to receiving a read data mode selection signal and read address information, selecting a read data storage cell array for reading weight data from the two storage cell arrays according to the read address information, and determining a target read data storage cell from the read data storage cell array; The read data storage unit array is used to: output the weight data stored in the target read data storage unit.

5. The circuit according to claim 4, wherein: The control unit is further configured to: In response to receiving the read data mode selection signal and the read address information, controlling the calculation unit array to enable a read data function; Using the calculation storage unit array as a read data storage unit array, and determining a target read data storage unit from the read data storage unit array according to the read address information; The read data storage unit array is further used to: send the weight data stored in the target read data storage unit to the corresponding target computing unit in the computing unit array; The target calculation unit is used to output the received weight data.

6. The circuit according to claim 1, wherein: The target calculation unit includes a multiplier, which is used to perform multiplication calculation on the data to be calculated and the weight data stored in the target calculation storage unit to obtain a calculation result and output the calculation result.

7. The circuit according to claim 1, wherein: The circuit further comprises two word line arrays, each of the two word line arrays corresponding to one of the two memory cell arrays; The control unit is further configured to: Determine a write data word line array from the two word line arrays according to the write address information, and determine a target word line for writing weight data from the write data word line array; determining a storage cell in the write data storage cell array corresponding to the target word line as a target write data storage cell; The write data storage unit array is used to store the received weight data into the target write data storage unit by using the word line of the weight data to be written.

8. The circuit according to any one of claims 1 to 7, wherein: The circuit also includes an addition tree and a shift accumulator; The addition tree is used to accumulate the calculation results corresponding to the same weight output by the calculation unit array to obtain a first accumulation result; The shift accumulator is used to perform shift accumulation on each first accumulation result to obtain a second accumulation result.

9. A chip comprising the dual-port storage-computation integrated circuit according to any one of claims 1-8.

10. An electronic device comprising the chip according to claim 9.

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