Silicon carbide device

Abstract

The invention relates to a silicon carbide device. A method for forming an interfacial layer on a silicon carbide body includes removing an oxide layer from a surface of the silicon carbide body to obtain a silicon carbide surface. The silicon carbide body includes a source region of a first conductivity type and a body region of a second conductivity type. The method further includes depositing an interface layer directly on the silicon carbide surface after removing the oxide layer. The interfacial layer has a thickness less than or equal to 15 nm. The method further includes forming an electrical insulator over the interface layer; and forming a gate electrode over the electrical insulator.

Description

Technical Field

[0001] Examples of the present disclosure relate to a silicon carbide device, in particular to a silicon carbide device having a gate electrode and an electrical insulator disposed between the gate electrode and the silicon carbide body of the silicon carbide device and to a corresponding method for forming the electrical insulator. Background Art

[0002] In a transistor, the gate electrode is typically electrically insulated from the source region, body region, and drift / drain region of the transistor, and is positioned adjacent to the body region. The source region is typically connected to a source terminal, and the drain region is typically connected to a drain terminal. For silicon carbide devices, it may be desirable to adjust the electrical insulator between the gate electrode and the silicon carbide body. Summary of the invention

[0003] A method for forming an interface layer on a silicon carbide body may include: removing an oxide layer from a surface of the silicon carbide body to obtain a silicon carbide surface. The silicon carbide body may include a source region of a first conductivity type and a body region of a second conductivity type. The method may also include: depositing the interface layer directly on the silicon carbide surface after removing the oxide layer. The interface layer may have a thickness of less than or equal to 15 nm. The method may also include: forming an electrical insulator on the interface layer; and forming a gate electrode on the electrical insulator.

[0004] A silicon carbide device may include: a source region of a first conductivity type formed in a silicon carbide body, a main region of a second conductivity type formed in the silicon carbide body, and a drain region. In addition, the silicon carbide device may include: a gate electrode configured to switch current between the source region and the drain region. The silicon carbide device may also include: an interface layer directly disposed on the silicon carbide body and arranged between the silicon carbide body and the gate electrode. The thickness of the interface layer may be less than or equal to 15nm. The interface layer may include a first surface in contact with the silicon carbide body and a second surface opposite to the first surface. The concentration of carbon in the interface layer may decrease from a first concentration of carbon at the first surface of the interface layer to a second concentration of carbon at the second surface of the interface layer opposite to the first surface of the interface layer in a direction pointing from the first surface to the second surface. The concentration of carbon may be less than half of the first concentration in at least 75% of the interface layer. The silicon carbide device may also include: an electrical insulator disposed between the interface layer and the gate electrode. The electrical insulator may be configured to electrically insulate the gate electrode from the silicon carbide body. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, wherein like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily drawn to scale relative to each other. The features of the various illustrated examples can be combined unless they exclude each other.

[0006] Figure 1AA vertical cross-sectional view of a silicon carbide device, particularly a vertical silicon carbide device with a planar gate, is shown.

[0007] Figure 1B A vertical cross-sectional view of a silicon carbide device, particularly a vertical silicon carbide device having a gate disposed in a trench, according to the present disclosure is illustrated.

[0008] Figure 1C A typical profile of carbon concentration within the interface layer is shown.

[0009] Figure 1D Graph showing the profile of carbon concentration within an interfacial layer according to the present disclosure.

[0010] Figure 1E Graph showing the profile of carbon concentration within an interfacial layer according to the present disclosure.

[0011] Figure 2 A vertical cross-sectional view illustrating an electrical insulator of a silicon carbide device disposed between a silicon carbide body and a gate electrode according to the present disclosure.

[0012] Figure 3 A vertical cross-sectional view illustrating an electrical insulator of a silicon carbide device disposed between a silicon carbide body and a gate electrode according to the present disclosure.

[0013] Figure 4 A method for forming an electrical insulator and a gate electrode on a silicon carbide body of a silicon carbide device according to the present disclosure is illustrated.

[0014] Figures 5A-5D A vertical cross-sectional view illustrating an electrical insulator of a silicon carbide device disposed between a silicon carbide body and a gate electrode according to the present disclosure.

[0015] Figures 6A-6D A vertical cross-sectional view of a silicon carbide device (particularly, a lateral silicon carbide device) according to the present disclosure is illustrated.

[0016] Figures 7A-7D A vertical cross-sectional view of a silicon carbide device (particularly, a vertical silicon carbide device) according to the present disclosure is illustrated.

[0017] Figure 8 A method for forming an electrical insulator and a gate electrode on a silicon carbide body of a silicon carbide device according to the present disclosure is illustrated.

[0018] Figures 9A-9E A vertical cross-sectional view illustrating an electrical insulator of a silicon carbide device disposed between a silicon carbide body and a gate electrode according to the present disclosure.

[0019] Figures 10A-10E A vertical cross-sectional view of a silicon carbide device (particularly, a lateral silicon carbide device) according to the present disclosure is illustrated.

[0020] Figures 11A-11E A vertical cross-sectional view of a silicon carbide device (particularly, a vertical silicon carbide device) according to the present disclosure is illustrated. DETAILED DESCRIPTION

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific embodiments of silicon carbide devices can be implemented are shown as illustrations. It should be understood that other embodiments can be used and structural or logical changes can be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment can be used on other embodiments or used in combination with other embodiments to produce another embodiment. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only.

[0022] If not indicated otherwise, corresponding elements are designated by the same reference numerals in different drawings.

[0023] The terms "having", "containing", "including", "comprising" and the like are open ended and indicate the presence of stated structures, elements or features but do not exclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0024] The term "electrically connected" may describe a permanent low resistance ohmic contact between electrically connected elements, such as a direct contact between the elements involved or a low resistance connection via metal and / or heavily doped semiconductor material.

[0025] The term "electrically coupled" may include that one or more intermediate elements suitable for signal and / or power transfer may be connected between the electrically coupled elements, such as elements that can be controlled to temporarily provide a low resistance connection in a first state and a high resistance electrical decoupling in a second state.

[0026] The term "ohmic contact" may describe a non-rectifying electrical junction between two electrically connected elements. An ohmic contact may have a linear or nearly linear current-voltage (IV) characteristic, such as a linear IV curve in the first and third quadrants of an IV diagram consistent with Ohm's law.

[0027] The accompanying drawings illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.

[0028] Two adjacent doped regions of the same conductivity type and having different dopant concentrations may form a unipolar junction, for example, an n / n+ or p / p+ junction along the boundary surface between the two doped regions. At a unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may show a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa.

[0029] Ranges given for physical dimensions include the boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value (e.g., "at most" and "at least").

[0030] The term “on” should not be interpreted as meaning “directly on.” Conversely, if an element is disposed “on another element” (e.g., a layer is “on another layer” or “on a substrate”), another component (e.g., another layer) may be disposed between the two elements (e.g., if a layer is “on a substrate,” another layer may be disposed between the layer and the substrate).

[0031] The terms “power semiconductor device” and “SiC power device” may refer to a semiconductor device having a high voltage blocking capability of at least 30 V (e.g., 100 V, 600 V, 1.6 kV, 3.3 kV, or greater) and having a nominal on-state current or forward current of at least 1 A (e.g., 10 A or greater).

[0032] A silicon carbide device may include a transistor cell having a gate electrode and a source region. The source region may be formed in a silicon carbide body and has a conductivity type.

[0033] The silicon carbide body may have: two essentially parallel main surfaces (such as, a first main surface and a second main surface), which may have approximately the same shape and size; and a side surface, connecting the edges of the two main surfaces. For example, the silicon carbide body may be a cylinder or a polygonal (e.g., rectangular or hexagonal) prism with or without rounded edges. The silicon carbide body may have surface extensions along two horizontal directions, and may have a thickness along a vertical direction perpendicular to the horizontal direction. In the following, the horizontal direction is also referred to as the lateral direction.

[0034] As an example, the material of the silicon carbide body can be single-crystalline silicon carbide, such as 15R-SiC (silicon carbide of 15R polymorph) or silicon carbide with a hexagonal polymorph, such as 2H-SiC, 4H-SiC or 6H-SiC. In addition to the main components silicon and carbon, the silicon carbide body can also include dopant atoms, such as nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al) and / or gallium (Ga). The silicon carbide body can include additional impurities, such as hydrogen, fluorine and / or oxygen.

[0035] The transistor cell may be or may include an insulated gate transistor cell having an insulated gate electrode. The gate electrode may be a planar gate electrode formed on the first main surface of the silicon carbide body, or may be a trench gate electrode formed in a trench extending from the first main surface into the silicon carbide body. A combination of planar and trench gate electrodes may also be possible.

[0036] The silicon carbide body may also include a drain / drift region. At least a portion of the drain / drift region may have the same conductivity type as the source region and may effectively serve as a drain of the transistor cell.

[0037] The transistor cell may also include a body region of a conductivity type complementary to the source region and the drift / drain region. The body region may spatially separate portions of the source region and the drain / drift region. A gate dielectric may be formed between the gate electrode and the body region. The potential applied to the gate electrode controls the distribution of mobile charge carriers in the body region through a field effect.

[0038] Figure 1A The figure shows a vertical cross-sectional view of a silicon carbide device 1 (particularly, a vertical silicon carbide device with a planar gate structure). The silicon carbide device 1 includes a silicon carbide body 100 and one or more device primitives 10a, 10b integrated in the silicon carbide body 100. In the following, the device primitive will also be referred to as a transistor primitive. Figure 1A In FIG. 1 , only one device cell 10 is illustrated. However, the silicon carbide device 1 may include more than two device cells, such as tens, hundreds, thousands, tens of thousands, hundreds of thousands, or even millions of device cells, integrated in one silicon carbide body 100 . Figure 1A , the transistor cells 10a and 10b each include a source region 12, a body region 13, and a drift / drain region 14. The body region 13 may be arranged between the source region 12 and the drift / drain region 14.

[0039] Reference Figure 1A, the device cell 10a, 10b also includes a gate electrode 21, which is arranged on top of the silicon carbide device 1 (e.g., arranged above a portion of the body region 13) and is electrically insulated from the silicon carbide body 100 including the source region 12, the body region 13 and the drift / drain region 14 by an electrical insulator 22. For example, the electrical insulator 22 can be implemented as silicon oxide (SiO2) or as a high-k material, and can be arranged between the gate electrode 21 and the silicon carbide body 100. In some examples, the electrical insulator 22 can also extend over the source region 12 and the body region 13 (e.g., as a layer covering the silicon carbide body 100). The gate electrode 21 of the device cell 10 can have a surface 21a (e.g., a planar surface) in contact with the electrical insulator 22. The body region 13 of the device cell 10 can be adjacent to the electrical insulator 22, so that the gate electrode 21 is arranged above the electrical insulator 22 and above the body region 13.

[0040] Still refer to Figure 1A , an electrical insulating layer (insulating layer) 51 may cover the electrical insulator 22 and the gate electrode 21. The insulating layer 51 may have contact openings 52a, 52b, in which the insulating layer 51 and the electrical insulator 22 may expose the source region 12a of the device cell 10a and the source region 12b of the device cell 10b. The first and second source electrodes 41a, 41b may be formed in or on the insulating layer 51 and formed in the contact openings 52a, 52b. The source electrodes 41a, 41b may be electrically insulated from the gate electrode 21 by the insulating layer 51, and the source regions 12a and 12b may be electrically connected to the source terminal S (only in the case of the source region 12a and 12b). Figure 1A ), or may form a source terminal S. The source electrode 41 may be made of or include a material such as titanium (Ti), platinum (Pt), nickel (Ni), aluminum (Al), copper (Cu), a metal alloy (such as a nickel alloy), or the like.

[0041] Still refer to Figure 1A , the silicon carbide device 1 may further include a drain / drift region 14 adjacent to the body region 13. A drain electrode (not shown) may be formed on the second main surface of the silicon carbide body 100. The drain electrode may be made of or include a material such as titanium (Ti), platinum (Pt), nickel (Ni), aluminum (Al), copper (Cu), a metal alloy (such as a nickel alloy), etc.

[0042] A plurality of device cells 10a, 10b may be connected in parallel by connecting the individual source regions 12a, 12b to the source terminal S via the source electrodes 41a and 41b, by connecting the individual drain regions 14 to the drain terminal, and by electrically connecting the individual gate electrodes 21 to the common gate terminal G. The connection of the gate electrode 21 to the gate terminal G is only possible at Figure 1ASchematically illustrated in FIG.

[0043] Figure 1A The silicon carbide device 1 is a MOS transistor device, which can be implemented as an n-type device or as a p-type device. In an n-type device, the source region 12 and the drain / drift region 14 are n-doped, while the body region 13 is p-doped. In a p-type device, the source region 12 and the drain / drift region 14 are p-doped, while the body region 13 is n-doped.

[0044] By applying a load voltage between the drain and source terminals and by applying a drive potential to the gate electrode G, Figure 1A The silicon carbide device 1 is capable of operating like a conventional MOS transistor. This operating principle is briefly explained with reference to an n-type silicon carbide device 1. However, this operating principle also applies to p-type devices, where in p-type devices, the polarity of the voltage explained below must be reversed. When a load voltage is applied between the drain and source terminals, the silicon carbide device 1 is in a forward operating mode. In an n-type device, this voltage is a positive voltage. In the forward operating mode, the MOS transistor can be turned on and off by a drive potential applied to the gate terminal G. When the drive potential applied to the gate terminal G produces a conductive channel in the body region 13 between the source region 12 and the drain / drift region 14, the MOS transistor is turned on (in the on state), and when the conductive channel in the body region 13 is interrupted, the MOS transistor is turned off (in the off state). The absolute value of the drive potential that turns the transistor device on or off depends on the specific type of the transistor device.

[0045] The device cell 10 includes a channel region, which is a region of the body region 13 along the electrical insulator 22. The channel region along the electrical insulator 22 enables charge carriers to flow from the source region 12 to the drain / drift region 14 when the transistor device is in an on-state.

[0046] The doping concentration of the drain / drift region 14 is, for example, 1E14 cm -3 and 1E17 cm -3 (in the drift region), and for example above 1E19 cm -3 (in the drain region). The doping concentration of the body region 13 is, for example, 5E16 cm -3 and 5E17 cm -3 The doping concentration of the source region 12 is, for example, higher than 1E19 cm -3 .

[0047] The gate electrode 21 can be an elongated gate electrode 21. For example, in Figure 1AThe gate electrode 21 can be connected to the gate terminal G at one or more locations not visible in the vertical cross-sectional view of FIG. The source electrodes 41a, 41b can cover the insulating layer 51 in the region where the contact openings 52a, 52b are located, and can be electrically connected to the source regions 12a, 12b in the contact openings 52a, 52b. The gate connection electrode ( Figure 1A ) may be separated from the source electrode 41 and the drain electrode 43 in the first lateral direction x, and may be arranged at a contact opening ( Figure 1A The insulating layer 51 is covered in those areas where the gate connection electrode 42 is located. Figure 1A (not shown) is electrically connected to the gate electrode 21.

[0048] Figure 1B A vertical cross-sectional view of a silicon carbide device 1, in particular, a vertical silicon carbide device, and more particularly, a vertical silicon carbide power device (optionally with an integrated diode) is shown. The silicon carbide device 1 includes a silicon carbide body 100 and one or more device primitives 101, 102 integrated in the silicon carbide body 100. In the following, the device primitive will also be referred to as a transistor primitive. Figure 1B In FIG. 1 , only two device cells 101 , 102 are illustrated. However, the silicon carbide device 1 may include more than two device cells integrated in one silicon carbide body 100 , such as tens, hundreds, thousands, tens of thousands, hundreds of thousands, or even millions of device cells.

[0049] exist Figure 1B In the embodiment of the present invention, the two device primitives 101, 102 are labeled with different reference numerals, while similar features of the individual device primitives 101, 102 are labeled with similar reference numerals. Figure 1B Each transistor cell 101, 102 includes a drift region 11, a source region 12, and a body region 13. The body region 13 may be arranged between the source region 12 and the drift region 11. Each device cell 101, 102 may also (optionally) include a diode region 30 and a pn junction formed between the diode region 30 and the drift region 11. Figure 1B In the embodiment of FIG. 1 , the individual device cells 101 and 102 share the drift region 11 . That is, the individual device cells 101 and 102 have one drift region 11 in common.

[0050] Reference Figure 1B, each device cell 101, 102 further comprises a gate electrode 21, which is arranged in the trench and is electrically insulated from the silicon carbide body 100 including the body region 13, the diode region 30 and the drift region 11 by an electrical insulator 22. For example, the electrical insulator 22 may be implemented as silicon oxide (SiO2) or as a high-k material. The trench with the gate electrode 21 of each device cell 101, 102 has a first sidewall 1101, a second sidewall 1102 opposite to the first sidewall 1101, and a bottom 1103. The body region 13 of each device cell 101, 102 is adjacent to the first sidewall 1101 of the corresponding trench, the diode region 30 is adjacent to the second sidewall 1102 of the corresponding trench, and the pn junction between the drift region 11 and the diode region 30 is adjacent to the bottom 1103 of the corresponding trench.

[0051] Still refer to Figure 1B , the individual diode region 30 of one device cell (such as device cell 101) may extend from the first surface 101 of the silicon carbide body 100 adjacent to the source region 12 and the body region 13 of an adjacent device cell (such as device cell 102) into the drift region 11 where the pn junction is formed. An electrically insulating layer (insulating layer) 51 may cover the first surface 101 and the gate electrode 21. The insulating layer 51 may have a contact opening 52, in which the insulating layer 51 may expose the diode region 32 and the source region 12 of the individual device cells 101, 102. The source electrode 41 may be formed on the insulating layer 51 and in the contact opening 52. The source electrode 41 may be electrically insulated from the gate electrode 21 by the insulating layer 51, and may electrically connect the individual diode region 30 and the individual source region 12 to the source terminal S (only in the case of the gate electrode 21). Figure 1B ), or may form a source terminal S. Optionally, the source electrode 41 may include: a first source electrode layer 411, electrically contacting the diode region 30 and the source region 12; and a second source electrode layer 412, electrically connecting the first source electrode layer 411. The second source electrode layer 412 may be connected to the source terminal S, or may form the source terminal S of the silicon carbide device 1. The first electrode layer 411 may include, for example, titanium (Ti), platinum (Pt), a nickel alloy, etc. The second electrode layer 412 may include, for example, aluminum (Al), copper (Cu), etc.

[0052] Still refer to Figure 1B The silicon carbide device 1 may further include a drain region 14 adjacent to the drift region 11. Optionally, a field stop region (not shown) of the same doping type as the drift region 11 but more highly doped in the drift region 11 is arranged between the drift region 11 and the drain region 14. The drain region 14 may be electrically connected to the drain terminal D (only in Figure 1B). The individual device cells 101, 102 may share one drain region 14. That is, there may be one drain region 14 that is common to the individual device cells 101, 102.

[0053] The individual device cells 101, 102 can be connected in parallel by connecting the individual source regions 12 to the source terminal S via the source electrode 41, by sharing the drain region 14 and connecting the drain region 14 to the drain terminal D, and by connecting the individual gate electrodes 21 electrically to the common gate terminal G. The connection of the gate electrode 21 to the gate terminal G is only at Figure 1B Schematically illustrated in FIG.

[0054] Figure 1B The silicon carbide device 1 is a MOS transistor device with an integrated diode. The transistor device can be implemented as an n-type device or as a p-type device. In an n-type device, the source region 12 and the drift region 11 are n-doped, while the body region 13 is p-doped. In a p-type device, the source region 12 and the drift region 11 are p-doped, while the body region 13 is n-doped.

[0055] In addition, the transistor device can be implemented as a MOSFET or as an IGBT. In a MOSFET, the drain region 14 has the same doping type as the source region 12 and the drift region 11, while in an IGBT, the drain region 14 has a doping type complementary to the doping type of the source region 12 and the drift region 11. In an IGBT, the drain region 14 is also called a collector region.

[0056] The diode region 30 may have the same doping type as the body region 13, which is a doping type complementary to the doping type of the drift region 11. Figure 1B The diode region 30 of the device cell 101 in FIG. 1 and the adjacent device cell (such as Figure 1B The main regions 13 of the device cells 102 in the device cell 102 are adjacent, so the main region 13 of each device cell is electrically connected to the source electrode 41 through the diode region 30 of the adjacent device cell. Optionally, each diode region 30 includes two differently doped silicon carbide regions, that is: a first region 31, adjacent to the drift region 11 and forming a pn junction with the drift region 11; and a second region 32, electrically connecting the first region 31 to the source electrode 41. The second region 32 will also be referred to as the contact region below, and may have a higher doping concentration than the first region 31. Figure 1B In an embodiment of the present invention, a device primitive (such as, Figure 1B The contact region 32 of the device cell 101 in the embodiment of the present invention can be adjacent to the second sidewall of the corresponding trench and electrically connect the adjacent device cell (such as, Figure 1B The main region 13 of the device cell 102 in the embodiment is connected to the source electrode 41.

[0057] The diode region 30 of each device cell 101, 102 can form a diode with the drift region 11 and the drain region 14. The circuit symbol of such a diode is also shown in FIG. Figure 1B middle( Figure 1B The polarity of the circuit symbols illustrated in relates to n-type silicon carbide devices; in p-type devices, the polarity is reversed). The respective pn junctions formed between the diode region 30 and the drift region 11 of the individual device cells 101, 102 are connected in parallel and in parallel with the load path (drain-source path) of the MOS transistor. The drain-source path of the MOS transistor is an internal path between the drain terminal D and the source terminal S. When a voltage having a first polarity is applied between the drain and source terminals D, S of the MOS transistor, the individual diode is reverse biased (blocked), and when a voltage having a second polarity is applied between the drain and source terminals D, S, the individual diode is forward biased (conducted). In an n-type silicon carbide device, when a positive voltage is applied between the drain and source terminals D, S, the diode is reverse biased, and when a negative voltage is applied between the drain and source terminals D, S (the negative voltage is a positive voltage between the source and drain terminals S, D), the diode is forward biased. The individual diode is connected in parallel with the body diode of the transistor cell. The body diode is a diode formed by the body region 13 and the drift region 11 of the individual device cells 101, 102. However, unlike the body diode, the properties of the diode between the diode region 30 and the drift region 11 can be widely adjusted independently of the properties of the MOS transistor. In particular, by implementing the diode region 30 so that the pn junction between the diode region 30 and the drift region 11 has a relatively large area, the diode between the diode region 13 and the drift region 11 can be implemented to have a high rated current.

[0058] By applying a load voltage between the drain and source terminals D, S and by applying a drive potential to the gate electrode G, Figure 1BThe silicon carbide device 1 can operate like a conventional MOS transistor. This operating principle is briefly explained with reference to an n-type silicon carbide device. However, this operating principle is also applicable to p-type devices, in which the polarity of the voltage explained below must be reversed in the p-type device. When a load voltage is applied between the drain and source terminals D, S, the silicon carbide device is in a forward operating mode, and the load voltage reversely biases the body diode and the additional diode (the diode between the diode region 30 and the drift region 11) of the individual device primitives 101, 102. In an n-type device, this voltage is a positive voltage. In the forward operating mode, the MOS transistor can be turned on and off by a driving potential applied to the gate terminal G. When the driving potential applied to the gate terminal G generates a conductive channel in the body region 13 between the source region 12 and the drift region 11, the MOS transistor is turned on (in an on state), and when the conductive channel in the body region 13 is interrupted, the MOS transistor is turned off (in an off state). The absolute value of the drive potential that turns a transistor device on or off depends on the specific type of transistor device (enhancement mode device or depletion mode device).

[0059] The silicon carbide device 1 is in a reverse operation mode when a voltage is applied between the drain and source terminals D, S, which voltage forward biases the body diode and the additional diode. In this operation mode, the silicon carbide device 1 can only be controlled by the polarity of the load voltage, but not by the drive potential applied to the gate terminal G.

[0060] When the silicon carbide device 1 is in the forward operation mode, and when the silicon carbide device 1 is turned off, the pn junction between the diode region 30 and the drift region 11 and the pn junction between the main region 13 and the drift region 11 are reverse biased, so that the depletion region expands in the drift region 11. When the load voltage increases, the depletion region expands deeper in the drift region 11 in the direction of the drain region 14. When the load voltage increases and the depletion region expands deeper in the drift region 11, the electric field strength at the pn junction also increases. Since the pn junction between the main region 13 and the first drift region 11 is close to the electrical insulator 22, the electrical insulator 22 may be damaged when a high load voltage is applied, that is, when a high field strength occurs. However, in Figure 1BIn the silicon carbide device 1, the diode regions 30 of two adjacent device elements 101, 102 can be used as a JFET (junction field effect transistor) together with the drift region 11. Such a JFET has a channel region 111 between the two adjacent diode regions 30. As the load voltage increases and as the potential of the drift region 11 increases, the JFET pinches off the channel region 111 and prevents the field strength of the electric field of the pn junction between the body region 13 and the drift region 11 from further increasing when the load voltage further increases. The load voltage at which the channel 111 of the JFET is pinched off depends, for example, on the distance between the two adjacent diode regions 30 in the lateral direction of the silicon carbide body 100. The "lateral direction" of the silicon carbide body 100 is perpendicular to the vertical direction, in which the drain region 14 is separated from the body region 13 and the diode region 30, and the "lateral direction" is essentially parallel to the first surface 101. Such a lateral distance between two adjacent diode regions 30 is, for example, between 0.5 μm (micrometer) and 2 μm (micrometer), or between 0.25 and 1.5 times the width of the trench accommodating the gate electrode 21. The “width” of the trench is the distance between the first and second sidewalls 1101, 1102. In the case where the trench is tapered, such as Figure 1B In the embodiment shown, the width is the maximum distance between the first and second side walls.

[0061] Each device cell 101, 102 includes a channel region, which is a region of the body region 13 along the electrical insulator 22 or an optional channel region 15 (in Figure 1B 1). When the transistor device is in the on state, the channel region along the electrical insulator 22 enables charge carriers to flow from the source region 12 to the drift region 11. The diode region 30 of each device cell 101, 102 does not overlap with the channel region. That is, the pn junction between the diode region 30 and the drift region 11 is adjacent to the bottom of the individual gate trenches and does not extend beyond the gate trenches in the direction of the channel region. Therefore, the diode region 30 does not constrain the flow of charge carriers from the channel region to the drain region 14.

[0062] The voltage blocking capability of the silicon carbide device 1 depends in particular on the distance between the diode region 30 and the drain region 14. This distance can be adjusted during the manufacturing process according to the desired voltage blocking capability. According to experience, in the silicon carbide body 100, the distance between the drain region 14 and the diode region 30 is between 0.8 micrometers and 1.0 micrometers per 100V of voltage blocking capability.

[0063] The doping concentration of the drift region 11 is, for example, 1E14 cm -3 and 1E17 cm -3 The doping concentration of the main region 13 is, for example, 5E16 cm -3 and 5E17 cm -3The doping concentration of the source region and the drain region 12, 14 is, for example, higher than 1E19 cm -3 The doping concentration of the diode region 30 is, for example, 1E18 cm -3 and 1E19 cm -3 between.

[0064] Still refer to Figure 1B , the body region 13 of each device element 101, 102 is adjacent to the corresponding gate trench at the first side wall 1101. In particular, when the gate trench has a tapered side wall, the first and second side walls 1101, 1102 may correspond to different crystal planes of the crystal lattice of the silicon carbide body 100. According to one embodiment, the silicon carbide body 100 includes a hexagonal SiC crystal, and the gate trench has a tapered side wall so that the first side wall 1101 corresponds to the 11-20 plane in the SiC crystal. In this case, the individual channel regions are characterized by a relatively low resistance. In this embodiment, the first side wall 1101 is aligned with the c-axis of the crystal of the silicon carbide body. The c-axis (hexagonal principal axis) is perpendicular to the growth plane (0001 plane) of the SiC crystal. Such a growth plane is not shown in the figure. Figure 1B The bottom 1103 of the groove is substantially parallel to the first surface 101 .

[0065] The angle α (alpha) between the first sidewall 1101 of the trench 110 and the first surface 101 depends on the orientation of the first surface relative to the growth plane (0001 plane). According to one embodiment, the first surface 101 is inclined relative to the growth plane, wherein the angle between the first surface 101 and the growth plane may be between 1° and 10°, in particular between 2° and 8°. In this case, α is between 80° (90°-10°) and 89° (90°-1°), and in particular between 82° (90°-8°) and 88° (90°-2°). According to a specific embodiment, the angle between the first surface 101 and the growth plane is 4°, whereby the angle α between the first surface 101 and the first sidewall 1101 of the trench 110 is 86°. There is a high charge carrier mobility along the 11-20 plane in the SiC crystal, whereby the alignment of the first sidewall with the c-axis results in a low resistance in the channel region along the electrical insulator 22 in the body region 13.

[0066] The gate trench can be an elongated trench wherein Figure 1B The gate electrode 21 can be connected to the gate terminal electrode at a position not visible in the vertical cross-sectional view of FIG.

[0067] The gate connection electrode (gate runner) 42 may be spaced apart from the source electrode 41 in the first lateral direction x and cover the insulating layer 51 in those regions where the second contact openings 52 are arranged. The gate connection electrode 42 is electrically connected to the gate electrode 21 in the second contact openings 53.

[0068] In silicon carbide MOSFET devices, charge trapping is a known problem that may be caused by defects at the interface between the silicon carbide body and the electrical insulator that insulates the gate electrode from the silicon carbide body. Charge trapping may cause the electrical parameters of the silicon carbide device to drift during operation, which is undesirable. In particular, charge trapping may occur when carbon atoms are present in the interface layer between the silicon carbide body and the electrical insulator that insulates the gate electrode from the silicon carbide body. Typically, such an interface layer is formed by oxidizing (or oxynitriding) the silicon carbide body to silicon oxide (or silicon oxynitride), for example, by annealing. Oxidizing (or oxynitriding) the silicon carbide body not only results in silicon oxide (silicon oxynitride), but also leaves behind carbon atoms incorporated in the silicon oxide (silicon oxynitride). The presence of these carbon atoms may be the cause of charge trapping. As such, it may be desirable to reduce the amount of carbon atoms in the interface layer between the silicon carbide body and the electrical insulator that insulates the gate electrode.

[0069] Figure 1C The silicon carbide body 100 and the electrical insulator 220 (such as Figure 1A and 1B 1 and 2 ) between the gate electrode 21 and the electrical insulator 220, which insulates the gate electrode 21 from the interfacial layer 210 and / or from the silicon carbide body 100. Typically, carbon atoms are incorporated into the interfacial layer 210 due to oxidation (or oxynitride) of the silicon carbide body. As such, the carbon concentration C along a cross-section through the silicon carbide body 100, the interfacial layer 210, and the electrical insulator 220 may be non-zero in the interfacial layer 210, and may generally decrease across the interfacial layer 210 (e.g., decreasing from a first carbon concentration C1 at a first surface 301 of the interfacial layer 210 in contact with the silicon carbide body 100 to approximately zero within the electrical insulator 220). As discussed above, the presence of carbon atoms may cause charge trapping.

[0070] The first carbon concentration C1 at the first surface 301 may be approximately the same as the carbon concentration within the silicon carbide body 100 (which may be approximately 0.5). The carbon concentration C within the interface layer may then decrease to reach half of the first carbon concentration at a distance d1 relative to the first surface 301 (this point 10011 of the profile 10001 is at Figure 1Cd1). A typical value of distance d1 is 1 to 2 nm. In addition, distance d1 is generally located approximately in the middle between first surface 301 and second surface 302 of interface layer 210. In other words, carbon concentration C is generally greater than half of first carbon concentration C1 in approximately 50% of interface layer 210 (i.e., the region from first surface 301 to distance d1), and less than the first carbon concentration in the remainder of the interface layer (i.e., from first distance d1 to second surface 302). That is, distance d1 may be approximately half of thickness t of interface layer 210.

[0071] For example, by depositing the interface layer 210 as further described below, the method according to the present disclosure may allow obtaining an interface layer 210 having a reduced amount of carbon in the interface layer 210. This may prevent carbon atoms from being incorporated into the interface layer 210. However, some carbon atoms may still diffuse from the silicon carbide body 100 into the interface layer 210 (e.g., due to subsequent processing steps). As such, the profile of the carbon concentration (when using the method according to the present disclosure) may not necessarily show a sharp drop (such as a step) at the first surface 301 of the interface layer 210, but some carbon atoms may still be incorporated into the interface layer 210. Figure 1D and 1E For example, within more than 75% of the interface layer 210 or within more than 90% of the interface layer 210 , the carbon concentration C may be less than half of the first carbon concentration C1 ( C1 is at the first surface 301 of the interface layer 210 ).

[0072] Figure 1D and 1E Each of the diagrams illustrates a profile 10002, 10003 of a carbon concentration C within an interface layer 210 according to the present disclosure. In some embodiments, the interface layer 210 is deposited on a (cleaned) silicon carbide surface of a silicon carbide body 100 by atomic layer deposition (ALD) or in an epitaxial manner. This may allow fewer carbon atoms to be incorporated into the interface layer 210, which may reduce charge trapping. According to the present disclosure, the interface layer 210 is placed directly on the silicon carbide body 100 and is arranged between the silicon carbide body 100 and an electrical insulator 220, which insulates the gate electrode 21 from the silicon carbide body 100 and / or from the interface layer 210. The thickness t of the interface layer may be less than or equal to 15 nm. The interface layer may include a first surface 301 in contact with the silicon carbide body 100 and a second surface 302 opposite to the first surface 301. The concentration of carbon in the interface layer 210 may decrease along a direction d directed from the first surface 301 to the second surface 302 from a first concentration C1 of carbon at the first surface 301 of the interface layer 210 to a second concentration C2 of carbon at the second surface 302 of the interface layer 210 opposite to the first surface 301 .

[0073] In an embodiment, the carbon concentration C is less than half of the first concentration C1 in at least 75% of the interface layer 210. Figure 1D , where point 10012 is on contour 10002. In other words, distance d1 may be approximately 0.25 of the thickness t of interface layer 210.

[0074] In another embodiment, the carbon concentration C in at least 90% of the interface layer 210 is less than half of the first concentration C1. Figure 1E , where point 10013 is on contour 10003. In other words, distance d1 may be approximately 0.1 of the thickness t of interface layer 210.

[0075] exist Figure 1D and 1E In the embodiment, the distance d1 from the first surface 301 to the points 10012 , 10013 at which the carbon concentration reaches half of the carbon concentration C1 present on the first surface 301 may be less than 1 nm.

[0076] Reference Figure 2 According to the present disclosure, a silicon carbide device 1 (such as, Figure 1A and 1B The silicon carbide device 1) shown in the figure includes a source region 12 of a first conductivity type formed in a silicon carbide body 100, a body region 13 of a second conductivity type formed in the silicon carbide body, a drain region 14, a gate electrode 21 configured to switch current between the source region 12 and the drain region 14, and an electrical insulator 22, 220, which is arranged between the gate electrode 21 and the silicon carbide body 100 and is configured to electrically insulate the gate electrode 21 from the silicon carbide body 100. In addition, the silicon carbide device includes an interface layer 210, which is arranged between the silicon carbide body 100 and the electrical insulator 220. The electrical insulator 220 may include a material different from that of the interface layer 210, or consist of the material. The interface layer 210 is in direct contact with the silicon carbide body 100. The thickness t of the interface layer 210 is less than or equal to 15 nm (nanometers), in particular less than or equal to 10 nm or 5 nm. In other examples, the interface layer 210 can have a thickness t less than or equal to 4 nm, 3 nm, or 2 nm, or can be a monolayer (i.e., a layer consisting of only one layer of atoms or molecules). For example, the interface layer 210 can be composed of a material selected from the group consisting of silicon, aluminum nitride, titanium nitride, silicon nitride, aluminum oxide, zirconium oxide, hafnium oxide, gadolinium oxide, lanthanum oxide, silicon oxynitride, aluminum oxynitride, zirconium silicate, aluminum zirconium oxide, yttrium oxide, and aluminosilicate.

[0077] In addition, silicon carbide is generally oxidized to silicon oxide, and carbon is incorporated into the silicon oxide. This may increase charge trapping compared to the case of silicon oxide without incorporating carbon. Thus, oxidizing silicon carbide to form silicon oxide as an electrical insulator may be susceptible to charge trapping. Thus, according to the present disclosure, the interface layer 210 may be composed of a material including fewer carbon atoms than when silicon carbide is oxidized. In particular, according to the present disclosure, the material forming the interface layer 210 may be deposited (such as by ALD or epitaxial growth).

[0078] More generally, according to the present disclosure, the interface layer 210 may be composed of a uniform material or composed of a non-uniform material. For example, the interface layer 210 may be composed of a material including a first compound and a second compound, wherein the concentration of the first compound of the material decreases along a direction d pointing from one surface 301 of the interface layer 210 (in contact with the silicon carbide body 100) to another surface 302 of the interface layer 210, and the concentration of the second compound of the material increases along such direction d. In this example, the first compound may be selected from the group consisting of silicon, aluminum, titanium, zirconium, hafnium, gadolinium, and lanthanum, and the second compound may be selected from the group consisting of oxygen, nitrogen, and nitrogen oxides.

[0079] The electrical insulator 220 may be composed of a material different from that of the interface layer 210. For example, the electrical insulator 220 may be composed of silicon oxide or a high-k material such as aluminum nitride, titanium nitride, silicon nitride, aluminum oxide, zirconium oxide, hafnium oxide, silicon oxynitride, aluminosilicate, yttrium oxide, gadolinium oxide, or lanthanum oxide. The electrical insulator 220 may have a thickness of 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or even greater.

[0080] Still refer to Figure 2 , a cross-sectional view of an interface layer 210 and an electrical insulator 220 of a silicon carbide device 1 is shown, the electrical insulator 220 being arranged between the silicon carbide body 100 and the gate electrode 21 . Figure 2 The electrical insulator 220, the silicon carbide body 100 and the gate electrode 21 may correspond to Figure 1A and 1B For illustrative purposes, Figure 1A and 1B The remaining components are not shown in Figure 2 For example, Figure 2 The cross section shown in FIG. Figure 1B The sidewalls 1101, 1102 and bottom 1103 of the gate trench shown in (or at least along a portion of the sidewalls or bottom), or located as shown in Figure 1A The gate electrode 21 is shown in the region above the electrical insulator 22. Typically, as Figure 2As shown in FIG. 1 , the stack 2 may be formed by a gate electrode 21 , an electrical insulator 220 , an interface layer 210 and a silicon carbide body 100 . Figure 1A and 1B The gate electrode 21 may be configured to switch current between the source region 11 and the drain region 14 of the silicon carbide device 1. The electrical insulator 220 is disposed between the gate electrode 21 and the silicon carbide body 100 of the silicon carbide device 1 and is configured to electrically insulate the gate electrode 22 from the silicon carbide body 100. The interface layer 210 is disposed between the silicon carbide body 100 and the electrical insulator 220. The electrical insulator 220 is disposed between the interface layer 210 and the gate electrode 21. Optionally, as described below with respect to Figure 3 As further discussed, additional layers may be disposed between the interface layer 210 and the electrical insulator 220. The interface layer 210 is in direct contact with the silicon carbide body 100. The thickness t of the interface layer 210 is less than or equal to 15 nm, and specifically less than or equal to 10 nm or 5 nm. In other examples, the interface layer 210 can have a thickness less than or equal to 4 nm, 3 nm, or 2 nm, or can be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0081] Several stacks 2 envisioned by the present disclosure will be described below. However, other stacks may also be envisioned, so that the stacks discussed are not to be construed as limiting the general concept of the present disclosure.

[0082] In a first embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including silicon nitride, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material that may include silicon oxide or a high-k material. Typical high-k materials are Al2O3, ZrO2, HfO2, AlN, aluminosilicate AlSiO x , silicon doped HfO2, TiO2, Y2O3 and Si3N4. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of silicon and the same or substantially the same concentration of nitrogen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of nitrogen at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100) and a second concentration of nitrogen at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of silicon at the first surface 301 of the interface layer 210 and a second concentration of silicon at the second surface 302 of the interface layer 210.

[0083] In one example, the concentration of nitrogen may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of nitrogen is the first concentration of nitrogen) to the second surface 302 (at the second surface 302, the concentration of nitrogen is the second concentration of nitrogen), and the concentration of silicon may increase along the direction d from the first concentration of silicon (at the first surface 301) to the second concentration of silicon (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of nitrogen to silicon may be, for example, 90:10, while the ratio of nitrogen to silicon at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of nitrogen to silicon may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0084] In another example of the first embodiment, within the interface layer 210, the concentration of nitrogen may increase along the direction d from the first surface 301 to the second surface 302, while the concentration of silicon may decrease along the direction d. In other words, at the first surface 301 of the interface layer 210, the ratio of nitrogen to silicon may be, for example, 10:90, while at the second surface 302, the ratio of nitrogen to silicon may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of nitrogen to silicon may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and so on.

[0085] As discussed above, the thickness t of the silicon nitride interface layer 210 is equal to or less than 15 nm, and is particularly equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0086] In a second embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including silicon oxynitride, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of silicon, the same or substantially the same concentration of oxygen, and the same or substantially the same concentration of nitrogen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of nitrogen at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100), and a second concentration of nitrogen at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 can have a first concentration of silicon at the first surface 301 of the interface layer 210 and a second concentration of silicon at the second surface 302 of the interface layer 210, and a first concentration of oxygen at the first surface 301 and a second concentration of oxygen at the second surface 302.

[0087] In one example, the concentration of silicon may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of silicon is the first concentration of silicon) to the second surface 302 (at the second surface 302, the concentration of silicon is the second concentration of silicon), and the concentrations of oxygen and nitrogen may increase along the direction d from the first concentration of oxygen and the first concentration of nitrogen (at the first surface 301) to the second concentration of oxygen and the second concentration of nitrogen (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of silicon to oxygen plus nitrogen may be, for example, 90:10, while the ratio of silicon to oxygen plus nitrogen at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of silicon to oxygen plus nitrogen may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0088] In another example, such as the second embodiment, within the interface layer 210, the concentration of silicon may increase along the direction d from the first surface 301 to the second surface 302, while the concentration of nitrogen and oxygen may decrease. In other words, at the first surface 301 of the interface layer 210, the ratio of silicon to oxygen plus nitrogen may be, for example, 10:90, while at the second surface 302, the ratio of silicon to oxygen plus nitrogen may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of silicon to oxygen plus nitrogen may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and the like.

[0089] In addition, the ratio of oxygen to nitrogen may also be increased or decreased, for example, from 10:90 at the first surface 301 to 90:10 at the second surface 302 (or vice versa).

[0090] As discussed above, the thickness t of the silicon oxynitride interface layer 210 is equal to or less than 15 nm, and in particular is equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0091] In a third embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including aluminum nitride, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of aluminum and the same or substantially the same concentration of nitrogen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of nitrogen at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100) and a second concentration of nitrogen at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 can have a first concentration of aluminum at the first surface 301 of the interface layer 210 and a second concentration of aluminum at the second surface 302 of the interface layer 210.

[0092] In one example, the concentration of nitrogen may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of nitrogen is the first concentration of nitrogen) to the second surface 302 (at the second surface 302, the concentration of nitrogen is the second concentration of nitrogen), and the concentration of aluminum may increase along the direction d from the first concentration of aluminum (at the first surface 301) to the second concentration of aluminum (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of nitrogen to aluminum may be, for example, 90:10, while the ratio of nitrogen to aluminum at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of nitrogen to aluminum may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0093] In another example such as the third embodiment, within the interface layer 210, the concentration of nitrogen may increase along the direction d from the first surface 301 to the second surface 302, while the concentration of aluminum may decrease along the direction d. In other words, at the first surface 301 of the interface layer 210, the ratio of nitrogen to aluminum may be, for example, 10:90, while at the second surface 302, the ratio of nitrogen to aluminum may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0.

[0094] As discussed above, the thickness t of the aluminum nitride interface layer 210 is equal to or less than 15 nm, and is particularly equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0095] In a fourth embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including aluminum oxynitride, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of aluminum, the same or substantially the same concentration of oxygen, and the same or substantially the same concentration of nitrogen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of nitrogen at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100), and a second concentration of nitrogen at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of aluminum at the first surface 301 of the interface layer 210 and a second concentration of aluminum at the second surface 302 of the interface layer 210, and a first concentration of oxygen at the first surface 301 and a second concentration of oxygen at the second surface 302.

[0096] In one example, the concentration of aluminum may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of aluminum is the first concentration of aluminum) to the second surface 302 (at the second surface 302, the concentration of aluminum is the second concentration of aluminum), and the concentrations of oxygen and nitrogen may increase along the direction d from the first concentration of oxygen and the first concentration of nitrogen (at the first surface 301) to the second concentration of oxygen and the second concentration of nitrogen (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of aluminum to oxygen plus nitrogen may be, for example, 90:10, while the ratio of aluminum to oxygen plus nitrogen at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of aluminum to oxygen plus nitrogen may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0097] In another example, such as the fourth embodiment, within the interface layer 210, the concentration of aluminum may increase along the direction d from the first surface 301 to the second surface 302, while the concentration of nitrogen and oxygen may decrease. In other words, at the first surface 301 of the interface layer 210, the ratio of aluminum to oxygen plus nitrogen may be, for example, 10:90, while at the second surface 302, the ratio of aluminum to oxygen plus nitrogen may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of aluminum to oxygen plus nitrogen may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and the like.

[0098] In addition, the ratio of oxygen to nitrogen may also be increased or decreased, for example, from 10:90 at the first surface 301 to 90:10 at the second surface 302 (or vice versa).

[0099] As discussed above, the thickness t of the aluminum oxynitride interface layer 210 is equal to or less than 15 nm, and in particular is equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0100] In a fifth embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including titanium nitride, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of titanium and the same or substantially the same concentration of nitrogen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of nitrogen at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100) and a second concentration of nitrogen at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of titanium at the first surface 301 of the interface layer 210 and a second concentration of titanium at the second surface 302 of the interface layer 210.

[0101] In one example, the concentration of nitrogen may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of nitrogen is the first concentration of nitrogen) to the second surface 302 (at the second surface 302, the concentration of nitrogen is the second concentration of nitrogen), and the concentration of titanium may increase along the direction d from the first concentration of titanium (at the first surface 301) to the second concentration of titanium (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of nitrogen to titanium may be, for example, 90:10, while the ratio of nitrogen to titanium at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of nitrogen to titanium may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0102] In another example such as the fifth embodiment, within the interface layer 210, the concentration of nitrogen may increase from the first surface 301 to the second surface 302 along the direction d, while the concentration of titanium may decrease along the direction d. In other words, at the first surface 301 of the interface layer 210, the ratio of nitrogen to titanium may be, for example, 10:90, while at the second surface 302, the ratio of nitrogen to titanium may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of nitrogen to titanium may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and so on.

[0103] As discussed above, the thickness t of the titanium nitride interface layer 210 is equal to or less than 15 nm, and is particularly equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0104] In a sixth embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including zirconium oxide, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of zirconium and the same or substantially the same concentration of oxygen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of zirconium at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100) and a second concentration of zirconium at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of oxygen at the first surface 301 of the interface layer 210 and a second concentration of oxygen at the second surface 302 of the interface layer 210.

[0105] In one example, the concentration of zirconium may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of zirconium is the first concentration of zirconium) to the second surface 302 (at the second surface 302, the concentration of zirconium is the second concentration of zirconium), and the concentration of oxygen may increase along the direction d from the first concentration of oxygen (at the first surface 301) to the second concentration of oxygen (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of zirconium to oxygen may be, for example, 90:10, while the ratio of zirconium to oxygen at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of zirconium to oxygen may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0106] In another example, such as the sixth embodiment, within the interface layer 210, the concentration of zirconium may increase along the direction d from the first surface 301 to the second surface 302, while the concentration of oxygen may decrease along the direction d. In other words, at the first surface 301 of the interface layer 210, the ratio of zirconium to oxygen may be, for example, 10:90, while at the second surface 302, the ratio of zirconium to oxygen may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of zirconium to oxygen may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and so on.

[0107] As discussed above, the thickness t of the zirconium oxide interface layer 210 is equal to or less than 15 nm, and is particularly equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0108] In the seventh embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including hafnium oxide, and the electrical insulator in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of hafnium and the same or substantially the same concentration of oxygen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of hafnium at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100) and a second concentration of hafnium at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of oxygen at the first surface 301 of the interface layer 210 and a second concentration of oxygen at the second surface 302 of the interface layer 210.

[0109] In one example, the concentration of hafnium may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of hafnium is the first concentration of hafnium) to the second surface 302 (at the second surface 302, the concentration of hafnium is the second concentration of hafnium), and the concentration of oxygen may increase along the direction d from the first concentration of oxygen (at the first surface 301) to the second concentration of oxygen (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of hafnium to oxygen may be, for example, 90:10, while the ratio of hafnium to oxygen at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of hafnium to oxygen may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0110] In another example such as the seventh embodiment, in the interface layer 210, the concentration of hafnium may increase from the first surface 301 to the second surface 302 along the direction d, while the concentration of oxygen may decrease along the direction d. In other words, at the first surface 301 of the interface layer 210, the ratio of hafnium to oxygen may be, for example, 10:90, while at the second surface 302, the ratio of hafnium to oxygen may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of hafnium to oxygen may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and so on.

[0111] As discussed above, the thickness t of the hafnium oxide interfacial layer 210 is equal to or less than 10 nm, and in particular is equal to or less than 5 nm. For example, the thickness t of the interfacial layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0112] In the eighth embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including gadolinium oxide, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of gadolinium and the same or substantially the same concentration of oxygen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of gadolinium at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100), and has a second concentration of gadolinium at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of oxygen at the first surface 301 of the interface layer 210, and has a second concentration of oxygen at the second surface 302 of the interface layer 210.

[0113] In one example, the concentration of gadolinium may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of gadolinium is the first concentration of gadolinium) to the second surface 302 (at the second surface 302, the concentration of gadolinium is the second concentration of gadolinium), and the concentration of oxygen may increase along the direction d from the first concentration of oxygen (at the first surface 301) to the second concentration of oxygen (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of gadolinium to oxygen may be, for example, 90:10, while the ratio of gadolinium to oxygen at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of gadolinium to oxygen may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0114] In another example such as the eighth embodiment, within the interface layer 210, the concentration of gadolinium may increase along the direction d from the first surface 301 to the second surface 302, while the concentration of oxygen may decrease along the direction d. In other words, at the first surface 301 of the interface layer 210, the ratio of gadolinium to oxygen may be, for example, 10:90, while at the second surface 302, the ratio of gadolinium to oxygen may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of gadolinium to oxygen may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and so on.

[0115] As discussed above, the thickness t of the gadolinium oxide interface layer 210 is equal to or less than 15 nm, and is particularly equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0116] In a ninth embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including lanthanum oxide, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of lanthanum and the same or substantially the same concentration of oxygen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of lanthanum at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100) and a second concentration of lanthanum at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of oxygen at the first surface 301 of the interface layer 210 and a second concentration of oxygen at the second surface 302 of the interface layer 210.

[0117] In one example, the concentration of lanthanum may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of lanthanum is the first concentration of lanthanum) to the second surface 302 (at the second surface 302, the concentration of lanthanum is the second concentration of lanthanum), and the concentration of oxygen may increase along the direction d from the first concentration of oxygen (at the first surface 301) to the second concentration of oxygen (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of lanthanum to oxygen may be, for example, 90:10, while the ratio of lanthanum to oxygen at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of lanthanum to oxygen may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0118] In another example, such as the ninth embodiment, in the interface layer 210, the concentration of lanthanum may increase from the first surface 301 to the second surface 302 along the direction d, while the concentration of oxygen may decrease along the direction d. In other words, at the first surface 301 of the interface layer 210, the ratio of lanthanum to oxygen may be, for example, 10:90, while at the second surface 302, the ratio of lanthanum to oxygen may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of lanthanum to oxygen may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and the like.

[0119] As discussed above, the thickness t of the lanthanum oxide interfacial layer 210 is equal to or less than 15 nm, and in particular is equal to or less than 10 nm or 5 nm. For example, the thickness t of the interfacial layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0120] In the tenth embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including aluminum oxide, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of aluminum and the same or substantially the same concentration of oxygen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of aluminum at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100) and a second concentration of aluminum at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of oxygen at the first surface 301 of the interface layer 210 and a second concentration of oxygen at the second surface 302 of the interface layer 210.

[0121] In one example, the concentration of aluminum may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of aluminum is the first concentration of aluminum) to the second surface 302 (at the second surface 302, the concentration of aluminum is the second concentration of aluminum), and the concentration of oxygen may increase along the direction d from the first concentration of oxygen (at the first surface 301) to the second concentration of oxygen (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of aluminum to oxygen may be, for example, 90:10, while the ratio of aluminum to oxygen at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of aluminum to oxygen may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0122] In another example, such as the tenth embodiment, within the interface layer 210, the concentration of aluminum may increase from the first surface 301 to the second surface 302 along the direction d, while the concentration of oxygen may decrease along the direction d. In other words, at the first surface 301 of the interface layer 210, the ratio of aluminum to oxygen may be, for example, 10:90, while at the second surface 302, the ratio of aluminum to oxygen may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of aluminum to oxygen may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and the like.

[0123] As discussed above, the thickness t of the aluminum oxide interface layer 210 is equal to or less than 15 nm, and in particular is equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0124] In the eleventh embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including silicon oxide, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of silicon and the same or substantially the same concentration of oxygen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of silicon at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100), and has a second concentration of silicon at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of oxygen at the first surface 301 of the interface layer 210, and has a second concentration of oxygen at the second surface 302 of the interface layer 210.

[0125] In one example, the concentration of silicon may decrease along a direction d pointing from the first surface 301 (at the first surface 301, the concentration of silicon is the first concentration of silicon) to the second surface 302 (at the second surface 302, the concentration of silicon is the second concentration of silicon), and the concentration of oxygen may increase along the direction d from the first concentration of oxygen (at the first surface 301) to the second concentration of oxygen (at the second surface 302). In other words, at the first surface 301 of the interface layer 210, the ratio of silicon to oxygen may be, for example, 90:10, while the ratio of silicon to oxygen at the second surface 302 may be one of 80:20, 70:30, 60:40, 50:50, 40:60, 30:70, 20:80, 10:90, or 0:100. Of course, another ratio of silicon to oxygen may exist at the first surface 301, such as 100:0, 80:20, 70:30, and so on.

[0126] In another example such as the eleventh embodiment, in the interface layer 210, the concentration of silicon may increase from the first surface 301 to the second surface 302 along the direction d, while the concentration of oxygen may decrease along the direction d. In other words, at the first surface 301 of the interface layer 210, the ratio of silicon to oxygen may be, for example, 10:90, while at the second surface 302, the ratio of silicon to oxygen may be one of 20:80, 30:70, 40:60, 50:50, 60:40, 70:30, 80:20, 90:10, or 100:0. Of course, another ratio of silicon to oxygen may also exist at the first surface 301, such as 0:100, 20:80, 30:70, and the like.

[0127] As discussed above, the thickness t of the silicon oxide interface layer 210 is equal to or less than 15 nm, and is particularly equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0128] In the twelfth embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including zirconium oxide aluminum, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of zirconium, the same or substantially the same concentration of aluminum, and the same or substantially the same concentration of oxygen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of zirconium at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100), and has a second concentration of zirconium at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of aluminum and oxygen at the first surface 301 of the interface layer 210, and has a second concentration of aluminum and oxygen at the second surface 302 of the interface layer 210.

[0129] Again, some of the concentrations of zirconium, aluminum, and oxide may increase along direction d, while the remaining concentrations of zirconium, aluminum, and oxide may decrease along direction d. For example, the ratio of zirconium to aluminum to oxide can be 60:30:10 at the first surface 301 of the interface layer 210, and 10:30:60 at the second surface 302 of the interface layer 210. Of course, other ratios at the first and second surfaces 301, 302 are possible and are contemplated by the present disclosure.

[0130] As discussed above, the thickness t of the zirconia aluminum interface layer 210 is equal to or less than 15 nm, and is particularly equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0131] In the thirteenth embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including zirconium silicate, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of zirconium, the same or substantially the same concentration of silicon, and the same or substantially the same concentration of oxygen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of zirconium at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100), and has a second concentration of zirconium at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of silicon and oxygen at the first surface 301 of the interface layer 210, and has a second concentration of silicon and oxygen at the second surface 302 of the interface layer 210.

[0132] Again, some of the concentrations of zirconium, silicon, and oxide may increase along direction d, while the remaining concentrations of zirconium, silicon, and oxide may decrease along direction d. For example, the ratio of zirconium to silicon to oxide can be 60:30:10 at the first surface 301 of the interface layer 210, and 10:30:60 at the second surface 302 of the interface layer 210. Of course, other ratios at the first and second surfaces 301, 302 are possible and are contemplated by the present disclosure.

[0133] As discussed above, the thickness t of the zirconium silicate interface layer 210 is equal to or less than 15 nm, and in particular is equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0134] In the fourteenth embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including aluminum silicate, and the electrical insulator 220 in direct contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be uniform (i.e., having the same or substantially the same concentration of aluminum, the same or substantially the same concentration of silicon, and the same or substantially the same concentration of oxygen throughout the interface layer 210). In another example, the material of the interface layer 210 has a first concentration of aluminum at a first surface 301 of the interface layer 210 (in direct contact with the silicon carbide body 100), and has a second concentration of aluminum at a second surface 302 of the interface layer 210 (in direct contact with the electrical insulator 220). Similarly, the material of the interface layer 210 has a first concentration of silicon and oxygen at the first surface 301 of the interface layer 210, and has a second concentration of silicon and oxygen at the second surface 302 of the interface layer 210.

[0135] Again, some of the concentrations of aluminum, silicon, and oxide may increase along direction d, while the remaining concentrations of aluminum, silicon, and oxide may decrease along direction d. For example, the ratio of aluminum to silicon to oxide can be 60:30:10 at the first surface 301 of the interface layer 210, and 10:30:60 at the second surface 302 of the interface layer 210. Of course, other ratios at the first and second surfaces 301, 302 are possible and are contemplated by the present disclosure.

[0136] As discussed above, the thickness t of the aluminum silicate interface layer 210 is equal to or less than 15 nm, and in particular is equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0137] In the fifteenth embodiment, the interface layer 210 directly in contact with the silicon carbide body 100 is composed of a material including silicon, and the electrical insulator 220 directly in contact with the interface layer 210 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. The material of the interface layer 210 may include at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon.

[0138] As discussed above, the thickness t of the silicon interface layer 210 may be equal to or less than 15 nm, and in particular, equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0139] In the case where the material of the interface layer 210 includes or consists of single crystal silicon, the interface layer may be thin enough so that the interface layer is not relaxed due to lattice mismatch with silicon carbide.

[0140] In addition to the stacks 2 discussed above, there are also stacks 2 in which the interface layer 210 may be composed of a material including hafnium oxide, titanium oxide, tantalum oxide, yttrium oxide, or a mixture of such oxides with Al or Si. As described in more detail above, the concentration of the compound may vary from the first surface 301 of the interface layer 210 to the second surface 302 of the interface layer 210.

[0141] Reference Figure 3 , a cross-sectional view of a silicon carbide device 1 is shown, the silicon carbide device 1 comprising a silicon carbide body 100 , an interface layer 210 , an electrical insulator 220 , and a gate electrode 21 . Figure 3 The electrical insulator 220, the silicon carbide body 100 and the gate electrode 21 may correspond to Figure 1A , 1B and electrical insulators 22 , 220 , silicon carbide body 100 and gate electrode 21 . Figure 2 and 3 The difference between the two is that the electrical insulator 22 includes not only the interface layer 210 and the electrical insulator 220, but also includes an additional layer 230 disposed between the interface layer 210 and the electrical insulator 220 of the electrical insulator 22. For illustrative purposes, Figure 1A and 1B The remaining components are not shown in Figure 3 For example, Figure 3 The cross section shown in FIG. Figure 1B The sidewalls 1101, 1102 and bottom 1103 of the gate trench shown in (or at least along a portion of the sidewalls or bottom), or located as shown in Figure 1A The gate electrode 21 is shown in the region above the electrical insulator 22. Typically, as Figure 3As shown in FIG. 1 , the stack 2 may be formed by a gate electrode 21 , an electrical insulator 220 , an additional layer 230 , an interface layer 210 and a silicon carbide body 100 . Figure 1A , 1B As discussed in and 2, the gate electrode 21 can be configured to switch current between the source region 11 and the drain region 14 of the silicon carbide device 1. The electrical insulator 220 is disposed between the gate electrode 21 of the silicon carbide device 1 and the silicon carbide body 100, and is configured to electrically insulate the gate electrode 21 from the silicon carbide body 100. The interface layer 210 is disposed between the silicon carbide body 100 and the additional layer 230. The additional layer 230 is disposed between the interface layer 210 and the electrical insulator 220. The bulk layer 220 is disposed between the additional layer 230 and the gate electrode 21. The interface layer 210 is in direct contact with the silicon carbide body 100. The thickness t of the interface layer 210 is less than or equal to 15 nm, and in particular less than or equal to 10 nm or 5 nm. In other examples, the interface layer 210 can have a thickness less than or equal to 4 nm, 3 nm, or 2 nm, or can be a single layer (i.e., a layer consisting of only one layer of atoms or molecules). Figure 3 The interface layer 210 and the electrical insulator 220 in the context of can be made as described above with respect to Figure 2 The additional layer 230 may be composed of a material different from the material of the interface layer 210 and from the material of the electrical insulator 220. The additional layer 230 may be composed of a material selected from the group consisting of silicon, aluminum nitride, titanium nitride, silicon nitride, aluminum oxide, silicon oxide, zirconium oxide, hafnium oxide, gadolinium oxide, lanthanum oxide, silicon oxynitride, aluminum oxynitride, zirconium silicate, aluminum zirconium oxide, and aluminosilicate.

[0142] Several stacks 2 envisioned by the present disclosure will be described below. However, other stacks may also be envisioned, so that the stacks discussed are not to be construed as limiting the general concept of the present disclosure.

[0143] In an embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including silicon. The additional layer 230 in direct contact with the interface layer 210 is composed of a material including silicon oxide, and the electrical insulator 220 in direct contact with the additional layer 230 and with the gate electrode 21 is composed of a material including a high-k material or silicon oxide. In one example, the material of the interface layer 210 can be single crystalline. In another example, the material of the interface layer 210 can be polycrystalline or amorphous.

[0144] As discussed above, the thickness t of the silicon interface layer 210 is equal to or less than 15 nm, and is particularly equal to or less than 10 nm, 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules). The additional layer 230 may have a thickness of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or even greater.

[0145] In another embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of silicon. The additional layer 230 in direct contact with the interface layer 210 is composed of a material including silicon nitride, and the electrical insulator 220 in direct contact with the additional layer 230 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be single crystalline. In another example, the material of the interface layer 210 can be polycrystalline or amorphous.

[0146] As discussed above, the thickness t of the silicon interface layer 210 is equal to or less than 15 nm, and in particular is equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0147] In another embodiment, the interface layer 210 in direct contact with the silicon carbide body 100 is composed of a material including silicon. The additional layer 230 in direct contact with the interface layer 210 is composed of a material including silicon nitride, and the electrical insulator 220 in direct contact with the additional layer 230 and with the gate electrode 21 is composed of a material including silicon oxide or a high-k material. In one example, the material of the interface layer 210 can be single crystalline. In another example, the material of the interface layer 210 can be polycrystalline or amorphous.

[0148] As discussed above, the thickness t of the silicon interface layer 210 is equal to or less than 15 nm, and in particular is equal to or less than 10 nm or 5 nm. For example, the thickness t of the interface layer 210 may be less than or equal to 4 nm, 3 nm, or 2 nm, or may be a single layer (i.e., a layer consisting of only one layer of atoms or molecules).

[0149] Figure 4 1 is a diagram illustrating a method 300 for forming an interface layer 210 on a silicon carbide body 100 of a silicon carbide device 1 according to the present disclosure. The silicon carbide device may be as described above with respect to Figure 1A and 1B The disclosed silicon carbide device 1 comprises a source region 12 of a first conductivity type and a body region 13 of a second conductivity type. In addition, Figure 1A and 1BThe remaining components of the silicon carbide device 1 shown in FIG. Figure 3 The step of the interface layer 210 of the stack 2 is shown in Figures 5A to 5D , formed by referring to the diagram Figure 1A The step of forming the interface layer 210 of the silicon carbide device 1 is shown in Figures 6A to 6D , and formed by referring to the diagram Figure 1B The step of forming the interface layer 210 of the silicon carbide device 1 is shown in Figures 7A to 7D , method 300 will be explained.

[0150] Method 300 includes removing 310 an oxide layer (such as a native oxide, a deposited oxide, or a grown oxide) from a surface of silicon carbide body 100 to obtain a silicon carbide surface 303 (e.g., a surface consisting essentially of silicon carbide, such that the surface includes a concentration of 90% silicon carbide or greater, such as 95% or 99%). Fig. 6A and 7A As shown in , this step can be performed on a first surface 101 (such as, an upper surface) of the silicon carbide body 100 (for example, in the case of a lateral silicon carbide device), or in a trench (such as, a gate trench) of the silicon carbide body 100 (for example, in the case of a vertical silicon carbide device), such as at one or more of the first sidewall 1101, the second sidewall 1102, and the bottom 1103.

[0151] Removing 310 the oxide layer from the surface of silicon carbide body 100 is performed to obtain an oxide-free or substantially oxide-free silicon carbide surface 303 (where substantially oxide-free may mean less than 10% oxygen atoms on silicon carbide surface 303), such that silicon carbide surface 303 consists essentially of silicon carbide. An exemplary process for removing oxide from the surface of silicon carbide body 100 is an in-situ cleaning process (e.g., using nitrogen trifluoride or hydrogen).

[0152] After the oxide layer is removed 310 , the method 300 includes depositing 320 an interface layer 210 on the silicon carbide surface 301 .

[0153] Depositing 320 the interface layer 210 includes depositing the interface layer 210 in direct contact with the silicon carbide surface 301 (in step 310, the oxide is removed from the silicon carbide surface 301), the interface layer 210 having a thickness t, wherein the thickness t is less than or equal to 15nm, and in particular less than or equal to 10nm or 5nm. In other examples, the interface layer 210 may be deposited to have a thickness t less than or equal to 4nm, 3nm, or 2nm, or may be a monolayer (i.e., a layer consisting of only one layer of atoms or molecules). Figure 2 and 3The materials of the interface layer 210 are explained in detail and are not repeated here for the sake of brevity. Figure 6B and 7B As shown in , step 320 of depositing the interface layer 210 can be performed on a first surface 101 (such as, an upper surface) of the silicon carbide body 100 (e.g., in the case of a lateral silicon carbide device), or can be performed in a trench (such as, a gate trench) of the silicon carbide body 100 (e.g., in the case of a vertical silicon carbide device), such as being performed at one or more of the first sidewall 1101, the second sidewall 1102, and the bottom 1103.

[0154] Subsequently, the method 300 includes forming 330 an electrical insulator 220 over the interface layer 210. Figure 2 As discussed above, the electrical insulator 220 may be formed 330 in direct contact with the interface layer 210, or an additional layer 230 (or multiple additional layers) may be formed between the interface layer 210 and the electrical insulator 220 (as described above with respect to Figure 3 The electrical insulator may be composed of a material different from that of the interface layer 210 (and different from that of the additional layer 230, if present). The bulk layer may be formed by ALD, or may be deposited (e.g., by chemical vapor deposition, such as low pressure chemical vapor deposition or molecular vapor deposition). Figure 6C and 7C As shown in , this step can be performed on a first surface 101 (such as, an upper surface) of the silicon carbide body 100 (for example, in the case of a lateral silicon carbide device), or in a trench (such as, a gate trench) of the silicon carbide body 100 (for example, in the case of a vertical silicon carbide device), such as at one or more of the first sidewall 1101, the second sidewall 1102, and the bottom 1103.

[0155] Optionally, before forming 330 the electrical insulator 220 , the method 300 may include forming 325 one or more additional layers 230 in direct contact with the interface layer 210 . The electrical insulator 220 is then formed 330 in direct contact with one of the additional layers 230 .

[0156] Using atomic layer deposition (ALD), the steps of depositing 320 the interface layer 210 and (optionally) forming 325 the one or more additional layers 230 may be performed. As such, the step of depositing 320 the interface layer 210 may include depositing a material on the silicon carbide surface 303 via ALD, wherein the deposited material forms the interface layer 210 (e.g., the interface layer 210 consists of the deposited material). The material may be deposited uniformly, so that the material of the interface layer 210 is uniform. In some embodiments, the material may include a first compound and a second compound. In this case, during the ALD, the ratio of the concentration of the first compound to the concentration of the second compound may vary. For example, at the beginning, such a ratio may be 100:0, and such a ratio will be continuously modified to become 0:100 at the end of the ALD (or vice versa). Such a process may produce an interfacial layer 210 composed of deposited materials (including first and second compounds) whose concentration of the first compound decreases along a direction (d) pointing from a first surface 301 of the interfacial layer 210 to a second surface 302 of the interfacial layer 210 opposite the first surface 301, and whose concentration of the second compound increases along the direction d pointing from the first surface 301 to the second surface 302 (or vice versa). For example, the first compound may be deposited directly on the silicon carbide surface 303 via ALD during a first time period, and the second compound may be deposited on the silicon carbide surface 303 via ALD during a second time period. The first compound may be selected from the group consisting of silicon, aluminum, titanium, zirconium, hafnium, gadolinium, yttrium, and lanthanum, and the second compound may be selected from the group consisting of oxygen, nitrogen, and oxynitrides, or vice versa.

[0157] Subsequently, the method 300 includes forming 340 a gate electrode 21 over the electrical insulator 220. For example, the gate electrode 21 may be in direct contact with the electrical insulator 220. The gate electrode 21 may be made of, for example, polysilicon, titanium, or aluminum. Fig.6D and 7D As shown in , this step can be performed on a first surface 101 (such as an upper surface) of the silicon carbide body 100 (e.g., in the case of a lateral silicon carbide device), or in a trench (such as a gate trench) of the silicon carbide body 100 (e.g., in the case of a vertical silicon carbide device), such as at one or more of the first sidewall 1101, the second sidewall 1102, and the bottom 1103. Fig.6D As can be seen in FIG. 1 , for a lateral silicon carbide device, the electrode may be positioned adjacent to the body region 13 and between the source electrode 41 and the drain electrode 43. Alternatively, Fig.7D As can be seen in FIG. 1 , the gate electrode 22 can be located in the trench. The gate electrode 22 can be formed by filling the trench with the material of the gate electrode 22 .

[0158] Figure 84 shows a method 400 for forming an interface layer 210 on a silicon carbide body 100 of a silicon carbide device 1 according to the present disclosure. The silicon carbide device may be as described above with respect to Figure 1A and 1B The disclosed silicon carbide device 1 comprises a source region 12 of a first conductivity type and a body region 13 of a second conductivity type. In addition, Figure 1A and 1B The remaining components of the silicon carbide device 1 shown in FIG. Figure 3 The steps of stack 2 are shown in Figures 9A to 9E , formed by referring to the diagram Figure 1A The steps of the silicon carbide device 1 are shown in Figures 10A to 10E , and formed by referring to the diagram Figure 1B The steps of the silicon carbide device 1 are shown in Figures 11A to 11E , method 400 will be explained.

[0159] Similar to method 300, method 400 includes the steps of removing 410 an oxide layer from a surface of silicon carbide body 100 to obtain silicon carbide surface 303, depositing 420 an interface layer 210 on silicon carbide surface 303 after removing the oxide layer, forming 430 an electrical insulator 220 over interface layer 210, and forming 440 a gate electrode 21 over electrical insulator 220. The steps of removing 410 the oxide layer and forming 440 the gate electrode 21 of method 400 may be the same as corresponding steps 310 and 340 of method 300 as discussed above.

[0160] As discussed above with respect to method 300, the step of depositing 420 the interfacial layer 210 on the silicon carbide surface 303 according to method 400 includes depositing the interfacial layer 210 in direct contact with the silicon carbide surface 303. According to method 400, the step of depositing 420 the interfacial layer 210 corresponds to depositing the silicon layer 810 on the silicon carbide surface 303. In some embodiments, the silicon layer 810 has a thickness less than or equal to 15 nm or 10 nm. In other embodiments, the silicon layer 810 may also be thicker, depending on the circumstances. For example, in the case where the silicon layer 810 is converted (such as oxidized) into the additional layer 230 or is converted (such as oxidized) into the electrical insulator 210 (as discussed further below), the thickness of the silicon layer may define the sum of the thickness of the interfacial layer 210 and the additional layer 230 (or the electrical insulator 210). In this case, the thickness of the silicon layer 810 may be 100 nm or more.

[0161] In addition, the step 325 of forming the additional layer 230 or the step of forming 330 the electrical insulator 220 corresponds to converting 425 the silicon layer 810 and stopping the conversion 424 before the entire silicon layer 810 is converted to obtain a converted layer formed of the converted silicon layer (which is the additional layer 230 or the electrical insulator 220, depending on the application) and the remaining silicon layer of the silicon layer 810 (which is the interface layer 210). In the case where the converted layer is used as the additional layer 230, a further step of forming the electrical insulator 220 may be present (for example, to obtain a stack in which the interface layer 210 is made of silicon, the additional layer 230 is made of silicon oxide, and the electrical insulator is made of a high-k material).

[0162] Depositing 420 the silicon layer 810 may include depositing a silicon layer having a thickness less than or equal to 5 nm, or 4 nm, or 3 nm, or 2 nm. In particular, depositing a very thin silicon layer 810 (such as approximately 3 nm or thinner) may allow the silicon layer 810 to be formed into a single crystalline structure. In this case, the silicon layer 810 may be strained and may not relax. Alternatively, the silicon layer 810 may also be formed into a polycrystalline or amorphous structure.

[0163] The step of converting 425 silicon layer 810 may include oxidizing and / or nitriding a portion of silicon layer 810. Before the entire silicon layer 810 is oxidized and / or nitrided, the oxidation and / or nitridation is stopped. The oxidized and / or nitrided portion of silicon layer 810 is the additional layer 230 (or electrical insulator 220, as discussed above), and the remaining silicon layer (which is not oxidized and / or nitrided) is the interface layer 210. In other words, silicon layer 810 may form the basis of both interface layer 210 and additional layer 230 (or electrical insulator 220), and by oxidizing and / or nitriding a portion of silicon layer 810, the additional layer (or electrical insulator) is obtained. The stopping of the transformation 425 of the silicon layer 810 may be performed such that the remaining silicon layer (i.e., the interface layer) has a thickness of 1 nm or less (such as one to three silicon monolayers). In other examples, the thickness of the remaining silicon layer may also be thicker than 1 nm. The stopping of the transformation 425 may be achieved by a low temperature oxidation that slows down after a few nm or after tens of nm (such as a self-limiting redox (radox) process).

[0164] Although specific examples have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific examples discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

[0165] It should be noted that the methods and apparatus as outlined in this document including preferred embodiments thereof may be used independently or in combination with other methods and apparatus disclosed in this document. In addition, features outlined in the context of an apparatus may also be applicable to the corresponding method and vice versa. In addition, all aspects of the methods and apparatus outlined in this document may be combined arbitrarily. In particular, the features of the claims may be combined with each other in any manner.

[0166] It should be noted that the description and drawings illustrate only the principles of the proposed method and system. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the present invention and are included in the spirit and scope of the present invention. In addition, all examples and embodiments outlined in this document are primarily intended to be used explicitly only for explanation purposes to help the reader understand the principles of the proposed method and system. In addition, all statements of the principles, aspects and embodiments of the present invention and specific examples of the present invention provided herein are intended to cover their equivalents.

Claims

1. A method (300; 400) for forming an interface layer on a silicon carbide body, wherein the silicon carbide body comprises a source region (12) of a first conductivity type and a body region (13) of a second conductivity type, the method comprising: Removing (310; 410) an oxide layer from a surface of a silicon carbide body to obtain a silicon carbide surface (303); After removing the oxide layer, depositing (320; 420) an interface layer (210) directly on the silicon carbide surface (303), wherein the interface layer (210) has a thickness (t) less than or equal to 15 nm; forming (330; 430) an electrical insulator (22; 220) on the interface layer (210); and A gate electrode (21) is formed (340; 440) over the electrical insulator.

2. The method (300) of claim 1, wherein depositing the interface layer (210) comprises depositing (320) a material on the silicon carbide surface (303) by atomic layer deposition (ALD), The deposited material forms the interface layer.

3. The method (300) of claim 2, The material is selected from the group consisting of silicon, aluminum nitride, titanium nitride, silicon nitride, aluminum oxide, silicon oxide, zirconium oxide, hafnium oxide, gadolinium oxide, lanthanum oxide, silicon oxynitride, aluminum oxynitride, zirconium silicate, zirconium aluminum oxide, yttrium oxide and aluminosilicate.

4. The method (300) of claim 2, The material deposited (320) by ALD comprises: depositing a first compound directly on the silicon carbide surface (303) via ALD during a first time period, and depositing a second compound on the silicon carbide surface via ALD during a second time period, The first time period starts before the second time period.

5. The method (300) as claimed in claim 4, wherein the first compound is selected from the group consisting of silicon, aluminum, titanium, zirconium, hafnium, gadolinium, tantalum, yttrium and lanthanum, and Wherein the second compound is selected from the group consisting of oxides, nitrides and oxynitrides.

6. The method (300) of claim 4, wherein the first compound is selected from the group consisting of oxides, nitrides and oxynitrides, and Wherein the second compound is selected from the group consisting of silicon, aluminum, titanium, zirconium, hafnium, gadolinium, tantalum, yttrium and lanthanum.

7. The method (400) of claim 1, Wherein depositing (420) the interface layer (210) comprises: depositing (422) a silicon layer (810) on the silicon carbide surface (301), converting (424) the silicon layer, and stopping the conversion before the entire silicon layer is converted to obtain a converted layer formed of the converted silicon layer and a remaining silicon layer of the silicon layer, wherein the remaining silicon layer is the interface layer (210) of the silicon carbide body, and The layer being converted is at least one of the electrical insulator and an additional layer (230) between the interface layer and the electrical insulator.

8. The method according to claim 7, The interface layer (210) has a thickness less than or equal to 2 nm.

9. The method (400) according to claim 7 or 8, Wherein converting (425) the silicon layer (810) comprises at least one of oxidizing the silicon layer and nitriding the silicon layer, so that the converted layer is at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

10. The method according to any one of the preceding claims, The electrical insulator (22; 220) comprises silicon oxide or a high-k material.

11. A silicon carbide device, comprising: A source region (12) of a first conductivity type formed in a silicon carbide body (100), a body region (13) of a second conductivity type formed in the silicon carbide body, and a drain region (14); a gate electrode (21) configured to switch current between the source region and the drain region; an interface layer (210) disposed directly on the silicon carbide body and arranged between the silicon carbide body and the gate electrode, wherein the thickness (t) of the interface layer is less than or equal to 15 nm, wherein the interface layer comprises a first surface (301) in contact with the silicon carbide body (100) and a second surface (302) opposite to the first surface, wherein the concentration of carbon in the interface layer decreases along a direction (d) from the first surface to the second surface from a first concentration of carbon at the first surface of the interface layer to a second concentration of carbon at a second surface of the interface layer opposite to the first surface of the interface layer, and wherein the concentration of carbon is less than half of the first concentration in at least 75% of the interface layer; as well as An electrical insulator (22; 220) is disposed between the interface layer (210) and the gate electrode and is configured to electrically insulate the gate electrode from the silicon carbide body.

12. The silicon carbide device according to claim 11, The interface layer (210) is made of a material selected from the group consisting of silicon, aluminum nitride, titanium nitride, silicon nitride, aluminum oxide, silicon oxide, zirconium oxide, hafnium oxide, gadolinium oxide, lanthanum oxide, silicon oxynitride, aluminum oxynitride, zirconium silicate, zirconium aluminum oxide, tantalum oxide, yttrium oxide and aluminosilicate.

13. The silicon carbide device according to claim 11 or 12, wherein the interface layer (210) comprises a first compound and a second compound, wherein the first compound is selected from the group consisting of silicon, aluminum, titanium, zirconium, hafnium, gadolinium, tantalum and lanthanum, wherein said second compound is selected from the group consisting of oxygen, nitrogen and nitrogen oxides, wherein the concentration of the first compound of the material decreases along a direction (d) from the first surface to the second surface, and The concentration of the second compound of the material increases along a direction from the first surface to the second surface.

14. The silicon carbide device according to claim 11, wherein the interface layer (210) comprises a first compound and a second compound, wherein the first compound is selected from the group consisting of oxygen, nitrogen and nitrogen oxides, wherein the second compound is selected from the group consisting of silicon, aluminum, titanium, zirconium, hafnium, gadolinium, tantalum, yttrium and lanthanum, wherein the concentration of the first compound of the material decreases along a direction (d) from the first surface to the second surface, and The concentration of the second compound of the material increases along a direction from the first surface to the second surface.

15. The silicon carbide device according to claim 11, The interface layer (210) comprises single crystal silicon.

16. The silicon carbide device according to claim 11, Also includes: an additional layer (230) comprising a material selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride, The additional layer is disposed between the interface layer (210) and the electrical insulator (22; 220).

17. The silicon carbide device according to any one of claims 11 to 16, wherein the gate electrode (21), the interface layer (210) and the electrical insulator (22; 220) are arranged in a gate trench extending from the first main surface (101) into the silicon carbide body (100); or The gate electrode (21), the interface layer (210) and the electrical insulator (22; 220) are arranged on the first main surface (101) of the silicon carbide body (100).

Images