Semiconductor device and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a cell region, a gate bus, and a transition region. The transition region is located between the cell region and the gate bus. The transition region includes a substrate, an epitaxial layer, a main junction layer, a gate oxide layer, and a gate dielectric layer. The epitaxial layer is disposed on one side of the substrate, and the main junction layer is disposed on a side of the epitaxial layer facing away from the substrate. The main junction layer includes an adjustment region, which is located on a side of the main junction layer facing away from the substrate. The adjustment region and the main junction layer have opposite conductivity types. The gate oxide layer is disposed on a side of the main junction layer facing away from the substrate and includes a first gate oxide structure proximate the cell region and a second gate oxide structure proximate the gate bus. The thickness of the first gate oxide structure is greater than that of the second gate oxide structure. The gate dielectric layer is disposed on a side of the gate oxide layer facing away from the substrate. The second gate oxide structure contacts the adjustment region, and the orthographic projection of the second gate oxide structure on the substrate falls within the orthographic projection of the adjustment region on the substrate.

Description

Technical Field

[0001] The present application belongs to the field of power semiconductor technology, and in particular relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the field of power semiconductors, silicon carbide MOSFET is widely used in high-voltage scenarios due to its many advantages such as high breakdown voltage, high power, low on-resistance and high temperature resistance.

[0003] For silicon carbide MOSFET devices, electric field concentration is likely to occur in the transition region, which in turn causes oxide layer breakdown in this region, resulting in device failure and adversely affecting device reliability. Summary of the Invention

[0004] An embodiment of the present application provides a semiconductor device and a method for preparing the same. The semiconductor device introduces an adjustment region of opposite conductivity type in the main junction layer. The adjustment region can reduce the electric field strength of the gate oxide layer in the transition region, thereby improving the reliability of the semiconductor device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising a cell region, a gate bus, and a transition region, wherein the transition region is located between the cell region and the gate bus, and comprises a substrate, an epitaxial layer, a main junction layer, a gate oxide layer, and a gate dielectric layer arranged in sequence, wherein the epitaxial layer is arranged on one side of the substrate; the main junction layer is arranged on a side of the epitaxial layer facing away from the substrate, the main junction layer comprises an adjustment region, the adjustment region is located on a side of the main junction layer facing away from the substrate, and the conductivity type of the adjustment region is opposite to that of the main junction layer; the gate oxide layer is arranged on a side of the main junction layer facing away from the substrate, and comprises a first gate oxide structure proximate the cell region and a second gate oxide structure proximate the gate bus, wherein the thickness of the first gate oxide structure is greater than the thickness of the second gate oxide structure; and the gate dielectric layer is arranged on a side of the gate oxide layer facing away from the substrate.

[0006] The second gate oxide structure is in contact with the adjustment region, and the orthographic projection of the second gate oxide structure on the substrate falls within the range of the orthographic projection of the adjustment region on the substrate.

[0007] In some embodiments, the gate oxide layer further includes a third gate oxide structure, which is located between the first gate oxide structure and the second gate oxide structure, and the thickness of the third gate oxide structure gradually decreases from the cell region to the gate bus line.

[0008] In some embodiments, an orthographic projection of the third gate oxide structure on the substrate at least partially falls within an orthographic projection range of the adjustment region on the substrate.

[0009] In some embodiments, the conductive ion concentration of the adjustment region is greater than the conductive ion concentration of the epitaxial layer.

[0010] In some of these embodiments, the transition zone further comprises:

[0011] an isolation dielectric layer, located on a side of the gate dielectric layer facing away from the substrate;

[0012] a gate metal, located on a side of the isolation dielectric layer facing away from the substrate and in contact with the gate dielectric layer;

[0013] A source metal is located on a side of the isolation dielectric layer facing away from the substrate and in contact with the main junction layer;

[0014] The source metal and the gate metal are separated by an isolation dielectric layer, and the source metal and the gate dielectric layer are separated by an isolation dielectric layer.

[0015] In some embodiments, along the direction from the cell region to the gate bus, the orthographic projection of the source metal on the substrate and the orthographic projection of the first gate oxide structure on the substrate are spaced apart.

[0016] In some embodiments, an orthographic projection of the source metal on the substrate partially overlaps with an orthographic projection of the second gate oxide structure on the substrate.

[0017] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0018] providing a substrate and growing a drift region on one side of the substrate;

[0019] Implanting ions of the first conductivity type into a side of the drift region facing away from the substrate to obtain an epitaxial layer and a main junction layer located in the drift region;

[0020] Setting a first mask and implanting ions of the second conductivity type into the side of the main junction layer facing away from the substrate to obtain an adjustment region;

[0021] forming a gate oxide layer on a side of the main junction layer facing away from the substrate;

[0022] A gate dielectric layer is formed on the side of the gate oxide layer facing away from the substrate.

[0023] In some embodiments, the step of forming a gate oxide layer on a side of the main junction layer facing away from the substrate includes:

[0024] Depositing a thick oxide layer on the side of the main junction layer facing away from the substrate, setting a second mask, and etching the thick oxide layer to obtain a first gate oxide structure;

[0025] A thin oxide layer is grown on the side of the main junction layer facing away from the substrate, a third mask is set, and the thin oxide layer is etched to obtain a second gate oxide structure.

[0026] In some embodiments, the preparation method further comprises:

[0027] Depositing an isolation dielectric layer on the side of the gate dielectric layer facing away from the substrate, setting a fourth mask, and etching the isolation dielectric layer to obtain a gate contact hole and a source contact hole;

[0028] The gate metal is obtained by metal deposition in the gate contact hole, and the source metal is obtained by metal deposition in the source contact hole.

[0029] The embodiments of the present application introduce a regulation region of opposite conductivity to the main junction layer in the transition region of a semiconductor device. This increases the growth rate of the second gate oxide structure above the regulation region, allowing a thicker gate oxide layer to be grown in the same amount of time, thereby improving the device's withstand voltage performance. Furthermore, the regulation region covering the second gate oxide structure weakens the electric field strength above the second gate oxide structure, reducing the probability of device failure caused by breakdown of the second gate oxide structure and improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0031] Figure 1 A schematic diagram of the layout of a semiconductor device according to some embodiments of the present application;

[0032] Figure 2 for Figure 1 A schematic structural diagram of the semiconductor device shown;

[0033] Figures 3a to 3e A schematic diagram of a process of a semiconductor device manufacturing method according to some embodiments of the present application;

[0034] Figure 4 Schematic diagram of a process for preparing a semiconductor device according to some embodiments of the present application;

[0035] Figure 5 Schematic diagram of a sub-flow of a method for preparing a semiconductor device according to some embodiments of the present application;

[0036] Figure 6 A schematic diagram of the transition region structure of a semiconductor device with a traditional structure;

[0037] Figures 7a to 7b The electric field intensity distribution diagram of the traditional structure under experimental conditions;

[0038] Figures 8a to 8b This is a diagram of the electric field intensity distribution under experimental conditions of an embodiment of the present application;

[0039] Figure 91 is a graph showing the electric field intensity distribution characteristics of the thin gate oxide layer region of the conventional structure and the embodiment of the present application under experimental conditions.

[0040] The accompanying drawings in the specific implementation manner are as follows:

[0041] 11. Cell region; 12. Transition region; 13. Gate bus; 14. Gate region; 15. Terminal region;

[0042] 110, substrate; 120, epitaxial layer; 200, main junction layer; 210, adjustment region; 300, gate oxide layer; 310, first gate oxide structure; 320, second gate oxide structure; 330, third gate oxide structure; 400, gate dielectric layer; 500, isolation dielectric layer; 610, gate metal; 620, source metal; 630, drain metal. DETAILED DESCRIPTION

[0043] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0045] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0046] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0047] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0048] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0049] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0050] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0051] In the field of power semiconductors, silicon carbide MOSFET is widely used in high-voltage scenarios of power electronic systems due to its many advantages such as high breakdown voltage, high power, low on-resistance, and high temperature resistance.

[0052] For silicon carbide MOSFET devices, electric field concentration is likely to occur in the transition region, which in turn causes oxide layer breakdown in this region, resulting in device failure and adversely affecting device reliability.

[0053] In order to solve the problems in the prior art, the present invention provides a semiconductor device and a method for manufacturing the same.

[0054] See also Figures 1 to 2The embodiment of the present application provides a semiconductor device, which includes a cell region 11, a gate bus 13 and a transition region 12. The transition region 12 is located between the cell region 11 and the gate bus 13. The transition region 12 includes a substrate 110, an epitaxial layer 120, a main junction layer 200, a gate oxide layer 300 and a gate dielectric layer 400 arranged in sequence. The epitaxial layer 120 is arranged on one side of the substrate 110; the main junction layer 200 is arranged on the side of the epitaxial layer 120 away from the substrate 110. The main junction layer 200 includes an adjustment region 210. The node region 210 is located on the side of the main junction layer 200 facing away from the substrate 110. The conductivity type of the adjustment region 210 is opposite to that of the main junction layer 200. The gate oxide layer 300 is disposed on the side of the main junction layer 200 facing away from the substrate 110. The gate oxide layer 300 includes a first gate oxide structure 310 located near the cell region 11 and a second gate oxide structure 320 located near the gate bus 13. The thickness of the first gate oxide structure 310 is greater than that of the second gate oxide structure 320. The gate dielectric layer 400 is disposed on the side of the gate oxide layer 300 facing away from the substrate 110. The second gate oxide structure 320 is in contact with the adjustment region 210, and the orthographic projection of the second gate oxide structure 320 on the substrate 110 falls within the orthographic projection of the adjustment region 210 on the substrate 110.

[0055] Specifically, the substrate 110 and the epitaxial layer 120 have the same conductivity type, and the epitaxial layer 120 and the main junction layer 200 have opposite conductivity types.

[0056] Exemplarily, the main junction layer 200 is doped with P-type ions, and the adjustment region 210 is doped with N-type ions.

[0057] Exemplarily, the material of the gate dielectric layer 400 includes polysilicon.

[0058] In some of these embodiments, see Figure 1 The semiconductor device further includes a gate region 14, which is connected to the gate bus 13. For example, in a horizontal plane, along the circumference of the gate region 14 and the gate bus 13, the cell region 11 is arranged on the outside.

[0059] In some of these embodiments, please refer to Figure 1 The semiconductor device further includes a terminal region 15. Exemplarily, in a horizontal plane, along the circumference of the cell region 11, the terminal region 15 is disposed on the outside.

[0060] It should be understood that the "thickness" herein refers to the minimum dimension of the first gate oxide structure 310 and the second gate oxide structure 320 perpendicular to their coverage surfaces. For example, along the direction perpendicular to the coverage surface, the first gate oxide structure 310 has a first portion with a smaller size and a second portion with a larger size, wherein the first portion is larger than the second gate oxide structure 320; or, along the direction perpendicular to the coverage surface, the second gate oxide structure 320 has a third portion with a larger size and a fourth portion with a smaller size, wherein the third portion is smaller than the first gate oxide structure 310. Of course, in some embodiments, the first gate oxide structure 310 has a uniform dimension perpendicular to its coverage surface, or the second gate oxide structure 320 has a uniform dimension perpendicular to its coverage surface.

[0061] Therefore, providing the adjustment region 210 of the opposite conductivity type within the main junction layer 200 can accelerate the growth of the second gate oxide structure 320 above the adjustment region 210, allowing the second gate oxide structure 320 to have a greater thickness within the same growth time, thereby reducing the probability of device failure in the transition region 12 at the second gate oxide structure 320. In addition, the adjustment region 210 provided over the second gate oxide structure 320 can also weaken the electric field strength at the second gate oxide structure 320, further improving the withstand voltage performance of the transition region 12, thereby improving the reliability of the semiconductor device.

[0062] According to certain embodiments of the present application, the gate oxide layer 300 further includes a third gate oxide structure 330 , which is located between the first gate oxide structure 310 and the second gate oxide structure 320 . The thickness of the third gate oxide structure 330 is less than or equal to the first gate oxide structure 310 , and the thickness of the third gate oxide structure 330 is greater than or equal to the second gate oxide structure 320 .

[0063] Optionally, the third gate oxide structure 330 is made of the same material as the first gate oxide structure 310 and the second gate oxide structure 320, or the third gate oxide structure 330 is made of a material different from the first gate oxide structure 310 and the second gate oxide structure 320. Exemplarily, the third gate oxide structure 330 is made of silicon dioxide.

[0064] Optionally, the thickness of the third gate oxide structure 330 gradually decreases along the direction from the cell region 11 to the gate bus line 13 .

[0065] Further optionally, the maximum thickness of the third gate oxide structure 330 is the same as the thickness of the first gate oxide structure 310 .

[0066] Further optionally, the minimum thickness of the third gate oxide structure 330 is the same as the thickness of the second gate oxide structure 320 .

[0067] Exemplarily, the cross section of the third gate oxide structure 330 in the height direction is distributed in an inclined straight line, or the cross section of the third gate oxide structure 330 in the height direction is distributed in a curved line.

[0068] Therefore, the third gate oxide structure 330 can serve as a transition between the first gate oxide structure 310 and the second gate oxide structure 320 with a thickness difference, adapting to the changes in the electric field above the first gate oxide structure 310 and the electric field above the second gate oxide structure 320, so as to protect the junction between the first gate oxide structure 310 and the second gate oxide structure 320 and reduce the probability of breakdown in this area leading to device failure.

[0069] According to some embodiments of the present application, the orthographic projection of the third gate oxide structure 330 on the substrate 110 at least partially falls within the orthographic projection range of the adjustment region 210 on the substrate 110 .

[0070] Optionally, an orthographic projection of the third gate oxide structure 330 on the substrate 110 falls within a range of an orthographic projection of the adjustment region 210 on the substrate 110 .

[0071] Optionally, the orthographic projections of the third gate oxide structure 330 on the substrate 110 all fall within the orthographic projection range of the adjustment region 210 on the substrate 110 .

[0072] Therefore, on the one hand, it helps the third gate oxide structure 330 to grow thicker during preparation to have better voltage resistance performance. On the other hand, the adjustment region 210 can at least form protection for part of the third gate oxide structure 330 to reduce the probability of device failure due to breakdown at the third gate oxide structure 330.

[0073] According to some embodiments of the present application, the conductive ion concentration of the adjustment region 210 is greater than the conductive ion concentration of the epitaxial layer 120 .

[0074] Optionally, the conductive ion concentration of the adjustment region 210 is greater than the conductive ion concentration of the substrate 110 .

[0075] Exemplarily, the substrate 110 , the epitaxial layer 120 , and the adjustment region 210 are all doped with N-type ions.

[0076] Therefore, the adjustment region 210 with a higher ion doping concentration is provided to accelerate the growth of the second gate oxide structure 320 and at least a portion of the third gate oxide structure 330 above the adjustment region 210 , and thicken the second gate oxide structure 320 and the third gate oxide structure 330 to improve the withstand voltage performance of the semiconductor device.

[0077] According to certain embodiments of the present application, the transition region 12 also includes an isolation dielectric layer 500, a gate metal 610 and a source metal 620, the isolation dielectric layer 500 is located on the side of the gate dielectric layer 400 away from the substrate 110, the gate metal 610 is located on the side of the isolation dielectric layer 500 away from the substrate 110 and in contact with the gate dielectric layer 400, and the source metal 620 is located on the side of the isolation dielectric layer 500 away from the substrate 110 and in contact with the main junction layer 200.

[0078] See also Figure 2 It can be understood that the transition region 12 further includes a drain metal 630 , and the drain metal 630 is disposed on a side of the substrate 110 facing away from the epitaxial layer 120 .

[0079] It is understandable that the source metal 620 is separated from the gate metal 610 by the isolation dielectric layer 500 , and the source metal 620 is separated from the gate dielectric layer 400 by the isolation dielectric layer 500 to prevent short circuit between the source metal 620 and the gate metal 610 .

[0080] Optionally, along the direction from the cell region 11 to the gate bus 13 , the orthographic projection of the source metal 620 on the substrate 110 and the orthographic projection of the gate metal 610 on the substrate 110 are spaced apart.

[0081] Optionally, an isolation dielectric layer 500 is provided between the source metal 620 and the gate metal 610 along a direction from the cell region 11 to the gate bus 13 .

[0082] According to some embodiments of the present application, along the direction from the cell region 11 to the gate bus 13 , the orthographic projection of the source metal 620 on the substrate 110 and the orthographic projection of the first gate oxide structure 310 on the substrate 110 are spaced apart.

[0083] Optionally, an orthographic projection of the source metal 620 on the substrate 110 and an orthographic projection of the third gate oxide structure 330 on the substrate 110 are spaced apart from each other.

[0084] Further optionally, the orthographic projection of the source metal 620 on the substrate 110 partially overlaps with the orthographic projection of the second gate oxide structure 320 on the substrate 110 .

[0085] Therefore, on the one hand, the distance between the source metal 620 and the gate metal 610 is extended to improve the safety of the device, and on the other hand, the electric field strength in the thin gate oxide layer 300 area is significantly reduced, reducing the probability of device failure due to breakdown and improving device reliability.

[0086] Second, see Figure 4 and Figures 3a to 3e The present invention provides a method for preparing a semiconductor device according to any one of the above embodiments. The method comprises:

[0087] S100, providing a substrate 110, and growing a drift region on one side of the substrate 110;

[0088] S200 , implanting ions of the first conductivity type into a side of the drift region facing away from the substrate 110 to obtain an epitaxial layer 120 and a main junction layer 200 located in the drift region;

[0089] S300 , setting a first mask, and implanting ions of the second conductivity type into the side of the main junction layer 200 facing away from the substrate 110 to obtain an adjustment region 210 ;

[0090] S400 , forming a gate oxide layer 300 on a side of the main junction layer 200 facing away from the substrate 110 ;

[0091] S500 , forming a gate dielectric layer 400 on a side of the gate oxide layer 300 facing away from the substrate 110 .

[0092] Optionally, the ions of the first conductivity type are P-type ions, and the ions of the second conductivity type are N-type ions.

[0093] Optionally, in step S300 , after the second conductive type ions are implanted, high temperature annealing is performed to activate the impurities.

[0094] See also Figure 5 According to some embodiments of the present application, step S400 includes:

[0095] S410 , depositing a thick oxide layer on the side of the main junction layer 200 facing away from the substrate 110 , setting a second mask, and etching the thick oxide layer to obtain a first gate oxide structure 310 ;

[0096] S420 , growing a thin oxide layer on the side of the main junction layer 200 facing away from the substrate 110 , setting a third mask, and etching the thin oxide layer to obtain a second gate oxide structure 320 .

[0097] Optionally, in step S420 , a thin oxide layer is prepared by low-temperature growth to improve the quality of the second gate oxide structure 320 .

[0098] According to certain embodiments of the present application, the preparation method further comprises:

[0099] S610 , depositing an isolation dielectric layer 500 on the side of the gate dielectric layer 400 facing away from the substrate 110 , setting a fourth mask, and etching the isolation dielectric layer 500 to form a gate contact hole and a source contact hole;

[0100] S620 , depositing metal in the gate contact hole to obtain gate metal 610 , and depositing metal in the source metal 620 hole to obtain source metal 620 .

[0101] In order to further verify the protective effect of the structure of the present application on the thin gate oxide layer area, TACD simulation verification is performed on the transition region structure of the present application and the prior art. GS =20V, source-drain voltage V DS =0V.

[0102] The traditional structure used in the experiment sets a shielding layer with the same conductivity type as the main junction layer between the main junction layer and the gate oxide layer in the transition region. For the specific structure, please refer to Figure 6 , please refer to the embodiment of the present application for the structure selected for the experiment Figure 2 Compared with the traditional structure, the embodiment of the present application does not introduce a P-type high-concentration doped region in the main junction layer, but instead sets a high-concentration N-type doped region below the thin gate oxide layer, and shortens the length of the source metal to above the thin gate oxide layer so that it no longer covers the thick oxide layer area.

[0103] Figure 7a is the electric field intensity distribution diagram of the traditional structure under experimental conditions, Figure 7b for Figure 7a A magnified view of the local electric field intensity distribution in the thin gate oxide layer area.

[0104] Figure 8a This is a diagram of the electric field intensity distribution under experimental conditions in the embodiment of this application. Figure 8b for Figure 8a A local enlarged view of the electric field strength distribution of the second gate oxide structure.

[0105] Figure 9 Based on Figure 7b and Figure 8b The obtained electric field intensity distribution characteristic curve of the traditional structure and the embodiment of the present application in the thin gate oxide layer area. Figure 7b and Figure 8b Combined with Figure 9 It is easy to see that compared with the traditional structure, the present application significantly weakens the electric field strength in the thin gate oxide layer area. The peak intensity of the traditional structure in the thin gate oxide layer is about 4.9MV / cm, and the peak intensity of the embodiment of the present application in the thin gate oxide layer is about 3.8MV / cm.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: The invention comprises a cell region, a gate bus and a transition region, wherein the transition region is located between the cell region and the gate bus, and the transition region comprises: substrate; an epitaxial layer, disposed on one side of the substrate; a main junction layer, disposed on a side of the epitaxial layer facing away from the substrate, the main junction layer comprising an adjustment region, the adjustment region being located on a side of the main junction layer facing away from the substrate, the adjustment region having a conductivity type opposite to that of the main junction layer; a gate oxide layer, disposed on a side of the main junction layer facing away from the substrate, comprising a first gate oxide structure close to the cell region, a second gate oxide structure close to the gate bus, and a third gate oxide structure located between the first and second gate oxide structures, wherein the thickness of the first gate oxide structure is greater than that of the second gate oxide structure, and the thickness of the third gate oxide structure gradually decreases along the direction from the cell region to the gate bus; a gate dielectric layer, disposed on a side of the gate oxide layer facing away from the substrate; The second gate oxide structure is in contact with the adjustment region, the orthographic projection of the second gate oxide structure on the substrate falls within the orthographic projection range of the adjustment region on the substrate, and the orthographic projection of the third gate oxide structure on the substrate at least partially falls within the orthographic projection range of the adjustment region on the substrate.

2. The semiconductor device according to claim 1, wherein The conductive ion concentration of the adjustment region is greater than the conductive ion concentration of the epitaxial layer.

3. The semiconductor device according to claim 1, wherein The transition zone also includes: an isolation dielectric layer, located on a side of the gate dielectric layer facing away from the substrate; a gate metal, located on a side of the isolation dielectric layer facing away from the substrate and in contact with the gate dielectric layer; a source metal, located on a side of the isolation dielectric layer facing away from the substrate and in contact with the main junction layer; The source metal and the gate metal are separated by the isolation dielectric layer, and the source metal and the gate dielectric layer are separated by the isolation dielectric layer.

4. The semiconductor device according to claim 3, wherein Along the direction from the cell region to the gate bus, the orthographic projection of the source metal on the substrate and the orthographic projection of the first gate oxide structure on the substrate are distributed alternately.

5. The semiconductor device according to claim 3, wherein The orthographic projection of the source metal on the substrate partially overlaps with the orthographic projection of the second gate oxide structure on the substrate.

6. A method for preparing a semiconductor device, for preparing the semiconductor device according to any one of claims 1 to 5, characterized in that: The preparation method comprises: providing a substrate and growing a drift region on one side of the substrate; Implanting ions of the first conductivity type into a side of the drift region facing away from the substrate to obtain an epitaxial layer and a main junction layer located in the drift region; Setting a first mask and implanting ions of the second conductivity type into the side of the main junction layer facing away from the substrate to obtain an adjustment region; forming a gate oxide layer on a side of the main junction layer facing away from the substrate; A gate dielectric layer is formed on the side of the gate oxide layer facing away from the substrate.

7. The method for preparing a semiconductor device according to claim 6, wherein: The step of forming a gate oxide layer on a side of the main junction layer facing away from the substrate comprises: Depositing a thick oxide layer on the side of the main junction layer facing away from the substrate, setting a second mask, and etching the thick oxide layer to obtain a first gate oxide structure; A thin oxide layer is grown on the side of the main junction layer facing away from the substrate, a third mask is set, and the thin oxide layer is etched to obtain a second gate oxide structure.

8. The method for preparing a semiconductor device according to claim 7, wherein: The preparation method further comprises: Depositing an isolation dielectric layer on the side of the gate dielectric layer facing away from the substrate, setting a fourth mask, and etching the isolation dielectric layer to obtain a gate contact hole and a source contact hole; The gate metal is obtained by metal deposition in the gate contact hole, and the source metal is obtained by metal deposition in the source contact hole.

Images