Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device and a manufacturing method thereof. The electronic device includes an electronic component, an encapsulation layer, a circuit structure, a bonding element, and a bolt. The encapsulation layer surrounds the electronic component. The circuit structure is electrically connected to the electronic component. The bonding element is electrically connected to the electronic element through the circuit structure. The plug pin is arranged between the circuit structure and the packaging layer.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a manufacturing method thereof. Background Art

[0002] During the manufacturing process of electronic devices, such as chip transfer or packaging, the chip may shift due to process deviation or thermal expansion and contraction, resulting in misalignment between the circuit structure formed on the chip and the chip, thereby affecting the electrical performance of the chip. Summary of the invention

[0003] The present disclosure provides an electronic device and a manufacturing method thereof, which are helpful to reduce the adverse effects caused by chip shift.

[0004] According to some embodiments of the present disclosure, an electronic device includes an electronic component, a packaging layer, a circuit structure, a bonding element, and a plug. The packaging layer surrounds the electronic component. The circuit structure is electrically connected to the electronic component. The bonding element is electrically connected to the electronic component through the circuit structure. The plug is arranged between the circuit structure and the packaging layer.

[0005] According to other embodiments of the present disclosure, an electronic device includes a packaging structure and a circuit structure. The packaging structure includes a first electronic component, a second electronic component, and a packaging layer surrounding the first electronic component and the second electronic component. The first electronic component is electrically connected to the second electronic component through the circuit structure. The circuit structure includes a first contact portion overlapping a first pad of the first electronic component and a second contact portion overlapping a second pad of the second electronic component. The first contact portion is aligned with the first pad, and the second contact portion is misaligned with the second pad.

[0006] According to some other embodiments of the present disclosure, an electronic device includes an electronic component, a packaging layer, and a circuit structure. The packaging layer surrounds the electronic component. The circuit structure is electrically connected to the electronic component. The electronic component includes a plurality of pads, and the circuit structure includes a plurality of contact portions respectively overlapping the plurality of pads. One of the plurality of contact portions is aligned with a corresponding pad, and another of the plurality of contact portions is misaligned with another corresponding pad.

[0007] According to some further embodiments of the present disclosure, a method for manufacturing an electronic device includes: transferring multiple electronic components to a carrier; forming a packaging layer around the multiple electronic components; obtaining position information of at least one electronic component among the multiple electronic components; comparing the position information of the at least one electronic component with a reference value to obtain an offset; and forming a circuit structure on the multiple electronic components and the packaging layer, wherein the circuit structure includes multiple contact portions that contact multiple pads of the multiple electronic components, and the position of each of the multiple contact portions is compensated according to the offset so that at least one of the multiple contact portions is aligned with the corresponding at least one pad.

[0008] In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a top view schematic diagram showing the transfer of a plurality of electronic components onto a carrier board;

[0010] Figure 2 It corresponds to Figure 1 A schematic cross-sectional view of the middle section line I-I';

[0011] Figure 3 is a schematic cross-sectional view showing a packaging layer formed around a plurality of electronic components;

[0012] Figure 4 is a cross-sectional schematic diagram showing a flip carrier;

[0013] Figure 5 is a top view schematic diagram showing obtaining position information of at least one electronic component among a plurality of electronic components and comparing the position information of the at least one electronic component with a reference value to obtain an offset;

[0014] Figure 6 is a cross-sectional schematic diagram showing a circuit structure formed on a plurality of electronic components and a packaging layer;

[0015] Figure 7 is a cross-sectional schematic diagram showing a cut circuit structure and a packaging layer;

[0016] Figure 8 is a schematic cross-sectional view showing the formation of a bonding element on a circuit structure;

[0017] Fig. 9 is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0018] FIG. 10A to FIG. 10C They are Fig. 9 A top view of the middle area RA, the area RB and the area RC;

[0019] Fig.11A as well as Fig. 11B They are respectively top view schematic diagrams of two electronic devices according to other embodiments of the present disclosure;

[0020] Fig.12 is a cross-sectional schematic diagram of an electronic device according to some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0022] Certain words are used throughout the present disclosure and in the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, the words "including" and "comprising" are open-ended words and should therefore be interpreted as "including but not limited to..."

[0023] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0024] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in various embodiments to describe the relative relationship of one element of the drawings to another element. It is understood that if the device in the drawings is turned upside down, the element described as being on the "lower" side will become the element on the "upper" side. The embodiments of the present disclosure may be used in conjunction with the attached drawings. Figure 1 It is also understood that the drawings of the present disclosure are also considered as part of the disclosure.

[0025] A structure (or layer, element, substrate) described in the present disclosure is located on / above another structure (or layer, element, substrate), which may refer to the two structures being adjacent and directly connected, or it may refer to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate interval) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is disposed "on" another structure, it may refer to that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0026] The terms "approximately", "substantially" or "substantially" are generally interpreted as within 10% of a given value or range, or as within 5%, 3%, 2%, 1% or 0.5% of a given value or range. In addition, the phrases "a range is from a first value to a second value", "a range is between a first value and a second value" indicate that the range includes the first value, the second value and other values ​​therebetween.

[0027] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements. They do not imply or represent any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the element with a certain name clearly distinguishable from another element with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claim.

[0028] The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or a combination of the above components between the endpoints of the components on the two circuits, but it is not limited to these.

[0029] In the present disclosure, the thickness, length and width can be measured by using an optical microscope (OM), and the thickness or width can be measured by a cross-sectional image in an electron microscope, but it is not limited thereto. In addition, any two values ​​or directions used for comparison may have a certain error. In addition, the term "a given range is from a first value to a second value", "a given range falls within the range from a first value to a second value" or "a given range is between a first value and a second value" means that the given range includes the first value, the second value and other values ​​therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0031] In the present disclosure, the electronic device may include a power device, a semiconductor packaging device, a display device, a backlight device, an antenna device, a packaging device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The display device may, for example, include liquid crystal, light-emitting diode, fluorescence, phosphor, quantum dot (quantum dot, QD), other suitable display media or a combination of the foregoing. The antenna device may, for example, include a reconfigurable surface (Reconfigurable Intelligent Surface, RIS), a frequency selective surface (Frequency Selective Surface, FSS), a radio frequency filter (RF-Filter), a polarizer (Polarizer), a resonator (Resonator) or an antenna (Antenna), etc. The antenna may be a liquid crystal type antenna or a varactor diode (Varactor Diodes) antenna. The sensing device may be a sensing device that senses capacitance, light, heat energy or ultrasound, but is not limited thereto. In the present disclosure, the electronic device may include electronic components, and the electronic components may include passive components and active components, such as known good chips (KGD), capacitors, resistors, inductors, diodes, transistors, varactors, variable capacitors, filters, sensors, micro-electromechanical system components (MEMS), liquid crystal chips, semiconductor-related process structures, or semiconductor-related process structures disposed on a substrate (such as polyimide, glass, silicon substrate or other suitable substrate materials), but not limited thereto. The diode may include a light-emitting diode, a varactor diode or a photodiode. The light-emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED or a quantum dot light-emitting diode (quantum dot LED), but not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but not limited thereto. It should be noted that the electronic device may be any combination of the foregoing, but not limited thereto. The packaged device may be a packaged device applicable to wafer-level package (WLP) technology or panel-level package (WLP) technology, such as a chip first process or a chip last load (RDLfirst) process.In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, a wearable device (for example, including augmented reality or virtual reality), a vehicle-mounted device (for example, including a car windshield) or a splicing device. The following embodiments illustrate some implementation forms of electronic devices with packaging devices as examples, but are not limited to this. According to the embodiments of the present disclosure, the manufacturing method of the provided electronic device can be applied, for example, to a wafer-level package (WLP) process or a panel-level package (PLP) process, and a chip first process or a chip last / RDL first process can be adopted, which will be further described in detail below. According to the embodiments of the present disclosure, the packaging structure of the electronic device may include a system on package (SoC), a system in package (SiP), an antenna package (AiP) or a combination thereof, but is not limited to this.

[0032] Figure 1 is a top view schematically showing the transfer of a plurality of electronic components onto a carrier board. Figure 2 It corresponds to Figure 1 Schematic cross-section diagram along the center line II'. Figure 3 2 is a schematic cross-sectional view showing a packaging layer formed around a plurality of electronic components. Figure 4 2 is a cross-sectional schematic diagram showing a flipped carrier. Figure 5 The diagram is a top view schematically showing the process of obtaining position information of at least one electronic component among a plurality of electronic components and comparing the position information of the at least one electronic component with a reference value to obtain an offset. Figure 6 It is a cross-sectional schematic diagram showing a circuit structure formed on multiple electronic components and packaging layers. Figure 7 is a cross-sectional schematic diagram showing a cut circuit structure and a packaging layer. Figure 8 1 is a schematic cross-sectional view showing the formation of a bonding element on a circuit structure. Fig. 9 is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure. FIG. 10A to FIG. 10C They are Fig. 9 Schematic top view of the middle area RA, area RB and area RC. Fig.11A as well as Fig. 11B The figures are top views of two electronic devices according to other embodiments of the present disclosure. Fig.122 is a cross-sectional schematic diagram of an electronic device according to some other embodiments of the present disclosure. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0033] Figures 1 to 8 is a flow chart of a method for manufacturing an electronic device according to some embodiments of the present disclosure. According to some embodiments, the method for manufacturing an electronic device may include transferring a plurality of electronic components 10 to a carrier board CR1 (eg Figure 1 as well as Figure 2 Forming a packaging layer 11 around a plurality of electronic components 10 (as shown in Figure 3 as well as Figure 4 ); obtaining position information of at least one electronic component among the plurality of electronic components 10 (such as Figure 5 ); comparing the position information of at least one electronic component with a reference value to obtain an offset (such as Figure 5 ); and forming a circuit structure 12 on the plurality of electronic components 10 and the packaging layer 11, wherein the circuit structure 12 includes a plurality of contact portions 120 contacting the plurality of pads 102 of the plurality of electronic components 10, and the position of each of the plurality of contact portions 120 is compensated according to the offset, so that at least one of the plurality of contact portions 120 is aligned with the corresponding at least one pad 102 (as shown in FIG. Figure 6 shown).

[0034] For details, please refer to Figure 1 as well as Figure 2 , the multiple electronic components 10 can be transferred to the carrier CR1, for example, by a pick and place (PnP) process. In some embodiments, an adhesive layer or a release layer (not shown) can be formed on the carrier CR1 first, and then the multiple electronic components 10 can be transferred to the carrier CR1, so that the multiple electronic components 10 can be temporarily fixed on the carrier CR1 by the adhesive layer or the release layer. The adhesive layer or the release layer can lose its viscosity by being heated or exposed to light, so that the multiple electronic components 10 can be separated from the carrier CR1.

[0035] In some embodiments, the plurality of electronic components 10 may be transferred to the carrier CR1 through multiple pick-and-place processes. In some embodiments, the plurality of electronic components 10 may include a plurality of electronic components having different design parameters such as purpose, size, type, shape, number of pads and / or pad pitch. For example, transferring the plurality of electronic components 10 to the carrier CR1 may include transferring a plurality of first electronic components 10A and a plurality of second electronic components 10B to the carrier CR1, wherein the first electronic component 10A, for example, has a greater number of pads than the second electronic component 10B or has a smaller pad pitch P (pitch) than the second electronic component 10B. The pad pitch P may be the distance between two corresponding side edges of two adjacent pads (for example, the distance between the two right sides of two adjacent pads or the distance between the two left sides of two adjacent pads) or the distance between the two center lines of two adjacent pads. As an example, Figure 2 The pad pitch P is indicated by the distance between the two right sides of two adjacent pads.

[0036] by Figure 2 For example, each electronic component 10 may include a chip 100, a pad 102, and a buffer layer 104, wherein the pad 102 is disposed on the chip 100, and the buffer layer 104 is disposed on the chip 100 and has an opening (such as opening A or opening B) exposing the pad 102. In this document, a component is disposed on another component to describe the relative arrangement relationship between the two components, and does not limit the process steps or sequence of the two components.

[0037] exist Figure 2In the embodiment, the first electronic component 10A includes a first chip 100A, a first pad 102A, and a first buffer layer 104A, wherein the first pad 102A is disposed on the first chip 100A, and the first buffer layer 104A is disposed on the first chip 100A and has an opening A exposing the first pad 102A. In some embodiments, the first electronic component 10A may include a plurality of first pads 102A, and the first buffer layer 104A may have a plurality of openings A respectively exposing the plurality of first pads 102A. Among the plurality of surfaces of the first chip 100A, the surface on which the first pad 102A is disposed is an active surface SA1 of the first chip 100A, and the surface opposite to the active surface SA1 is a back surface SA2 of the first chip 100A. The second electronic component 10B includes a second chip 100B, a second pad 102B, and a second buffer layer 104B, wherein the second pad 102B is disposed on the second chip 100B, and the second buffer layer 104B is disposed on the second chip 100B and has an opening B exposing the second pad 102B. In some embodiments, the second electronic component 10B may include a plurality of second pads 102B, and the second buffer layer 104B may have a plurality of openings B respectively exposing the plurality of second pads 102B. Among the plurality of surfaces of the second chip 100B, the surface on which the second pad 102B is disposed is the active surface SB1 of the second chip 100B, and the surface opposite to the active surface SB1 is the back surface SB2 of the second chip 100B.

[0038] exist Figure 2 In the embodiment, multiple electronic components 10 (such as multiple first electronic components 10A and multiple second electronic components 10B) are arranged on the carrier CR1 with the active surface (such as active surface SA1 and active surface SB1) facing downward, so that the active surface (such as active surface SA1 and active surface SB1) of multiple chips 100 (such as multiple first chips 100A and multiple second chips 100B) is located between the back surface (such as back surface SA2 and back surface SB2) and the carrier CR1. This process can be called a chip-down process, but the present disclosure is not limited thereto. In other embodiments, although not shown, multiple electronic components 10 can be arranged on the carrier CR1 with the active surface facing upward, so that the back surface of the multiple chips 100 is located between the active surface and the carrier CR1. This process can be called a chip-up process.

[0039] The first electronic component 10A has a greater number of pads than the second electronic component 10B, for example, means that the total number of first pads 102A in at least one of the plurality of first electronic components 10A is greater than the total number of second pads 102B in at least one of the plurality of second electronic components 10B. The first electronic component 10A has a smaller pad pitch than the second electronic component 10B, for example, means that the pitch PA between the plurality of first pads 102A in at least one of the plurality of first electronic components 10A is smaller than the pitch PB between the plurality of second pads 102B in at least one of the plurality of second electronic components 10B. The pitch between the plurality of pads may be the pitch between two adjacent pads in the direction D1, the pitch between two adjacent pads in the direction D2, or the pitch between two adjacent pads in the direction D1 and the direction D2. As an example, Figure 2 The pitch PA in the figure indicates the pitch between two adjacent first pads 102A in the direction D1, and the pitch PB indicates the pitch between two adjacent second pads 102B in the direction D1. In the case where the first electronic components 10A have a larger number of pads than the second electronic components 10B or a smaller pad pitch than the second electronic components 10B, the first electronic components 10A have a higher requirement for alignment accuracy.

[0040] In some embodiments, the first chip 100A and the second chip 100B may be digital chips, analog chips, mixed signal chips, logic chips, sensor chips, structures of semiconductor-related processes, or structures of semiconductor-related processes disposed on a substrate (e.g., polyimide, glass, silicon substrate or other suitable substrate materials) or other types of integrated circuit chips or combinations thereof. For example, the first chip 100A may be a system-on-chip (SoC), and the second chip 100B may be a high bandwidth memory (HBM), but not limited thereto. The materials of the first buffer layer 104A and the second buffer layer 104B include, for example, inorganic insulating materials or organic insulating materials or combinations thereof, but not limited thereto. Inorganic insulating materials include, for example, silicon oxide, silicon nitride, nitride, oxide or combinations thereof, but not limited thereto. Organic insulating materials include, for example, photosensitive polyimide (PSPI), polyimide, epoxy, polymer or combinations thereof, but not limited thereto. In some embodiments, the buffer layer may be a multi-layer stack. Specifically, along direction D3, at least one inorganic insulating material may be first formed on the chip, and then at least one organic insulating material may be formed on the inorganic insulating material, so that the inorganic insulating material is disposed between the chip and the organic insulating material, or part of the inorganic insulating material is disposed between the pad and the organic insulating material. In some embodiments, the material of the first buffer layer 104A and the second buffer layer 104B may further include a filler, and the particle size of the filler may be 0.05 μm to 10 μm (0.05 ≤ filler particle size ≤ 10 μm), but not limited thereto. The coefficient of thermal expansion (CTE) of the first buffer layer 104A and the second buffer layer 104B is, for example, 1 ppm / °C to 50 ppm / °C, but not limited thereto. The Young's modulus of the first buffer layer 104A and the second buffer layer 104B is, for example, 3 GPa to 20 GPa, but not limited thereto. The tensile strength of the first buffer layer 104A and the second buffer layer 104B is, for example, 50 MPa to 110 MPa, but is not limited thereto. The material of the first pad 102A and the second pad 102B includes, for example, a transparent conductive material or an opaque conductive material. The transparent conductive material may include metal oxide, graphene, other suitable transparent conductive materials, or a combination thereof. The metal oxide may include indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other metal oxides. The opaque conductive material may include a metal, an alloy, or a combination thereof.The pad may be, for example, one end of a transistor (eg, a source electrode, a gate electrode, and a drain electrode), but is not limited thereto.

[0041] In some embodiments, a plurality of first electronic components 10A are formed, for example, by forming a first buffer layer 104A on a wafer and then performing a singulation process on the first buffer layer 104A and the wafer. By using the first buffer layer 104A to absorb the stress in the singulation process, the damage to the wafer caused by the singulation process can be reduced. Similarly, a plurality of second electronic components 10B are formed, for example, by forming a second buffer layer 104B on another wafer and then performing a singulation process on the second buffer layer 104B and the other wafer. By using the second buffer layer 104B to absorb the stress in the singulation process, the damage to the other wafer caused by the singulation process can be reduced.

[0042] exist Figure 1 In the embodiment, each unit U may include a plurality of electronic components, for example, each unit U may include two electronic components, three electronic components or more than three electronic components, and the electronic components may have the same function or different functions. For example, each unit U may include a first electronic component 10A and two second electronic components 10B. The two second electronic components 10B (such as the second electronic component 10B1 and the second electronic component 10B2) may be respectively arranged on opposite sides of the first electronic component 10A in the direction D1. The plurality of units U may be arranged in an array along the direction D1 and the direction D2. The direction D1 and the direction D2 intersect with each other and are both perpendicular to the thickness direction of the carrier CR1 (such as the direction D3). In some embodiments, the direction D1 and the direction D2 are perpendicular to each other, but are not limited thereto. It should be understood that the types of the plurality of electronic components 10, the relative arrangement relationship of the plurality of electronic components in each unit U (such as the plurality of first electronic components 10A and the plurality of second electronic components 10B), the design parameters such as the size and / or shape may all be changed according to the needs, without being limited to the above. Figure 1 Shown are limited.

[0043] Please refer to Figure 3 After transferring a plurality of electronic components 10 (such as a plurality of first electronic components 10A and a plurality of second electronic components 10B) onto the carrier CR1, a packaging layer 11 surrounding the plurality of electronic components 10 may be formed. In this context, a component surrounding another component means that in a cross-sectional view, a component at least contacts one side surface of another component. In some embodiments, for example, Figure 3In the embodiment, the encapsulation layer 11 may contact all side surfaces and the back surface (such as the back surface SA2 and the back surface SB2) of each electronic component 10, but the present disclosure is not limited thereto. The encapsulation material of the encapsulation layer 11 may include, for example, a molding compound, a resin (such as an epoxy resin), a polymer, or a combination thereof, but is not limited thereto. In some embodiments, although not shown, the encapsulation layer 11 may be thinned by a planarization process. The planarization process may include a mechanical grinding process, a chemical mechanical polishing (CMP) process, or a combination thereof.

[0044] In some embodiments, Figure 2 As shown, before forming the packaging layer 11, the surface SCR1 of the carrier CR1 carrying the plurality of electronic components 10 may be selectively formed with one or more recesses R recessed into the surface SCR1. Figure 3 As shown, the packaging material may be filled into one or more recesses R, so that one or more bolts 14 may be formed simultaneously with the packaging layer 11. In other words, the bolts 14 and the packaging layer 11 may have the same material, and the bolts 14 and the packaging layer 11 may be integrally formed, but not limited thereto.

[0045] Please refer to Figure 4 After forming the encapsulation layer 11, the structure can be flipped onto another carrier CR2, and the carrier CR1 can be separated from the structure. For example, the release layer on the carrier CR1 can be heated or illuminated to make the release layer on the carrier CR1 lose its viscosity, so that the carrier CR1 can be separated from the structure. After flipping the structure onto another carrier CR2, the pads 102 of the electronic components 10 face upward, which is convenient for subsequent processes. In some embodiments, another release layer (not shown) can be formed on the carrier CR2 first, and then the structure can be flipped onto the carrier CR2, so that the encapsulation layer 11 can be temporarily fixed on the carrier CR2 through the other release layer. The other release layer can lose its viscosity by heating or irradiating light, so that the encapsulation layer 11 can be separated from the carrier CR2.

[0046] In some other embodiments, although not shown, if a plurality of electronic components 10 are disposed on the carrier CR1 with the active surface facing upward, the Figure 4 In the step of forming the packaging layer 11, the packaging material covering the plurality of pads 102 (such as the plurality of first pads 102A and the plurality of second pads 102B) may be removed by a planarization process or other patterning process. Optionally, in the step of removing the packaging material, one or more plugs 14 may be formed by a patterning process, but the present invention is not limited thereto.

[0047] Please refer to Figure 5 After forming the encapsulation layer 11 and forming the circuit structure 12 (refer to Figure 6 ), the offset of the electronic component may be detected before. Specifically, the position information of at least one electronic component among the plurality of electronic components 10 may be obtained first, and then the position information of the at least one electronic component may be compared with a reference value to obtain the offset. The reference value may be the position information of at least one position comparison reference (such as an alignment pattern), and the position information of at least one electronic component and at least one position comparison reference may be obtained by, for example, an automated optical inspection (AOI) system or other image capture device, and then the offset may be obtained by comparing the two position information.

[0048] In some embodiments, obtaining the position information of the at least one electronic component includes, for example, obtaining the position information of the center of the at least one electronic component, obtaining the position information of at least one pad of the at least one electronic component, or obtaining the position information of an alignment pattern (not shown) of the at least one electronic component. The center of the electronic component 10 is the intersection of two diagonal lines of the electronic component 10 in the top view, such as Figure 5 The alignment pattern of the electronic component 10 may be any line segment or mark in the electronic component 10 that is convenient for image recognition.

[0049] In some embodiments, comparing the position information of the at least one electronic component with the reference value includes, for example, comparing the position information of the at least one electronic component with the position information of the position comparison reference. The position information of the position comparison reference may be the position information of the alignment pattern on the carrier, the position information of the latch 14, or the position information of any pattern on the carrier.

[0050] The monitoring method can obtain the position information of at least one electronic component 10 on the carrier CR2. For example, if the total number of electronic components 10 on the carrier CR2 is N, only the position information of M electronic components can be detected, where M is a positive integer less than N. Through the above method, the time for offset detection can be shortened and the production capacity can be improved without affecting the electrical performance, but it is not limited to this.

[0051] The method proposed in the present disclosure includes: detecting the offset of at least one electronic component of at least one unit U, as described below. If the position information of a single electronic component 10 in a unit U is taken to perform offset detection, the position information of an electronic component with a higher requirement for alignment accuracy (such as a first electronic component 10A with a larger number of pads or a smaller pad pitch) may be taken to perform offset detection. For example, the center position information of the first electronic component 10A may be obtained, the position information of at least one first pad 102A of the first electronic component 10A may be obtained, or the position information of the alignment pattern of the first electronic component 10A may be obtained, and then this position information may be compared with a position comparison reference (such as an alignment pattern AR on the carrier CR2 or Figure 4 The offset can then be provided to the manufacturing circuit structure 12 (refer to Figure 6 ) is used to calculate a suitable compensation value according to the offset, and to compensate the plurality of contact portions 120 (such as the plurality of first pads 102A and the plurality of second pads 102B) in contact with the plurality of pads 102 (such as the plurality of first pads 102A and the plurality of second pads 102B) according to the offset. Figure 6 The position of each of the plurality of first contact portions 120A and the plurality of second contact portions 120B shown in the figure is compensated, and the machine may include, for example, a mask exposure machine, a maskless exposure machine, a laser machine or any machine equipment required in the electronic component manufacturing process.

[0052] The method proposed in the present disclosure includes: detecting the offset of at least one electronic component of at least one unit U, as described below. If the position information of more than one electronic component 10 in a unit U is used for offset detection, multiple electronic components 10 of the same type, such as the position information of more than two first electronic components 10A or the position information of more than two second electronic components 10B, can be used for offset detection, or multiple electronic components 10 of different types, such as the position information of at least one first electronic component 10A and the position information of at least one second electronic component 10B, can be used for offset detection.

[0053] If the position information of multiple electronic components 10 of the same type is used for offset detection, multiple electronic components with higher alignment accuracy requirements, such as multiple first electronic components 10A with a larger number of pads or a smaller pad pitch, can be used for offset detection. For example, the position information of M center positions of M first electronic components 10A, the position information of at least one first pad 102A of each of the M first electronic components 10A, or the position information of multiple alignment patterns (not shown) of the M first electronic components 10A can be obtained, and then these position information can be compared with the position comparison reference (such as the alignment pattern AR on the carrier CR2 or Figure 4The position information of the plug 14) is compared to obtain multiple offsets. At this time, the multiple offsets can be averaged, and then the average offset can be provided to the machine for manufacturing the circuit structure 12, so that the machine can compensate the position of each of the multiple contact portions 120 that contact the multiple pads 102 according to the offset, and then provide a qualified circuit structure 12. The above method can improve the electrical quality of the electronic device, but is not limited to this. In detail, after receiving the offset, the machine can compare it with the standard position and then compensate the position of the circuit structure, so that the formed circuit structure can be electrically connected to the electronic component.

[0054] If the position information of multiple electronic components 10 of different types is used for offset detection, the position information of at least one first electronic component 10A and at least one second electronic component 10B in at least one unit U may be obtained to perform offset detection. Figure 5 The schematic diagram shows obtaining the position information of all electronic components 10 in a unit U and the position information of the alignment pattern AR on the carrier CR2, and comparing these position information to obtain the offset. The position information may include coordinates on the plane where the direction D1 and the direction D2 are located. Figure 5 The coordinates (X1, Y1) represent the position information of the alignment pattern AR, the coordinates (X2, Y2) represent the position information of the center of the first electronic component 10A, and the coordinates (X3, Y3) and the coordinates (X4, Y4) represent the position information of the centers of the second electronic component 10B1 and the second electronic component 10B2, respectively.

[0055] In some embodiments, the offset of the first electronic component 10A (e.g., referred to as the first offset) can be confirmed by comparing the coordinates (X1, Y1) with the coordinates (X2, Y2). In some embodiments, the offset of the second electronic component 10B1 (e.g., referred to as the second offset) can be confirmed by comparing the coordinates (X2, Y2) with the coordinates (X3, Y3), or by comparing the coordinates (X1, Y1) with the coordinates (X3, Y3). Similarly, the offset of the second electronic component 10B2 (e.g., also referred to as the second offset) can be confirmed by comparing the coordinates (X2, Y2) with the coordinates (X4, Y4), or by comparing the coordinates (X1, Y1) with the coordinates (X4, Y4).

[0056] Next, the offset of the first electronic component 10A, the offset of the second electronic component 10B1, and the offset of the second electronic component 10B2 may be provided to the manufacturing circuit structure 12 (refer to Figure 6) is configured to calculate three compensation values ​​according to the offsets, wherein the position of each of the plurality of first contact portions 120A contacting the plurality of first pads 102A of the plurality of first electronic components 10A can be compensated according to the offset of the first electronic components 10A, the position of each of the plurality of second contact portions 120B contacting the plurality of second pads 102B of the plurality of second electronic components 10B1 (such as the second electronic components located on the left side of the first electronic components 10A in the plurality of units U) can be compensated according to the offset of the second electronic components 10B1, and the position of each of the plurality of second contact portions 120B contacting the plurality of second pads 102B of the plurality of second electronic components 10B2 (such as the second electronic components located on the right side of the first electronic components 10A in the plurality of units U) can be compensated according to the offset of the second electronic components 10B2.

[0057] Optionally, the offset detection of at least one second electronic component 10B in the unit U may be omitted. For example, the offset detection may be performed on more than one (i.e., greater than or equal to one) second electronic component 10B1 or second electronic component 10B2 in the unit U, and the position of each of the multiple second contact portions 120B in contact with the multiple second pads 102B of the multiple second electronic components 10B (such as the multiple second electronic components 10B1 and the multiple second electronic components 10B2) is compensated based on the obtained offset, so as to further simplify the offset detection or shorten the time of the offset detection.

[0058] That is, in the method for manufacturing an electronic device, obtaining the position information of the at least one electronic component 10 may at least include obtaining the position information of at least one first electronic component 10A among the plurality of first electronic components 10A, and comparing the position information of the at least one electronic component 10 with a reference value may at least include comparing the position information of the at least one first electronic component 10A with a position comparison reference to obtain a first offset of the offset. Figure 6 As shown, in the circuit structure 12, the plurality of contact portions 120 may include a plurality of first contact portions 120A contacting a plurality of first pads 102A of a plurality of first electronic components 10A and a plurality of second contact portions 120B contacting a plurality of second pads 102B of a plurality of second electronic components 10B, and the position of each of the plurality of first contact portions 120A and each of the plurality of second contact portions 120B may be compensated according to a first offset.

[0059] Alternatively, in the method for manufacturing an electronic device, obtaining the position information of the at least one electronic component 10 may further include obtaining the position information of at least one second electronic component (such as at least one second electronic component 10B1 or at least one second electronic component 10B2) among the plurality of second electronic components 10B, and comparing the position information of the at least one electronic component 10 with the reference value may further include comparing the position information of the at least one second electronic component with the position information of at least one first electronic component 10A, or with the position information of the position comparison reference, to obtain a second offset of the offset, and as Figure 6 As shown, the multiple contact portions 120 include multiple first contact portions 120A contacting multiple first pads 102A of multiple first electronic components 10A and multiple second contact portions 120B contacting multiple second pads 102B of multiple second electronic components 10B, wherein the position of each of the multiple first contact portions 120A is compensated according to the first offset, and the position of each of the multiple second contact portions 120B is compensated according to the second offset.

[0060] By detecting the offset of at least one electronic component 10 and compensating the position of each of the multiple contact portions 120 in the circuit structure 12 to be formed subsequently according to the obtained offset, the time for offset detection can be shortened, the amount of calculation can be simplified, or costs can be saved while improving production capacity.

[0061] Please refer to Figure 6 After the offset detection is performed, a circuit structure 12 may be formed on the plurality of electronic components 10 and the packaging layer 11, wherein the circuit structure 12 may include a plurality of contact portions 120 contacting the plurality of pads 102 of the plurality of electronic components 10, and the position of each of the plurality of contact portions 120 is compensated according to the offset, so that at least one of the plurality of contact portions 120 is aligned with the corresponding at least one pad 102. For example, at least one of the plurality of first contact portions 120A contacting the plurality of first pads 102A among the plurality of contact portions 120 may be aligned with the corresponding at least one first pad 102A, but is not limited thereto. In some embodiments, the plurality of first contact portions 120A contacting the plurality of first pads 102A among the plurality of contact portions 120 may be aligned with the plurality of first pads 102A, respectively, and the plurality of second contact portions 120B contacting the plurality of second pads 102B among the plurality of contact portions 120 may be aligned with the plurality of second pads 102B, respectively. In this article, alignment of a certain element with another element means that the center of a certain element overlaps with the center of another element in the direction D3. On the contrary, a misalignment between one element and another element means that the center of one element does not overlap with the center of another element in the direction D3, or that the overlapping area of ​​the two elements is smaller than the area of ​​the element with a smaller area of ​​the two elements.

[0062] The circuit structure 12 may also be referred to as a redistribution structure. In some embodiments, the circuit structure 12 may include at least one insulating layer and at least one conductive layer. Figure 6 In the example, two insulating layers and three conductive layers are used, but the circuit structure 12 may include more or fewer insulating layers and conductive layers as required. Through the above-mentioned at least one insulating layer and at least one conductive layer, the circuit can be re-routed and / or the circuit fan-out or fan-in area can be increased, or different electronic components 10 can be electrically connected to each other through the circuit structure 12. For example, the spacing between two adjacent contact pads of the circuit structure contacting one end of the chip can be less than or equal to the spacing between two adjacent contact pads of the circuit structure away from one end of the chip, so the circuit structure can adjust the circuit fan-out condition, but is not limited to this. The method of forming the circuit structure 12 may include using a lithography etching process, a surface treatment process, a laser process, an electroplating process, a deposition process or other processes to form at least one insulating layer and at least one conductive layer. The surface treatment process includes roughening the surface of the insulating layer or the surface of the conductive layer to improve its bonding ability.

[0063] The surface roughness can be measured by using a scanning electron microscope (SEM), a transmission electron microscope (TEM), etc., to observe the surface undulations at the same appropriate magnification, and the undulations can be compared by taking a unit length (e.g., 10 μm). An appropriate magnification means that at least 10 undulating peaks can be seen on at least one surface under the field of view of this magnification. In some embodiments, the surface undulations of the insulating layer or the conductive layer can be made to have a height difference of 0.15 μm to 3 μm in the peaks and valleys of the surface undulations. For example, the peaks and valleys of the surface undulations of the conductive layer C3 can be made to have a height difference of 0.15 μm to 3 μm to improve its bonding ability.

[0064] like Figure 6As shown, the circuit structure 12 may include a conductive layer C1, an insulating layer IN1, a conductive layer C2, an insulating layer IN2, and a conductive layer C3, but is not limited thereto. Each of the conductive layer C1, the conductive layer C2, and the conductive layer C3 may be a single conductive layer or a conductive stack. In addition, the materials of the conductive layer C1, the conductive layer C2, and the conductive layer C3 may include metals, alloys, or a combination thereof. The materials of the insulating layer IN1 and the insulating layer IN2 may include organic insulating materials, inorganic insulating materials, or a combination thereof. Organic insulating materials, for example, include polymethyl methacrylate (PMMA), epoxy resin, acrylic-based resin, silicone, polyimide polymer, or a combination thereof, but is not limited thereto. Inorganic insulating materials, for example, include silicon oxide or silicon nitride, but are not limited thereto.

[0065] The conductive layer C1 may be a patterned conductive layer and may include a plurality of circuits CK1 and a plurality of contact portions 120. The plurality of circuits CK1 may be disposed on the plurality of chips 10, the packaging layer 11 and the plurality of plugs 14. Each contact portion 120 may extend from a corresponding circuit CK1 into the opening A or the opening B and contact a corresponding pad 102.

[0066] The insulating layer IN1 is disposed on the conductive layer C1, the plurality of chips 10, the packaging layer 11, and the plurality of plugs 14. The conductive layer C2 is disposed on the insulating layer IN1. The conductive layer C2 may be a patterned conductive layer and may include a plurality of circuits CK2 and a plurality of conductive vias V2. The plurality of circuits CK2 may be disposed on the insulating layer IN1. Each conductive via V2 may penetrate the insulating layer IN1 from a corresponding circuit CK2 and be electrically connected to a corresponding circuit CK1.

[0067] The insulating layer IN2 is disposed on the conductive layer C2 and the insulating layer IN1 and includes a plurality of vias TH. Each via TH exposes a local area of ​​a corresponding line CK2. The conductive layer C3 may be a patterned conductive layer and may include a plurality of conductive pillars CC. Each conductive pillar CC is disposed in a corresponding via TH and contacts a local area of ​​a corresponding line CK2.

[0068] like Figure 6As shown, a plurality of plugs 14 may be disposed between the packaging layer 11 and the circuit structure 12. In some embodiments, the thickness T14 of the plug 14 is, for example, less than the thickness TIN1 of the insulating layer IN1 and the thickness TC1 of the conductive layer C1. Specifically, in the same cross-sectional view, the maximum thickness T14 of the plug 14 is less than or equal to half of the maximum thickness of the insulating layer IN1 (T14≤1 / 2*TIN1), or the maximum thickness T14 of the plug 14 is less than or equal to one-third of the maximum thickness of the insulating layer IN1 (T14≤1 / 3*TIN1), and the maximum thickness T14 of the plug 14 is less than or equal to one-half of the maximum thickness TC1 of the conductive layer C1 (T14≤1 / 2*TC1), or the maximum thickness T14 of the plug 14 is less than or equal to one-third of the maximum thickness TC1 of the conductive layer C1 (T14≤1 / 3*TC1), so as to reduce the probability of disconnection of the plurality of lines CK1 due to the plug 14. In some embodiments, as Figure 6 As shown, the number of electronic components 10 surrounded by the packaging layer 11 can be multiple, and the width W14 of the plug 14 can be smaller than the distance D10 between two adjacent electronic components 10. The packaging layer 11 and the circuit structure 12 are interlocked by the plug 14, which helps to improve the peeling problem caused by the opposite warping directions of the packaging layer 11 and the circuit structure 12 in the subsequent process.

[0069] Please refer to Figure 7 In some embodiments, the method for manufacturing an electronic device may further include cutting the packaging layer 11 and the circuit structure 12 to separate the plurality of units U from each other. The cutting tool may include a laser or a knife, which is not limited here.

[0070] Please refer to Figure 8 In some embodiments, the method for manufacturing an electronic device may further include forming a plurality of bonding elements 13 on the circuit structure 12, wherein the plurality of bonding elements 13 are, for example, respectively electrically connected to a plurality of conductive pillars CC in the circuit structure 12. In some embodiments, the method for manufacturing an electronic device may further include heating or irradiating a release layer (not shown) on the carrier CR2 to make the release layer on the carrier CR2 lose its viscosity, so as to separate the carrier CR2 from the packaging layer 11. In this way, the manufacturing of the electronic device 1 can be preliminarily completed.

[0071] It should be understood that Figures 1 to 8 The steps shown are merely examples, and the method for manufacturing an electronic device may add or reduce one or more steps in the above steps, or may improve the above steps.

[0072] In some embodiments, Fig. 9As shown, the electronic device 1A may include an electronic component 10, a packaging layer 11, a circuit structure 12, a bonding element 13 and a plug 14. The packaging layer 11 surrounds the electronic component 10. The circuit structure 12 is electrically connected to the electronic component 10. The bonding element 13 is electrically connected to the electronic component 10 through the circuit structure 12. The plug 14 is arranged between the circuit structure 12 and the packaging layer 11.

[0073] In the electronic device 1A, the contact portion 120 in the circuit structure 12 that contacts the pad 102 may be misaligned with the pad 102. Fig. 9 As shown, in the same cross-sectional view, the number of pads 102 of the electronic component 10 may be multiple, and the circuit structure 12 may include multiple contact portions 120 overlapping the multiple pads 102, wherein the overlapping degrees of the multiple contact portions 120 and the multiple pads 102 may be different. For example, the electronic component 10 may include a first pad 102A and a first pad 102A' (not labeled), and the circuit structure 12 may include a first contact portion 120A and a first contact portion 120A' (not labeled), the first contact portion 120A overlaps the first pad 102A, and the first contact portion 120A' overlaps the first pad 102A', then the overlapping degree of the first contact portion 120A may be different from the overlapping degree of the first contact portion 120A'. The different overlapping degrees include: (1) the overlapping area is the same, but the distance between the center of the pad and the center of the contact portion is different; and (2) the overlapping area is different. In some embodiments, the area ratio of the plurality of pads 102 that completely overlaps with the plurality of contact portions 120 may be greater than or equal to 70% to have good electrical performance. In this context, two elements completely overlap means that the centers of the two elements overlap or align in the direction D3. Fig. 10A An example is shown in which the pad 102 and the contact portion 120 are misaligned or not completely overlapped. Fig. 10A In the diagram, the center C102 of the pad 102 and the center C120 of the contact portion 120 do not overlap in the direction D3, and in the top view, the overlapping area between the pad 102 and the contact portion 120 is smaller than the area of ​​the pad 102, for example, the orthographic projection of the pad 102 on the packaging layer 11 does not completely fall within the orthographic projection of the contact portion 120 on the packaging layer 11, and a portion of the orthographic projection of the pad 102 on the packaging layer 11 protrudes outside the orthographic projection of the contact portion 120 on the packaging layer 11.

[0074] Fig. 10B Another example is shown in which the pad 102 and the contact portion 120 are misaligned or not completely overlapped. Fig. 10B In the diagram, the center C102 of the pad 102 and the center C120 of the contact portion 120 do not overlap in the direction D3 , but in the top view, the orthographic projection of the pad 102 on the packaging layer 11 completely falls within the orthographic projection of the contact portion 120 on the packaging layer 11 .

[0075] Fig. 10C An example is shown where the pad 102 is aligned with or completely overlaps the contact portion 120. Fig. 10C In the embodiment, the center C102 of the pad 102 overlaps with the center C120 of the contact portion 120 in the direction D3.

[0076] The aforementioned different overlapping degrees between the plurality of contact portions 120 and the plurality of pads 102 may refer to the plurality of contact portions 120 and the plurality of pads 102 having a variety of different overlapping areas, for example Fig. 10A The overlapping area between the middle contact portion 120 and the pad 102 is less than Fig. 10B or Fig. 10C The overlapping area between the contact portion 120 and the pad 102. In the case where the pad 102 and the contact portion 120 are misaligned or not completely overlapped, the overlapping area between the pad 102 and the contact portion 120 is, for example, 70% or more of the area of ​​the pad 102 to have good electrical performance. In detail, the area referred to in the present disclosure refers to the area A of the pad 102 exposed by the buffer layer 104 in a projection direction (such as direction D3), and the contact portion 120 contacting the pad 102 has an area B, where (B-the area of ​​the contact portion 120 that does not overlap the contact pad 102 (for example Fig. 10A The middle oblique line portion)) / A*100≥70% can maintain good electrical performance, wherein the area of ​​the contact portion 120 is the bottom area, that is, the area of ​​the contact portion 120 can be the area of ​​the portion directly contacting the pad 102. According to some embodiments, the area of ​​the pad 102 is almost equal to the bottom area of ​​the contact portion 120. For ease of description, circles of different sizes are used in the figure for illustration.

[0077] Alternatively, the aforementioned different overlapping degrees between the plurality of contact portions 120 and the plurality of pads 102 may refer to the plurality of contact portions 120 and the plurality of pads 102 having different degrees of center offset. The center offset refers to the offset between the center C102 of the pad 102 and the center C120 of the contact portion 120. For example Fig. 10A The offset between the center C102 of the middle pad 102 and the center C120 of the contact portion 120 is greater than Fig. 10B The offset between the center C102 of the middle pad 102 and the center C120 of the contact portion 120, and Fig. 10B The center offset in is greater than Fig. 10C The offset between the center C102 of the middle pad 102 and the center C120 of the contact portion 120 .

[0078] In the electronic device 1A, the positions of the multiple pads 102 of the same electronic component 10 may be offset due to process deviation or thermal expansion and contraction, resulting in different distances DT102 between the center C102 of the multiple pads 102 adjacent to the edge S11 of the packaging layer 11 and the edge S11. FIG. 10A to FIG. 10C On the other hand, since the positions of the multiple contact portions 120 corresponding to the same electronic component 10 are compensated according to the same deviation value (see above), the distance DT120 between the center C120 of the multiple contact portions 120 adjacent to the edge S11 of the packaging layer 11 and the edge S11 is the same, as shown in FIG. FIG. 10A to FIG. 10C shown.

[0079] exist Fig. 9 In the embodiment, the encapsulation layer 11 and the circuit structure 12 are interlocked with each other by using the plug 14, which helps to improve the peeling problem caused by the opposite warping directions of the encapsulation layer 11 and the circuit structure 12. However, in other embodiments, although not shown in Fig. 9 , the electronic device 1A may not include the plug 14. For example, the plug 14 may be cut during the aforementioned step of cutting the packaging layer 11 and the circuit structure 12 (eg Figure 7 ) is removed, but not limited thereto. Thus, the electronic device 1A includes an electronic component 10, a packaging layer 11, and a circuit structure 12. The packaging layer 11 surrounds the electronic component 10. The circuit structure 12 is electrically connected to the electronic component 10. The electronic component 10 includes a plurality of pads 102, and the circuit structure 12 includes a plurality of contact portions 120 respectively overlapping the plurality of pads 102. One of the plurality of contact portions 120 can be aligned with a corresponding pad 102 (e.g., Fig. 10C ), and another contact portion 120 among the plurality of contact portions 120 may be misaligned with another corresponding pad 102 (as shown in FIG. Fig. 10A or Fig. 10B As mentioned above, in the structure where the contact portion 120 is aligned with the corresponding pad 102, as shown in FIG. Fig. 10C As shown, the overlapping area of ​​the contact portion 120 and the corresponding pad 102 may be equal to the area of ​​the corresponding pad 102; on the other hand, in the structure where the contact portion 120 and the corresponding pad 102 are misaligned, as shown in FIG. Fig. 10A As shown, the overlapping area between the contact portion 120 and the corresponding pad 102 may be 70% or more and less than 100% of the area of ​​the corresponding pad 102 , that is, the overlapping area may be greater than or equal to 0.7 times the area of ​​the pad 102 and less than or equal to the area of ​​the pad 102 .

[0080] Please refer to Fig.11A as well as Fig. 11B .exist Fig.11A as well as Fig. 11BIn order to clearly show the relative arrangement relationship between the multiple electronic components, only the multiple electronic components 10 and the packaging layer 11 are schematically shown, and the aforementioned circuit structure 12 is omitted. In addition, to simplify the description, Fig.11A as well as Fig. 11B Only one first pad 102A and one corresponding first contact portion 120A of the first electronic component 10A are schematically shown.

[0081] Fig.11A as well as Fig. 11B The electronic device shown is, for example, Figures 1 to 8 The two packaged devices formed by the steps shown. Fig.11A as well as Fig. 11B In the two electronic devices shown, the position of the pad (such as the first pad 102A) of the electronic component 10 (such as the first electronic component 10A) may be offset due to process deviation or thermal expansion and contraction, so the distance (such as the distance DT102) between the center (such as the center C102) of the pad (such as the first pad 102A) of the same electronic component (such as the first electronic component 10A) in different electronic devices and the edge S11 of the packaging layer 11 is not the same. On the other hand, since the position of the contact portion (such as the first contact portion 120A) corresponding to the same electronic component (such as the first electronic component 10A) in different electronic devices is compensated according to the same deviation value (refer to the above), the distance DT120 between the center (such as the center C120) of the contact portion (such as the first contact portion 120A) in different electronic devices and the edge S11 is the same.

[0082] Please refer to Fig.12 , the electronic device 1B may include a packaging structure and a circuit structure 12. The packaging structure may include a first electronic component 10A, a second electronic component 10B, and a packaging layer 11 surrounding the first electronic component 10A and the second electronic component 10B. The first electronic component 10A is electrically connected to the second electronic component 10B through the circuit structure 12. The circuit structure 12 includes a first contact portion 120A overlapping the first pad 102A of the first electronic component 10A and a second contact portion 120B overlapping the second pad 102B of the second electronic component 10A. The first contact portion 120A is aligned with the first pad 102A (for example, with reference to region RC), and the second contact portion 120B is misaligned with the second pad 102B (for example, with reference to region RA).

[0083] In some embodiments, Fig. 10C As shown, the overlapping area of ​​the first contact portion 120A and the first pad 102A may be equal to the area of ​​the first pad 102A; on the other hand, Fig. 10AAs shown, the overlapping area between the second contact portion 120B and the second pad 102B may be 70% or more and less than 100% of the area of ​​the second pad 102B, that is, the overlapping area may be greater than or equal to 0.7 times the area of ​​the second pad 102B and less than or equal to the area of ​​the pad 102. In some embodiments, as Fig.12 As shown, the first electronic component 10A and the second electronic component 10B may satisfy at least one of the following: the first electronic component 10A has a greater number of pads than the second electronic component 10B; and the first electronic component 10A has a smaller pad pitch than the second electronic component 10B (for example, the pitch PA is smaller than the pitch PB).

[0084] In summary, in the embodiments of the present disclosure, by performing offset detection and compensating the positions of multiple contact portions in the circuit structure according to the obtained offset, the adverse effects caused by chip offset can be reduced.

[0085] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0086] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure, and the features between the embodiments can be arbitrarily mixed and replaced with each other to form other new embodiments. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any technician in the technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure content of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment. The scope of protection of the present disclosure shall be determined by the attached claims.

Claims

1. An electronic device, characterized in that: include: Electronic components; A packaging layer surrounding the electronic component; A circuit structure electrically connected to the electronic component; a bonding element electrically connected to the electronic element through the circuit structure; as well as The plug is arranged between the circuit structure and the packaging layer.

2. The electronic device according to claim 1, characterized in that: The circuit structure includes an insulating layer and a conductive layer, and the thickness of the plug is smaller than the thickness of the insulating layer and the thickness of the conductive layer.

3. The electronic device according to claim 1, characterized in that: There are multiple electronic components surrounded by the packaging layer, and the width of the plug is smaller than the distance between two adjacent electronic components.

4. The electronic device according to claim 1, characterized in that: The electronic components include: chip; a pad disposed on the chip and having an opening; and The buffer layer is disposed on the chip and has an opening exposing the pad.

5. The electronic device according to claim 4, characterized in that: The contact portion in the circuit structure that contacts the pad is misaligned with the pad.

6. The electronic device according to claim 4, characterized in that: The electronic component includes at least two first pads, and the circuit structure includes at least two contact portions respectively overlapping the at least two first pads, wherein the degree to which one of the at least two first pads overlaps one of the at least two contact portions is different from the degree to which the other one of the at least two first pads overlaps the other one of the at least two contact portions.

7. The electronic device according to claim 6, characterized in that: The ratio of one of the at least two first pads overlapping one of the at least two contact portions is greater than or equal to 70%, and the ratio of the other of the at least two first pads overlapping the other of the at least two contact portions is greater than or equal to 70%.

8. A method for manufacturing an electronic device, characterized in that: include: Transferring multiple electronic components to a carrier board; forming an encapsulation layer surrounding the plurality of electronic components; Acquire location information of at least one electronic component among the plurality of electronic components; comparing the position information of the at least one electronic component with a reference value to obtain an offset; as well as A circuit structure is formed on the multiple electronic components and the packaging layer, wherein the circuit structure includes multiple contact portions that contact multiple pads of the multiple electronic components, and the position of each of the multiple contact portions is compensated according to the offset so that at least one of the multiple contact portions is aligned with at least one corresponding pad.

9. The method for manufacturing an electronic device according to claim 8, characterized in that: Acquiring the position information of the at least one electronic component includes: Acquiring position information of a center of the at least one electronic component; Acquiring position information of at least one pad of the at least one electronic component; or The position information of the alignment pattern of the at least one electronic component is obtained.

10. The method for manufacturing an electronic device according to claim 8, wherein: Comparing the position information of the at least one electronic component with the reference value includes comparing the position information of the at least one electronic component with position information of a position comparison reference.

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