A double-sided heat-dissipating power module with a planar mosaic structure

Abstract

The application relates to a double-sided heat-dissipation power module with a planar mosaic structure, comprising a first substrate with a first conductive metal layer, a second substrate with a second conductive metal layer and a plurality of power chips; the first conductive metal layer comprises an AC conductive metal layer and a plurality of upper DC-conductive metal layers; the second conductive metal layer comprises a DC+ conductive metal layer and a plurality of lower DC-conductive metal layers; the plurality of power chips comprises a plurality of upper pipe power chips and a plurality of lower pipe power chips; the plurality of lower pipe power chips are arranged on the AC conductive metal layer, are staggered with the plurality of upper pipe power chips and are connected with the plurality of lower DC-conductive metal layers one by one; there is an independent power loop between each upper pipe power chip and the adjacent lower pipe power chip, and the mutual inductance of the two power loops in the vertical direction and the horizontal direction is cancelled. The power module improves the mutual inductance cancellation effect by increasing the number of current paths.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power module technology, and specifically relates to a double-sided heat dissipation power module with a planar inlay structure. Background Technology

[0002] Power devices are the core components of power conversion. Compared to silicon devices, silicon carbide (SiC) devices have lower leakage current, higher withstand voltage, higher operating temperature, stronger radiation resistance, and higher switching speed. Compared to Si devices of the same voltage level, they have lower on-resistance, better heat dissipation, and a higher theoretical maximum allowable operating temperature. To meet the needs of high-power applications, high-current SiC devices are required. SiC power modules often connect multiple SiC power chips in parallel. However, this results in significant parasitic parameters, such as parasitic inductance. Due to the high switching speed of SiC power chips, parasitic parameters caused by packaging can lead to greater switching losses, voltage stress, and EMI noise. Furthermore, imbalances in package parasitic inductance can cause imbalances in thermal stress and power loss, leading to localized overheating and uneven aging of parallel devices, which is detrimental to their normal operation.

[0003] Therefore, it is necessary to reduce the parasitic inductance within silicon carbide power chip modules and optimize the heat dissipation path. Traditional module design approaches, such as copper interconnect technology, flip-chip technology, and two-terminal technology, reduce self-inductance by shortening the loop path or by using the reverse current in adjacent paths to achieve mutual inductance cancellation, thereby reducing the parasitic inductance within the power module. However, due to limitations in module layout and component placement, these methods can only achieve mutual inductance reduction on some paths. In traditional power modules, the parallel upper and lower transistor chips typically share a single power loop. This design limits the realization of mutual inductance cancellation, making it impossible to fully utilize mutual inductance cancellation to minimize parasitic inductance, thus making further reduction of parasitic inductance difficult and limiting the improvement of module performance. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a double-sided heat dissipation power module with a planar inlay structure. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a double-sided heat dissipation power module with a planar grooving structure, comprising: a first substrate having a first conductive metal layer, a second substrate having a second conductive metal layer, and a plurality of power chips, wherein the first conductive metal layer and the second conductive metal layer are parallel and opposite to each other.

[0006] The first conductive metal layer includes an AC conductive metal layer and several upper DC-conductive metal layers, with the several upper DC-conductive metal layers embedded in the AC conductive metal layer;

[0007] The second conductive metal layer includes a DC+ conductive metal layer and several lower DC- conductive metal layers; the opposite sides of the DC+ conductive metal layer form a square serrated structure, and the serrations of the square serrated structure are staggered; the several lower DC- conductive metal layers are distributed one-to-one in the several grooves of the square serrated structure, and two diagonally adjacent lower DC- conductive metal layers are connected through the upper DC- conductive metal layer, and / or, two diagonally adjacent lower DC- conductive metal layers are connected through metal clips;

[0008] The plurality of power chips include a plurality of upper power chips and a plurality of lower power chips; the plurality of upper power chips are disposed one-to-one on the plurality of serrations of the square serrated structure and connected to the AC conductive metal layer; the plurality of lower power chips are disposed on the AC conductive metal layer, staggered with the plurality of upper power chips, and connected one-to-one to the plurality of lower DC-conductive metal layers.

[0009] Each of the upper power chips and the adjacent lower power chip have an independent power circuit, and the two power circuits cancel each other out in both the vertical and horizontal directions.

[0010] In one embodiment of the present invention, the first substrate further includes a first insulating layer and a first heat dissipation metal layer, wherein the first conductive metal layer, the first insulating layer and the first heat dissipation metal layer are stacked sequentially.

[0011] The second substrate further includes a second insulating layer and a second heat-dissipating metal layer, wherein the second conductive metal layer, the second insulating layer and the second heat-dissipating metal layer are stacked sequentially;

[0012] The first heat dissipation metal layer and the second heat dissipation metal layer are used to install an external heat sink.

[0013] In one embodiment of the present invention, a first AC terminal and a second AC terminal are provided on opposite sides of the AC conductive metal layer;

[0014] Each serration of the DC+ conductive metal layer is connected to a DC+ terminal.

[0015] Each of the lower DC-conductive metal layers is connected to a DC terminal.

[0016] In one embodiment of the present invention, a plurality of metal blocks are further included, wherein,

[0017] Each of the upper-side power chips is connected to the AC conductive metal layer via the metal block;

[0018] Each of the lower-side power chips is connected to the corresponding lower DC-conductive metal layer via the metal block;

[0019] The two diagonally adjacent lower DC-conductive metal layers are connected to the upper DC-conductive metal layer through the metal block.

[0020] In one embodiment of the present invention, the power chip includes a silicon carbide MOSFET power chip, wherein the silicon carbide MOSFET power chip includes a gate, a power source, a Kelvin source, and a drain, wherein...

[0021] The power source, the Kelvin source, and the gate are all disposed on the first side surface of the silicon carbide MOSFET power chip;

[0022] The drain is disposed on the second side surface of the silicon carbide MOSFET power chip, and the second side surface is opposite to the first side surface.

[0023] The drain of the upper power chip is disposed on the surface of the DC+ conductive metal layer, and the power source is connected to the AC conductive metal layer.

[0024] The drain of the lower power chip is disposed on the surface of the AC conductive metal layer, and the power source is connected to the corresponding lower DC conductive metal layer.

[0025] In one embodiment of the present invention, a Kelvin source terminal and a gate terminal are provided near each power chip as conductive metal layer driving terminals, the Kelvin source terminal and the gate terminal being close to each other and disposed on the insulating layer of the substrate;

[0026] The Kelvin source terminal is connected to the Kelvin source electrode, and the gate terminal is connected to the gate electrode.

[0027] In one embodiment of the present invention, the first conductive metal layer includes an AC conductive metal layer, a first DC-conductive metal layer and a second DC-conductive metal layer, wherein the first DC-conductive metal layer and the second DC-conductive metal layer are embedded in the AC conductive metal layer;

[0028] The second conductive metal layer includes a DC+ conductive metal layer, a third DC- conductive metal layer, a fourth DC- conductive metal layer, a fifth DC- conductive metal layer, and a sixth DC- conductive metal layer. The DC+ conductive metal layer has a square sawtooth structure with four serrations on its opposite sides, and the four serrations are staggered. The third, fourth, fifth, and sixth DC- conductive metal layers are distributed in the grooves opposite each sawtooth. The third and fourth DC- conductive metal layers are diagonally arranged and interconnected through a first DC- conductive metal layer. The fourth and fifth DC- conductive metal layers are diagonally arranged and interconnected through copper clips. The fifth and sixth DC- conductive metal layers are diagonally arranged and interconnected through a second DC- conductive metal layer.

[0029] In one embodiment of the present invention, the plurality of upper-side power chips include: a first upper-side power chip, a second upper-side power chip, a third upper-side power chip, and a fourth upper-side power chip, wherein the first upper-side power chip, the second upper-side power chip, the third upper-side power chip, and the fourth upper-side power chip are disposed on the four serrations of the square serrated structure in a one-to-one correspondence, and are all connected to the AC conductive metal layer.

[0030] The plurality of lower-side power chips include: a first lower-side power chip, a second lower-side power chip, a third lower-side power chip, and a fourth lower-side power chip, wherein the first lower-side power chip, the second lower-side power chip, the third lower-side power chip, and the fourth lower-side power chip are distributed on the AC conductive metal layer and correspond to the third DC-conductive metal layer, the fourth DC-conductive metal layer, the fifth DC-conductive metal layer, and the sixth DC-conductive metal layer, respectively.

[0031] In one embodiment of the present invention, a first power circuit is formed between the first upper power chip, the first lower power chip, and the third DC-conductive metal layer; a second power circuit is formed between the first upper power chip, the second lower power chip, and the fourth DC-conductive metal layer.

[0032] A third power circuit is formed between the second upper power chip, the first lower power chip, and the third DC-conductive metal layer; a fourth power circuit is formed between the second upper power chip, the second lower power chip, and the fourth DC-conductive metal layer; and a fifth power circuit is formed between the second upper power chip, the third lower power chip, and the fifth DC-conductive metal layer.

[0033] A sixth power circuit is formed between the third upper power chip, the second lower power chip, and the fourth DC-conductive metal layer; a seventh power circuit is formed between the third upper power chip, the third lower power chip, and the fifth DC-conductive metal layer; and an eighth power circuit is formed between the third upper power chip, the fourth lower power chip, and the sixth DC-conductive metal layer.

[0034] A ninth power circuit is formed between the fourth upper power chip, the third lower power chip, and the fifth DC-conductive metal layer; a tenth power circuit is formed between the fourth upper power chip, the fourth lower power chip, and the sixth DC-conductive metal layer.

[0035] The first power circuit and the fourth power circuit cancel each other out in the vertical and horizontal directions; the fourth power circuit and the seventh power circuit cancel each other out in the vertical and horizontal directions; the seventh power circuit and the tenth power circuit cancel each other out in the vertical and horizontal directions; the second power circuit and the third power circuit cancel each other out in the vertical and horizontal directions; the fifth power circuit and the sixth power circuit cancel each other out in the vertical and horizontal directions; and the eighth power circuit and the ninth power circuit cancel each other out in the vertical and horizontal directions.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] 1. The planar inlay structure of the double-sided heat dissipation power module of the present invention, through the structural design of an AC conductive metal layer, a DC+ conductive metal layer, a lower DC- conductive metal layer, and several upper power chips and several lower power chips, enables each power chip in the module to have multiple power circuits. Each upper power chip and its adjacent lower power chip have independent power circuits, and the two power circuits are mutually inductively canceled in both the vertical and horizontal directions. By increasing the number of power circuits, current can flow from the parallel upper chips through any adjacent parallel lower chips to form a commutation circuit, thereby increasing the number of current paths. Based on the principle of magnetic flux cancellation, the current directions of the opposite commutation circuits in the vertical and horizontal directions are opposite, thereby achieving mutual inductance cancellation, reducing the parasitic inductance inside the module, and effectively reducing the switching losses and electrical stress generated by the power module during high-speed switching.

[0038] 2. By increasing the number of power circuits and optimizing the current path, the power module of the present invention can effectively avoid current concentration in some chips and local areas inside the module. This design can balance the heat distribution, avoid the module temperature from being too high, and thus improve the performance and reliability of the module. The uniform current distribution helps to reduce the formation of hot spots inside the module, reduce the thermomechanical stress of the module, and extend the service life of the module.

[0039] 3. The power module of the present invention places the upper power chip and the lower power chip alternately to optimize the heat dissipation path, avoid local overheating, ensure uniform heat distribution and efficient heat conduction, and reduce thermal coupling between chips. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the overall structure of a double-sided heat dissipation power module with a planar inlay structure provided in an embodiment of the present invention;

[0041] Figure 2 A front view of a double-sided heat dissipation power module with a planar inlay structure provided in an embodiment of the present invention;

[0042] Figure 3 A side view of a double-sided heat dissipation power module with a planar inlay structure provided in an embodiment of the present invention;

[0043] Figure 4 This is a first substrate layout diagram provided in an embodiment of the present invention. Figure 5 This is a layout diagram of the second substrate provided in an embodiment of the present invention;

[0044] Figure 6 A schematic diagram illustrating the connection method of the first substrate, the second substrate, and the power chip provided in an embodiment of the present invention;

[0045] Figure 7 This is a connection diagram of the DC+ conductive metal layer provided in an embodiment of the present invention;

[0046] Figure 8 A connection diagram of the AC conductive metal layer provided in an embodiment of the present invention;

[0047] Figure 9 This is a connection diagram of the DC-conductive metal layer provided in an embodiment of the present invention;

[0048] Figure 10 A schematic diagram of the power circuit of a double-sided heat dissipation power module with a planar inlay structure provided for an embodiment of the present invention;

[0049] Figure 11 This is a schematic diagram of the power chip provided in an embodiment of the present invention. Detailed Implementation

[0050] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0051] Example 1

[0052] To reduce the parasitic inductance of the silicon carbide power chip module, this embodiment provides a double-sided heat dissipation power module with a planar inlay structure, suitable for high-current power modules with multiple power chips connected in parallel. Each upper transistor chip has an independent power loop between it and its nearest adjacent lower transistor chip, increasing the number of current paths to improve the mutual inductance cancellation effect.

[0053] Please see Figures 1-10 , Figure 1 This is a schematic diagram of the overall structure of a double-sided heat dissipation power module with a planar inlay structure provided in an embodiment of the present invention. Figure 2 This is a front view of a double-sided heat dissipation power module with a planar inlay structure provided in an embodiment of the present invention. Figure 3 This is a side view of a double-sided heat dissipation power module with a planar inlay structure provided in an embodiment of the present invention. Figure 4 This is a first substrate layout diagram provided in an embodiment of the present invention. Figure 5 This is a layout diagram of the second substrate provided in an embodiment of the present invention. Figure 6 This is a schematic diagram illustrating the connection method of the first substrate, the second substrate, and the power chip provided in an embodiment of the present invention. Figure 7 This is a connection diagram of the DC+ conductive metal layer provided in an embodiment of the present invention. Figure 8 This is a connection diagram of the AC conductive metal layer provided in an embodiment of the present invention. Figure 9 This is a connection diagram of the DC-conductive metal layer provided in an embodiment of the present invention. Figure 10 A schematic diagram of the power circuit of a double-sided heat dissipation power module with a planar inlay structure provided for an embodiment of the present invention.

[0054] Please combine Figure 1 , Figure 2 and Figure 3 The dual-sided heat dissipation power module with a planar inlay structure provided in this embodiment includes: a first substrate 100 having a first conductive metal layer 101, a second substrate 200 having a second conductive metal layer 201, and a plurality of power chips 701~708, wherein the first conductive metal layer 101 and the second conductive metal layer 201 are parallel to each other.

[0055] Please combine Figure 4 and Figure 8 The first conductive metal layer 101 includes an AC conductive metal layer 301 and several upper DC conductive metal layers 302-303. The several upper DC conductive metal layers 302-303 are embedded in the AC conductive metal layer 301.

[0056] Please combine Figure 5 , Figure 7 and Figure 9The second conductive metal layer 201 includes a DC+ conductive metal layer 501 and several lower DC- conductive metal layers 502-505. The opposite sides of the DC+ conductive metal layer 501 form a square serrated structure, and the serrations of the square serrated structure are staggered. The several lower DC- conductive metal layers 502-505 are distributed one-to-one in the several grooves of the square serrated structure, and two diagonally adjacent lower DC- conductive metal layers are connected through an upper DC- conductive metal layer, and / or, two diagonally adjacent lower DC- conductive metal layers are connected through a metal clip.

[0057] Please combine Figure 4 , Figure 5 , Figure 6 and Figure 10 The system comprises several power chips, including several upper-side power chips 701-704 and several lower-side power chips 705-708. The upper-side power chips 701-704 are arranged one-to-one on several serrations of a square sawtooth structure and connected to the AC conductive metal layer 301. The lower-side power chips 705-708 are arranged on the AC conductive metal layer 301, alternating with the upper-side power chips 701-704, and are connected one-to-one to several lower DC conductive metal layers 502-505. Each upper-side power chip has an independent power loop with its adjacent lower-side power chip, and the mutual inductance of the two power loops cancels each other out in both the vertical and horizontal directions.

[0058] Specifically, the first substrate 100 is an upper direct copper-clad ceramic substrate, and the second substrate 200 is a lower direct copper-clad ceramic substrate. The two substrates are arranged parallel to each other, and the power chip is disposed between the inner surfaces of the two substrates. An AC conductive metal layer 301 and several upper DC-conductive metal layers 302-303 form the first conductive metal layer 101 and serve as the upper conductive metal layer. A DC+ conductive metal layer 501 and several lower DC-conductive metal layers 502-505 form the second conductive metal layer 201 and serve as the lower conductive metal layer. The several lower DC-conductive metal layers are diagonally adjacent, and these diagonally adjacent lower DC-conductive metal layers can be connected by upper DC-conductive metal layers or by metal clips, such as copper clips. For example, diagonally adjacent lower DC-conductive metal layers on both sides are connected by upper DC-conductive metal layers, and diagonally adjacent lower DC-conductive metal layers in the middle are connected by metal clips, such as... Figure 5 As shown; or, multiple pairs of diagonally adjacent lower DC-conductive metal layers are connected through upper DC-conductive metal layers.

[0059] Both opposite sides of the DC+ conductive metal layer 501 form a square sawtooth structure, which includes sawtooths and grooves. For any side of the DC+ conductive metal layer 501, the sawtooths and grooves are alternately distributed and staggered with those on the other side. Each groove corresponds to a lower DC- conductive metal layer. An upper power chip is disposed on each sawtooth, and a lower power chip is disposed at the position corresponding to the AC conductive metal layer 301 and the lower DC- conductive metal layer. This results in an alternating distribution of upper and lower power chips, creating a power loop between the upper power chip and the adjacent lower power chip. Current in each power loop flows from the upper power chip on the second substrate 200 to the lower power chip on the first substrate 100, and then to the corresponding lower DC- conductive metal layer. The two power loops with opposite current directions cancel each other out in the vertical and horizontal directions.

[0060] Please combine Figure 1 , Figure 2 and Figure 3 The first substrate 100 and the second substrate 200 have a sandwich structure, each including a conductive metal layer, an insulating layer and a heat dissipation metal layer.

[0061] Specifically, the first substrate 100 includes a first conductive metal layer 101, a first insulating layer 102, and a first heat-dissipating metal layer 103, wherein the first conductive metal layer 101, the first insulating layer 102, and the first heat-dissipating metal layer 103 are stacked sequentially. The second substrate 200 includes a second conductive metal layer 201, a second insulating layer 202, and a second heat-dissipating metal layer 203, wherein the second conductive metal layer 201, the second insulating layer 202, and the second heat-dissipating metal layer 203 are stacked sequentially, and the first conductive metal layer 101 and the second conductive metal layer 201 are parallel to each other. The first heat-dissipating metal layer 103 and the second heat-dissipating metal layer 203 are used to provide an external heat sink, achieving double-sided heat dissipation and facilitating heat dissipation.

[0062] Please combine Figure 4 , Figure 5 , Figure 6 and Figure 9 The double-sided heat dissipation power module with a planar inlay structure also includes several metal blocks 801-812, wherein each upper power chip is connected to the AC conductive metal layer 301 through the metal block; each lower power chip is connected to the corresponding lower DC conductive metal layer through the metal block; and two diagonally adjacent lower DC conductive metal layers are connected to the upper DC conductive metal layer through the metal block.

[0063] Specifically, the metal block is a molybdenum compound metal block.

[0064] In this embodiment, a metal block is used to vertically connect the upper power chip to the AC conductive metal layer 301, and to vertically connect the lower power chip to the corresponding lower DC conductive metal layer. The power circuits are connected at the same potential through the molybdenum compound metal block and copper clips.

[0065] Please combine Figure 4 and Figure 5 The AC conductive metal layer 301 has a first AC terminal 401 and a second AC terminal 402 on opposite sides; each serration of the DC+ conductive metal layer 501 is connected to a DC+ terminal, and multiple serrations correspond one-to-one with multiple DC+ terminals 601~604; each lower DC- conductive metal layer is connected to a DC- terminal, and multiple lower DC- conductive metal layers 502~505 correspond one-to-one with multiple DC- terminals 605~608.

[0066] Please see Figure 11 , Figure 11 This is a schematic diagram of the power chip structure provided in an embodiment of the present invention. The power chip includes a silicon carbide MOSFET power chip, which includes a gate, a power source, a Kelvin source, and a drain. The power source, Kelvin source, and gate are all disposed on a first side surface of the silicon carbide MOSFET power chip; the drain is disposed on a second side surface of the silicon carbide MOSFET power chip, and the second side surface is opposite to the first side surface; the drain of the upper power chip is disposed on the surface of the DC+ conductive metal layer 501, and the power source is connected to the AC conductive metal layer 301; the drain of the lower power chip is disposed on the surface of the AC conductive metal layer 301, and the power source is connected to the corresponding lower DC- conductive metal layer.

[0067] Furthermore, the power source of the upper power chip is connected to the AC conductive metal layer 301 through a metal block, and the power source of the lower power chip is connected to the corresponding lower DC conductive metal layer through a metal block.

[0068] Please combine Figure 4 and Figure 5 Near each power chip, there are Kelvin source terminals and gate terminals as conductive metal layer driving terminals. The Kelvin source terminals and gate terminals are close to each other and are disposed on the insulating layer of the substrate. The Kelvin source terminals are connected to the Kelvin source electrode through bonding wires, and the gate terminals are connected to the gate electrode through bonding wires. Figure 4 In the middle, 403~410 are the driving terminals of the upper conductive metal layer. Figure 5 In the middle, 609~616 are driving terminals for the lower conductive metal layer.

[0069] This embodiment forms a double-sided heat dissipation power module with a planar inlay structure, consisting of a first conductive metal layer 101, a second conductive metal layer 201, several power chips, several metal blocks, a first AC terminal 401, a second AC terminal 402, several DC+ terminals, several DC- terminals, and several conductive metal layer drive terminals. The number of power chips is not limited to... Figures 1-10 There are 8 in total, and the specific number can be set according to the device requirements.

[0070] Taking a power module with eight power chips (four upper-side silicon carbide MOSFETs and four lower-side silicon carbide MOSFETs) as an example, the specific structure of the double-sided heat dissipation power module with a planar inlay structure is as follows:

[0071] Please see Figure 4 and Figure 8 The first conductive metal layer 101 includes an AC conductive metal layer 301, a first DC conductive metal layer 302, and a second DC conductive metal layer 303, wherein the first DC conductive metal layer 302 and the second DC conductive metal layer 303 are embedded in the AC conductive metal layer 301 to form an upper DC conductive metal layer.

[0072] Please see Figure 5 , Figure 7 and Figure 9 The second conductive metal layer 201 includes a DC+ conductive metal layer 501, a third DC- conductive metal layer 502, a fourth DC- conductive metal layer 503, a fifth DC- conductive metal layer 504, and a sixth DC- conductive metal layer 505. The DC+ conductive metal layer 501 has a square sawtooth structure with four serrations on its opposite sides, and the four serrations are staggered. The third DC- conductive metal layer 502, the fourth DC- conductive metal layer 503, the fifth DC- conductive metal layer 504, and the sixth DC- conductive metal layer 505 are distributed in the grooves opposite each sawtooth. The third DC- conductive metal layer 502 and the fourth DC- conductive metal layer 503 are diagonally arranged and interconnected through the first DC- conductive metal layer 302. The fourth DC- conductive metal layer 503 and the fifth DC- conductive metal layer 504 are diagonally arranged and interconnected through copper clips. The fifth DC- conductive metal layer 504 and the sixth DC- conductive metal layer 505 are diagonally arranged and interconnected through the second DC- conductive metal layer 303.

[0073] It can be understood that the AC conductive metal layer 301 is approximately shaped like a horizontally placed figure 8, while the first DC conductive metal layer 302 and the second DC conductive metal layer 303 are approximately rectangular in shape, and are embedded in the two gaps on the left and right sides of the figure 8. Figure 8 As shown. The shape of the first DC+ conductive metal layer 501 is approximately a rectangle formed by four adjacent right angles connected sequentially, as shown. Figure 7 As shown, the third DC-conductive metal layer 502, the fourth DC-conductive metal layer 503, the fifth DC-conductive metal layer 504, and the sixth DC-conductive metal layer 505 are approximately rectangular in shape and are embedded in the remaining area of ​​the lower conductive metal layer, as shown. Figure 9 As shown, this gives the double-sided heat dissipation power module a planar inlay structure.

[0074] Please see Figure 9 In this embodiment, molybdenum compound metal blocks 809-812 and copper clips 813 are used to achieve the connection of the power circuit at the same potential. Specifically, molybdenum compound metal block 809 connects the first DC-conductive metal layer 302 and the third DC-conductive metal layer 502, molybdenum compound metal block 810 connects the first DC-conductive metal layer 302 and the fourth DC-conductive metal layer 503, copper clips 813 connect the fourth DC-conductive metal layer 503 and the fifth DC-conductive metal layer 504, molybdenum compound metal block 811 connects the second DC-conductive metal layer 303 and the fifth DC-conductive metal layer 504, and molybdenum compound metal block 812 connects the second DC-conductive metal layer 303 and the sixth DC-conductive metal layer 505.

[0075] Please see Figure 7 , Figure 8 and Figure 9 The first AC terminal 401 and the second AC terminal 402 are welded to the left and right sides of the AC conductive metal layer 301; the first DC+ terminal 601, the second DC+ terminal 602, the third DC+ terminal 603, and the fourth DC+ terminal 604 are sequentially welded to the four serrations on the DC+ conductive metal layer 501; the first DC- terminal 605, the second DC- terminal 606, the third DC- terminal 607, and the fourth DC- terminal 608 are respectively welded to the third DC- conductive metal layer 502, the fourth DC- conductive metal layer 503, the fifth DC- conductive metal layer 504, and the sixth DC- conductive metal layer 505.

[0076] Specifically, the plurality of upper-side power chips include: a first upper-side power chip 701, a second upper-side power chip 702, a third upper-side power chip 703, and a fourth upper-side power chip 704. The first upper-side power chip 701, the second upper-side power chip 702, the third upper-side power chip 703, and the fourth upper-side power chip 704 are respectively disposed on the four serrations of the square serrated structure, and are all connected to the AC conductive metal layer 301.

[0077] The plurality of lower-side power chips include: a first lower-side power chip 705, a second lower-side power chip 706, a third lower-side power chip 707, and a fourth lower-side power chip 708. The first lower-side power chip 705, the second lower-side power chip 706, the third lower-side power chip 707, and the fourth lower-side power chip 708 are distributed on the AC conductive metal layer 301 and correspond to the third DC conductive metal layer 502, the fourth DC conductive metal layer 503, the fifth DC conductive metal layer 504, and the sixth DC conductive metal layer 505, respectively, and are vertically connected.

[0078] Several metal blocks include molybdenum compound metal blocks 801-812. The first conductive metal layer 101 and the second conductive metal layer 201 each include four sets of driving terminals. The upper conductive metal layer driving terminals 403-410 and the lower conductive metal layer driving terminals 609-616 are each composed of gate terminals and Kelvin source terminals that are close to each other.

[0079] Specifically, the drain of the first upper power chip 701 is located at the first rectangular position from left to right in the DC+ conductive metal layer 501. The power source is connected to the AC conductive metal layer 301 through the molybdenum metal block 805. The Kelvin source and gate are connected to the lower conductive metal layer drive terminals 613 and 614 through bonding wires.

[0080] The drain of the second upper power chip 702 is located at the second rectangular position from left to right in the DC+ conductive metal layer 501. The power source is connected to the AC conductive metal layer 301 through the molybdenum metal block 807. The Kelvin source and gate are connected to the lower conductive metal layer drive terminals 609 and 610 through bonding wires.

[0081] The drain of the third upper-side power chip 703 is located at the third rectangular position from left to right in the DC+ conductive metal layer 501. The power source is connected to the AC conductive metal layer 301 through the molybdenum metal block 806. The Kelvin source and gate are connected to the lower conductive metal layer drive terminals 615 and 616 through bonding wires.

[0082] The drain of the fourth upper power chip 704 is located at the fourth rectangular position from left to right in the DC+ conductive metal layer 501. The power source is connected to the AC conductive metal layer 301 through the molybdenum metal block 808. The Kelvin source and gate are connected to the lower conductive metal layer drive terminals 611 and 612 through bonding wires.

[0083] The drain of the first lower-side power chip 705 is located at the position of AC conductive metal layer 301 at the lower left corner of the first DC-conductive metal layer 302. The power source is connected to the third DC-conductive metal layer 502 through the molybdenum metal block 801. The Kelvin source and gate are connected to the upper conductive metal layer drive terminals 407 and 408 through bonding wires.

[0084] The drain of the second lower-side power chip 706 is located at the AC conductive metal layer 301 in the upper right corner of the first DC-conductive metal layer 302. The power source is connected to the fourth DC-conductive metal layer 503 and the fifth DC-conductive metal layer 504 through the molybdenum metal block 803. The Kelvin source and gate are connected to the upper conductive metal layer drive terminals 403 and 404 through bonding wires.

[0085] The drain of the third lower-side power chip 707 is located at the position of AC conductive metal layer 301 at the lower left corner of the second DC-conductive metal layer 303. The power source is connected to the fifth DC-conductive metal layer 504 through the molybdenum metal block 802. The Kelvin source and gate are connected to the upper conductive metal layer drive terminals 409 and 410 through bonding wires.

[0086] The drain of the fourth lower-side power chip 708 is located at the AC conductive metal layer 301 in the upper right corner of the second DC-circuit 303 region. The power source is connected to the sixth DC-conductive metal layer 505 through the molybdenum metal block 804. The Kelvin source and gate are connected to the upper conductive metal layer drive terminals 405 and 406 through bonding wires.

[0087] Please see Figure 10 In this embodiment, ten power circuits are formed by eight power chips, and each upper silicon carbide chip has multiple power circuits.

[0088] A first power circuit is formed between the first upper power chip 701, the first lower power chip 705, and the third DC-conductive metal layer 502; a second power circuit is formed between the first upper power chip 701, the second lower power chip 706, and the fourth DC-conductive metal layer 503.

[0089] Specifically, current flows in from the first DC+ terminal 601, through the lower plate DC+ conductive metal layer 501 to the drain at the bottom of the first upper power chip 701, and then flows out from the power source through the molybdenum metal block 805 to the upper plate. If it flows through the AC conductive metal layer 301 to the drain at the bottom of the first lower power chip 705, then through the molybdenum metal block 801 to the lower plate third DC- conductive metal layer 502, and finally flows out from the first DC- terminal 605, then a first power circuit is formed. If it flows through the AC conductive metal layer 301 to the drain at the bottom of the second lower power chip 706, then through the molybdenum metal block 803 to the lower plate fourth DC- conductive metal layer 503, and finally flows out from the second DC- terminal 606, then a second power circuit is formed.

[0090] A third power circuit is formed between the second upper power chip 702, the first lower power chip 705, and the third DC-conductive metal layer 502; a fourth power circuit is formed between the second upper power chip 702, the second lower power chip 706, and the fourth DC-conductive metal layer 503; and a fifth power circuit is formed between the second upper power chip 702, the third lower power chip 707, and the fifth DC-conductive metal layer 504.

[0091] Specifically, current flows in from the second DC+ terminal 602, through the lower plate DC+ conductive metal layer 501 to the drain at the bottom of the second upper power chip 702, and then flows out from the power source through the molybdenum compound metal block 807 to the upper plate. If it flows through the AC conductive metal layer 301 to the drain at the bottom of the first lower power chip 705, then through the molybdenum compound metal block 801 to the lower plate third DC- conductive metal layer 502, and finally flows out from the first DC- terminal 605, then a third power circuit is formed; if it flows through the A... The current flows from the C-conductive metal layer 301 to the drain at the bottom of the second lower-side power chip 706, then through the molybdenum compound metal block 803 to the fourth DC-conductive metal layer 503 on the lower plate, and finally out from the second DC-terminal 606, thus forming the fourth power circuit. If the current flows through the AC-conductive metal layer 301 to the drain at the bottom of the third lower-side power chip 707, then through the molybdenum compound metal block 802 to the fifth DC-conductive metal layer 504 on the lower plate, and finally out from the third DC-terminal 607, then forming the fifth power circuit.

[0092] A sixth power circuit is formed between the third upper power chip 703, the second lower power chip 706, and the fourth DC-conductive metal layer 503; a seventh power circuit is formed between the third upper power chip 703, the third lower power chip 707, and the fifth DC-conductive metal layer 504; and an eighth power circuit is formed between the third upper power chip 703, the fourth lower power chip 708, and the sixth DC-conductive metal layer 505.

[0093] Specifically, current flows in from the third DC+ terminal 603, through the lower board DC+ conductive metal layer 501 to the drain at the bottom of the third upper power chip 703, and then out from the power source through the molybdenum compound metal block 806 to the upper board. If it flows through the AC conductive metal layer 301 to the drain at the bottom of the second lower power chip 706, then through the molybdenum compound metal block 803 to the lower board fourth DC- conductive metal layer 503, and finally out from the second DC- terminal 606, then a sixth power circuit is formed; if it flows through the A... The C-conductive metal layer 301 flows to the drain at the bottom of the third lower-side power chip 707, then through the molybdenum compound metal block 802 to the fifth DC-conductive metal layer 504 on the lower plate, and finally flows out from the third DC-terminal 607, thus forming the seventh power circuit; if the flow passes through the AC-conductive metal layer 301 to the drain at the bottom of the fourth lower-side power chip 708, then through the molybdenum compound metal block 804 to the sixth DC-conductive metal layer 505 on the lower plate, and finally flows out from the fourth DC-terminal 608, then forming the eighth power circuit.

[0094] The fourth upper power chip 704, the third lower power chip 707, and the fifth DC-conductive metal layer 504 form a ninth power circuit; the fourth upper power chip 704, the fourth lower power chip 708, and the sixth DC-conductive metal layer 505 form a tenth power circuit.

[0095] Specifically, the current flows in from the fourth DC+ terminal 604, through the lower plate DC+ conductive metal layer 501 to the drain at the bottom of the fourth upper power chip 704, and then flows out from the power source through the molybdenum metal block 808 to the upper plate. If it flows through the AC conductive metal layer 301 to the drain at the bottom of the third lower power chip 707, then through the molybdenum metal block 802 to the fifth DC- conductive metal layer 504 on the lower plate, and finally flows out from the third DC- terminal 607, then the ninth power circuit is formed. If it flows through the AC conductive metal layer 301 to the drain at the bottom of the fourth lower power chip 708, then through the molybdenum metal block 804 to the sixth DC- conductive metal layer 505 on the lower plate, and finally flows out from the fourth DC- terminal 608, then the tenth power circuit is formed.

[0096] The aforementioned ten power circuits have short absolute lengths, low self-inductance in the power converter circuits, and small power module size. Furthermore, multiple pairs of mutually canceling paths exist between the power circuits, such as: mutual inductance cancellation between the first and fourth power circuits in both vertical and horizontal directions; mutual inductance cancellation between the fourth and seventh power circuits in both vertical and horizontal directions; mutual inductance cancellation between the seventh and tenth power circuits in both vertical and horizontal directions; mutual inductance cancellation between the second and third power circuits in both vertical and horizontal directions; mutual inductance cancellation between the fifth and sixth power circuits in both vertical and horizontal directions; and mutual inductance cancellation between the eighth and ninth power circuits in both vertical and horizontal directions. Through these mutual inductance cancellations between each pair of power circuits in both vertical and horizontal directions, the parasitic inductance of the power module is significantly reduced to 0.8nH, making this power module suitable for high-current, high-power-density applications.

[0097] The planar inlay structure of the double-sided heat dissipation power module in this embodiment utilizes an AC conductive metal layer, a DC+ conductive metal layer, a DC- conductive metal layer, and a combination of several upper-side power chips and several lower-side power chips. This design ensures that each power chip within the module has multiple power loops. Each upper-side power chip has an independent power loop with its adjacent lower-side power chip, and the two power loops cancel each other out in both the vertical and horizontal directions. By increasing the number of power loops, current can flow from the parallel upper-side chips through any adjacent parallel lower-side chips, forming a commutation loop and thus increasing the number of current paths. Based on the principle of magnetic flux cancellation, the current directions of the opposite commutation loops are opposite in the vertical and horizontal directions, thereby achieving mutual inductance cancellation, reducing the parasitic inductance inside the module, and effectively reducing the switching losses and electrical stress generated by the power module during high-speed switching.

[0098] The power module in this embodiment can effectively avoid current concentration in some chips and local areas inside the module by increasing the number of power loops and optimizing the current path. This design can balance the heat distribution, prevent the module temperature from getting too high, and thus improve the module's performance and reliability. The uniform current distribution helps to reduce the formation of hot spots inside the module, reduce the module's thermomechanical stress, and extend the module's service life.

[0099] The power module structure in this embodiment adopts double-sided heat dissipation and staggers the upper and lower power chips to optimize the heat dissipation path, avoid local overheating, ensure uniform heat distribution and efficient heat conduction, and reduce thermal coupling between chips.

[0100] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A double-sided heat dissipation power module with a planar inlay structure, characterized in that, include: The system comprises a first substrate (100) having a first conductive metal layer (101), a second substrate (200) having a second conductive metal layer (201), and a plurality of power chips, wherein the first conductive metal layer (101) and the second conductive metal layer (201) are parallel to each other. The first conductive metal layer (101) includes an AC conductive metal layer (301) and a plurality of upper DC-conductive metal layers, wherein the plurality of upper DC-conductive metal layers are embedded in the AC conductive metal layer (301); The second conductive metal layer (201) includes a DC+ conductive metal layer (501) and a plurality of lower DC- conductive metal layers; the opposite sides of the DC+ conductive metal layer (501) form a square sawtooth structure, and the plurality of sawtooths of the square sawtooth structure are staggered; the plurality of lower DC- conductive metal layers are distributed one-to-one in the plurality of grooves of the square sawtooth structure, and two diagonally adjacent lower DC- conductive metal layers are connected through the upper DC- conductive metal layer, and / or, two diagonally adjacent lower DC- conductive metal layers are connected through metal clips; The plurality of power chips include a plurality of upper power chips and a plurality of lower power chips; the plurality of upper power chips are disposed one-to-one on the plurality of serrations of the square serrated structure and are connected to the AC conductive metal layer (301); the plurality of lower power chips are disposed between the AC conductive metal layer (301) and the plurality of lower DC-conductive metal layers, and are staggered with the plurality of upper power chips and are connected one-to-one with the plurality of lower DC-conductive metal layers. Each of the upper power chips and the adjacent lower power chips have an independent power circuit. The current in each power circuit flows from the upper power chip of the second substrate (200) into the lower power chip of the first substrate (100), and then flows into the lower DC-conductive metal layer corresponding to the lower power chip. The two power circuits with opposite current directions cancel each other out in both the vertical and horizontal directions.

2. The double-sided heat dissipation power module with a planar inlay structure according to claim 1, characterized in that, The first substrate (100) further includes a first insulating layer (102) and a first heat dissipation metal layer (103), wherein the first conductive metal layer (101), the first insulating layer (102) and the first heat dissipation metal layer (103) are stacked sequentially; The second substrate (200) further includes a second insulating layer (202) and a second heat-dissipating metal layer (203), wherein the second conductive metal layer (201), the second insulating layer (202) and the second heat-dissipating metal layer (203) are stacked sequentially; The first heat dissipation metal layer (103) and the second heat dissipation metal layer (203) are used to install an external heat sink.

3. The double-sided heat dissipation power module with a planar inlay structure according to claim 1, characterized in that, The AC conductive metal layer (301) has a first AC terminal (401) and a second AC terminal (402) on opposite sides; A DC+ terminal is connected to each serration of the DC+ conductive metal layer (501); Each of the lower DC-conductive metal layers is connected to a DC terminal.

4. The double-sided heat dissipation power module with a planar inlay structure according to claim 1, characterized in that, It also includes several metal blocks, among which, Each of the upper-side power chips is connected to the AC conductive metal layer (301) via the metal block; Each of the lower-side power chips is connected to the corresponding lower DC-conductive metal layer via the metal block; The two diagonally adjacent lower DC-conductive metal layers are connected to the upper DC-conductive metal layer through the metal block.

5. The double-sided heat dissipation power module with a planar inlay structure according to claim 1, characterized in that, The power chip includes a silicon carbide MOSFET power chip, which comprises a gate, a power source, a Kelvin source, and a drain. The power source, the Kelvin source, and the gate are all disposed on the first side surface of the silicon carbide MOSFET power chip; the drain is disposed on the second side surface of the silicon carbide MOSFET power chip, and the second side surface is opposite to the first side surface. The drain of the upper power chip is disposed on the surface of the DC+ conductive metal layer (501), and the power source is connected to the AC conductive metal layer (301). The drain of the lower power chip is disposed on the surface of the AC conductive metal layer (301), and the power source is connected to the corresponding lower DC conductive metal layer.

6. The double-sided heat dissipation power module with a planar inlay structure according to claim 5, characterized in that, Kelvin source terminals and gate terminals are provided near each power chip as conductive metal layer driving terminals. The Kelvin source terminals and gate terminals are close to each other and are disposed on the insulating layer of the substrate. The Kelvin source terminal is connected to the Kelvin source electrode, and the gate terminal is connected to the gate electrode.

7. The double-sided heat dissipation power module with a planar inlay structure according to claim 1, characterized in that, The first conductive metal layer (101) includes an AC conductive metal layer (301), a first DC conductive metal layer (302), and a second DC conductive metal layer (303), wherein the first DC conductive metal layer (302) and the second DC conductive metal layer (303) are embedded in the AC conductive metal layer (301); The second conductive metal layer (201) includes a DC+ conductive metal layer (501), a third DC- conductive metal layer (502), a fourth DC- conductive metal layer (503), a fifth DC- conductive metal layer (504), and a sixth DC- conductive metal layer (505). The DC+ conductive metal layer (501) has a square sawtooth structure with four serrations on its opposite sides, and the four serrations are staggered. The third DC- conductive metal layer (502), the fourth DC- conductive metal layer (503), the fifth DC- conductive metal layer (504), and the sixth DC- conductive metal layer (505) are... - A conductive metal layer (505) is distributed in the grooves opposite each serration. The third DC-conductive metal layer (502) and the fourth DC-conductive metal layer (503) are diagonally arranged and interconnected through the first DC-conductive metal layer (302). The fourth DC-conductive metal layer (503) and the fifth DC-conductive metal layer (504) are diagonally arranged and interconnected through copper clips. The fifth DC-conductive metal layer (504) and the sixth DC-conductive metal layer (505) are diagonally arranged and interconnected through the second DC-conductive metal layer (303).

8. The double-sided heat dissipation power module with a planar inlay structure according to claim 7, characterized in that, The plurality of upper-side power chips include: a first upper-side power chip (701), a second upper-side power chip (702), a third upper-side power chip (703), and a fourth upper-side power chip (704), wherein the first upper-side power chip (701), the second upper-side power chip (702), the third upper-side power chip (703), and the fourth upper-side power chip (704) are respectively disposed on the four serrations of the square serrated structure, and are all connected to the AC conductive metal layer (301); The plurality of lower-side power chips include: a first lower-side power chip (705), a second lower-side power chip (706), a third lower-side power chip (707), and a fourth lower-side power chip (708), wherein the first lower-side power chip (705), the second lower-side power chip (706), the third lower-side power chip (707), and the fourth lower-side power chip (708) are distributed on the AC conductive metal layer (301) and correspond to the third DC-conductive metal layer (502), the fourth DC-conductive metal layer (503), the fifth DC-conductive metal layer (504), and the sixth DC-conductive metal layer (505), respectively.

9. The double-sided heat dissipation power module with a planar inlay structure according to claim 8, characterized in that, A first power circuit is formed between the first upper power chip (701), the first lower power chip (705), and the third DC-conductive metal layer (502); a second power circuit is formed between the first upper power chip (701), the second lower power chip (706), and the fourth DC-conductive metal layer (503). A third power circuit is formed between the second upper power chip (702), the first lower power chip (705), and the third DC-conductive metal layer (502); a fourth power circuit is formed between the second upper power chip (702), the second lower power chip (706), and the fourth DC-conductive metal layer (503); and a fifth power circuit is formed between the second upper power chip (702), the third lower power chip (707), and the fifth DC-conductive metal layer (504). A sixth power circuit is formed between the third upper power chip (703), the second lower power chip (706), and the fourth DC-conductive metal layer (503); a seventh power circuit is formed between the third upper power chip (703), the third lower power chip (707), and the fifth DC-conductive metal layer (504); and an eighth power circuit is formed between the third upper power chip (703), the fourth lower power chip (708), and the sixth DC-conductive metal layer (505). The fourth upper power chip (704) forms a ninth power circuit with the third lower power chip (707) and the fifth DC-conductive metal layer (504); the fourth upper power chip (704) forms a tenth power circuit with the fourth lower power chip (708) and the sixth DC-conductive metal layer (505). The first power circuit and the fourth power circuit cancel each other out in the vertical and horizontal directions; the fourth power circuit and the seventh power circuit cancel each other out in the vertical and horizontal directions; the seventh power circuit and the tenth power circuit cancel each other out in the vertical and horizontal directions; the second power circuit and the third power circuit cancel each other out in the vertical and horizontal directions; the fifth power circuit and the sixth power circuit cancel each other out in the vertical and horizontal directions; and the eighth power circuit and the ninth power circuit cancel each other out in the vertical and horizontal directions.

Images