Integrated circuit structure with reduced terminal capacitance

Abstract

An integrated circuit structure is disclosed that includes a first vertical stack or a first fin of horizontal nanowires having a first lateral width. A first gate electrode is over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width. The second vertical stack of horizontal nanowires or the second fin is laterally spaced apart from the first vertical stack of horizontal nanowires or the first fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width, the third lateral width being less than the first lateral width. A second gate electrode is over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode laterally spaced from the first gate electrode, and the second gate electrode has a fourth lateral width that is less than the second lateral width.

Description

Technical Field

[0001] Embodiments of the present disclosure pertain to the field of integrated circuit structures and processing, and more particularly, to integrated circuit structures with reduced terminal capacitance, and methods of fabricating integrated circuit structures with reduced terminal capacitance. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features allows for increased functional unit density to be achieved on the limited chip area of ​​a semiconductor chip. For example, shrinking the size of transistors allows a higher number of memory or logic devices to be incorporated onto a chip, thereby creating a product with increased capacity. However, the drive to ever-larger capacity is not without its problems. The necessity to optimize the performance of each device becomes ever greater.

[0003] In the manufacture of integrated circuit devices, as device size continues to shrink, multi-gate transistors (e.g., tri-gate transistors) become increasingly dominant. In conventional processes, tri-gate transistors are typically manufactured on bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and because they enable less complex tri-gate manufacturing processes. On the other hand, maintaining mobility improvements and short channel control when microelectronic device size is reduced to below the 10 nanometer (nm) node presents a challenge to device manufacturing. Nanowires used to manufacture devices provide improved short channel control.

[0004] However, scaling multi-gate and nanowire transistors is not without consequences. As the size of these functional building blocks of microelectronic circuitry decreases and as the absolute number of functional building blocks fabricated in a given area increases, the constraints on the photolithographic processes used to pattern these building blocks have become increasingly greater. Specifically, there may be a trade-off between the minimum size (critical dimension) of a feature patterned in a semiconductor stack and the spacing between such features. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1A-1C Angled cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a uniform grid metal gate and trench contact cuts are illustrated in accordance with an embodiment of the present disclosure.

[0006] Figure 1D-1H Cross-sectional views representing various operations in a method of fabricating an integrated circuit structure with reduced terminal capacitance are illustrated in accordance with an embodiment of the present disclosure.

[0007] Fig. 1IA cross-sectional view representing an integrated circuit structure having reduced terminal capacitance according to an embodiment of the present disclosure is shown.

[0008] Figure 2A A cross-sectional view of an integrated circuit structure with fins and metal-first gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0009] Figure 2B A cross-sectional view of an integrated circuit structure with fins and cut metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0010] Figure 3A A cross-sectional view of an integrated circuit structure with nanowires and metal-first gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0011] Figure 3B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0012] Figure 4A A cross-sectional view of an integrated circuit structure with nanowires and metal-first gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0013] Figure 4B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0014] Figures 5A-5C A plan view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown.

[0015] Figures 6A-6C A cross-sectional view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown.

[0016] Figures 7A-7J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0017] Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0018] Fig. 9 Cross-sectional views taken through nanowires and fins are shown for a non-endcap architecture (left side (a)) compared to a self-aligned gate endcap (SAGE) architecture (right side (b)) in accordance with an embodiment of the present disclosure.

[0019] Fig.10Cross-sectional views are shown representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with a gate-around device in accordance with an embodiment of the present disclosure.

[0020] Fig.11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0021] Fig. 11B The diagram according to an embodiment of the present disclosure is taken along the a-a' axis. Fig.11A A cross-sectional source or drain view of a nanowire-based integrated circuit structure.

[0022] Fig. 11C FIG. 2 shows a cross-sectional view taken along the bb' axis according to an embodiment of the present disclosure. Fig.11A Cross-sectional channel diagram of a nanowire-based integrated circuit structure.

[0023] Fig.12 A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0024] Fig.13 An interposer including one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0025] Integrated circuit structures with reduced terminal capacitance and methods of manufacturing integrated circuit structures with reduced terminal capacitance are described. In the following description, many specific details are set forth, such as specific integration and material systems, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other cases, well-known features, such as integrated circuit design layouts, are not described in detail to avoid unnecessary obscurity to the embodiments of the present disclosure. In addition, it should be recognized that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0026] Certain terms are also used in the following description for reference purposes only, and therefore these terms are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," and "side" describe the orientation and / or position of parts of a component within a consistent but arbitrary frame of reference, which orientation and / or position can be clearly understood by reference to the text describing the component in question and the associated drawings. Such terminology may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0027] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or semiconductor layer. FEOL typically encompasses every operation up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0028] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring (e.g., one or more metallization layers) on a wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0029] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although the FEOL processing context is used to illustrate the exemplary processing scheme, such an approach may also be applicable to BEOL processing. Similarly, although the BEOL processing context may be used to illustrate the exemplary processing scheme, such an approach may also be applicable to FEOL processing.

[0030] In a first aspect, one or more embodiments described herein relate to integrated circuit structures fabricated by reducing gate end capacitance (end-cap) using isotropic metal etch back. One or more embodiments described herein relate to gate wrap-around devices with reduced end capacitance. It should be appreciated that references to nanowires herein may indicate nanowires or nanoribbons or nanosheets unless otherwise noted. One or more embodiments described herein relate to FinFET structures with reduced end capacitance. One or more embodiments described herein relate to cutting work function metal for achieving gate end-to-end isolation.

[0031] To provide context, for the same cell size, a narrower Z device will have a greater amount of metal in the gate, contributing to capacitance. The embodiments described herein may be implemented to allow for selective removal of gate metal to reduce capacitance.

[0032] In another aspect, one or more embodiments described herein relate to an integrated circuit structure that is fabricated into a uniform grid including metal gate and trench contact cuts, which may be referred to as a pixel structure. One or more embodiments described herein relate to a gate surround device fabricated using multiple common and extended metal gate cuts (MGC) trench contacts (TCN) cut plug structures. It should be appreciated that, unless otherwise noted, references to nanowires herein may indicate nanowires or nanobelts or nanosheets. One or more embodiments described herein relate to a FinFET structure fabricated using multiple common and extended metal gate cuts (MGC) trench contacts (TCN) cut plug structures. One or more embodiments described herein relate to cutting work function metal for achieving gate end-to-end isolation.

[0033] To provide context, it may be desirable to simplify the trench contact and polysilicon cut (gate cut) processes, for example, to improve device performance and reduce process variations.

[0034] According to one or more embodiments of the present disclosure, a metal gate process is performed and a trench contact process is performed without a plug. A single "infinite" long grid is then used to generate each possible trench contact plug and gate cut plug. The resulting structure may be referred to as a pixel structure. The pixel structure may then be partially plug removed to effectively recombine or reconnect the cut gate portion and / or recombine the cut contact portion.

[0035] As an exemplary treatment scheme, Figures 1A-1C An oblique cross-sectional view representing various operations in a method of fabricating an integrated circuit structure with uniform grid metal gate and trench contact cuts in accordance with an embodiment of the present disclosure is shown. It should be appreciated that the embodiments described and illustrated herein may also be applicable to fin structures that replace stacks of nanowires or nanoribbons or nanosheets.

[0036] refer to Figure 1A, shows a starting structure 100 before a nanowire release and replacement gate process. The starting structure 100 includes a sub-fin 104 extending from a substrate 102, such as a silicon sub-fin extending from a silicon substrate. The sub-fin 104 extends through a shallow trench isolation (STI) structure 106, such as a silicon oxide or silicon dioxide trench isolation structure. One or more stacks of horizontal nanowires 108 (e.g., a stack of horizontal silicon nanowires) are above the corresponding sub-fin 104. At this stage, sacrificial interlayers 110, such as sacrificial silicon germanium interlayers, alternate with the horizontal nanowires 108 in the stack of nanowires. A sacrificial gate oxide 112, such as a silicon oxide or silicon dioxide sacrificial gate oxide, is above the stack of silicon horizontal nanowires 108. A sacrificial gate structure 114, such as a polysilicon sacrificial gate structure, is above the sacrificial gate oxide 112 and above the channel region of the stack of horizontal nanowires 108. A hard mask layer 116 , such as a silicon nitride hard mask layer, may be included on the sacrificial gate structure 114 , as depicted. A gate spacer-forming material 118 , such as a silicon nitride gate spacer-forming material 118 , may be included on and along the sides of the sacrificial gate structure 114 .

[0037] Reference again Figure 1A , an epitaxial source or drain structure 120, such as an epitaxial silicon or epitaxial silicon germanium source or drain structure, is at the end of the stack of horizontal nanowires 108, at a location between adjacent sacrificial gate structures 114. An internal gate spacer 126, such as an internal silicon nitride internal gate spacer 126, can be formed by recessing the sacrificial intervening layer 110 and depositing an internal gate spacer material before forming the epitaxial source or drain structure 120. The epitaxial source or drain structure 120 can be formed over a lower spacer recess fill 122, such as a silicon nitride spacer fill, which can be formed simultaneously with the internal gate spacer 126 and / or the gate spacer-forming material 118. A contact insulator structure 128, such as a silicon oxide or silicon dioxide structure, is included over the epitaxial source or drain structure 120 and can occupy a location where a conductive trench contact is ultimately formed.

[0038] refer to Figure 1B, the starting structure 100 is subjected to a replacement gate and nanowire release process flow. Specifically, the structure 100 is planarized and / or etched to expose the sacrificial gate structure 114. Planarization can remove the hard mask layer 116, can form a gate spacer 118A from a gate spacer forming material 118, and can form a planarized contact insulator structure 128A. The sacrificial gate structure 114 and the sacrificial gate oxide 112 are then removed using a selective etch. The sacrificial intervening layer 110 is then removed using a selective etch. A permanent gate dielectric structure 132, such as a gate dielectric structure comprising a high-k dielectric layer, is then formed in the resulting trenches and cavities, including around the channel region of each of the nanowires 108. A permanent gate electrode 134, such as a gate electrode comprising a metal, is formed over the permanent gate dielectric structure 132, including in a location around the channel region of the nanowire 108. For example, a gate insulating cap layer 136 , such as a silicon nitride cap layer, may be formed on the resulting permanent gate electrode structure 134 by recessing the gate structure and backfilling with a dielectric.

[0039] refer to Figure 1C , a pixel structure 149 is shown with a cross-sectional view of an exposed gate structure. The pixel structure 149 is formed by first replacing the planarized contact insulator structure 128A with a trench contact material. At this stage, the trench contact material is "infinite" along each contact trench, extending over all source / drain structures along a given trench contact line, effectively shorting all trench contacts along a single trench contact line. Similarly, at this stage, the gate electrode material is "infinite" along each gate trench, extending over all nanowire stack channel regions along a given gate line, effectively shorting all gates along a single gate line contact line. If included, the gate insulating cap layer 136 may have been removed at this stage.

[0040] Subsequently, non-selective cuts are made in a direction orthogonal to the gate and trench contact lines, thereby effectively cutting and isolating all trench contacts along a single trench contact line, and cutting and isolating all gate electrodes along a single gate line. The cuts are then filled with a dielectric plug 148, which extends through all trench contact lines and through all gate lines. The resulting "pixel" structure 149 includes a plurality of isolated / cut trench contact structures 140, which may include an insulating cap 142 thereon. The trench contact structure 140 may contact a silicide layer on a corresponding epitaxial source or drain structure 120 at a location exposed by the etch stop layer. The resulting "pixel" structure 149 also includes a plurality of isolated / cut gate structures, for example, a structure including a cut gate dielectric 132A and a cut gate electrode 134A.

[0041] Reference again Figure 1C, according to an embodiment of the present disclosure, an integrated circuit structure 149 includes a vertical stack of horizontal nanowires 108. A gate electrode 134A is above the vertical stack of horizontal nanowires 108. A conductive trench contact 140 is adjacent to the gate electrode 134A. A dielectric sidewall spacer 118A is between the gate electrode 134A and the conductive trench contact 140. A first dielectric notch plug structure 148 extends through the gate electrode 134A, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. A second dielectric notch plug structure 148 extends through the gate electrode 134A, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. The second dielectric notch plug structure 148 is laterally spaced apart and parallel to the first dielectric notch plug structure 148. It should be appreciated that the pixel structure 149 can then be processed by an etching process or a local interconnect formation process to selectively recombine / reconnect multiple ones of the isolated / cut trench contact structures 140, and / or selectively recombine / reconnect multiple ones of the isolated / cut gate structures 132A / 134A.

[0042] In another aspect, as initially mentioned above, a gate terminal capacitance reduction method is implemented. As an example, Figure 1D-1H Cross-sectional views representing various operations in a method of fabricating an integrated circuit structure with reduced terminal capacitance are illustrated in accordance with an embodiment of the present disclosure.

[0043] Fig. 1I A cross-sectional view representing an integrated circuit structure with reduced terminal capacitance according to an embodiment of the present disclosure is shown. It should be appreciated that the embodiments described and illustrated herein may also be applicable to fin structures that replace stacks of nanowires or nanoribbons or nanosheets.

[0044] refer to Figure 1D , showing that after cutting and isolating all gate electrodes along a single gate line and using a combination of Figure 1CThe dielectric plug of the dielectric plug 148 described above is a starting structure 150 before the dielectric plug fills the cut. The starting structure 150 includes a vertical stack of horizontal nanowires 158A / 158B above the corresponding sub-fin structure 154 (which may be above the substrate 152), such as a vertical stack of horizontal silicon nanowires above the corresponding silicon sub-fin structure above the silicon substrate. The sub-fin structure 154 may protrude through a shallow trench isolation structure 156, such as a silicon oxide or silicon dioxide trench isolation structure. A gate structure is formed on a corresponding plurality of the vertical stacks of horizontal nanowires 158A / 158B, the gate structure including a gate electrode 162 and a gate dielectric 160, such as a metal gate electrode and a high-k gate dielectric. Each gate structure may include an insulating gate cap 164, such as a silicon nitride gate cap. The trench 166 separates adjacent device structures, such as device structures 151A and 151B. In this particular example, the device structure 151A includes a vertical stack of horizontal nanowires 158A having a first lateral width. The device structures 151B each include a vertical stack of horizontal nanowires 158B having a second lateral width that is less than the first lateral width.

[0045] In an embodiment, Figure 1D As shown, at this stage, the lateral width of gate electrode 162 is the same for both device structure 151A and device structure 151B. Therefore, the volume of conductive material of gate electrode 162 laterally adjacent to the vertical stack of horizontal nanowires 158B is larger than the volume of conductive material of gate electrode 162 laterally adjacent to the vertical stack of horizontal nanowires 158A. This increased volume may result in undesirable gate capacitance.

[0046] refer to Figure 1E ,exist Figure 1D An etch stop layer 168 is formed over the starting structure 150. In an embodiment, the etch stop layer 168 is a silicon nitride etch stop layer.

[0047] refer to Figure 1F A hard mask layer 170, such as a carbon hard mask layer, is formed and patterned to cover the device structure 151A and expose the device structure 151B. The etch stop layer 168 is patterned to form a patterned etch stop layer 168A.

[0048] refer to Figure 1G , an isotropic etching process, such as an isotropic wet etching process, is performed to remove conductive material from the gate electrode of the device structure 151B at location 172 .

[0049] refer to Figure 1HAfter the isotropic etching process, the gate electrode 162 of the device structure 151B is laterally recessed to provide a recessed gate electrode 162A. The lateral width of the recessed gate electrode 162A of the device structure 151B is smaller than the lateral width of the gate electrode 162 of the device structure 151A. The hard mask layer 170 and the patterned etch stop layer 168A are then removed. A dielectric plug 174 is then formed between adjacent devices.

[0050] As Figure 1H An enlarged exemplary embodiment of the structure of Fig. 1I , showing that in combination Figure 1D-1H Device structures 151A and 151B after the processing described. Implementations may result in visible artifacts. For example, in an embodiment, at location 182, a metal gate step (recess) is located at the interface of the insulating gate cap 164 and the recessed gate electrode 162A. In an embodiment, at location 184, a metal gate step (recess) is located at the interface of the trench isolation structure 156 and the recessed gate electrode 162A. In an embodiment, at location 186, the gate electrode 162 has no step.

[0051] On the other hand, in order to reduce the cell height in future or scaled technology nodes, the gate terminal capacitance and gate cut size need to be reduced. The gate cut before the gate metal fill may limit the effective terminal capacitance available for the work function and may become challenging for metal fill capabilities in more compact spaces. The defects may be more severe for any gate end-to-end misalignment that creates space for smaller end capacitance.

[0052] According to one or more embodiments of the present disclosure, in order to solve the problems briefly described above, a metal gate cutting process is performed after the gate dielectric and work function metal deposition and patterning are completed. In any case, in an embodiment, the above-mentioned Figures 1A-1I The gate / contact plugs described use a gate plug formed after metal gate formation ("plug last") and / or a gate plug formed before metal gate formation ("plug first") (both described below).

[0053] Advantages of implementing the methods described herein may include a so-called "plug last" approach, which results in no gate dielectric layer (e.g., a high-k gate dielectric layer) being deposited on the gate plug sidewalls, effectively saving additional space for work function metal deposition. In contrast, during the so-called conventional "plug first" approach, the metal gate fill material may be pinched off between the plug and the fin. Due to plug misalignment in the latter approach, the space for the metal fill may be narrower and may result in voids during metal filling. In the embodiments described herein, using the "plug last" approach, the work function metal deposition may be seamless (e.g., void-free).

[0054] According to one or more embodiments of the present disclosure, an integrated circuit structure has a clean interface between a gate plug dielectric and a gate metal. It should be appreciated that many embodiments may benefit from the methods described herein, such as the plug last method. For example, the following Figure 2B Metal gate cutting on FinFET devices is described. A metal gate cutting scheme can be implemented for a gate-all-around (GAA) device, such as the following combined Figure 3B and Figure 4B Furthermore, the metal gate cut and plug formation may look different based on the structure being entered. For example, the plug may land on a shallow trench isolation (STI) structure, such as in combination with Figure 2B and Figure 3B As described above, or can land on the pre-fabrication gate wall made of dielectric, for example in combination with Figure 4B The metal gate cutting method can be selective to the gate spacer dielectric, for example in combination with Figure 5B and Figure 6B or may not be selective for the gate spacer material, for example in combination with Figure 5C and Figure 6C Non-selective metal gate cut embodiments may require alternative contact metal schemes to accommodate dielectric plugs between epitaxial source / drain electrodes. Plug etch selectivity for epitaxial source / drain material is optional. However, in one embodiment, if the epitaxial source / drain is exposed to the plug etch (e.g., due to device size), the etch may anisotropically trim the source / drain, such as described below in conjunction with Figure 5C Such an approach may be implemented to achieve compact end cap spacing.

[0055] A dielectric gate plug can be fabricated for a FinFET device. As a comparative example, Figure 2A A cross-sectional view of an integrated circuit structure with fins and metal-first gate dielectric plugs according to an embodiment of the present disclosure is shown. Figure 2B A cross-sectional view of an integrated circuit structure with fins and cut metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0056] refer to Figure 2A, the integrated circuit structure 200 includes a fin 202 having a portion protruding above a shallow trench isolation (STI) structure 204. A gate dielectric material layer 206, such as a high-k gate dielectric layer, is over the protruding portion of the fin 202 and over the STI structure 204. It should be appreciated that, although not depicted, an oxidized portion of the fin 202 may be between the protruding portion of the fin 202 and the gate dielectric material layer 206 and may be included with the gate dielectric material layer 206 to form a gate dielectric structure. A conductive gate layer 208, such as a work function metal layer, is over the gate dielectric material layer 206 and may be directly on the gate dielectric material layer 206 as shown. A conductive gate fill material 210 is over the conductive gate layer 208 and may be directly on the conductive gate layer 208 as shown. A dielectric gate cap 212 is over the conductive gate fill material 210. A dielectric gate plug 214 is laterally spaced apart from the fin 202 and over the STI structure 204. The gate dielectric material layer 206 and the conductive gate layer 208 are along the sides of the dielectric gate plug 214 .

[0057] refer to Figure 2B , the integrated circuit structure 250 includes a fin 252 having a portion protruding above a shallow trench isolation (STI) structure 254. A gate dielectric material layer 256, such as a high-k gate dielectric layer, is over the protruding portion of the fin 252 and over the STI structure 254. It should be appreciated that, although not depicted, an oxidized portion of the fin 252 may be between the protruding portion of the fin 252 and the gate dielectric material layer 256 and may be included with the gate dielectric material layer 256 to form a gate dielectric structure. A conductive gate layer 258, such as a work function metal layer, is over the gate dielectric material layer 256 and may be directly on the gate dielectric material layer 256 as shown. A conductive gate fill material 260 is over the conductive gate layer 258 and may be directly on the conductive gate layer 258 as shown. A dielectric gate cap 262 is on the conductive gate fill material 260.

[0058] In an embodiment, the dielectric gate plug 264 is laterally spaced apart from the fin 252 and is on the STI structure 254 but does not pass through the STI structure 254. As used throughout this disclosure, a dielectric plug referred to as being "on but not through" an STI structure may refer to a dielectric plug that lands on the top or uppermost surface of the STI, or may refer to a plug that extends into the STI but does not penetrate the STI. In other embodiments, the plugs described herein may extend completely through or penetrate the STI.

[0059] In an embodiment, the gate dielectric material layer 256 and the conductive gate layer 258 are not along the sides of the dielectric gate plug 264. Instead, the conductive gate fill material 260 contacts the sides of the dielectric gate plug 264. As a result, the area between the dielectric gate plug 264 and the fin 252 includes only one layer of the gate dielectric material layer 256 and only one layer of the conductive gate layer 258, easing spatial constraints in such a compact area of ​​the structure 250. Easing spatial constraints can improve metal filling and / or can facilitate patterning of multiple VTs.

[0060] Reference again Figure 2B In an embodiment, the dielectric gate plug 264 is formed after forming the gate dielectric material layer 256, the conductive gate layer 258, and the conductive gate filling material 260. As a result, the gate dielectric material layer 256 and the conductive gate layer 258 are not formed along the sides of the dielectric gate plug 264. In an embodiment, the uppermost surface of the dielectric gate plug 264 is coplanar with the uppermost surface of the dielectric gate cap 262, as depicted. In another embodiment not depicted, the dielectric gate cap 262 is not included, and the uppermost surface of the dielectric gate plug 264 is coplanar with the uppermost surface of the conductive gate filling material 260, for example, coplanar along the plane 280.

[0061] A dielectric gate plug can be fabricated for a nanowire device. As a comparative example, Figure 3A A cross-sectional view of an integrated circuit structure with nanowires and metal-first gate dielectric plugs according to an embodiment of the present disclosure is shown. Figure 3B A cross-sectional view of an integrated circuit structure with nanowires and cut gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0062] refer to Figure 3A, the integrated circuit structure 300 includes a sub-fin 302 having a portion protruding above a shallow trench isolation (STI) structure 304. A plurality of horizontally stacked nanowires 305 are above the sub-fin 302. A gate dielectric material layer 306, such as a high-k gate dielectric layer, is above the protruding portion of the sub-fin 302, above the STI structure 304, and around the horizontally stacked nanowires 305. It should be appreciated that, although not depicted, the oxidized portions of the sub-fin 302 and the horizontally stacked nanowires 305 can be between the protruding portion of the sub-fin 302 and the gate dielectric material layer 306, and between the horizontally stacked nanowires 305 and the gate dielectric material layer 306, and can be included with the gate dielectric material layer 306 to form a gate dielectric structure. A conductive gate layer 308, such as a work function metal layer, is above the gate dielectric material layer 306, and can be directly on the gate dielectric material layer 306 as shown. Conductive gate fill material 310 is above conductive gate layer 308 and may be directly on conductive gate layer 308 as shown. Dielectric gate cap 312 is on conductive gate fill material 310. Dielectric gate plug 314 is laterally spaced apart from sub-fin 302 and plurality of horizontally stacked nanowires 305 and is on STI structure 304. Gate dielectric material layer 306 and conductive gate layer 308 are along sides of dielectric gate plug 314.

[0063] refer to Figure 3B, the integrated circuit structure 350 includes a sub-fin 352 having a portion protruding above a shallow trench isolation (STI) structure 354. A plurality of horizontally stacked nanowires 355 are above the sub-fin 352. A gate dielectric material layer 356, such as a high-k gate dielectric layer, is above the protruding portion of the sub-fin 352, above the STI structure 354, and around the horizontally stacked nanowires 355. It should be appreciated that, although not depicted, the oxidized portion of the sub-fin 352 can be between the protruding portion of the sub-fin 352 and the gate dielectric material layer 356, and between the horizontally stacked nanowires 355 and the gate dielectric material layer 356, and can be included with the gate dielectric material layer 356 to form a gate dielectric structure. A conductive gate layer 358, such as a work function metal layer, is above the gate dielectric material layer 356, and can be directly on the gate dielectric material layer 356 as shown. The conductive gate fill material 360 is above the conductive gate layer 358 and may be directly on the conductive gate layer 358 as shown. The dielectric gate cap 362 is on the conductive gate fill material 360. The dielectric gate plug 364 is laterally spaced apart from the sub-fin 352 and the plurality of horizontally stacked nanowires 355 and is on the STI structure 354 but does not pass through the STI structure 354. However, the gate dielectric material layer 356 and the conductive gate layer 358 are not along the sides of the dielectric gate plug 364. Instead, the conductive gate fill material 360 contacts the sides of the dielectric gate plug 364. As a result, the area between the dielectric gate plug 364 and the combination of the sub-fin 352 and the plurality of horizontally stacked nanowires 355 includes only one layer of the gate dielectric material layer 356 and only one layer of the conductive gate layer 358, alleviating the spatial constraints in such a compact area of ​​the structure 350.

[0064] Reference again Figure 3B In an embodiment, dielectric gate plug 364 is formed after forming gate dielectric material layer 356, conductive gate layer 358, and conductive gate filling material 360. As a result, gate dielectric material layer 356 and conductive gate layer 358 are not formed along the sides of dielectric gate plug 364. In an embodiment, the uppermost surface of dielectric gate plug 364 is coplanar with the uppermost surface of dielectric gate cap 362, as depicted. In another embodiment not depicted, dielectric gate cap 362 is not included, and the uppermost surface of dielectric gate plug 364 is coplanar with the uppermost surface of conductive gate filling material 360, for example, coplanar along plane 380.

[0065] A dielectric gate plug can be fabricated on the gate end cap wall for a nanowire device. As a comparative example, Figure 4A A cross-sectional view of an integrated circuit structure with nanowires and metal-first gate dielectric plugs according to an embodiment of the present disclosure is shown. Figure 4BA cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0066] refer to Figure 4A , the integrated circuit structure 400 includes a sub-fin 402 having a portion protruding over a shallow trench isolation (STI) structure 404. A plurality of horizontally stacked nanowires 405 are over the sub-fin 402. A gate endcap structure 403, such as a self-aligned gate endcap structure, is over the STI structure 404 and laterally spaced apart from the sub-fin 402 and the plurality of horizontally stacked nanowires 405. A gate dielectric material layer 406, such as a high-k gate dielectric layer, is over the protruding portion of the sub-fin 402, over the STI structure 404, along the sides of the gate endcap structure 403, and around the horizontally stacked nanowires 405. It should be appreciated that, although not depicted, the oxidized portions of the sub-fin 402 and the horizontally stacked nanowires 405 can be between the protruding portions of the sub-fin 402 and the gate dielectric material layer 406, and between the horizontally stacked nanowires 405 and the gate dielectric material layer 406, and can be included with the gate dielectric material layer 406 to form a gate dielectric structure. A conductive gate layer 408, such as a work function metal layer, is above the gate dielectric material layer 406, and can be directly on the gate dielectric material layer 406 as shown. A conductive gate fill material 410 is above the conductive gate layer 408, and can be directly on the conductive gate layer 408 as shown. A dielectric gate cap 412 is on the conductive gate fill material 410. A dielectric gate plug 414 is on the gate end cap structure 403. The gate dielectric material layer 406 and the conductive gate layer 408 are along the sides of the dielectric gate plug 414.

[0067] refer to Figure 4B, the integrated circuit structure 450 includes a sub-fin 452 having a portion protruding above a shallow trench isolation (STI) structure 454. A plurality of horizontally stacked nanowires 455 are above the sub-fin 452. A gate endcap structure 453, such as a self-aligned gate endcap structure, is on but does not pass through the STI structure 454 and is laterally spaced apart from the sub-fin 452 and the plurality of horizontally stacked nanowires 455. A gate dielectric material layer 456, such as a high-k gate dielectric layer, is over the protruding portion of the sub-fin 452, over the STI structure 454, along the sides of the gate endcap structure 453, and around the horizontally stacked nanowires 455. It should be appreciated that, although not depicted, the oxidized portion of the sub-fin 452 can be between the protruding portion of the sub-fin 452 and the gate dielectric material layer 456, and between the horizontally stacked nanowires 455 and the gate dielectric material layer 456, and can be included with the gate dielectric material layer 456 to form a gate dielectric structure. A conductive gate layer 458, such as a work function metal layer, is above the gate dielectric material layer 456, and can be directly on the gate dielectric material layer 456 as shown. A conductive gate fill material 460 is above the conductive gate layer 458, and can be directly on the conductive gate layer 458 as shown. A dielectric gate cap 462 is on the conductive gate fill material 460. A dielectric gate plug 464 is on the gate end cap structure 453. However, the gate dielectric material layer 456 and the conductive gate layer 458 are not along the sides of the dielectric gate plug 464. Instead, the conductive gate fill material 460 contacts the sides of the dielectric gate plug 464.

[0068] Reference again Figure 4B In an embodiment, the dielectric gate plug 464 is formed after forming the gate dielectric material layer 456, the conductive gate layer 458, and the conductive gate filling material 460. As a result, the gate dielectric material layer 456 and the conductive gate layer 458 are not formed along the sides of the dielectric gate plug 464. In an embodiment, the uppermost surface of the dielectric gate plug 464 is coplanar with the uppermost surface of the dielectric gate cap 462, as depicted. In another embodiment not depicted, the dielectric gate cap 462 is not included, and the uppermost surface of the dielectric gate plug 464 is coplanar with the uppermost surface of the conductive gate filling material 460, for example, coplanar along the plane 480.

[0069] In another aspect, a selective or non-selective version of metal gate cutting can be implemented. As an example, Figures 5A-5C A plan view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 5A Representing a conventional "plug first" approach, two gate plugs in adjacent gates are shown. Figure 5BRepresenting the selective metal gate cutting method, two gate plugs in adjacent gates are shown. Figure 5C Representing the non-selective metal gate cutting method, a long gate plug spanning multiple gates is shown.

[0070] refer to Figure 5A , the integrated circuit structure 500 includes a gate line between a dielectric spacer 517 and a conductive source or drain contact 518. Each gate line includes a gate dielectric material layer 506, a conductive gate layer 508 such as a work function metal layer, and a conductive gate filling material 510. The dielectric gate plug 514 can interrupt a portion of the corresponding gate line. The dielectric gate plug 514 contacts the conductive gate layer 508, but does not contact the gate dielectric material layer 506 or the conductive gate filling material 510. Figure 5A The plane graph of Figure 2A , Figure 3A or Figure 4A It should be appreciated that, although referred to above as a conductive source or drain contact 518 , a placeholder dielectric or dielectric plug was in place of the conductive source or drain contact 518 at an earlier stage of processing or elsewhere in the integrated circuit structure.

[0071] refer to Figure 5B , the integrated circuit structure 550 includes a gate line between a dielectric spacer 567 and a conductive source or drain contact 568. Each gate line includes a gate dielectric material layer 556, a conductive gate layer 558 such as a work function metal layer, and a conductive gate filling material 560. The dielectric gate plug 564 can interrupt a portion of the corresponding gate line. The dielectric gate plug 564 contacts the conductive gate filling material 560. Figure 5B The plane graph of Figure 2B , Figure 3B or Figure 4B It should be appreciated that, although referred to above as a conductive source or drain contact 568 , a placeholder dielectric or dielectric plug was in place of the conductive source or drain contact 568 at an earlier stage of processing or elsewhere in the integrated circuit structure.

[0072] refer to Figure 5C , the integrated circuit structure 570 includes gate lines between dielectric spacers 587 and conductive source or drain contacts 588. Each gate line includes a gate dielectric material layer 576, a conductive gate layer 578 such as a work function metal layer, and a conductive gate fill material 580. A single dielectric gate plug 584 can interrupt portions of the gate line and can extend through the dielectric spacers 587 and even partially or completely into one or more of the conductive source or drain contacts 588. The dielectric gate plug 584 contacts the conductive gate fill material 580. Figure 5CThe plane graph of Figure 2B , Figure 3B or Figure 4B structure.

[0073] Reference again Figure 5C , it should be appreciated that, although referred to above as a conductive source or drain contact 588, at an earlier stage of the process or at other locations in the integrated circuit structure, a placeholder dielectric or dielectric plug was in the location of the conductive source or drain contact 588. In an embodiment, the etch used to form the opening in which the single dielectric gate plug 584 is ultimately formed is referred to as a non-selective etch. Where the conductive source or drain contact 588 has been formed, the non-selective etch can etch into the conductive material of the conductive source or drain contact 588. In other embodiments, where the placeholder dielectric or dielectric plug is in the location of the conductive source or drain contact 588, the non-selective etch can etch into the placeholder dielectric or dielectric plug. In either case, the non-selective etch can etch through the epitaxial semiconductor material of the source region or drain region formed below the location of the conductive source or drain contact 588, and possibly separate the epitaxial semiconductor material. In the case where a conductive source or drain contact 588 has been formed, the epitaxial semiconductor material of the source region or drain region may include a silicide portion.

[0074] Figures 6A-6C A cross-sectional view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown. Fig. 6A Represents the conventional "plug first" approach. Figure 6B Stands for Selective Metal Gate Cutting Method. Figure 6C Stands for non-selective metal gate cutting method.

[0075] refer to Fig. 6A , the integrated circuit structure 600 includes a dielectric gate plug 614 between a dielectric spacer 617 and a conductive source or drain contact 618 . Fig. 6A A cross-sectional view may correspond to Figure 2A , Figure 3A , Figure 4A or Figure 5A Orthogonal view of the structure.

[0076] refer to Figure 6B , the integrated circuit structure 650 includes a dielectric gate plug 664 between a dielectric spacer 667 and a conductive source or drain contact 668 . Figure 6B A cross-sectional view may correspond to Figure 2B , Figure 3B , Figure 4B or Figure 5B Orthogonal view of the structure.

[0077] refer to Figure 6C , the integrated circuit structure 670 includes a single dielectric gate plug 684 between conductive source or drain contacts 688. The dashed box 690 shows the Figure 6B Where will the corresponding discrete gate plugs, such as gate plug 664, be aligned in the case of Figure 6B Where would the non-recessed source or drain contact 668 be aligned in the case of . The area between the dashed box 690 and the dashed box 692 shows Figure 6B Where would the dielectric spacer 667 be in this case. Figure 6C A cross-sectional view may correspond to Figure 2B , Figure 3B , Figure 4B or Figure 5C Orthogonal view of the structure.

[0078] In embodiments, the metal work function can be: (a) the same metal system in NMOS and PMOS, (b) different metal systems between NMOS and PMOS, and / or (c) a single material or multiple layers of metal (e.g., W, TiN, TiXAlYCz, TaN, Mo, MoN). In embodiments, the metal cutting etch chemistry includes a chlorine-containing or fluorine-containing etchant, possibly with an additional carbon- or silicon-containing component to provide passivation.

[0079] It should be appreciated that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials including but not limited to Si and SiGe. For example, III-V materials may be used.

[0080] It should be appreciated that in certain embodiments, the nanowires or nanobelts or sacrificial intervening layers may be comprised of silicon. As used throughout, a silicon layer may be used to describe a silicon material comprised of a very large amount (if not all) of silicon. However, it should be appreciated that, in practice, 100% pure Si may be difficult to form, and may therefore include a small percentage of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition, or may "contaminate" Si during diffusion during post-deposition processing. In this way, embodiments described herein involving silicon layers may include silicon layers containing relatively small amounts (e.g., "impurity" levels) of non-Si atoms or substances (e.g., Ge, C, or Sn). It should be appreciated that the silicon layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0081] It should be appreciated that in certain embodiments, the nanowires or nanoribbons or sacrificial intervening layers may be composed of silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material composed of a significant portion of silicon and germanium (e.g., at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, the silicon germanium layer includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer includes about 30% germanium and about 70% silicon (Si 70 Ge 30 ). It should be appreciated that, in practice, 100% pure silicon germanium (generally referred to as SiGe) may be difficult to form, and therefore may include minute percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may "contaminate" the SiGe when diffused during post-deposition processing. As such, embodiments described herein involving silicon germanium layers may include silicon germanium layers containing relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or substances (e.g., carbon or tin). It should be appreciated that silicon germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0082] Described below are various devices and processing schemes that can be used to manufacture devices that can be integrated with cut metal gates. It should be appreciated that exemplary embodiments do not necessarily require all of the features described, or may include more features than described. For example, a nanowire release process can be performed by replacing the gate trench. An example of such a release process is described below. In addition, in yet another aspect, back-end (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to the complexity of patterning. The embodiments described herein may be implemented to enable front and back interconnect integration for nanowire transistors. The embodiments described herein may provide methods for achieving relatively wider interconnect spacing. The result may be improved product performance and lower patterning costs. Embodiments may be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0083] One or more embodiments described herein relate to a dual epitaxial (EPI) connection for a nanowire or nanoribbon transistor using a partial source or drain (SD) and an asymmetric trench contact (TCN) depth. In an embodiment, an integrated circuit structure is fabricated by forming a source-drain opening for a nanowire / nanoribbon transistor and partially filling the opening with SD epitaxy. The remainder of the opening is filled with a conductive material. A deep trench is formed on one of the source or drain sides to enable direct contact to a backside interconnect level.

[0084] As an exemplary process flow for manufacturing a gate-around device of a gate-around integrated circuit structure, Figure 7A-7J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0085] refer to Fig. 7A , a method of manufacturing an integrated circuit structure includes forming a starting stack including alternating sacrificial layers 704 and nanowires 706 above fins 702 (e.g., silicon fins). Nanowires 706 may be referred to as a vertical arrangement of nanowires. As shown, protective caps 708 may be formed above alternating sacrificial layers 704 and nanowires 706. Also as shown, a relaxed buffer layer 752 and a defect modification layer 750 may be formed below alternating sacrificial layers 704 and nanowires 706.

[0086] refer to Figure 7B , a gate stack 710 is formed over the vertical arrangement of the horizontal nanowires 706. The vertically arranged portion of the horizontal nanowires 706 is then released by removing a portion of the sacrificial layer 704 to provide a recessed sacrificial layer 704' and a cavity 712, such as Figure 7C shown.

[0087] It should be recognized that it is possible to manufacture Figure 7C In either case (e.g., with or without the asymmetric contact processing), in an embodiment, the manufacturing process involves using a process scheme that provides a gate-around integrated circuit structure with an epitaxial block, which may be a vertically discrete source or drain structure.

[0088] refer to Fig.7D , an upper gate spacer 714 is formed at the sidewalls of the gate structure 710. A cavity spacer 716 is formed in the cavity 712 below the upper gate spacer 714. A deep trench contact etch is then optionally performed to form a trench 718 and form a recessed nanowire 706'. As shown, there may also be a patterned relaxed buffer layer 752' and a patterned defect modification layer 750'.

[0089] Then, a sacrificial material 720 is formed in the trench 718, such as Fig. 7E In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0090] refer to Figure 7F, a first epitaxial source or drain structure (e.g., left feature 722) is formed at a first end of the vertical arrangement of horizontal nanowire 706'. A second epitaxial source or drain structure (e.g., right feature 722) is formed at a second end of the vertical arrangement of horizontal nanowire 706'. In an embodiment, as depicted, epitaxial source or drain structure 722 is a vertically discrete source or drain structure and may be referred to as an epitaxial nub.

[0091] like Figure 7G As shown, an interlayer dielectric (ILD) material 724 is then formed on the side of the gate electrode 710 and adjacent to the source or drain structure 722. Figure 7H , a permanent gate dielectric 728 and a permanent gate electrode 726 are formed using a replacement gate process. The ILD material 724 is then removed, as shown in FIG. Fig.7I The sacrificial material 720 is then removed from one of the source drain locations (eg, the right side) to form the trench 732 , but the sacrificial material is not removed from the other of the source drain locations to form the trench 730 .

[0092] refer to Figure 7J , forming a first conductive contact structure 734 coupled to the first epitaxial source or drain structure (e.g., left feature 722). Forming a second conductive contact structure 736 coupled to the second epitaxial source or drain structure (e.g., right feature 722). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In an embodiment, although Figure 7J Not shown, the method also includes forming an exposed surface of a second conductive contact structure 736 at the bottom of the fin 702. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, where examples may include Ti, Ni, Co for the former and W, Ru, Co for the latter.

[0093] In an embodiment, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734, as depicted. In one such embodiment, the first conductive contact structure 734 is not along the fin 702, as depicted. In another such embodiment not depicted, the first conductive contact structure 734 is partially along the fin 702.

[0094] In an embodiment, the second conductive contact structure 736 is along the entire fin 702. In an embodiment, although not depicted, the second conductive contact structure 736 has an exposed surface at the bottom of the fin 702 where the bottom of the fin 702 is exposed by a backside substrate removal process.

[0095] In an embodiment, the offset gate cutting method described above may be used to form Figure 7J structure or Figures 7A-7J The relevant structure.

[0096] In another aspect, in order to be able to access the two conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be manufactured using a manufacturing method that exposes the back side of the front structure. In some exemplary embodiments, the back side exposure of transistors or other device structures requires wafer-level back side processing. In contrast to conventional TSV-type technologies, the back side exposure of transistors described herein can be performed at the density of device cells and even in sub-regions of the device. In addition, such back side exposure of transistors can be performed to remove substantially all of the donor substrate on which the device layer is disposed during front device processing. In this way, micron-deep TSVs become unnecessary in the case where the semiconductor thickness in the device cell may be only tens or hundreds of nanometers after the back side of the transistor is exposed.

[0097] The revealing techniques described herein can shift the paradigm from "bottom-up" device manufacturing to "center-out" manufacturing, where the "center" is any layer that is employed in front-side manufacturing, revealed from the back side, and employed again in back-side manufacturing. Processing of the front side and the revealed back side of the device structure can solve many of the challenges associated with making 3D ICs when relying primarily on front-side processing.

[0098] For example, a backside exposure method of a transistor can be used to remove at least a portion of a carrier layer and an intervening layer of a donor-acceptor substrate assembly. The process flow begins with the input of a donor-acceptor substrate assembly. The thickness of the carrier layer in the donor-acceptor substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and / or wet / dry etching process known to be suitable for the carrier layer component can be used. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0099] In some embodiments, prior to the above operations, the carrier layer is cleaved along a fracture plane substantially parallel to the intervening layer. A significant portion of the carrier layer can be removed as a bulk using a cleaving or fracture process to reduce the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved off by practicing any uniform thickness implant known to promote wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted to a uniform target depth within the carrier layer where a fracture plane is desired. After such a cleaving process, the remaining carrier layer thickness in the donor-acceptor substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a greater thickness of the carrier layer.

[0100] Next, the exposure of the intervening layer is detected. Detection is used to identify the point when the back surface of the donor substrate is almost advanced to the device layer. Any endpoint detection technology known to be suitable for detecting the transition between the material used for the carrier layer and the intervening layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting the change in light absorption or emission of the back surface of the donor substrate during polishing or etching. In some other embodiments, the endpoint criteria are associated with the change in light absorption or emission of the byproduct during polishing or etching the back surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproduct can be changed according to the different components of the carrier layer and the intervening layer. In other embodiments, the endpoint criteria are associated with the change in the mass of the substance in the byproduct of polishing or etching the back surface of the donor substrate. For example, the byproduct of the process can be sampled by a quadrupole mass analyzer, and the change in the mass of the substance can be related to the different components of the carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criteria are associated with the change in the friction between the back surface of the donor substrate and the polishing surface in contact with the back surface of the donor substrate.

[0101] Detection of an intervening layer can be enhanced where the removal process is selective to the carrier layer relative to the intervening layer because the non-uniformity of the carrier removal process can be mitigated by the difference in etch rates between the carrier layer and the intervening layer. Detection can even be skipped if the grinding, polishing and / or etching removes the intervening layer at a rate sufficiently lower than the rate at which the carrier layer is removed. If an endpoint criterion is not employed, a predetermined fixed duration grinding, polishing and / or etching operation can stop on the intervening layer material if the thickness of the intervening layer is sufficient for the selectivity of the etch. In some examples, the carrier etch rate:intervening layer etch rate is 3:1-10:1 or greater.

[0102] When exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more constituent layers of the intervening layer may be removed. The thickness of the intervening layer may be uniformly removed, for example, by polishing. Alternatively, the thickness of the intervening layer may be removed using a masked or blanket etching process. The process may employ the same polishing or etching process as the process used to thin the carrier, or may be a different process with different process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, subsequent operations may employ a different polishing or etching process that favors the removal of the intervening layer relative to the removal of the device layer. When less than a few hundred nanometers of intervening layer thickness is to be removed, the removal process may be slower, optimized for uniformity across the wafer, and more precisely controlled than the process used to remove the carrier layer. The CMP process employed may, for example, employ a slurry that provides extremely high selectivity (e.g., 100:1-300:1 or greater) between semiconductors (e.g., silicon) and dielectric materials (e.g., SiO) that surround the device layers and are embedded within the intervening layer, for example, as electrical isolation between adjacent device regions.

[0103] For embodiments where the device layer is exposed by completely removing the intervening layer, the backside processing can begin on the exposed backside of the device layer or on specific device regions therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer between the intervening layer and the device region (e.g., source region or drain region) previously fabricated in the device layer.

[0104] In some embodiments where wet and / or plasma etching is used to recess the back side of a carrier layer, an intermediate layer, or a device layer, such etching may be a patterned etch or a material selective etch that imparts significant non-planarity or topography to the back side surface of the device layer. As further described below, patterning may be within a device cell (i.e., "intra-cell" patterning) or may span a device cell (i.e., "inter-cell" patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the back side device layer. Thus, the masked etching process may serve as the beginning of a corresponding masked device layer etch.

[0105] The processing scheme described above can produce a donor-acceptor substrate assembly including an IC device having an exposed back side of an intervening layer, a back side of a device layer, and / or a back side of one or more semiconductor regions within a device layer, and / or front side metallization. Additional back side processing of any of these exposed regions can then be performed during downstream processing.

[0106] It should be appreciated that the structure obtained from the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete the manufacture of devices, such as PMOS and / or NMOS devices. As an example of a completed device, Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0107] refer to Figure 8 , the semiconductor structure or device 800 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 804 and a sub-fin region 805) within a trench isolation region 806. In an embodiment, instead of a solid fin, the non-planar active region is separated into nanowires (e.g., nanowires 804A and 804B) above the sub-fin region 805, as indicated by the dotted lines. In either case, for ease of describing the non-planar integrated circuit structure 800, the non-planar active region 804 is referred to as the protruding fin portion below. In an embodiment, the sub-fin region 805 also includes a relaxed buffer layer 842 and a defect modification layer 840, as depicted.

[0108] The gate line 808 is disposed over the protruding portion 804 of the non-planar active area (including the surrounding nanowires 804A and 804B, where applicable) and over a portion of the trench isolation region 806. As shown, the gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. Also visible from this perspective is the gate contact 814 and the gate contact via 816 thereover, along with the metal interconnect 860 thereover, all disposed in an interlayer dielectric stack or layer 870. As also shown in FIG. Figure 8 As shown in the perspective view of FIG. 8 , in one embodiment, the gate contact 814 is disposed above the trench isolation region 806 but not above the non-planar active region. In another embodiment, the gate contact 814 is above the non-planar active region.

[0109] In an embodiment, the semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a FinFET device, a tri-gate device, a nanobelt device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed as a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 808 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body.

[0110] Also like Figure 8As shown in , in an embodiment, there is an interface 880 between the protruding fin portion 804 and the sub-fin region 805. The interface 880 can be a transition region between the doped sub-fin region 805 and the lightly doped or undoped upper fin portion 804. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally supplied from an adjacent solid-state doping layer at the sub-fin location. In a specific such embodiment, each fin is less than 10 nanometers wide.

[0111] although Figure 8 Not shown, but it will be appreciated that the source or drain region of the protruding fin portion 804 or a source or drain region adjacent to the protruding fin portion 804 is on either side of the gate line 808, i.e., either side in and out of the page. In one embodiment, material of the protruding fin portion 804 in the source or drain position is removed and replaced with another semiconductor material, for example by epitaxial deposition, to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 806, i.e., into the sub-fin region 805. According to an embodiment of the present disclosure, the more heavily doped sub-fin region, i.e., the doped portion of the fin below the interface 880, inhibits leakage of the source to the drain through that portion of the bulk semiconductor fin. In an embodiment, the source and drain regions have associated asymmetric source and drain contact structures, as described above in conjunction with Figure 7J described.

[0112] Reference again Figure 8 In an embodiment, fins 804 / 805 (and possibly nanowires 804A and 804B) are comprised of a crystalline silicon germanium layer, which may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0113] In an embodiment, the trench isolation region 806 and the trench isolation regions (trench isolation structures or trench isolation layers) described throughout the present application may be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of a portion of the permanent gate structure from the underlying bulk substrate, or isolating an active region (e.g., an isolation fin active region) formed within the bulk substrate. For example, in one embodiment, the trench isolation region 806 is composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0114] The gate line 808 may be composed of a gate electrode stack, which includes a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 852 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium titanium oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer 852 may include a native oxide layer formed by several layers at the top of the substrate fin 804. In an embodiment, the gate dielectric layer 852 is composed of a high-k portion at the top and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 852 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, a portion of the gate dielectric is a "U" shaped structure including a bottom portion substantially parallel to a substrate surface and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0115] In one embodiment, the gate electrode layer 850 is composed of a metal layer, such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or a conductive metal oxide. In a specific embodiment, the gate electrode layer 850 is composed of a non-work function setting filling material formed above the metal work function setting layer. The gate electrode layer 850 can be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor will be a PMOS or NMOS transistor. In some embodiments, the gate electrode layer 850 can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include but are not limited to ruthenium, palladium, platinum, cobalt, nickel, tungsten and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9eV and about 5.2eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may be composed of a "U"-shaped structure, the U-shaped structure including a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate, and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In other embodiments of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0116] The spacer associated with the gate electrode stack can be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of the permanent gate structure from an adjacent conductive contact (e.g., a self-aligned contact). For example, in one embodiment, the spacer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0117] The gate contact 814 and the gate contact via 816 above may be made of a conductive material. In an embodiment, one or more of the contact or via is made of a metal species. The metal species may be a pure metal such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material).

[0118] In an embodiment (although not depicted), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 808, while eliminating the use of a photolithography step with an extremely tight registration budget. In an embodiment, the contact pattern is a vertically symmetrical contact pattern or an asymmetrical contact pattern, such as a combination of Figure 7J As described. In other embodiments, all contacts are frontally connected and are not asymmetric. In one such embodiment, a self-aligned method enables the use of an inherently highly selective wet etch (e.g., relative to conventionally implemented dry or plasma etching) to produce contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, this approach makes it possible to eliminate the need for a lithography operation that is otherwise critical to producing a contact pattern as used in a conventional manner. In an embodiment, a trench contact grid is not patterned separately, but is formed between polysilicon (gate) lines. For example, in one such embodiment, a trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0119] In an embodiment, providing structure 800 involves making gate stack structure 808 by a replacement gate process. In such an approach, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, as opposed to performing formation of the layer by an earlier process. In an embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is formed of polysilicon or amorphous silicon and is replaced using a process including using SF 6 In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed by using a dry etching process including using a water-based NH 4 In one embodiment, the dummy gate is made of silicon nitride and is removed using a wet etch including water-based phosphoric acid.

[0120] Reference again Figure 8 , the arrangement of the semiconductor structure or device 800 places the gate contact above the isolation region. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region (e.g., above the fin 805) and in the same layer as the trench contact via.

[0121] In an embodiment, the offset gate cutting method described above may be used to form Figure 8 structure.

[0122] It should be appreciated that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. Moreover, the processes described herein can be used to make one or more semiconductor devices. The semiconductor device can be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for a logic unit or a memory, or a bipolar transistor. Moreover, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanobelt device, a tri-gate device, an independently accessed dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for manufacturing semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0123] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO 2 )), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the prior art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0124] In an embodiment, as used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. A common example is a structure using copper lines and a barrier layer that may or may not include copper and surrounding ILD materials. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Thus, the interconnect may be a single material layer, or may be formed by several layers, including a conductive liner layer and a filling layer. Any suitable deposition process such as electroplating, chemical vapor deposition, or physical vapor deposition may be used to form the interconnect. In an embodiment, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or an alloy thereof. In the art, interconnects are sometimes referred to as traces, wires, lines, metals, or simply interconnects.

[0125] In an embodiment, as also used throughout this specification, the hard mask material, cap layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In an embodiment, different hard mask, cap, or plug materials may be used in different regions to provide different growth or etching selectivities relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, cap, or plug layer includes a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, cap, or plug layers known in the art may be used. The hard mask, cap, or plug layer may be formed by CVD, PVD, or by other deposition methods.

[0126] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV lithography, and / or EBDW lithography, etc. Positive tone or negative tone resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0127] In another aspect, one or more embodiments relate to adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may relate to integrating multi-width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by SAGE wall spaces. In an embodiment, nanowires / nanoribbons with multiple Wsi are integrated in the SAGE architecture portion of the front-end process flow. Such a process flow may involve integrating nanowires and nanoribbons with different Wsi to provide robust functionality of next-generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., removing portions of the nanowires and then performing source or drain (S / D) growth).

[0128] To provide further context, the advantages of the self-aligned gate endcap (SAGE) architecture can include enabling higher layout density and, in particular, scaling of diffusion to diffusion spacing. To provide an illustrative comparison, Fig. 9 Cross-sectional views taken through nanowires and fins are shown for a non-endcap architecture (left side (a)) compared to a self-aligned gate endcap (SAGE) architecture (right side (b)) in accordance with an embodiment of the present disclosure.

[0129] refer to Fig. 9On the left side (a), the integrated circuit structure 900 includes a substrate 902 having a fin 904 that protrudes from the substrate to an amount 906 above an isolation structure 908 that laterally surrounds a lower portion of the fin 904. As shown, the upper portion of the fin may include a relaxed buffer layer 922 and a defect modification layer 920. A corresponding nanowire 905 is above the fin 904. A gate structure may be formed above the integrated circuit structure 900 to fabricate a device. However, such a discontinuity in the gate structure may be accommodated by increasing the spacing between the fin 904 / nanowire 905 pairs.

[0130] In comparison, reference Fig. 9 On the right side (b), the integrated circuit structure 950 includes a substrate 952 having a fin 954 that protrudes from the substrate to an amount 956 above an isolation structure 958 that laterally surrounds the lower portion of the fin 954. As shown, the upper portion of the fin may include a relaxed buffer layer 972 and a defect modification layer 970. The corresponding nanowire 955 is above the fin 954. An isolation SAGE wall 960 (which may include a hard mask, as depicted) is included within the isolation structure 952 and between adjacent fin 954 / nanowire 955 pairs. The distance between the isolation SAGE wall 960 and the nearest fin 954 / nanowire 955 pair defines a gate end cap spacing 962. A gate structure can be formed above the integrated circuit structure 900 and between the isolation SAGE walls to make a device. This interruption in the gate structure can be imposed by the isolation SAGE wall. Since the isolation SAGE walls 960 are self-aligned, it is possible to minimize the limitations from conventional schemes, thereby achieving more aggressive diffusion to diffusion spacing. In addition, since the gate structure includes interrupts at all locations, the various gate structure portions can be layered through local interconnects formed on the isolation SAGE walls 960. In an embodiment, as depicted, the SAGE walls 960 each include a lower dielectric portion and a dielectric cap on the lower dielectric portion. According to an embodiment of the present disclosure, the gate structure is connected to the local interconnects formed on the isolation SAGE walls 960. Fig. 9 The fabrication process of the associated structure involves using a process scheme that provides a gate-around integrated circuit structure with an epitaxial source or drain structure.

[0131] In an embodiment, the offset gate cutting method described above may be used to form Fig. 9 In an embodiment, the structure of part (a) can be formed using, for example, the offset gate cutting method described above. Fig. 9 The structure of part (b).

[0132] A self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned to the fin without requiring additional length to address the problem of mask misalignment. Thus, embodiments may be implemented to enable a reduction in transistor layout area. Embodiments described herein may involve the manufacture of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate end cap (SAGE) wall.

[0133] In an exemplary processing scheme for a structure having SAGE walls separating adjacent devices, Fig.10 Cross-sectional views are shown representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with a gate-around device in accordance with an embodiment of the present disclosure.

[0134] refer to Fig.10 , a starting structure includes a nanowire patterned stack 1004 above a substrate 1002. A lithographically patterned stack 1006 is formed above the nanowire patterned stack 1004. As shown, the nanowire patterned stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be above a relaxation buffer layer 1082 and a defect modification layer 1080. A protective mask 1014 is between the nanowire patterned stack 1004 and the lithographically patterned stack 1006. In one embodiment, the lithographically patterned stack 1006 is a three-layer mask consisting of a topography masking portion 1020, an anti-reflective coating (ARC) layer 1022, and a photoresist layer 1024. In a particular such embodiment, the topography masking portion 1020 is a carbon hard mask (CHM) layer, and the anti-reflective coating layer 1022 is a silicon ARC layer.

[0135] refer to Fig.10 In part (b), the stack of part (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 1002 and trenches 1030.

[0136] refer to Fig.10 1. The structure of portion (c) of portion (b) has an isolation layer 1040 and a SAGE material 1042 formed in the trench 1030. The structure is then planarized to leave the patterned topographic masking layer 1020' as an exposed upper layer.

[0137] refer to Fig.10 , recessing the isolation layer 1040 below the upper surface of the patterned substrate 1002 , for example, to define a protruding fin portion and provide a trench isolation structure 1041 below the SAGE wall 1042 .

[0138] refer to Fig.10In the step (e), the sacrificial layer 1010 is removed at least in the channel region to release the nanowires 1012A and 1012B. Fig.10 After forming the structure of portion (e), a gate stack can be formed around nanowire 1012B or 1012A, over the protruding fin of substrate 1002, and between SAGE walls 1042. In one embodiment, the remaining portion of protective mask 1014 is removed before forming the gate stack. In another embodiment, the remaining portion of protective mask 1014 is retained as an insulating fin cap, which is an artifact of the processing scheme.

[0139] Reference again Fig.10 In part (e), it should be appreciated that a channel view is depicted in which the source or drain region is positioned in and out of the page. In an embodiment, the channel region including nanowire 1012B has a width that is less than the channel region including nanowire 1012A. Thus, in an embodiment, the integrated circuit structure includes multi-width (multi-Wsi) nanowires. Although the structures of 1012B and 1012A can be distinguished as nanowires and nanoribbons, respectively, both such structures are generally referred to as nanowires in this document. It should also be appreciated that references or depictions of fin / nanowire pairs throughout the text may refer to a fin and one or more upper nanowires (e.g., Fig.10 According to an embodiment of the present disclosure, the structure of the two upper nanowires is shown in FIG. Fig.10 The fabrication process of the associated structure involves using a process scheme that provides a gate-around integrated circuit structure with an epitaxial source or drain structure.

[0140] In an embodiment, the offset gate cutting method described above may be used to form Fig.10 The structure of part (e).

[0141] In an embodiment, as described throughout this document, a self-aligned gate end cap (SAGE) isolation structure can be composed of one or more materials suitable for ultimately electrically isolating portions of a permanent gate structure from each other or contributing to such isolation. Exemplary materials or material combinations include single material structures, such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multilayer stack having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a higher dielectric constant material (e.g., hafnium oxide).

[0142] To highlight an exemplary integrated circuit structure with three vertically arranged nanowires, Fig.11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Fig. 11B The image taken along the a-a' axis is shown. Fig.11AA cross-sectional source or drain view of a nanowire-based integrated circuit structure. Fig. 11C The image taken along the b-b' axis is shown. Fig.11A Cross-sectional channel view of a nanowire-based integrated circuit structure.

[0143] refer to Fig.11A , the integrated circuit structure 1100 includes one or more vertically stacked nanowires (1104 set) above a substrate 1102. In an embodiment, as depicted, a relaxation buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are all included in the substrate 1102, as depicted. For the purpose of illustration, the optional fins located below the bottommost nanowire and formed from the substrate 1102 are not depicted, which is to emphasize the nanowire portion. The embodiments herein target both single-wire devices and multi-wire devices. As an example, for the purpose of illustration, a device based on three nanowires with nanowires 1104A, 1104B, and 1104C is shown. For ease of description, nanowire 1104A is used as an example, in which the description focuses on one of the nanowires. It should be recognized that in the case of describing the properties of a nanowire, embodiments based on multiple nanowires can have the same or substantially the same properties for each nanowire.

[0144] Each of the nanowires 1104 includes a channel region 1106 in the nanowire. The channel region 1106 has a length (L). Fig. 11C , the channel region also has a perimeter (Pc) orthogonal to the length (L). Fig.11A and Fig. 11C In both, the gate electrode stack 1108 surrounds the entire perimeter (Pc) of each channel region 1106. The gate electrode stack 1108 includes a gate electrode, along with a gate dielectric layer between the channel region 1106 and the gate electrode (not shown). In an embodiment, the channel region is discrete because it is completely surrounded by the gate electrode stack 1108 without intervening materials, such as substrate material below or channel fabrication material above. Therefore, in an embodiment with multiple nanowires 1104, the channel regions 1106 of the nanowires are also discrete relative to each other.

[0145] refer to Fig.11A and Fig. 11BIn both, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. The pair of non-discrete source or drain regions 1110 / 1112 are on either side of a channel region 1106 of a plurality of vertically stacked nanowires 1104. In addition, the pair of non-discrete source or drain regions 1110 / 1112 abut the channel region 1106 of the plurality of vertically stacked nanowires 1104. In one such embodiment, which is not depicted, the pair of non-discrete source or drain regions 1110 / 1112 are directly vertically abutting the channel region 1106 because epitaxial growth is on and between portions of the nanowires that extend beyond the channel region 1106, where the nanowire ends are shown as being within the source or drain structure. In another embodiment, as shown in FIG. Fig.11A As shown in FIG. 1 , the pair of non-discrete source or drain regions 1110 / 1112 are indirectly vertically adjacent to the channel region 1106 because they are formed at the ends of the nanowires rather than between the nanowires.

[0146] In an embodiment, as depicted, the source or drain regions 1110 / 1112 are non-discrete in that there is not an individual and discrete source or drain region for each channel region 1106 of the nanowire 1104. Thus, in an embodiment having multiple nanowires 1104, the source or drain regions 1110 / 1112 of the nanowires are global or unified source or drain regions as opposed to being discrete for each nanowire. That is, the non-discrete source or drain regions 1110 / 1112 are global in that a single unified feature is used as the source or drain region for multiple (in this case, 3) nanowires 1104, and more specifically, for more than one discrete channel region 1106. In one embodiment, each of the pair of non-discrete source or drain regions 1110 / 1112 is substantially rectangular in shape, having a bottom tapered portion and a top apex portion, as viewed from a cross-sectional perspective orthogonal to the length of the discrete channel region 1106. Fig. 11B However, in other embodiments, the source or drain region 1110 / 1112 of the nanowire is a relatively large but discrete non-vertically fused epitaxial structure, such as a combination of Figures 7A-7J Small pieces as described.

[0147] According to the embodiments of the present disclosure, and as Fig.11A and Fig. 11BAs depicted in , the integrated circuit structure 1100 also includes a pair of contacts 1114, each contact 1114 being on one of the pair of non-discrete source or drain regions 1110 / 1112. In one such embodiment, each contact 1114 completely surrounds the corresponding non-discrete source or drain region 1110 / 1112 in a vertical sense. In another aspect, the non-discrete source or drain region 1110 / 1112 may not be accessible throughout its entire perimeter for contact with the contacts 1114, and the contacts 1114 thus only partially surround the non-discrete source or drain region 1110 / 1112, as shown in FIG. Fig. 11B In a comparative embodiment not depicted, the entire perimeter of the non-discrete source or drain region 1110 / 1112 is surrounded by the contact 1114 as taken along the aa′ axis.

[0148] Reference again Fig.11A In an embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As depicted, peripheral portions of the pair of spacers 1116 may overlap portions of the non-discrete source or drain regions 1110 / 1112 to provide “embedded” portions of the non-discrete source or drain regions 1110 / 1112 below the pair of spacers 1116. Also as depicted, the embedded portions of the non-discrete source or drain regions 1110 / 1112 may not extend below the entirety of the pair of spacers 1116.

[0149] Substrate 1102 may be formed of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate 1102 includes a lower bulk substrate formed of a single crystal of a material, which may include but is not limited to silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or a III-V compound semiconductor material. An upper insulator layer composed of a material that may include but is not limited to silicon dioxide, silicon nitride, or silicon oxynitride is located on the lower bulk substrate. Thus, structure 1100 may be manufactured from a starting semiconductor-on-insulator substrate. Alternatively, structure 1100 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion in the place of the upper insulator layer. In another alternative embodiment, substrate 1100 is formed directly from a bulk substrate, and doping is used to form an electrically isolated active region, such as a nanowire, thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an Ω-FET type structure.

[0150] In an embodiment, the nanowires 1104 may be sized as wires or ribbons, as described below, and may have square or rounded corners. In an embodiment, the nanowires 1104 are made of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, for silicon nanowires 1104, the single crystalline nanowires may be based on a (100) global orientation, e.g., <100> The plane is in the z-direction. As described below, other orientations are also contemplated. In an embodiment, the dimensions of the nanowires 1104 are on the nanometer scale from a cross-sectional perspective. For example, in a specific embodiment, the smallest dimension of the nanowires 1104 is less than about 20 nanometers. In an embodiment, particularly in the channel region 1106, the nanowires 1104 are composed of a strained material.

[0151] refer to Fig. 11C , in an embodiment, each channel region 1106 has a width (Wc) and a height (Hc), the width (Wc) being approximately the same as the height (Hc). That is, in both cases, the cross-sectional profile of the channel region 1106 is square, or circular if the corners are rounded. In another aspect, the width and height of the channel region need not be the same, for example, as is the case with the nanoribbons described throughout.

[0152] In an embodiment, as described throughout, an integrated circuit structure includes a non-planar device, such as, but not limited to, a FinFET or a tri-gate device with a corresponding one or more upper nanowire structures. In such an embodiment, the corresponding semiconductor channel region is composed of or formed as a three-dimensional body with one or more discrete nanowire channel portions overlying the three-dimensional body. In one such embodiment, the gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, and also surrounds each of the one or more discrete nanowire channel portions.

[0153] In an embodiment, the offset gate cutting method described above may be used to form Figures 11A-11C structure.

[0154] In an embodiment, as described throughout, the underlying substrate may be composed of a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate composed of crystalline silicon, silicon / germanium or germanium layers doped with charge carriers, such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of epitaxial layers grown on different crystalline substrates, such as silicon epitaxial layers grown on boron-doped bulk silicon monomolecular crystal substrates. The bulk substrate may alternatively be composed of III-V materials. In an embodiment, the bulk substrate is composed of III-V materials, such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide or a combination thereof. In one embodiment, the bulk substrate is composed of III-V materials, and the charge carrier dopant impurity atoms are impurity atoms such as but not limited to carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

[0155] The embodiments disclosed herein can be used to manufacture a wide range of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, and microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a wide range of various electronic devices known in the prior art. For example, in computer systems (e.g., desktops, laptop computers, servers), cellular phones, personal electronic devices, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the method disclosed herein.

[0156] Fig.12 A computing device 1200 is shown in accordance with one implementation of an embodiment of the present disclosure. The computing device 1200 houses a board 1202. The board 1202 may include several components, including, but not limited to, a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the board 1202. In some implementations, the at least one communication chip 1206 is also physically and electrically coupled to the board 1202. In other implementations, the communication chip 1206 is part of the processor 1204.

[0157] Depending on its application, computing device 1200 may include other components that may or may not be physically and electrically coupled to board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (e.g., hard disk drive, compact disk (CD), digital versatile disk (DVD), etc.).

[0158] The communication chip 1206 is capable of wireless communication for transmitting data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 1206 may implement any of several wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher versions. The computing device 1200 may include multiple communication chips 1206. For example, the first communication chip 1206 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 1206 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO or others.

[0159] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures constructed according to implementations of embodiments of the present disclosure, such as a gate-around integrated circuit structure with reduced terminal capacitance. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0160] The communication chip 1206 also includes an integrated circuit die packaged within the semiconductor chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures constructed according to implementations of embodiments of the present disclosure, such as a gate-around integrated circuit structure with reduced terminal capacitance.

[0161] In other implementations, another component housed within computing device 1200 may include an integrated circuit die including one or more structures constructed in accordance with implementations of embodiments of the present disclosure, such as a gate-around integrated circuit structure with reduced terminal capacitance.

[0162] In various embodiments, computing device 1200 may be a laptop, a netbook, a notebook, an ultrabook, a smart phone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a cell phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other embodiments, computing device 1200 may be any other electronic device that processes data.

[0163] Fig.13 An interposer 1300 including one or more embodiments of the present disclosure is shown. Interposer 1300 is an intermediate substrate for bridging a first substrate 1302 to a second substrate 1304. First substrate 1302 may be, for example, an integrated circuit die. Second substrate 1304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 1300 is to extend a connection to a wider spacing or to reroute a connection to a different connection. For example, interposer 1300 may couple an integrated circuit die to a ball grid array (BGA) 1306, which in turn may be coupled to a second substrate 1304. In some embodiments, first and second substrates 1302 / 1304 are attached to opposite sides of interposer 1300. In other embodiments, first and second substrates 1302 / 1304 are attached to the same side of interposer 1300. In other embodiments, three or more substrates are interconnected by interposer 1300.

[0164] Interposer 1300 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In other embodiments, interposer 1300 may be formed of alternating rigid or flexible materials, which may include the same materials used in semiconductor substrates described above, such as silicon, germanium, and other III-V and IV materials.

[0165] The interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through silicon vias (TSVs) 1312. The interposer 1300 may further include embedded devices 1314, which include both passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices may also be formed on the interposer 1300, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used in the manufacture of the interposer 1300 or in the manufacture of components included in the interposer 1300.

[0166] Thus, embodiments of the present disclosure include integrated circuit structures having reduced terminal capacitance, and methods of fabricating integrated circuit structures having reduced terminal capacitance.

[0167] The above description of the exemplary embodiments of the present disclosure, including the contents described in the Abstract, is not intended to be exhaustive or limit the present disclosure to the precise form disclosed. Although the specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications may exist within the scope of the present disclosure, which will be recognized by those skilled in the art.

[0168] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be interpreted to limit the present disclosure to the specific embodiments disclosed in the specification and claims. Instead, the scope of the present disclosure is to be determined entirely by the following claims, which are to be interpreted in accordance with the principles established by claim interpretation.

[0169] Example embodiment 1: An integrated circuit structure includes a first vertical stack of horizontal nanowires having a first lateral width along a direction. A first gate electrode is above the first vertical stack of horizontal nanowires, the first gate electrode having a second lateral width along the direction. A second vertical stack of horizontal nanowires is laterally spaced apart from the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires having a third lateral width along the direction, the third lateral width being less than the first lateral width. A second gate electrode is above the second vertical stack of horizontal nanowires, the second gate electrode is laterally spaced apart from the first gate electrode, and the second gate electrode has a fourth lateral width along the direction, the fourth lateral width being less than the second lateral width.

[0170] Exemplary Embodiment 2: The integrated circuit structure according to Exemplary Embodiment 1, further comprising a dielectric plug laterally located between the first gate electrode and the second gate electrode.

[0171] Exemplary Embodiment 3: The integrated circuit structure according to Exemplary Embodiment 1 or 2, further comprising a first sub-fin under the first vertical stack of horizontal nanowires, and a second sub-fin under the second vertical stack of horizontal nanowires.

[0172] Exemplary Embodiment 4: The integrated circuit structure according to Exemplary Embodiment 1, 2 or 3, further comprising a first insulating gate cap over the first gate electrode, and a second insulating gate cap over the second gate electrode.

[0173] Exemplary Embodiment 5: The integrated circuit structure of Exemplary Embodiment 4, wherein the first gate electrode is not laterally recessed below the first insulating gate cap, and wherein the second gate electrode is laterally recessed below the second insulating gate cap.

[0174] Example 6: An integrated circuit structure includes a first fin having a first lateral width along a direction. A first gate electrode is above the first fin, and the first gate electrode has a second lateral width along the direction. A second fin is laterally spaced apart from the first fin, and the second fin has a third lateral width along the direction, and the third lateral width is less than the first lateral width. A second gate electrode is above the second fin, the second gate electrode is laterally spaced apart from the first gate electrode, and the second gate electrode has a fourth lateral width along the direction, and the fourth lateral width is less than the second lateral width.

[0175] Exemplary Embodiment 7: The integrated circuit structure according to Exemplary Embodiment 6, further comprising a dielectric plug laterally located between the first gate electrode and the second gate electrode.

[0176] Exemplary Embodiment 8: The integrated circuit structure according to Exemplary Embodiment 6 or 7, further comprising a first sub-fin under the first fin, and a second sub-fin under the second fin.

[0177] Exemplary Embodiment 9: The integrated circuit structure according to Exemplary Embodiment 6, 7 or 8, further comprising a first insulating gate cap over the first gate electrode, and a second insulating gate cap over the second gate electrode.

[0178] Example Embodiment 10: The integrated circuit structure of Example Embodiment 9, wherein the first gate electrode is not laterally recessed below the first insulating gate cap, and wherein the second gate electrode is laterally recessed below the second insulating gate cap.

[0179] Example embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure including a first vertical stack of horizontal nanowires or a first fin having a first lateral width along a direction. A first gate electrode is above the first vertical stack of horizontal nanowires or the first fin, and the first gate electrode has a second lateral width along the direction. A second vertical stack of horizontal nanowires or a second fin is laterally spaced apart from the first vertical stack of horizontal nanowires or the first fin, and the second vertical stack of horizontal nanowires or the second fin has a third lateral width along the direction, and the third lateral width is less than the first lateral width. A second gate electrode is above the second vertical stack of horizontal nanowires or the second fin, the second gate electrode is laterally spaced apart from the first gate electrode, and the second gate electrode has a fourth lateral width along the direction, and the fourth lateral width is less than the second lateral width.

[0180] Example Embodiment 12: The computing device of Example Embodiment 11, comprising a first vertical stack of horizontal nanowires and a second vertical stack of horizontal nanowires.

[0181] Example 13: The computing device according to Example 11, comprising the first fin and the second fin.

[0182] Exemplary Embodiment 14: The computing device of Exemplary Embodiment 11, 12 or 13, further comprising a memory coupled to the board.

[0183] Exemplary Embodiment 15: The computing device of Exemplary Embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the board.

[0184] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14 or 15, wherein the component is a packaged integrated circuit die.

[0185] Exemplary Embodiment 17: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15 or 16, further comprising a battery coupled to the board.

[0186] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a display coupled to the board.

[0187] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, further comprising a camera coupled to the board.

[0188] Exemplary Embodiment 20: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: a first vertical stack of horizontal nanowires having a first lateral width along a direction; a first gate electrode over the first vertical stack of horizontal nanowires, the first gate electrode having a second lateral width along the direction; a second vertical stack of horizontal nanowires laterally spaced apart from the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires having a third lateral width along the direction, the third lateral width being less than the first lateral width; A second gate electrode is above the second vertical stack of horizontal nanowires, the second gate electrode being laterally spaced apart from the first gate electrode and having a fourth lateral width along the direction, the fourth lateral width being less than the second lateral width. 2 . The integrated circuit structure of claim 1 , further comprising a dielectric plug laterally located between the first gate electrode and the second gate electrode. 3 . The integrated circuit structure of claim 1 , further comprising a first sub-fin beneath a first vertical stack of horizontal nanowires, and a second sub-fin beneath a second vertical stack of horizontal nanowires. 4 . The integrated circuit structure of claim 1 , further comprising a first insulating gate cap over the first gate electrode, and a second insulating gate cap over the second gate electrode.

5. The integrated circuit structure according to claim 4, wherein: The first gate electrode is not laterally recessed below the first insulating gate cap, and wherein the second gate electrode is laterally recessed below the second insulating gate cap.

6. An integrated circuit structure comprising: a first fin having a first lateral width along a direction; a first gate electrode on the first fin, the first gate electrode having a second lateral width along the direction; a second fin laterally spaced apart from the first fin, the second fin having a third lateral width along the direction, the third lateral width being less than the first lateral width; A second gate electrode is over the second fin, the second gate electrode is laterally spaced apart from the first gate electrode, and the second gate electrode has a fourth lateral width along the direction, the fourth lateral width being smaller than the second lateral width. 7 . The integrated circuit structure of claim 6 , further comprising a dielectric plug laterally located between the first gate electrode and the second gate electrode. 8 . The integrated circuit structure according to claim 6 , further comprising a first sub-fin under the first fin, and a second sub-fin under the second fin.

9. The integrated circuit structure of claim 6 or 7, further comprising a first insulating gate cap over the first gate electrode, and a second insulating gate cap over the second gate electrode.

10. The integrated circuit structure according to claim 9, wherein: The first gate electrode is not laterally recessed below the first insulating gate cap, and wherein the second gate electrode is laterally recessed below the second insulating gate cap.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: a first vertical stack or first fin of horizontal nanowires having a first lateral width along a direction; a first gate electrode over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width along the direction; a second vertical stack of horizontal nanowires or a second fin laterally spaced apart from the first vertical stack of horizontal nanowires or the first fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width along the direction, the third lateral width being less than the first lateral width; A second gate electrode is disposed over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode being laterally spaced apart from the first gate electrode and having a fourth lateral width along the direction, the fourth lateral width being less than the second lateral width.

12. The computing device of claim 11, comprising a first vertical stack of the horizontal nanowires and a second vertical stack of the horizontal nanowires. 13 . The computing device of claim 11 , comprising the first fin and the second fin.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12 or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12 or 13, wherein: The component is a packaged integrated circuit die.

17. The computing device of claim 11, 12 or 13, further comprising: A battery coupled to the board.

18. The computing device of claim 11, 12 or 13, further comprising: A display is coupled to the panel.

19. The computing device of claim 11, 12 or 13, further comprising: A camera is coupled to the board.

20. The computing device of claim 11, 12 or 13, wherein: The component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

Images